Semiconductor switch including short circuit detection circuit

Abstract

A semiconductor switch includes a first main terminal, a second main terminal, and a control terminal. The semiconductor switch further includes: a III-nitride high electron mobility transistor (HEMT), the III-nitride HEMT including a first source terminal, a first drain terminal, and a first gate terminal; a first interface circuit operatively connected to the control terminal and the first gate terminal; a sensing transistor including a sensing source terminal, a sensing drain terminal, and a sensing gate terminal; and a second interface circuit operatively connected to the control terminal and the sensing gate terminal; wherein the sensing transistor is configured to sense the on-state drain voltage of the III-nitride HEMT; wherein the second interface circuit is configured to transmit a sensed voltage signal to the first interface circuit, the sensed voltage being based on the on-state drain voltage of the III-nitride HEMT; wherein the first interface circuit is configured to turn off the III-nitride HEMT and / or reduce the voltage at the first gate terminal when the sensed voltage signal exceeds a threshold level.

Description

Technical Field

[0001] This disclosure relates to a semiconductor switch, and more particularly to a semiconductor switch comprising a group III nitride high electron mobility transistor (HEMT), the semiconductor switch including short-circuit detection and protection circuitry. Background Technology

[0002] Gallium nitride (GaN) is a wide-bandgap material whose properties make it a suitable candidate for several applications requiring solid-state devices, such as radio frequency electronics, optoelectronics, and power electronics.

[0003] GaN technology allows for the design of transistors with high electron mobility and high saturation velocity. These properties of GaN make it a good candidate material for high-power and high-temperature microwave applications, such as radar and cellular communication systems.

[0004] Furthermore, with its wide bandgap, GaN offers the potential to emit light at higher frequencies, such as the green, blue, violet, and ultraviolet portions of the electromagnetic spectrum.

[0005] Recently, GaN has been considered a very promising material for power devices. Applications include portable consumer electronics, solar inverters, electric vehicles, and power supplies. The material's wide bandgap (Eg = 3.39 eV) results in a high critical electric field (Ec = 3.3 MV / cm), which allows for the design of devices with shorter drift regions and therefore lower on-state resistance compared to silicon-based devices with the same breakdown voltage.

[0006] The use of aluminum gallium nitride (AlGaN) / GaN heterostructures also allows for the formation of a two-dimensional electron gas (2DEG) at the hetero interface, where carrier mobilities can reach very high levels [µ = 2000 cm⁻¹]. 2 The value of [ / (Vs)]. Furthermore, the piezoelectric polarization charge present in the AlGaN / GaN heterostructure leads to a high electron density (e.g., 1 x 10⁻⁶) in the 2DEG layer. 13 cm -2 These characteristics allow for the development of high electron mobility transistors (HEMTs) and Schottky barrier diodes with highly competitive performance parameters. A common parameter for comparing power semiconductor transistors is the specific on-state resistance, or specific Rds(ON). Specific Rds(ON) is the product of the device resistance and the device area on the wafer. Extensive research has focused on the development of power devices using AlGaN / GaN heterostructures.

[0007] However, the 2DEG inherent at the AlGaN / GaN heterojunction presents a challenge when attempting to design enhancement-mode rather than depletion-mode devices. Nevertheless, several methods have been proposed to realize enhancement-mode devices, including using metal-insulator-semiconductor structures, fluorine treatment, recessed gate structures, and p-type guard layers. Due to the relatively mature and controllable epitaxial growth of pGaN layers compared to other technologies, pGaN / AlGaN / GaN HEMTs are currently the leading commercially viable structure. The high-frequency operation of GaN allows designers to increase device power density, which in turn improves system efficiency and reduces costs. High power density and system efficiency are particularly advantageous for high-power applications. High-power applications such as motor control and inverters require enhanced short-circuit immunity. However, increasing the operating frequency presents challenges for designing short-circuit and overcurrent protection circuits for these GaN HEMTs. Furthermore, enhanced short-circuit durability is extremely important in motor control applications. For example, in a half-bridge configuration, when the low-side and high-side devices operate at different times in the on and off states, a short circuit may occur if both devices turn on due to a fault. This can be detected, and a signal can be sent to the controller / driver to turn the devices off.

[0008] Traditional short-circuit protection methods for silicon-based power devices, such as IGBTs, use external circuitry (e.g., desaturation circuitry that senses when the device is saturated), which has a delay time ranging from 2 µs to 10 µs, potentially too high for GaN HEMTs [1]. Under short-circuit conditions with high DC link voltages, GaN HEMTs can fail within hundreds of nanoseconds [2]. Power GaN HEMTs exhibit shorter failure times compared to other competing technologies such as IGBTs and SiC MOSFETs, which is associated with improved specific Ron of the device and its lateral configuration. Given the shorter failure times of GaN HEMTs, there is a need for short-circuit protection methods that can detect short-circuit events and protect the device in a shorter time.

[0009] Short-circuit detection methods may involve current or voltage sensing, which can have both advantages and disadvantages. Shunt current sensing resistors add additional parasitic inductance and resistance to the circuit, negatively impacting the switching performance and on-state losses of GaN HEMTs. Voltage sensing across the common source inductance (or resistor) is impractical for GaN because proactive measures are needed to reduce stray inductance in GaN circuits to improve switching performance without increasing on-state losses. Therefore, GaN devices require alternative short-circuit and overcurrent protection methods. Recent research has proposed discrete short-circuit / overcurrent circuits for protection, but these are either limited to low-power circuits or require impractical components. Implementing such functionality monolithically rather than discretely would allow for a reduction in overall system size / cost, a smaller bill of materials, and improved performance by reducing parasitic components associated with interconnections between discrete devices.

[0010] US Patent No. 10818786 discloses an overcurrent protection and detection circuit utilizing a current-sensing transistor (sensing HEMT), which can be monolithically integrated with a main power switch. The sensing HEMT can communicate with a Miller clamp to reduce the voltage on the gate of the GaN power HEMT. Summary of the Invention

[0011] To ensure stable and reliable operation of group III nitride (e.g., GaN) power ICs (or GaN chips), a fast and reliable short-circuit detection and protection method is required. Existing protection circuits require the addition of additional sensing components and / or have longer detection and protection times, which are unsuitable for the protection of power GaN HEMTs.

[0012] The purpose of this disclosure is to provide a short-circuit detection circuit (which can form part of a short-circuit protection circuit) that uses minimal components and provides ultrafast protection against short-circuit events. This can be implemented using a power integrated circuit comprising a power HEMT, a Miller clamp, an auxiliary GaN HEMT connected to the gate of the power HEMT, and a short-circuit detection module. Since these components are monolithically integrated with the power HEMT, the proposed method provides a simple and cost-effective solution.

[0013] The short-circuit detection circuit can shut down the power HEMT via a short-circuit detection signal and / or reduce the gate bias of the power HEMT.

[0014] Short-circuit events can be classified into at least two categories, typically described as Type 1 and Type 2 short-circuit events. Effective short-circuit protection solutions are needed to protect both Type 1 and Type 2 devices. The protection time for a Type 2 short-circuit event may need to be shorter than the response time for a Type 1 short-circuit event. Therefore, additional circuit modules can be implemented specifically for Type 2 short circuits.

[0015] This document describes a semiconductor switch, which includes a first main terminal, a second main terminal, and a control terminal. The semiconductor switch also includes:

[0016] A group III nitride high electron mobility transistor (HEMT) includes a first source terminal, a first drain terminal, and a first gate terminal;

[0017] A first interface circuit, operably connected to the control terminal and the first gate terminal; and

[0018] A short-circuit detection circuit, operably connected to the first drain terminal and the first source terminal, is configured to:

[0019] Detecting a short circuit between the first drain terminal and the first source terminal; and

[0020] A short-circuit detection signal is sent to the first interface circuit, which is configured to turn off the group III nitride HEMT and / or reduce the voltage at the first gate terminal upon receiving the short-circuit detection signal.

[0021] The group III nitride HEMTs may be referred to as “high voltage HEMTs” and / or “power HEMTs”.

[0022] It should be understood that terms such as “first,” “second,” “third,” etc., used in this document to refer to terminals and circuits are merely arbitrary designations for the purpose of providing clarity.

[0023] As used herein, “group III nitride” transistors (e.g., HEMTs), devices, or integrated circuits generally refer to transistors or devices based on group III nitride materials, including GaN, AlN, InN, and their alloys.

[0024] In some examples, the first interface circuitry includes a pull-down transistor (e.g., a Miller clamp) and / or a voltage limiter. The pull-down transistor may be a "low-voltage" HEMT. The pull-down transistor may be a Group III nitride transistor.

[0025] In the example, the first interface circuit includes a pull-down transistor, which includes a second source terminal and a second drain terminal;

[0026] Wherein, the second drain terminal is operatively connected to the first gate terminal;

[0027] Wherein, the second source terminal is operatively connected to the first source terminal; and

[0028] The pull-down transistor is configured to turn on when the first interface circuit receives the short-circuit detection signal.

[0029] The pull-down transistor can be controlled via its gate terminal (designated herein as the "second gate terminal").

[0030] The short-circuit detection signal can be directly provided to the second gate terminal to control the pull-down transistor (for example, the first interface circuit can be configured to receive the short-circuit detection signal at the second gate terminal).

[0031] In some examples, the first interface circuitry further includes a pull-down transistor gate driver (e.g., a gate driver circuit) operatively connected to and configured to drive the second gate terminal. In such cases, the short-circuit detection signal can be provided to the pull-down transistor gate driver (e.g., the first interface circuitry can be configured to receive the short-circuit detection signal at the pull-down transistor gate driver).

[0032] The first interface circuit may include an auxiliary gate interface circuit. The auxiliary gate interface circuit may include a voltage limiter. The auxiliary gate interface circuit may include an auxiliary group III nitride HEMT (which may be referred to as a low-voltage HEMT). The auxiliary gate interface circuit may include a voltage limiter. The auxiliary group III nitride HEMT may include: a third source terminal operatively connected to the first gate terminal; a third drain terminal operatively connected to the control terminal; and a third gate terminal operatively connected to the voltage limiter. The voltage limiter may be configured to limit the voltage between the first gate terminal and the first source terminal. For example, the short-circuit detection signal may be received at the first interface circuit. The first interface circuit may be configured to, upon receiving the short-circuit detection signal, cause the voltage limiter to limit the voltage between the first gate terminal and the first source terminal to, for example, a voltage lower than the gate voltage during normal operation. For example, the voltage limiter may reduce the voltage between the first gate terminal and the first source terminal.

[0033] It should be understood that, in some examples, the short-circuit detection signal may be received at both the pull-down transistor (the second gate terminal and / or the pull-down transistor gate driver) and the auxiliary gate interface circuit of the first interface circuit.

[0034] The semiconductor switch may include one or more signal conditioning circuits configured to regulate the short-circuit detection signal. The signal conditioning circuits may be provided in one or more signal conditioning modules.

[0035] Examples of signal conditioning circuits include: latch circuits; diodes having a cathode connected to the second gate terminal (i.e., pull-down transistor); transistor-shaped diodes; resistors and / or capacitors; logic inverters; buffers; and / or level shifters.

[0036] In some examples, the semiconductor switch includes a latching circuit. The latching circuit can be configured to modulate the short-circuit detection signal. For example, the latching circuit can be configured or arranged to receive and modulate the short-circuit detection signal during its transmission from the short-circuit detection circuit to the first interface circuit (e.g., the latching circuit can be arranged in the signal path of the short-circuit detection signal).

[0037] The latch circuit can be configured to provide a regulated short-circuit detection signal, which is held in a given state until one or more release conditions are met (i.e., the latch circuit can hold the regulated short-circuit detection signal to the interface circuit until the one or more release conditions are met, even if the short circuit condition does not exist in the HEMT). The one or more release conditions may include, for example, the expiration of a time period (i.e., the latch circuit can hold the regulated short-circuit detection signal for the duration of the time period). In some examples, the time period may be in the range of 1 microsecond to 500 microseconds. Alternatively or additionally, the one or more release conditions may depend on a signal, such as a signal applied to the control terminal of the semiconductor switch. The signal to the control terminal of the semiconductor switch may be provided by a gate driver (or controller), which is common in power electronic circuits. The signal from the gate driver of the semiconductor switch releasing the latch may go from high to low, indicating that the gate driver is turning off the semiconductor switch, which will eliminate the short circuit condition present in the HEMT.

[0038] The short-circuit detection circuit may include a desaturation circuit configured to detect a voltage drop between the first drain terminal and the first source terminal. The desaturation circuit may include at least one blanking resistor and at least one blanking capacitor. The time constant of the desaturation circuit may be defined as the product of the resistance of the at least one blanking resistor and the capacitance of the at least one blanking capacitor. The desaturation circuit may be configured to detect when the Group III nitride HEMT (“High Voltage HEMT”) is in a saturated state. The desaturation circuit may be configured to detect when a specific voltage drop between the first drain terminal and the first source terminal is reached. This specific voltage drop may be significantly higher than the on-state voltage drop (e.g., 2 V), but significantly lower than the rated blocking voltage (e.g., 650 V). For example, the specific voltage drop may be approximately 10 V.

[0039] In some examples, the voltage drop is between 5 V and 30 V. In some examples, the time constant is between 50 ns and 1 microsecond.

[0040] The short-circuit detection circuit may include a resistor-capacitor (RC) network (e.g., resistors and capacitors arranged in a loop). The short-circuit detection circuit may also include a HEMT referred to as a sensing HEMT. The sensing HEMT may have the same geometry and structure as the group III nitride HEMT (“high-voltage HEMT”) described herein, but may have a relatively reduced gate width or area compared to the group III nitride HEMT (“high-voltage HEMT”). The sensing HEMT may include one or more group III nitride materials.

[0041] The sensing HEMT may include: a fourth source terminal operatively connected to the RC network; a fourth drain terminal operatively connected to the first drain terminal; and a fourth gate terminal operatively connected to the first gate terminal.

[0042] The fourth source terminal may be further operatively connected (e.g., directly connected, or connected via an interface) to the second gate terminal (i.e., the gate terminal of the pull-down transistor). The sensing HEMT may be configured to detect a voltage drop (caused by a short circuit) on the sensing RC network and may be further configured to turn on the pull-down transistor when the voltage drop is detected. As an example, the voltage drop may be between 2 V and 5 V.

[0043] The short-circuit detection circuit may include: a voltage detection circuit configured to compare the voltage between the first drain terminal and the first source terminal with a reference voltage, and to output a high-voltage detection signal when the voltage between the first drain terminal and the first source terminal is higher than the reference voltage; and a blanking time circuit configured to output a blanking time signal after a blanking time period has elapsed.

[0044] The short-circuit detection circuit can be configured to send the short-circuit detection signal based on the high-voltage detection signal and the blanking time signal (e.g., based on a combination of the high-voltage detection signal and the blanking time signal). For example, the short-circuit detection circuit may further include a logic combination circuit configured to receive the high-voltage detection signal and the blanking time signal, and output the short-circuit detection signal based on a combination of the high-voltage detection signal and the blanking time signal.

[0045] The voltage detection circuit can be enabled by the output of the blanking time circuit to output a high-voltage detection signal indicating short-circuit detection.

[0046] The voltage detection circuit may include a differential comparator circuit configured to compare the voltage between the first drain terminal and the first source terminal (which may be provided as the input voltage of the differential comparator circuit) with the reference voltage.

[0047] Any one of the short-circuit detection circuit, the pull-down transistor, the auxiliary HEMT, the interface, and / or the voltage limiter can be integrated on a single chip.

[0048] Any of the resistors, capacitors, and / or RC networks described above can be monolithically integrated with the group III nitride HEMT. In some examples, one or more resistors or capacitors may be provided externally (e.g., one of the resistors and capacitors in the RC network may be provided on-chip, while the other may be provided off-chip).

[0049] In the example, the first interface circuitry includes an additional pull-down transistor (e.g., the first interface circuitry may include the additional pull-down transistor), the additional pull-down transistor having a fifth source terminal and a fifth drain terminal; wherein the fifth drain terminal is operatively connected to the first gate terminal; wherein the fifth source terminal is operatively connected to the first source terminal. The additional pull-down transistor may be configured or optimized to control the Group III nitride HEMT in the absence of a short-circuit condition and to operate the Group III nitride HEMT under other conditions, such as normal switching (e.g., device off) and avoiding false turn-on events (e.g., acting as an active Miller clamp). For example, the additional pull-down transistor may have a larger area or gate width compared to the other pull-down transistor. For example, the additional pull-down transistor may have a lower on-state resistance than the other pull-down transistor.

[0050] The additional pull-down transistor can be a "low-voltage" HEMT. The additional pull-down transistor can be a Group III nitride transistor. The additional pull-down transistor can be a Miller clamp.

[0051] In some examples, the short-circuit detection circuit is configured to detect a rapid positive change (dV / dt) in the voltage between the first drain terminal and the first source terminal over time. Such a rapid dV / dt can indicate a type 2 short-circuit event.

[0052] The semiconductor switch may include a second short-circuit detection circuit.

[0053] The second short-circuit detection circuit can be configured to detect a positive change in voltage between the first drain terminal and the first source terminal over time; and the second short-circuit detection circuit can be configured to send (e.g., a second) short-circuit detection signal when the positive change in voltage over time exceeds a reference rate. For example, the reference rate can be 150 V / ns.

[0054] The (second) short-circuit detection signal generated by the second short-circuit detection circuit can be received by the first interface circuit.

[0055] In some examples, the semiconductor switch is a common-source cascode switch.

[0056] In some examples, the semiconductor switch is a parallel connection of multiple group III nitride switches.

[0057] In some examples, the semiconductor switch is a series combination of a group III nitride switch and a level shifter.

[0058] In some examples, the semiconductor switch is a combination switch, which further includes: a low-voltage auxiliary HEMT, the low-voltage auxiliary HEMT including an auxiliary HEMT source terminal, an auxiliary HEMT drain terminal, and an auxiliary HEMT gate terminal; a voltage limiter operatively connected to the auxiliary HEMT gate terminal; and a high-voltage transistor device, the high-voltage transistor device including a first transistor device terminal, a second transistor device terminal, and a transistor device gate terminal; wherein the auxiliary HEMT source terminal is operatively connected to the high-voltage HEMT gate terminal; wherein the high-voltage HEMT source terminal and the first transistor device terminal are operatively connected to a first master terminal; wherein the high-voltage HEMT drain terminal and the second transistor device terminal are operatively connected to a second master terminal; wherein the auxiliary HEMT drain terminal and the high-voltage transistor device gate terminal are operatively connected to a control terminal; wherein the voltage limiter is operatively connected to the high-voltage HEMT source terminal and the auxiliary HEMT gate terminal, and further wherein the voltage limiter is configured to limit the voltage between the high-voltage HEMT gate terminal and the high-voltage HEMT source terminal.

[0059] The high-voltage transistor device may include silicon transistors and / or silicon carbide transistors.

[0060] The high-voltage transistor device may include an insulated-gate bipolar transistor (IGBT). The first transistor device terminal may include an IGBT emitter terminal. The second transistor device terminal may include an IGBT collector terminal.

[0061] The high-voltage transistor device may include a metal-oxide-semiconductor field-effect transistor (MOSFET). The transistor device terminals may include a MOSFET source terminal. The second transistor device terminal may include a MOSFET drain terminal.

[0062] The high-voltage transistor device may include a superjunction. The first transistor device terminal may include a superjunction source terminal. The second transistor device terminal may include a superjunction drain terminal.

[0063] This document also describes a system comprising a semiconductor switch as described herein and an external gate driver (or controller). The external gate driver / controller may be configured to control the group III nitride HEMT (e.g., the external gate driver may be operatively connected to the first gate terminal). A short-circuit detection circuit may be configured to send a short-circuit detection signal to the external gate driver. For example, the short-circuit detection signal may be provided to the external gate driver / controller as a fault signal. The external gate driver / controller may record that the semiconductor switch is experiencing a short circuit.

[0064] The external gate driver can be configured to turn off the semiconductor switch when the external gate driver receives the short-circuit detection signal. Therefore, the external gate driver can provide additional protection for the group III nitride HEMT. For example, the short-circuit protection circuit (which may be on-chip and / or monolithically integrated with the group III nitride HEMT) can protect the group III nitride HEMT until sufficient time has elapsed to report a fault to the external gate driver / controller.

[0065] The short-circuit detection circuit can be configured to reset upon receiving a reset signal from the external gate driver / controller. For example, the reset of the latch in the short-circuit detection circuit may depend on the received reset signal. The reset signal may be a first high-to-low signal, or it may be a count of subsequent signals.

[0066] Furthermore, this paper describes a system comprising multiple semiconductor switches connected in parallel;

[0067] The first semiconductor switch among the plurality of semiconductor switches includes a first parallel mode detection circuit;

[0068] The second semiconductor switch among the plurality of semiconductor switches includes a second parallel mode detection circuit; and

[0069] Wherein, the short-circuit detection circuit of the first semiconductor switch is configured to send the short-circuit detection signal to the first parallel mode detection circuit, wherein the first parallel mode detection circuit is configured to send a detection signal to the second parallel mode detection circuit upon receiving the short-circuit detection signal; and

[0070] The second parallel mode detection circuit is configured to turn off the second semiconductor switch when the detection signal is received.

[0071] For example, the plurality of semiconductor switches can all be connected in parallel, each of the semiconductor switches including a parallel mode detection circuit, all of which are connected to each other. If any short-circuit detection circuit of one of the plurality of semiconductor switches detects a short circuit, it may cause the corresponding semiconductor switch to turn off. Simultaneously, a signal detection signal is sent to the other semiconductor switches in the plurality of semiconductor switches to cause them to also turn off.

[0072] In some examples, the semiconductor switch may include one or more of a common-source cascode device and / or a combination switch, the combination switch including a group III nitride switch connected in parallel with a high-voltage transistor switch, the high-voltage transistor switch being made of a material other than group III nitrides.

[0073] In some traditional systems, the sensing HEMT and the main power switch are driven by the same control signal, which can lead to limitations, such as the sensing HEMT being turned off when the main power switch is switched off for protection. Furthermore, many short-circuit detection circuits require additional timing and latching circuitry. Therefore, based on some examples described herein, a simple and reliable solution can be provided, reducing implementation complexity.

[0074] According to this disclosure, a short-circuit or overcurrent protection circuit is provided that uses minimal components and provides ultrafast protection against short-circuit or overcurrent events. This can be implemented using a power integrated circuit including a III-nitride HEMT, comprising its main interface circuitry and a sensing transistor (also referred to as a “sensing HEMT”) and its sensing interface circuitry. Because these components can be monolithically integrated with the III-nitride HEMT, the proposed method provides a simple and cost-effective solution.

[0075] III-nitride HEMTs can be referred to as "high-voltage HEMTs" or "power HEMTs".

[0076] The sensing HEMT may have the same geometry and architecture as the III-nitride HEMT (“High Voltage HEMT” / “Power HEMT”) described herein, but with a smaller gate width or area compared to the III-nitride HEMT (“High Voltage HEMT” / “Power HEMT”). The sensing HEMT may comprise one or more III-nitride materials.

[0077] The sensing HEMT can be considered part of a short-circuit detection circuit. The sensing HEMT is configured to sense the drain voltage of the III-nitride HEMT in its on-state and transmit a sensed voltage signal to the main interface circuit based on the on-state drain voltage. When a short-circuit event is indicated by the sensed voltage signal exceeding a certain threshold voltage, the main interface circuit reduces the voltage bias of the power HEMT gate or turns off the power HEMT. Optionally, the sensed voltage signal can be adjusted using signal conditioning circuitry (such as a level offset circuit).

[0078] The sensing interface circuitry is configured to control the gate of the sensing HEMT independently of the power HEMT. This allows the sensing HEMT to switch independently, avoiding a reduction in the turn-on speed of the power HEMT. For example, the sensing HEMT can turn on after a certain delay. This design allows the sensing HEMT to be fully turned on even when the sensing voltage signal rises significantly (e.g., reaching 2V or higher). The independent gate voltages of the sensing HEMT and the power HEMT allow the gate voltage of the power HEMT to be pulled down while maintaining full sensing capability.

[0079] This document describes a semiconductor switch, including a first main terminal, a second main terminal, and a control terminal. The semiconductor switch further includes:

[0080] III-nitride high electron mobility transistor (HEMT), the III-nitride HEMT including a first source terminal, a first drain terminal and a first gate terminal;

[0081] A first interface circuit is operatively connected to the control terminal and the first gate terminal;

[0082] A sensing transistor, comprising a sensing source terminal, a sensing drain terminal, and a sensing gate terminal; and

[0083] The second interface circuit is operably connected to the control terminal and the sensing gate terminal;

[0084] The sensing transistor is configured to sense the drain voltage of the III-nitride HEMT in its on-state.

[0085] The second interface circuit is configured to transmit a sensed voltage signal to the first interface circuit, the sensed voltage signal being based on the on-state drain voltage of the III-nitride HEMT; and

[0086] The first interface circuit is configured to turn off the III-nitride HEMT and / or reduce the voltage at the first gate terminal when the sensed voltage signal exceeds a threshold level.

[0087] Lowering the voltage at the first gate terminal will reduce the short-circuit current, thereby increasing the short-circuit withstand time.

[0088] In some examples described here, the first interface circuit is referred to as the "main interface circuit" and the second interface circuit is referred to as the "sensing interface circuit".

[0089] The sensing transistor is configured to sense the on-state voltage of the III-nitride HEMT (here referred to as the power HEMT) and generate a sense voltage signal. When the sense voltage signal exceeds a certain threshold or limit, it may indicate that the power HEMT is in a short-circuit state, so the sense voltage signal can also be referred to as a short-circuit detection signal (SCD).

[0090] It is understood that a semiconductor switch including the sensing transistor described herein may include one or more optional components of the semiconductor switch examples described above and involved herein, which have short-circuit detection circuitry and / or parallel mode detection circuitry.

[0091] Such a semiconductor switch may include a signal conditioning circuit configured to regulate the drain voltage of the on-state to generate a sensed voltage signal. The signal conditioning circuit may be operatively connected between the sense source terminal and a first main terminal. In some examples, the signal conditioning circuit may be operatively connected between the sense drain terminal and a second main terminal.

[0092] The signal conditioning circuit can be set in one or more signal conditioning modules.

[0093] Examples of signal conditioning circuits include: a diode having a cathode terminal connected to a second gate terminal (i.e., the terminal of a pull-down transistor); a transistor-like diode; a resistor and / or a capacitor; a logic inverter; and / or a buffer.

[0094] In some examples, the signal conditioning circuitry includes a resistor divider. In some examples, the signal conditioning circuitry includes a level shifter.

[0095] In cases where the sensed voltage signal is generated by adjusting the on-state drain voltage of a III-nitride HEMT (e.g., via the signal conditioning circuit described herein), the signal generated by adjusting the on-state drain voltage (also denoted as SCDC) may correspond to the sensed voltage signal. Generally, the sensed voltage signal reflects the on-state voltage of the III-nitride HEMT. Therefore, it can be understood that the terms "SCD (signal)," "SCDC (signal)," and "sensed voltage signal" can be used interchangeably in the examples described herein to transmit the sensed voltage signal to the first interface circuitry.

[0096] In some examples, the first interface circuitry includes a first pull-down device (e.g., a pull-down transistor) operatively connected to a first gate and configured to activate when a sensed voltage signal exceeds a threshold level. The sensed voltage signal (short-circuit detection signal) can be directly provided to the gate of the first pull-down transistor to control the pull-down transistor (e.g., the first interface circuitry can be configured to receive the sensed voltage signal at the gate of the pull-down transistor).

[0097] In some examples, the first interface circuitry includes a pull-down transistor gate driver (e.g., a gate drive circuitry) operatively connected to and configured to drive the gate terminal of the first pull-down transistor. In this case, a sensed voltage signal can be provided to the gate driver of the pull-down transistor (e.g., the first interface circuitry can be configured to receive the sensed voltage signal at the gate driver of the pull-down transistor).

[0098] In some examples, the first interface circuitry includes a second pull-down device (e.g., a pull-down transistor) operatively connected to the first gate terminal; wherein the second pull-down device is configured to control the shutdown of the III-nitride HEMT and / or prevent mis-turn-on of the III-nitride HEMT during normal operation of the semiconductor switch (i.e., in the absence of a short circuit between the first drain terminal and the first source terminal).

[0099] The second pull-down device may be connected in parallel with the first pull-down device. The second pull-down device may be configured or optimized for controlling a III-nitride HEMT in the absence of a short circuit, as well as for use under other conditions (such as normal switching operation, e.g., device shutdown) and to avoid false turn-on events (e.g., as active Miller clamping operation). For example, the second pull-down device may have a larger area or gate width compared to the first pull-down device configured to operate in a short-circuit state. For instance, the second pull-down device may have a lower on-state resistance than the first pull-down device.

[0100] The second pull-down device may include a "low-voltage" HEMT. The second pull-down device may include a III-nitride transistor.

[0101] In some examples, the first interface circuitry includes a first auxiliary gate interface circuitry. When the sensed voltage signal exceeds a threshold level, the first auxiliary gate interface circuitry may be configured to reduce the bias voltage at the first gate terminal, and / or the first auxiliary gate interface circuitry may be configured to adjust the voltage applied to the control terminal to be compatible with the operation of the first gate terminal. The first auxiliary gate interface circuitry may correspond to any auxiliary gate interface circuitry described and exemplified herein.

[0102] The first auxiliary gate interface circuit may include: a first auxiliary transistor, the first auxiliary transistor including a source terminal, a drain terminal, and a gate terminal. The source terminal of the first auxiliary transistor is operatively connected to the first gate terminal, and the drain terminal is operatively connected to a control terminal.

[0103] A first voltage limiter (e.g., a voltage limiter for a first interface circuit) can be configured to limit the potential applied to the gate of a first auxiliary transistor.

[0104] The first auxiliary gate interface circuit may include an auxiliary transistor pull-down device, wherein the auxiliary transistor pull-down device is configured to turn on when the sensed voltage signal exceeds a threshold level, and when the auxiliary transistor pull-down device is turned on, the auxiliary transistor pull-down device is configured to reduce the voltage at the gate terminal of the first auxiliary transistor.

[0105] It is understood that, in some examples, the sensed voltage signal may be simultaneously received by the first and / or second pull-down device (e.g., the gate terminal and / or the pull-down device gate driver of the first and / or second pull-down device), and the first auxiliary gate interface circuit of the first interface circuit.

[0106] In some examples, the second interface circuitry includes a sensing pull-down transistor (e.g., a Miller clamp) and / or a second voltage limiter. The sensing pull-down transistor may be a "low-voltage" HEMT. The sensing pull-down transistor may be a III-nitride transistor.

[0107] The sensing pull-down device can be driven by a first interface circuit or a second interface circuit.

[0108] For example, the second interface circuit may include a sensing pull-down device operatively connected to a sensing gate terminal.

[0109] The first pull-down device and the sensing pull-down device may both be configured to be driven by the same driving circuit.

[0110] In some examples, the second interface circuitry includes a second auxiliary gate interface circuitry operably connected to the sensing gate terminal and configured to adjust the voltage applied to the control terminal to be compatible with the operation of the sensing gate terminal.

[0111] The second auxiliary gate interface circuit may include a second auxiliary transistor, the second auxiliary transistor including a source terminal, a drain terminal, and a gate terminal, wherein the source terminal of the second auxiliary transistor is operatively connected to the sensing gate terminal, and the drain terminal of the second auxiliary transistor is operatively connected to the control terminal.

[0112] A second voltage limiter (e.g., a voltage limiter in a second interface circuit) may be configured to limit the potential applied to the gate of the second auxiliary transistor.

[0113] The second auxiliary gate interface circuit may include a current control circuit operatively connected between the drain terminal of the second auxiliary transistor and the gate terminal of the second auxiliary transistor.

[0114] The current control circuit may include resistive elements. The current control circuit may include a current source.

[0115] The second voltage limiter may include a threshold multiplier.

[0116] In some examples, the signal conditioning circuitry is part of the second interface circuitry.

[0117] In some examples, the signal conditioning circuitry includes a first voltage divider operably connected between the sensing source terminal and the first master terminal. The first voltage divider is configured to generate a regulated on-state drain voltage version at the sensing source terminal. As described herein, the sensed voltage signal may be referred to as a short-circuit detection signal. Alternatively, a level shifter may be provided to shift the regulated sensed on-state drain voltage version to generate the sensed voltage signal (also referred to as the short-circuit detection signal).

[0118] Alternatively, the sensing drain terminal can be connected to the first drain terminal via a second voltage divider, so that the sensing transistor receives a portion of the III-nitride HEMT drain voltage to generate a sensing voltage signal.

[0119] In some examples, the semiconductor switch includes other transistors configured to limit the voltage applied to the second voltage divider when the power high electron mobility transistor (HEMT) and the sensing transistor are in blocking mode. That is, when the III-nitride HEMT is turned off or when the voltage at the first gate is reduced. The second voltage divider and other transistors may be part of signal conditioning circuitry, which in turn may be part of a second interface circuitry.

[0120] For example, the further transistors may have additional gate terminals operatively connected to a control terminal and selectively connected via a second auxiliary gate interface circuit. The additional transistors may also have additional source terminals and other drain terminals.

[0121] The sensing transistor, the first interface circuit, and / or the second interface circuit may be monolithically integrated with a III-nitride HEMT.

[0122] Any one or more of the sensing transistor, second interface circuit, pull-down transistor, auxiliary transistor, interface, and / or voltage limiter may be monolithically integrated.

[0123] Any one or more of the resistors, capacitors, and / or RC networks mentioned above may be monolithically integrated with a III-nitride HEMT. In some examples, one or more resistors or capacitors may be externally supplied (e.g., one of the resistors and capacitors in the RC network may be on-chip while the other may be off-chip).

[0124] In some cases, semiconductor switches are cascaded.

[0125] In some cases, the semiconductor switch is a parallel connection of multiple III-nitride switches.

[0126] In some examples, the semiconductor switch is a series combination of III-nitride switches with level shifters.

[0127] Similar to other examples described herein, the sensed voltage signal can be reset or disabled (e.g., the generation of the sensed voltage signal can be reset or disabled), which is achieved by a reset signal. The reset signal can be controlled by timing or logic circuitry. The timing or logic circuitry can be part of a signal conditioning circuit. In some examples, the reset signal may be provided by an external driver.

[0128] In some examples, the semiconductor switch is a combination switch, and additionally includes a high-voltage transistor device connected in parallel with a power HEMT. The high-voltage transistor device includes a high-voltage transistor drain terminal, a high-voltage transistor source terminal, and a high-voltage transistor gate terminal; wherein the first source terminal and the high-voltage transistor source terminal are operatively connected to a first main terminal; the first drain terminal and the high-voltage transistor drain terminal are operatively connected to a second main terminal; and the gate terminal of the high-voltage transistor device is operatively connected to a control terminal.

[0129] High-voltage transistor devices may include silicon and / or silicon carbide transistors. Attached Figure Description

[0130] The invention will now be described by way of example with reference to the following figures:

[0131] Figure 1 A schematic circuit diagram of an overcurrent protection circuit according to US10818786B1 is shown.

[0132] Figure 2 An example of a semiconductor switch according to this disclosure is illustrated schematically;

[0133] Figure 3 An example of a semiconductor switch including a Miller clamp transistor and an auxiliary gate interface is shown;

[0134] Figure 4 A semiconductor switch including an auxiliary gate interface with short-circuit protection is shown;

[0135] Figure 5 A semiconductor switch is shown in which a short-circuit detection signal serves as the input to the Miller clamp driver / transistor and the auxiliary gate interface;

[0136] Figure 6 An example block diagram of a short-circuit detection circuit is shown;

[0137] Figure 7 Another example of a block diagram of a short-circuit detection circuit is shown;

[0138] Figure 8 An example of a short-circuit detection circuit is shown;

[0139] Figure 9 An example is shown where a sensing HEMT is driven by a signal from a power HEMT.

[0140] Figure 10 Another example of a short-circuit detection circuit is shown;

[0141] Figure 11 An example of a VDS detection module is shown;

[0142] Figure 12 Another example of a VDS detection module is shown;

[0143] Figure 13 Another example of a VDS detection module is shown;

[0144] Figure 14 Another example of a VDS detection module is shown;

[0145] Figure 15 An example of a VDS detection module with a glitch filter is shown;

[0146] Figure 16 An example of a blanking time module is shown;

[0147] Figure 17 The relationship between the voltage values ​​at the input of the comparator and the output of the blanking time module and the reset input level is shown.

[0148] Figure 18 Another example of a blanking time module is shown;

[0149] Figure 19 An example of a circuit is shown, which can be connected between the output and auxiliary gate interface of the SCD module and the Miller clamp / Miller clamp driver circuitry;

[0150] Figure 20 An example of a Miller Clamp Drive (MCD) block is shown;

[0151] Figure 21 An example of how a logic inverter is implemented is shown;

[0152] Figure 22 An exemplary implementation of the Miller Clamp Driver (MCD) module operating based on a short-circuit detection (SCD) signal is shown.

[0153] Figure 23 Another example of an MCD module is shown;

[0154] Figure 24It shows Figure 2 , Figure 3 , Figure 4 and Figure 5 An example of an auxiliary gate interface module, which is part of the circuit shown;

[0155] Figure 25 Another implementation of the auxiliary gate interface module is shown, wherein an exemplary configuration of the voltage limiter has a pull-down HEMT in a threshold multiplier configuration;

[0156] Figure 26 An exemplary implementation of the auxiliary gate interface module operating based on a short-circuit detection signal (SCD) is shown;

[0157] Figures 27 to 30 Further examples of how the auxiliary gate interface module provides protection during short-circuit conditions are shown;

[0158] Figure 31 The short-circuit detection and protection mechanism is shown;

[0159] Figure 32 It shows Figure 31 An exemplary implementation of the short-circuit detection and protection mechanism is shown;

[0160] Figure 33 Another example of stepwise adjustment of the power HEMT under short-circuit conditions is shown;

[0161] Figure 34 and Figure 35 Two examples of comparators are shown;

[0162] Figure 36 A schematic example of a power integrated circuit connected to a gate driver is shown;

[0163] Figure 37 This illustrates another example of the connection between a power integrated circuit and a gate driver;

[0164] Figure 38 An additional example is shown where a short-circuit event in a power IC can be reported to a gate driver with DESAT functionality;

[0165] Figure 39 A timing diagram of the pulse sequence in the case of a type 1 short-circuit event is shown;

[0166] Figure 40 A power integrated circuit enabled for short-circuit detection in a parallel connection is shown;

[0167] Figure 41An example including a parallel mode detector module is shown, the parallel mode detector module including an e-mode HEMT device whose drain is connected to an SCIO pin;

[0168] Figure 42 An example of a parallel implementation is shown, illustrating two power ICs connected in parallel with each other;

[0169] Figure 43 Another example of a power integrated circuit is shown, in which the power HEMT switch is replaced by a combination switch consisting of high-voltage transistors connected in parallel with the high-voltage power HEMT device;

[0170] Figure 44 An example is shown where the SCD signal is regulated by a series of signal conditioning modules and then provided as input to the auxiliary gate interface and Miller clamp driver;

[0171] Figure 45 An alternative example of how short-circuit detection and protection can be implemented in a combined switch including a high-voltage GaN HEMT device connected in parallel with a high-voltage device made of another material is shown.

[0172] Figure 46 Another aspect of this disclosure is shown, in which a short-circuit detection circuit, rather than a power HEMT, can be integrated with a common-source cascode switch;

[0173] Figure 47 Another aspect of the previous embodiment is shown, wherein a combined switch including a common source cascode device connected in parallel with a high voltage device is provided;

[0174] Figure 48 It shows Figure 46 An exemplary implementation of the short-circuit detection circuit is shown;

[0175] Figure 49 An alternative example of an implementation of a sensing transistor with short-circuit detection circuitry for a cascode switch is shown;

[0176] Figure 50 An example of a power IC including at least one additional transistor connected in the same configuration as a Miller-clamped HEMT is shown;

[0177] Figure 51 An example is shown that includes an additional circuit module optimized to protect the device in the event of a Type 2 short circuit; and

[0178] Figure 52 An exemplary dv / dt event detection circuit that can be formed as part of a type 2 short-circuit detection module is shown.

[0179] Figure 53An example of a semiconductor switch including a sensing transistor according to this disclosure is shown.

[0180] Figure 54 An example of a semiconductor switch including a sensing transistor is shown, wherein the first interface circuit includes a Miller clamping transistor and an auxiliary gate interface.

[0181] Figure 55 An example of a semiconductor switch including a sensing transistor is shown, wherein an auxiliary gate interface provides short-circuit protection.

[0182] Figure 56 An example of a semiconductor switch is shown, including a sensing transistor and a signal conditioning circuit, the signal conditioning circuit including a resistor divider.

[0183] Figure 57 The IV curve and its gate voltage during the turn-on switching of the III-nitride HEMT are shown.

[0184] Figure 58 An example of a semiconductor switch including a sensing transistor is shown, wherein the sensing (second) interface circuitry includes a pull-down transistor of the sensing transistor and a second auxiliary gate interface.

[0185] Figure 59 An example of a semiconductor switch including a sensing transistor is shown, further including a second pull-down device for controlling the shutdown of the III-nitride HEMT and / or preventing accidental activation during normal operation of the semiconductor switch.

[0186] Figure 60 An example of a semiconductor switch including a sensing transistor is shown, and a second auxiliary gate interface circuit consisting of a second auxiliary transistor is also included.

[0187] Figure 61 An example of a current control circuit is shown.

[0188] Figure 62 An example of a current control circuit including a threshold multiplier is shown.

[0189] Figure 63 An example of an auxiliary gate interface module operating based on a short-circuit detection signal is shown.

[0190] Figure 64 Another example of a semiconductor switch including a sensing transistor is shown.

[0191] Figure 65 An example of a semiconductor switch including a sensing transistor is shown, wherein a second interface circuit includes a second voltage divider, and the semiconductor switch also includes other transistors.

[0192] Figure 66 An example of a semiconductor switch including a sensing transistor is shown, which is connected to an external gate driver.

[0193] Figure 67 An example of a semiconductor switch including a sensing transistor is shown, which is part of a combined switch including a high-voltage transistor connected in parallel with a III-nitride HEMT. Detailed Implementation

[0194] Figure 1 A schematic circuit diagram of an overcurrent protection circuit according to US10818786B1 is shown, the contents of which are incorporated herein by reference in their entirety. US10818786B1 describes a low-voltage depletion-mode transistor (second transistor) of a resistor and an active switch, the low-voltage depletion-mode transistor being used to control the potential at the gate of a main power transistor. The overcurrent protection circuit includes a first power transistor 19 consisting of a current-sensing transistor 16 and a main power transistor 19, a depletion-mode transistor (second transistor) 14, and a current-sensing resistor 15.

[0195] When an over-drain current is detected in the current-sensing transistor 16, the circuitry reduces or limits the gate voltage on the first power transistor 19 by using the depletion-mode device 14 and resistor 15 or resistive elements described above. If an overcurrent is detected, the voltage drop across the current-sensing resistor 15 increases, thus increasing the voltage bias at the gate of transistor 14, resulting in a sharp drop in the resistance of transistor 14. This reduces the resistance of the path between the gate and source of the first power devices 16, 19, thereby limiting the potential at the first gate.

[0196] Figure 2An example of a semiconductor switch according to the present disclosure is illustrated schematically. The semiconductor switch includes: a high-voltage group III nitride power HEMT 101; a (first) interface circuit 1000 having at least one connection to a control terminal and at least one connection to the internal gate of the high-voltage HEMT; and a short-circuit detection circuit 300 having at least one connection to the drain of the HEMT, at least one connection to the source of the HEMT, and at least one connection to the interface circuit. In the example according to the present disclosure, the group III nitride power HEMT is a high-voltage lateral GaN HEMT. The interface circuit 1000 is positioned in front of the gate of the high-voltage lateral GaN HEMT to adapt the drive voltage of the control terminal to a suitable and permissible drive voltage of the GaN HEMT. This interface is preferably monolithically integrated with the power HEMT to provide lower parasitic effects, ease of fabrication, and fast response time. Alternatively, this interface may be part of a separate chip, such as a silicon companion chip or a driver chip. For example, the drive voltage on the control terminal can be from 0 V to 20 V, while the drive voltage directly used by the gate terminal of the lateral high-voltage GaN HEMT is maintained from 0 V to 7 V.

[0197] like Figure 3 As shown, the first interface circuit 1000 may include a Miller clamp transistor 102 and / or an auxiliary gate interface 200.

[0198] Miller clamp transistor 102 can be connected between the gate and source of a power HEMT, which acts as a pull-down device to ensure fast and safe shutdown, enhance immunity to dV / dt, and avoid the need for a negative gate voltage to turn off the power HEMT. As another example, the output signal of short-circuit detection module 300 can serve as the input to the gate of the Miller clamp transistor (or the gate driver—MCD—of the Miller clamp transistor), causing the Miller clamp to turn the power HEMT on and off when a short circuit is detected.

[0199] like Figure 4As shown, the auxiliary gate interface 200 may include short-circuit protection functionality. The interface may also include additional clamping circuitry, sensing and protection functions, pull-down devices to ensure fast and safe shutdown, enhance immunity to dV / dt, and absorb any transient voltage spikes on the gate. The short-circuit detection module is configured to change its output signal when a short circuit is detected on the power HEMT, for example, having a low output signal when no short circuit is detected and a high output signal when a short circuit is detected. The short-circuit output signal can serve as an input to the auxiliary gate interface module, allowing the auxiliary gate interface module to either shut down the power HEMT or regulate the voltage at the gate of the power HEMT to a reduced voltage. Reducing the bias at the gate of the power HEMT may help extend the time the power HEMT can withstand a short-circuit event, as reducing the gate bias can lead to a reduction in the saturation current of the power HEMT in the event of a short circuit.

[0200] In some examples, such as Figure 5 As shown, the short-circuit detection signal can serve as an input to the Miller clamp driver / transistor and auxiliary gate interface module 200.

[0201] The output of the short-circuit detection module can be directly applied to the aforementioned circuit block, or indirectly applied via additional circuit modules (e.g., signal condition blocks and / or latching blocks). Embodiments of these additional circuit modules will be described herein. As an example, these additional circuit modules can be monolithically integrated with a power HEMT device to form a GaN power IC.

[0202] Figure 6 A schematic example of a sub-block of the short-circuit detection module 300 is shown. The short-circuit detection module can be configured to include a detection module VDS detection module 3001, which detects whether the power HEMT may be in a short-circuit state by detecting whether the drain-to-source voltage (Vds) of the device is higher than a set reference value. However, the situation where the drain-to-source voltage of the device exceeds the set reference value can occur not only during a short-circuit event but also when the power HEMT is off. In addition, Vds may also exceed the set reference value for a short period of time during a device switching event. To avoid "false triggering" of the short-circuit detection circuit by detecting a short-circuit event when no short-circuit event has occurred, a blanking time module can be configured. The blanking time module 3002 can output a signal after a set amount of time has elapsed. The control signal of the power HEMT can be used as an input to the blanking time module, such that time measurement only begins when the control signal indicates that the power HEMT is in an on-state condition.

[0203] The outputs of the Vds detection module and the blanking time module can be used to detect whether a short-circuit event has occurred in the power HEMT. An AND function may be applicable, for example, to ensure that a short circuit is detected only when Vds exceeds a reference value and the blanking time has elapsed. The functions of the Vds detection module and the blanking time module can be combined in a single circuit. Alternatively, the functions of the Vds detection module 3001, the blanking time module 3002, and the combinational logic function 3003 can be combined in a single circuit.

[0204] Figure 7 Other examples of sub-blocks of the short-circuit detection module 300 are shown. In this example, the blanking time module 3002a can be applied to the Vds detection module 3001a to enable its operation, such that a high Vds signal is detected only when the blanking time has elapsed. The logic function block can be an optional block.

[0205] Figure 8 A schematic diagram of an example short-circuit detection (SCD) circuit block 300 is shown. In this example, the SCD module 300a includes an additional HEMT serving as a current-sensing transistor (sensing HEMT) 104, an RC network 301, and a comparator 302. The sensing HEMT and the power HEMT may be structurally identical, but the main power HEMT has a much larger active area (e.g., 10 times, 100 times, or 1000 times larger) than the sensing HEMT. The drains of the power HEMT and the sensing HEMT may be connected together, and their gates may be connected together, but their source terminals may be separable. The sensing HEMT can be used to sense the current flowing through the source of the main power transistor to identify a short-circuit condition in the power HEMT. The sensing HEMT may be driven by a control signal, or, in the case of using an auxiliary gate interface, by a signal that drives the power HEMT, such as... Figure 9 As shown. When the control signal is high, indicating that the power HEMT is on, the sensing HEMT also turns on, and the capacitor in the RC network charges through the sensing HEMT. The RC network can therefore be configured with a blanking time, as a given amount of time is required for the capacitor to charge to a sufficient level while the control signal is high. If a short circuit occurs, the current through the sensing HEMT increases significantly as V(T2) - V(T1). The sensing HEMT may saturate, thus the current through the device will be self-limiting. Because the RC network is fully charged during a short circuit, the voltage at the source of the sensing HEMT may exceed the reference value (Vref). Under this condition, the comparator's output signal may change, for example, from low to high. Therefore, Figure 8 and Figure 9 The circuit shown may include Figure 6 All the functions of the SCD module described in [the document].

[0206] Figure 10A schematic diagram of another example of a short-circuit detection (SCD) circuit block 300 is shown. The circuit 300b in this example includes a high-voltage diode 305, an RC network 304, a current source 303, and a comparator 302. When V(T2) - V(T1) is low, the HV diode is forward biased and therefore draws current from the current source. When V(T2) - V(T1) is high, the HV diode is reverse biased, and therefore the capacitor in the RC network can charge to V(T2) - Vth, where Vth is the threshold voltage of the high-voltage diode 305. When C is charged to a value higher than Vref, the comparator can change from low to high.

[0207] To prevent the RC network from being charged during the device's off-state, and instead to be charged only under short-circuit conditions, a high V(T2) - V(T1) and the power HEMT being in the on-state are required. To add this functionality, a transistor 306 may be included. Transistor 306 is driven by a control signal or a signal-conditioned version of the control signal. Signal conditioning may mean, for example, that the signal is level-shifted and / or inverted.

[0208] Figure 11 It shows Figure 6 A schematic diagram of an example of the VDS detection module 3001 is shown. This circuit 3001a is configured to have an output change when the drain-to-source voltage (V(T2) - V(T1)) of the power HEMT exceeds a set reference value. The detection module 3001a is used as a differential circuit to provide higher accuracy throughout process and temperature variations. Each branch of the differential circuit includes an HV diode, a current source, and a current-to-voltage converter. The voltage of each branch of the differential circuit is configured as the input of a comparator. In this arrangement, if V(T2) - V(T1) exceeds Vref, the comparator changes its output.

[0209] Figure 12 It shows Figure 7 A schematic diagram of an example of the VDS detection module 3001 is shown. This circuit 3001a1 is configured to have a varying output when the drain-to-source voltage (V(T2) - V(T1)) of the power HEMT exceeds a set reference value. However, the comparator of this block is enabled by the output BLK_enable signal of the blanking time module, which is only output after a set blanking time has elapsed. Therefore, the output of the VDS detection module changes only after the blanking time.

[0210] Figure 13 It shows something similar to Figure 11 An example of a VDS detection module in an embodiment is provided. In this embodiment, the HV diode is implemented using a high-voltage HEMT with a source-gate connection.

[0211] Figure 14An example of a VDS detection module similar to the above embodiment is shown, wherein Vref is applied directly to the gate of transistor 308.

[0212] Figure 15 It shows something similar to Figure 14 The example of a VDS detection module includes a glitch filter (low-pass filter) at the input of the comparator. This filter is included to prevent the output of the comparator circuit from changing due to noise or other high-frequency signals in Vds. Similar glitch filters can be added to other examples of VDS detection modules included herein.

[0213] Figure 16 It shows Figure 6 An example of a blanking time module 3002 is shown. The blanking time module 3002a outputs a signal after a certain time. The blanking time module 3002a includes an RC blanking circuit connected to a voltage source VDD via a corresponding current source. A low-voltage transistor 313 is connected to the blanking capacitor CBLK. As an example, transistor 313 can be a low-voltage p-GaN gate HEMT. The blanking time module receives a control signal or, alternatively, a regulated version of the control signal as an input to the control terminal of the power HEMT 101, such as... Figure 6 As shown. An inverted and preferably level-shifted version of the control signal can be connected to transistor 313 as a 'reset' signal. Signal conditioning of the control signal can be performed within or outside the blanking time module, and is therefore not shown here for simplicity.

[0214] Figure 17 The diagram illustrates the relationship between the voltage values ​​at the input of comparator Comp3 and the output of the blanking time module and the reset input level. When the control signal is "low" (reset is "high"), transistor 313 is turned on, pulling Vcap to ground and discharging capacitor CBLK. When the control signal goes "high", the reset input goes "low". Transistor 313 is turned off, thus allowing capacitor CBLK to be charged by a current source through a voltage source VDD. When Vcap ( Figure 17 Curve 2) in the middle exceeds Vref1 ( Figure 17 When curve 1) appears, the output becomes "high". In summary, Figure 16 The circuit output in this circuit will not return to high until a given time has elapsed after the control signal transitions from low to high. This time can be defined as the blanking time. The blanking time can be reduced or extended based on the selection of the current source and / or capacitor values. The blanking time defined by the circuit can vary depending on the manufacturing process variations of the aforementioned component values.

[0215] As mentioned above, the blanking time defines the time during which the SCD circuit cannot detect a short-circuit event at the start of the power HEMT's turn-on pulse, thus preventing the erroneous triggering of the short-circuit protection circuit during normal device switching. Therefore, it is desirable that variations in the blanking time process match variations in the power HEMT's switching time process. For example, a longer blanking time may be required if used in a circuit with a power HEMT that requires a longer time to complete a switching event, and a shorter blanking time may be required if used in a circuit with a power HEMT that requires a shorter time to complete a switching event. Figure 18 The diagram shows a circuit that can achieve better process matching between the power HEMT and the blanking time circuit.

[0216] Figure 18 It shows Figure 6 Another example of the blanking time module 3002 is shown. In this example, the blanking time module 3002b is designed to account for process variations of the power HEMT and is configured to calculate the overall blanking time based on the power HEMT Rdson. To achieve this, a small HEMT 315 identical to the power HEMT is provided on the capacitor CBLK; therefore, the discharge rate of CBLK depends on the Rdson of the small HEMT, and thus indirectly on the Rdson of the power HEMT, since the small HEMT and the power HEMT are likely to vary in the same way if process variations occur. The small HEMT 315 may be structurally identical to the power HEMT, but the main power HEMT has a much larger active area than the small HEMT (e.g., 10 times, 100 times, 1000 times larger). The output of logic 1 depends on RBLK2 and CBLK. The output of logic 1 drives the small HEMT 315 and also acts as the enable signal for comparator Comp3b. Therefore, the output of logic 2 (which is also the output of the overall blanking time module 3002b) depends on RBLK1, the small power HEMT 315 and CBLK, and the output of logic 1.

[0217] Figure 19An example of circuitry 500 is shown, which can be connected between the output of SCD module 300 and the auxiliary gate interface and Miller clamp / Miller clamp driver circuitry. The output of the SCD module can indicate whether a short-circuit event has occurred in the power HEMT 101, but some signal conditioning may be required to suit its use as an input for the auxiliary gate interface and Miller clamp, which can be used to protect the power HEMT. Signal conditioning modules 501 and 503 may refer to circuitry covering functions such as level shifting, buffering, filtering, or some combinational logic with other sensing signals in the power IC. Additionally, latching circuitry block 502 may be required. The function of latching circuitry block 502 is to hold the signal indicating that the power HEMT is in a short-circuit event in a set state until another condition is met. This is to prevent oscillation of the short-circuit event detection and protection circuitry. The additional condition can be time-dependent, signal-dependent, or both. An example of a time-dependent condition could be that sufficient time has elapsed since the short-circuit event occurred to allow the device to adequately dissipate the heat generated during the short-circuit event. An example of a signal-dependent condition could be a "high-to-low" control signal pulse received from the power HEMT gate driver. In one example, releasing the latch might require a logic function with two conditions, such as elapsed time and a "high-to-low" pulse from the gate driver. It should be noted that the above embodiment is merely an example of circuit 500 and may include any combination of blocks 501, 502, and / or 503, as all of these blocks are optional.

[0218] Figure 20 It was shown as Figure 3 and Figure 4 An example of a Miller clamp driver (MCD) module 400, which is a portion of a power integrated circuit, is shown. The Miller clamp driver 400a consists of a logic inverter 401 configured to operate an active switch Miller clamp transistor 102 that acts as a pull-down network. The logic inverter 401 may consist of a resistor or resistive element (i.e., a load transistor or current source) and an enhancement-mode transistor. Figure 21 An example of how the logic inverter 401 in module 400a is implemented is shown. However, this is provided merely as an exemplary configuration, and other logic inverter designs may be used as alternatives or supplements to it.

[0219] In operation, the logic inverter is operatively connected to a control signal from either a control terminal or an external gate terminal (i.e., a terminal connected to a gate driver). When the control signal is high, the gate bias of the active switching transistor in Miller clamp 102 is low (and therefore its resistance is high), and when the control signal is low, the gate bias of the active switching transistor in Miller clamp 102 is high (and therefore its resistance is low).

[0220] Figure 22An exemplary implementation of the Miller clamp driver (MCD) module 400 operating based on a short-circuit detection signal (SCD) is shown. The Miller clamp driver 400b consists of a logic inverter 404 and logic gates (NAND gates) 405. In this case, the Miller clamp driver 400b has two input signals—a control signal and a short-circuit detection signal SCD or based on... Figure 19 The regulated version of the SCD (SCDC). When the SCD signal / SCDC signal is "high" or the control signal is "low", the drive module 400b will output a "high" signal, thereby activating the Miller clamp transistor 102, which will be used to pull down the gate of the power HEMT 101.

[0221] Figure 23 It shows Figure 22 The example provided is an illustration of how the Miller clamp driver module 400b is implemented. However, this is provided merely as an exemplary configuration and other circuit designs may be used as alternatives or supplements to it.

[0222] Figure 24 An example of an auxiliary gate interface module 200 is shown, the auxiliary gate interface module being Figure 2 , Figure 3 , Figure 4 and Figure 5 This is a portion of the power integrated circuit shown. The integrated auxiliary gate interface module (200) consists of an auxiliary GaN HEMT 201, which is preferably a low-voltage device, wherein the gate of a high-voltage power HEMT is connected to the source of the integrated auxiliary GaN HEMT, and the drain of the auxiliary GaN HEMT is connected to the control terminal of the power integrated circuit (power IC). The auxiliary GaN HEMT is configured to adapt the drive voltage of the control terminal to a suitable and permissible drive voltage of the GaN HEMT.

[0223] The current control module 202 is connected between the drain and gate terminals of the auxiliary GaN HEMT 201. The current control block has a connection to the control terminal. The current control module can be a resistive element or incorporate a resistive element. Alternatively, the current control circuitry can be or include a current source, as shown here, for example. However, this is merely shown as an exemplary configuration, and other circuit designs can be utilized as alternatives to or supplements to the current source.

[0224] An integrated voltage limiting module 203 is connected between the gate of the auxiliary HEMT and the low-voltage side of the power IC. The voltage drop across the auxiliary gate interface module 200 is non-linear as the voltage signal at the control terminal increases linearly. Low gate leakage current in the high-voltage power HEMT is achieved by limiting the potential at the gate (active gate) of the power HEMT. This is achieved by allowing the voltage drop across the integrated auxiliary gate interface module. By appropriately designing the current control module and voltage limiting circuit module to define the limit on the power HEMT gate potential, the gate of the auxiliary GaN HEMT is pulled down when the gate signal at the power IC control terminal increases above a certain level. Therefore, the gate voltage operating window of the power IC (i.e., the voltage operating window applied to the control terminal) is larger compared to the gate voltage operating window of a conventional GaN HEMT.

[0225] Since the auxiliary GaN HEMT is preferably a low-voltage device, its source and drain terminals are interchangeable, as they are typically fabricated in a symmetrical (or similar) manner. A low-voltage device is defined as one that typically has a rated breakdown voltage below 20 V and a limited current capability (below 100 mA). However, it should be understood that the auxiliary gate can also be a high-power or high-voltage device, although this may increase cost and complexity.

[0226] Figure 25 Another implementation of the auxiliary gate interface module 200 is shown, wherein an exemplary configuration of the voltage limiter 203 has a pull-down HEMT 204 in a threshold multiplier configuration. The threshold multiplier configuration in this embodiment includes a voltage divider (R6 and R7) and a pull-down enhancement mode HEMT 204, wherein the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT 204. In this embodiment, the top of the voltage divider is connected to the drain of the pull-down enhancement mode HEMT 204 and the gate terminal of the auxiliary GaN HEMT 201. The gate potential of the HEMT 204 is controlled to set the voltage drop across the pull-down HEMT 204, which can be controlled by selecting resistors in the described voltage divider. This limits the gate voltage across the auxiliary GaN HEMT 201 and the voltage drop across the auxiliary gate module. This function protects the power HEMT gate terminal from overvoltage events.

[0227] Figure 26 An exemplary implementation of the auxiliary gate interface module 200c operating based on a short-circuit detection signal (SCD) is shown. The auxiliary gate interface module 200c includes... Figure 24The voltage limiter in the circuit shown is connected in parallel to an additional HEMT 205. The gate of the additional HEMT 205 is connected to a short-circuit detection signal SCD or a regulated version of SCD (SCDC). When a short circuit is detected and the SCD / SCDC signal is "on high", HEMT 205 is turned on, thereby pulling the gate of the auxiliary GaN HEMT 201 down to ground. This turns off the auxiliary GaN HEMT, and thus the power HEMT gate and control terminal become effectively electrically disconnected. Under this condition, if the bias of the power HEMT gate is reduced or grounded, a high signal from the control terminal will no longer generate a high signal at the power HEMT gate.

[0228] Figure 27 Another example of how an auxiliary gate interface module can provide protection during short-circuit conditions is shown. In this example, voltage limiter circuit 206 includes an additional resistor R8 added in series with voltage divider R6 / R7. An additional HEMT 205 is connected in parallel with resistor R6 such that when SCD / SCDC is "high" (short-circuit condition), the resistance ratio in the voltage divider changes, thus shorting resistor R6. The changed resistance ratio helps to alter the regulated voltage applied to the gate of the auxiliary GaN HEMT. In short-circuit conditions, reducing the regulated voltage on the power HEMT gate is beneficial because it reduces the power HEMT saturation current and allows the power HEMT to withstand short-circuit conditions for a longer period until failure occurs.

[0229] Figure 28 Another exemplary implementation of how the auxiliary gate interface module provides protection during short-circuit conditions is shown. Here, a voltage divider is connected between the gate of the power HEMT 101 and the low-voltage side of the power IC. Therefore, when the SCD / SCDC signal is "high," the resistance ratio of the voltage divider changes, thereby altering the regulated gate voltage of the auxiliary GaN HEMT.

[0230] Figure 29 This illustrates another exemplary implementation of how an auxiliary gate interface module can provide protection during short-circuit conditions. This example is similar to... Figure 26 The example operates in the manner described, but includes additional transistor 207 and resistor R9. These components are included to limit the voltage across current source 202 when transistor 205 is turned on in the event of a short-circuit event.

[0231] Figure 30 This illustrates another exemplary implementation of how an auxiliary gate interface module can provide protection during short-circuit conditions. This example is similar to... Figure 29The example operates in the manner described herein, but includes additional circuitry 208. Generally, there is a trade-off between bandwidth and power consumption in the example of the auxiliary gate interface presented herein. In this example, by including circuitry 208, the power dissipation of the auxiliary gate interface can be higher during normal operation and lower during a short-circuit event.

[0232] Figure 31 Another aspect of this disclosure is illustrated. Short-circuit detection and protection can be performed through a series of detection and protection stages rather than a single short-circuit detection step. Multiple short-circuit detection circuits can be connected between the drain and source of the power HEMT, each with a different voltage reference for the Vds detection module and different blanking times that generate a series of SCD signals. These signals can act on an auxiliary gate interface to regulate the gate voltage of the power HEMT, or act on a Miller clamp to pull down the gate of the power HEMT. The advantage of having multiple signals is that the signal from the detection module with the lower reference voltage may regulate the gate voltage to a lesser extent than the signal from the detection module with the higher reference voltage. Since the blanking times of all SCD modules are different, these signals will not go "high" simultaneously. Therefore, this provides a mechanism for gradually regulating the operation of the power device and avoids the device suddenly shutting down completely at the onset of a short-circuit event. If the short-circuit event lasts for a long time and exceeds a certain limit, the gate of the power HEMT can be fully pulled down, thereby completely shutting down the power HEMT, rather than simply regulating the saturation current of the power HEMT during the short-circuit condition. SCD modules 300_1 to 300_n can be implemented based on any of the embodiments in the previous embodiments.

[0233] Figure 32 It shows Figure 31 An exemplary implementation of the explained short-circuit detection and protection mechanism. This implementation follows... Figure 8 The detection mechanism is illustrated. Here, the sensing HEMT may be equipped with a series of RC networks, each with an output signal, which can be compared with a corresponding reference value to output a series of short-circuit detection signals. As an example, Figure 32Four RC networks generating SCD signals 1 through 4 are shown. However, it should be understood that the number of RC networks may be fewer or more. Based on the values ​​of the RC networks and the reference voltage level, the SCD signals will transition to a "high" value as the short-circuit condition may worsen and increase the drain-to-source voltage of the power HEMT. These signals, or their corresponding regulated versions (SCDC), can act on different levels of a voltage limiter (in this example, the voltage limiter comprises several diodes connected in series) to gradually regulate the gate voltage of the power HEMT, thereby reducing the gate voltage by a larger value as each SCD signal becomes "high". Thus, the gate voltage of the power HEMT will again be gradually controlled to reduce the operation of the power HEMT, rather than completely shutting it down. For simplicity, the application of the SCD signals to the Miller clamp driver is not shown in the schematic. When it is necessary to turn on the Miller clamp to pull the gate of the power HEMT down to a lower voltage level of T1, one or more SCD / SCDC signals can be applied to the Miller clamp driver based on the SCD level.

[0234] Figure 33 Another example of stepwise adjustment of a power HEMT in a short-circuit condition is shown. In this example, multiple sensing HEMTs are connected in parallel instead of combining resistors with sensing HEMTs in series, and an RC network is connected to the sensing load of each sensing HEMT. Three sensing HEMTs are shown as an example; however, it should be understood that fewer or more sensing HEMTs can be connected in the same manner. The dashed lines connecting the RC network to the SCD signals are shown as placeholders for the corresponding comparators, which are not shown for simplicity. In this configuration, the first few SCD signals (such as SCD5 and SCD6) will provide an initial indication of the presence of a short circuit based on the corresponding reference values, and therefore, these signals, or their regulated versions, can be applied to the voltage limiter of the auxiliary HEMT to regulate the operation of the power HEMT during the initial phase. If, even after regulation, the signal is still “high” compared to a higher reference value (e.g., SCD7) to indicate a short circuit, said signal can be provided as an input to a Miller clamp driver to completely shut down the power HEMT.

[0235] Figure 34 and Figure 35 Two examples of the comparators (302, 312) referenced in the previous embodiments are shown. The comparator circuitry receives a voltage measured in a corresponding circuit (Vds detection module or blanking block or any other circuitry) as an input signal and includes a fixed reference voltage as another input. The reference voltage can be generated on-chip or applied externally. However, it should be understood that these circuits 302a and 302b are provided merely as exemplary configurations, and other circuit designs can be utilized as alternatives to or supplements to these circuits.

[0236] Figure 34 The comparator circuit 302a shown includes an initial inverting differential amplifier stage 302a1, a transconductance amplifier stage 302a2, and a current subtractor stage 302a3. The differential amplifier 302a1 can be implemented using a differential pair (also called a long-tailed pair) comprising two enhancement-mode transistors, two resistors, and a current source. The differential amplifier typically performs two main functions in this circuit. It amplifies the differential input signal to the comparator and sets the bias point for the next stage, thus biasing the transconductance amplifier stage 302a2 in the high-gain region. The transconductance amplifier 302a2 receives the differential input voltage from the differential amplifier 302a1 and provides a differential current output (Ix, Iy) to the current subtractor stage 302a3. The transconductance amplifier consists of a differential pair with two enhancement-mode transistors and a current source. The current subtractor stage can be implemented using a current mirror block, such that Vout is high when Ix-Iy is negative and low when Ix-Iy is positive.

[0237] The transconductance amplifier stage and current subtractor stage enable a rail-to-rail comparator output. In this example, rail-to-rail refers to Vrail. DD For high output, V SS Low output.

[0238] Figure 35 Another example of a comparator circuit (302, 312) is shown. Comparator circuit 302b includes three stages—a differential voltage-to-current conversion stage, a current comparator stage, and a current-to-voltage converter stage. The differential voltage-to-current stage can be implemented using a pair of differential enhancement-mode transistors and a current source. This stage receives a measured voltage from a corresponding circuit as a first input and a predetermined voltage reference as a second input, converting them into corresponding current signals. The current comparator stage generates a differential current signal equivalent to the difference between the two inputs. The final stage converts this differential current to produce a voltage output. This example also allows for a rail-to-rail comparator output. In this example, rail-to-rail refers to V... DD For high output, V SS Low output.

[0239] Figure 36A schematic example of a power integrated circuit connected to a gate driver is shown. The gate driver is configured to provide a gate drive signal (control signal) to the control terminal of the power IC. Both the gate driver and the power IC can be powered by a voltage source VDD. The gate driver in this example is equipped with a DESAT pin that provides desaturation protection. This functionality is typically found in gate drivers used in automotive inverter applications. When the voltage on the DESAT pin exceeds a threshold voltage, the driver initiates a safe shutdown procedure to protect the power semiconductor switch. A short-circuit detection signal SCD can be connected to the DESAT input of the gate driver. When a short-circuit event occurs, the SCD signal goes "high," simultaneously acting on the auxiliary gate interface circuitry and / or the Miller clamp driver to internally protect the power HEMT, as shown in the embodiment above. Simultaneously, this signal also triggers fault detection on the DESAT pin so that the driver initiates a safe shutdown. The blanking time circuitry of the short-circuit detection module helps prevent accidental tripping of the DESAT protection.

[0240] Figure 37 Another example of the connection between the power integrated circuit and the gate driver is shown. In this implementation, the SCD signal is regulated by a combination of signal conditioning modules, a portion of the 500 shown in the previous embodiment. The regulated signal SCDC is applied to the driver's DESAT pin and the auxiliary gate interface (200) and / or the Miller clamp driver (400).

[0241] Figure 38 An additional example is shown of how a short-circuit event in a power IC can be reported to a gate driver with DESAT functionality. In this example, the power IC may have an open-drain output when a short-circuit event occurs. The open-drain pin can be implemented using a pull-down transistor as shown, which is turned on when no short-circuit event occurs and turned off when a short-circuit event occurs. This open-drain pin can be connected to the DESAT pin of the gate driver. The gate driver may include an internal pull-up component, such as... Figure 38 The current source is shown. When the power IC's output is open-drain, the gate driver can pull up this node. A capacitor can be connected to this node to set the time required to pull the node up to a given voltage, which may be necessary to avoid oscillations and false triggering of the gate driver protection function. When the voltage on the DESAT pin exceeds the gate driver's internal reference value, the gate driver may provide a low OUT signal to shut down the power IC and protect the power HEMT. It should be noted that this protection loop implemented via the gate driver may be too slow to protect the power HEMT, thus requiring the on-chip protection circuitry described in the previous examples.

[0242] Figure 39The timing diagram of the pulse sequence in the case of a Type 1 short-circuit event is shown. This activates the blanking time circuit, and after a predefined blanking time, the output of the blanking time circuit goes "high". The blanking time signal going "high" enables the VDS detector (e.g., Figure 7 As shown), if Vds on the device exceeds a set reference value, the VDS detector goes "high". Even if the external gate driver output may be "high", the "high" SCD signal (or a regulated version of the SCD signal) pulls down the gate of the power HEMT through the auxiliary gate interface circuitry and / or Miller clamp. This protects the power HEMT device from high currents caused by short-circuit events and prevents device failure. Figure 19 As shown, the SCD signal can be processed through a series of signal conditioning modules and latching circuits. Latching circuit 502 can hold the SCD signal "high" based on time dependence and / or hold the SCD signal "high" until a signal dependence condition is met. This conditioned signal (or simply the SCD signal) can be reported off-chip (e.g., as an input to the DESAT pin of the gate driver) to initiate a safe shutdown procedure for the gate driver / controller in the system, such as... Figure 37 and Figure 36 As shown.

[0243] In reality, there may be a delay between short-circuit detection and the power HEMT shutdown. This should be minimized as much as possible.

[0244] Similarly, Figure 39 There may also be delays between the other signals shown. As mentioned above, these delays can be minimized through monolithic integration of the presented circuit modules, enabling faster short-circuit detection and protection.

[0245] Figure 40 Another aspect of this disclosure is illustrated, wherein the power integrated circuit can be enabled for short-circuit detection in a parallel connection. During a parallel implementation, the power ICs can communicate with each other when a short-circuit condition is detected by any of the devices. The power ICs are equipped with short-circuit input / output pins (SCIO) connected to VDD and "high" during normal operation. All power ICs in a parallel connection connect their SCIO pins to each other. Furthermore, the power ICs may include a parallel mode detection module (600) that facilitates action on corresponding ICs based on the parallel connection.

[0246] As an example, a parallel-mode detector module may include an e-mode HEMT device whose drain is connected to an SCIO pin, such as... Figure 41 As shown. During normal operation, the SCIO pin is at the same voltage as VDD, and the SCIO signal is "high".

[0247] In the event of a short circuit, the SCD output of the short-circuit detection module 300 will be "high," as shown in the previous embodiment. The SCD signal can be adjusted in the signal conditioning module or applied directly to the parallel mode detector module 600. The "high" signal on the gate of HEMT 601 will turn on the HEMT and pull the SCIO pin down to ground. The SCIO signal can be further regulated to act on the corresponding auxiliary gate interface and / or Miller clamp driver of the power IC, or it can be applied directly to the auxiliary gate interface and / or Miller clamp driver depending on whether these circuits require an inverted signal. Additional conditioning circuitry may be included in the parallel mode detector module 600 or the auxiliary gate interface 200 / Miller clamp driver 400. This SCIO signal will be passed to other parallel power ICs via the SCIO connection, such as... Figure 42 As shown.

[0248] Figure 42 An example of a parallel implementation is shown, illustrating two power ICs connected in parallel. As shown above, if, for example, a short circuit is detected, power IC 1 pulls its SCIO pin down to ground. This information is relayed via the SCIO pin to the parallel mode detection module of power IC 2, which also goes "low" on IC 2's SCIO signal. This, in turn, affects the auxiliary gate interface and / or Miller clamp driver of power IC 2, shutting down the power HEMTs. In this way, all power HEMTs of the parallel-connected ICs can be simultaneously shut down via the SCIO connection. The SCIO pin can also be used to relay short-circuit event information to an external driver / controller for appropriate action.

[0249] Figure 43Another example of a power integrated circuit is shown, in which the power HEMT switch is replaced by a combination switch consisting of a high-voltage transistor (40) connected in parallel with the high-voltage power HEMT device (101). The high-voltage transistor device (40) may comprise materials or material systems other than group III nitride materials. In some examples, the high-voltage transistor device is a silicon transistor and / or a silicon carbide transistor, such as, but not limited to, Si IGBTs, Si MOSFETs, SiC MOSFETs, or superjunction MOSFETs. Generally, the listed devices have relatively long short-circuit withstand times (also known as endurance times) ranging from a few microseconds, while GaN HEMTs can only withstand a few hundred nanoseconds (especially when the rail voltage-DC link is higher and closer to its rated voltage). A short-circuit detection circuit is connected to the power HEMT device and outputs a HIGH SCD signal in the event of a short circuit, as shown in the previous embodiment. This SCD signal is input to an auxiliary gate interface and / or a Miller clamp driver to turn off or regulate the gate voltage of the power HEMT until the external driver turns off the control terminal. Reducing the bias at the gate of a power HEMT may help extend its withstand time during short-circuit events, as reducing the gate bias can lead to saturation current in the power HEMT during short-circuit events. Therefore, the short-circuit detection and protection circuitry of the HEMT device can extend the overall short-circuit withstand time of the combination switch. The SCD signal can be regulated by a series of signal conditioning modules (500) and then provided as input to the auxiliary gate interface and Miller clamp driver, such as... Figure 44 As shown.

[0250] Figure 45An alternative example of an implementation of short-circuit detection and protection in a combined switch comprising a high-voltage GaN HEMT device (e.g., Si IGBT, Si MOSFET, SiC MOSFET, superjunction MOSFET, etc.) connected in parallel with a high-voltage device made of another material is shown. This implementation also provides internal protection for the IGBT switch (40). An auxiliary depletion-mode HEMT (d-HEMT) (201b) is connected between the control terminal and the gate of the high-voltage IGBT (40). The gate of the auxiliary d-HEMT (201b) is connected to a voltage limiter (203b) to control the voltage applied to the gate of the auxiliary d-HEMT switch. Furthermore, similar to the Miller clamp (102a) connected between the gate and source of the power HEMT (101), the Miller clamp (102b) is connected between the gate and emitter of the IGBT (40). However, the Miller clamp 102b can be biased to voltages up to 15 V–20 V as needed by the IGBT. In this circuit, if the short-circuit detection circuit 300 detects a short-circuit event and changes the SCD signal to "high", the SCD / SCDC signal will act on both Miller clamps 102a and 102b and voltage limiters 203a and 203b to regulate or pull down the gate voltage of both the power HEMT and IGBT, thereby providing on-chip protection against short-circuit events until an external driver is available to shut down the control terminal.

[0251] Figure 46 Another aspect of this disclosure is illustrated, wherein a short-circuit detection circuit, rather than a power HEMT, can be integrated with a cascode switch. The cascode device includes a MOSFET (106) connected in series with a depletion-mode GaN HEMT (105). The gate of the depletion-mode GaN HEMT (105) is connected to the source of the MOSFET (106). The MOSFET (106) is preferably an n-channel MOSFET in a vertical or quasi-vertical configuration, and the blocking voltage of the MOSFET should be much smaller than the blocking voltage of the depletion-mode HEMT. For example, for a 650 V HEMT, the blocking voltage of the MOSFET could be 40 V. The short-circuit detection circuit monitors the voltage at the high-voltage and low-voltage ends of the cascode switch to identify short-circuit events, as shown in previous embodiments. The SCD signal can be adjusted by a combination of signal conditioning modules (500), or it can be directly applied to a Miller clamp driver to pull down the gate of the cascode switch to turn it off. As an alternative to or supplement to the Miller clamp driver, the SCD or SCDC signal can be applied to the auxiliary gate interface to protect the cascode switch from short-circuit conditions (although not shown in the figure for simplicity).

[0252] Figure 47Another aspect of the previous embodiment is shown, in which a combined switch is provided comprising a cascode device in parallel with a high-voltage device (40), wherein the high-voltage device may be an IGBT, a silicon carbide MOSFET, or a superjunction. The cascode device comprises a MOSFET (106) connected in series with a depletion-mode GaN HEMT (105). The gate of the depletion-mode GaN HEMT (105) is connected to the source of the MOSFET (106). The MOSFET (106) is preferably an n-channel MOSFET in a vertical or quasi-vertical configuration, and the blocking voltage of the MOSFET should be much smaller than the blocking voltage of the depletion-mode HEMT. For example, for a 650 V HEMT, the blocking voltage of the MOSFET may be 40 V. The gate of the MOSFET (106) may be shorted to the gate of the high-voltage switch (40) (e.g., an IGBT) and further connected to the control terminal of the combined switch. Alternatively, either gate may be connected to the control terminal via a slew rate structure (which may be a simple resistor or a resistor with a diode).

[0253] A short-circuit detection circuit monitors the voltages at the high and low ends of the cascode switch to identify short-circuit events, as shown in previous embodiments. The SCD signal can be adjusted via a combination of signal conditioning modules (500), or it can be directly applied to a Miller clamp driver to pull down the gate of the cascode switch to turn it off. As an alternative to or supplement to the Miller clamp driver, the SCD or SCDC signal can be applied to an auxiliary gate interface to protect the power HEMT from short-circuit conditions (although not shown in the figure for simplicity). The SCD / SCDC signal can also be transmitted to an external driver, as shown in previous embodiments, to initiate a safe shutdown of the device, which will protect the parallel cascode switch and high-voltage devices.

[0254] Figure 48 It shows Figure 46 The example implementation of the short-circuit detection circuit shown is illustrated. This can be implemented in... Figure 47 The example shown implements this. The short-circuit detection circuit 300c in this example includes an enhanced-mode HEMT 110 acting as a sensing HEMT, an RC network (R1, C1), and a comparator 302. The e-HEMT 110 is also equipped with an auxiliary gate interface circuit 200i to keep the drive voltage at the gate of the e-HEMT within a specific range (e.g., 0 V to 7 V), while the drive voltage at the control terminal can be 0 V to 20 V. The cascode switch may also have a parallel high-voltage Si switch, such as... Figure 47 As shown.

[0255] This circuit 300c is similar to Figure 8The short-circuit detection circuit operates as shown. An SCD or SCDC signal can be applied to the auxiliary gate interface (though not shown in the figure for simplicity) and / or the Miller clamp driver to protect the cascode switch from short-circuit conditions. The SCD / SCDC signal will also be sent to an external driver, as shown in the previous embodiment, to initiate a safe shutdown of the device, which will protect the cascode switch and parallel high-voltage devices.

[0256] Figure 49 An alternative example of an implementation of a sensing transistor with short-circuit detection circuitry for a cascode switch is shown. The sensing transistor consists of a sensing HEMT (107) in a GaN chip and a sensing FET (108) in a silicon chip. A capacitor connected in parallel with the sensing FET 108 provides the function of a blanking circuit, and the charging and discharging rate of the capacitor determines the timing of the SCD signal. The cascode switch may also have a high-voltage Si switch connected in parallel, such as... Figure 47 As shown.

[0257] exist Figure 50 In another example shown, the power IC may be expected to include at least one additional transistor 102_2, which is connected in the same configuration as the Miller-clamped HEMT described in the previous embodiment. The additional transistor may also be described as a Miller-clamped HEMT, or it may be described as a pull-down HEMT. It may be necessary to connect the two transistors in the same manner, as they can be optimized for different functions. The Miller-clamped transistor (102_1) in the Miller-clamped transistor configuration may be optimized to achieve fast shutdown of the power HEMT and / or prevent false turn-on of the power HEMT during normal operation of the power electronics circuit. In this case, the Miller-clamped transistor may preferably have a low on-state resistance, e.g., < 10 Ω. The second transistor (102_2) may be optimized to shut down the power HEMT to protect the device upon detection of a short circuit, as described in the previous example. In this case, the transistor may preferably have a higher on-state resistance (e.g., > 10 Ω) than the Miller-clamped transistor operating during normal operation of the device. This can be ideal in order to slow down the power HEMT's shutdown and avoid any overvoltage on the power HEMT (e.g., between the drain and source terminals of the power HEMT) due to parasitic effects in the circuit (e.g., the L*dI / dt voltage generated on the parasitic inductance in the power loop).

[0258] exist Figure 51In one example shown, an additional circuit module (700) may be included, optimized to protect the device in the event of a Type 2 short circuit. A Type 2 short circuit can increase the risk of device failure because a rapid positive dv / dt occurs between the drain and source terminals of the power HEMT during a Type 2 short circuit event. This dv / dt can pull up the voltage on the power HEMT gate via a Miller capacitance (Cgd). This shortens the maximum time the power HEMT can withstand a short circuit event because a higher gate voltage leads to a higher saturation current in the power HEMT, resulting in increased power dissipation. Furthermore, increasing the gate voltage itself can be problematic for power HEMTs. For some technologies, such as p-GaN gates, the acceptable gate bias window is very narrow, and exceeding a given voltage bias (e.g., 7.5 V) can cause gate damage.

[0259] Type 2 protection circuit blocks can be designed to detect fast dv / dt events to trigger device protection, unlike previous examples that relied on blanking time and Vds exceeding a given value. Figure 51 This type 2 detection circuit is shown. Figure 50 The illustration shows an implementation of a protection mechanism based on dual Miller clamping. It is understood that this is merely an example, and this detection module 700 can be implemented using any of the protection mechanisms shown in the previous examples.

[0260] Figure 52 An exemplary dv / dt event detection circuit that will be part of a Type 2 short-circuit detection module 700 is shown. The circuit is connected between the drain and source of a power HEMT, and its output can be connected to a Miller clamp to protect the power HEMT in the event of a dv / dt event. The circuit can be connected to a similar... Figure 51 The additional clamping transistor may be connected to the standard Miller clamp shown in the previous embodiment, or may be connected to another additional clamping transistor disposed in module 700.

[0261] Figure 53Other examples of semiconductor switches (or "power integrated circuits, ICs") according to this disclosure are shown. The semiconductor switch includes a high-voltage III-nitride power HEMT 101, a ("first" or "main") interface circuit 1000 having at least one connection to a control terminal and at least one connection to the gate of the high-voltage HEMT, a sensing transistor ("sensing HEMT") 104, a sensing (or "second") interface circuit 2000 having at least one connection to a control terminal and at least one connection to the gate of the sensing HEMT, and a signal conditioning circuit 300 having at least one connection to the source of the sensing HEMT and at least one connection to the source of the power HEMT. The sensing interface circuit has at least one connection to the source of the sensing HEMT (node ​​A). The output of the signal conditioning circuit 300 is connected to the main interface circuit.

[0262] According to an example of this disclosure, the III-nitride power HEMT 101 is a high-voltage lateral GaN HEMT. A main interface circuit 1000 is placed before the gate of the high-voltage lateral GaN HEMT to regulate the drive voltage at the control terminal to suit and allow the GaN HEMT to operate. This interface is preferably monolithically integrated with the power HEMT 101 to provide lower parasitic effects, ease of fabrication, and faster response time. Alternatively, this interface can be part of a separate chip (e.g., a silicon companion chip or driver chip). For example, the drive voltage at the control terminal can range from 0V to 20V, while the drive voltage directly seen by the gate of the lateral high-voltage GaN HEMT remains between 0V and 7V. Similarly, a sensing interface circuit 2000 is placed before the sensing HEMT to regulate the drive voltage at the control terminal to suit and allow the sensing HEMT to operate. The primary purpose of the sensing interface circuit is to drive the sensing HEMT independently of the main HEMT. Each interface circuit may also include other clamping circuitry, sensing and protection features, pull-down devices to ensure fast and safe shutdown, improve immunity to dV / dt, and absorb any transient voltage spikes on the gate.

[0263] The sensing HEMT 104 and power HEMT 101 may be structurally identical, but the effective area of ​​the main power HEMT 101 may be significantly larger than that of the sensing HEMT 104 (e.g., increased by 10, 100, or 1000 times). The power HEMT 101 and sensing HEMT 104 may have connected drains, but separate source and gate terminals. The gate of the sensing HEMT 104 is connected to the control terminal via sensing interface circuitry 2000. In some examples, the drains of the power HEMT 101 and sensing HEMT 104 may not be directly connected. It is important to note that in some examples, the power HEMT 101 and sensing HEMT 104 may be connected only after testing (e.g., short-circuit detection testing), such as after the manufacturing process. For example, this connection may be made post-manufacturing, or even at the packaging or PCB level.

[0264] The sensing HEMT is used to sense the turn-on voltage of the power HEMT. Ideally, its voltage drop should be zero, so the voltage at the source node A of the sensing HEMT is the same as the drain voltage of the power HEMT. When the control signal is high (indicating that the power HEMT is on), the sensing HEMT is also on. An increase in the drain voltage of the power HEMT causes an increase in the drain voltage of the sensing HEMT, which is reflected at node A (this signal can be called the "SCD" signal or "sensing voltage signal"). This voltage signal can be processed by the signal conditioning circuit 300 and provided as an input signal (SCDC) to the main interface circuit, where the SCDC signal can be called the "sensing voltage signal". Alternatively, the signal conditioning circuit can be omitted, and the SCD signal can be directly fed to the main interface circuit. When the voltage at node A exceeds a critical value (or "threshold"), the sensing voltage signal forces the main interface circuit to begin limiting the potential at the gate of the power HEMT to protect it from overcurrent or short-circuit events. In addition, when the sensing voltage signal exceeds a certain threshold, the main interface circuit may also completely turn off the power HEMT. Since the gate of the sensing HEMT is not connected to the gate of the power HEMT, the sensing voltage signal will not act on the sensing HEMT, and the sensing HEMT will continue to operate even if the operation of the power HEMT is limited.

[0265] In some embodiments, the sensing interface circuitry can enable independent switching of the sensing HEMT (e.g., switching timing independent of the power HEMT switching timing) to avoid a reduction in the power HEMT's turn-on speed. For example, the sensing HEMT can turn on after a certain delay, which provides a blanking time. This also allows the sensing HEMT to be fully turned on even if VDS rises to 2V or higher. Independent gate voltages for the sensing HEMT and the power HEMT allow the gate of the power HEMT to be pulled down while maintaining full sensing capability. In some cases, the independent control of the sensing HEMT described herein can enable the timing circuitry to be configured to provide selective short-circuit detection at different times, thereby providing protection against Type 1 and Type 2 short-circuit events described above.

[0266] For example, these additional circuit modules can be monolithically integrated with a power HEMT device to form a GaN power integrated circuit (IC).

[0267] like Figure 54 As shown, the first interface circuit 1000 may include a Miller clamp transistor 102 and / or an auxiliary gate interface 200. The Miller clamp transistor 102 may be driven by a Miller clamp driver 400 (MCD). For simplicity, the connection of the MCD is not shown in the figure. The signal conditioning module may include a resistor divider, which acts as a level shifter to generate an SCD signal from the midpoint of resistors R0 and R1. Alternative implementations of the resistor divider may employ nonlinear devices, such as HEMTs, or use clamping diodes (or threshold multipliers) to limit the voltage.

[0268] Examples of modulating the SCD signal include: adding a parallel combination of a capacitor and a sensing load resistor R to stabilize the voltage, adding a resistor-capacitor network to a level shifter, adding a resistor divider to a level shifter, or adding a resistor-capacitor network in combination with a pull-down HEMT to a level shifter.

[0269] The Miller clamp transistor 102 can be connected between the gate and source of the power HEMT as a pull-down device to ensure fast and safe turn-off, improve immunity to dV / dt, and avoid using a negative gate voltage to turn off the power HEMT. Another example is using the SCD signal as the gate input of the Miller clamp transistor (or the gate driver of the Miller clamp transistor - MCD). When the SCD signal exceeds a certain limit, indicating that the power HEMT is short-circuited, the Miller clamp transistor will reduce the voltage bias at the gate of the power HEMT or turn off the power HEMT.

[0270] Figure 55Another example is shown where the auxiliary gate interface 200 may include short-circuit protection. The SCD signal can be used as an input to the auxiliary gate interface module, allowing the module to either shut down the power HEMT or regulate the power HEMT gate voltage to a lower voltage. Reducing the bias voltage at the power HEMT gate may help extend the power HEMT's withstand time in a short-circuit event, as a lower gate bias reduces the power HEMT's saturation current under short-circuit conditions.

[0271] Additionally, in any of the examples described herein that include Miller clamp transistor 102, a short-circuit detection signal may be used as an input to the auxiliary gate interface module 200 and the Miller clamp driver 400 (or the Miller clamp transistor 102 itself).

[0272] Figure 56 Another example of a signal conditioning circuit 300 is shown. The voltage at the source of the sensed HEMT, ideally the same as the drain voltage of the power HEMT, is applied across a resistor divider (R0, R1) to generate an SCD signal. This signal is further passed through a level shifter to generate a conditioned (level-shifted) version of the SCD signal—SCDC. As previously described, this signal can be used as an input to the Miller clamp driver / transistor and / or the auxiliary gate interface module 200.

[0273] Figure 57 The I-V curve of the power HEMT in the on-state and the curve of the sense voltage VDS relative to the gate voltage of the power HEMT are shown. Figure 57 In (a), the dashed line represents the original output characteristics, while the solid line shows the IV curve when the power HEMT is equipped with the proposed sensing and protection features. The presence of the sensing and protection circuitry results in an active adjustment of the saturation current shape. In the linear region of the on-state characteristics, the current is initially high but decreases after reaching a certain threshold. Figure 57 (b) shows the gate voltage associated with the power HEMT, which decreases once a certain limit is reached at VDS.

[0274] Figure 58 An example of a sensing interface circuit 2000 is shown. In this example, the sensing interface circuit 2000 includes an additional HEMT, which serves as a pull-down transistor 105 for sensing HEMT 104, and an auxiliary gate interface 200S. The sensing pull-down transistor 105 can be connected between the gate and source of the sensing HEMT as a pull-down device to ensure fast and safe shutdown, improve immunity to dV / dt, and avoid using a negative gate voltage to shut down the sensing HEMT.

[0275] The sensing pull-down transistor 105 is likely a "low-voltage" HEMT. The sensing pull-down transistor is likely a III-nitride transistor.

[0276] Alternatively, the sensing pull-down transistor 105 of the sensing HEMT can be driven by a Miller clamp driver of the main interface circuit or an additional Miller clamp driver integrated into the main interface circuit. This reduces the complexity and number of components in the sensing interface circuit.

[0277] In another example, such as Figure 59 As shown, the semiconductor switch may require at least one additional transistor 103 (also referred to herein as a "second pull-down device") connected in the same configuration as the Miller-clamped HEMT 102 in the aforementioned example. This additional transistor may also be described as a Miller-clamped HEMT or a pull-down HEMT. The two transistors are connected in the same manner because they are optimized for different functions. The additional transistor 103 may be optimized for quickly shutting down the power HEMT and / or preventing the power HEMT from being falsely turned on during normal operation of the semiconductor switch. In this case, it may be desirable for the additional transistor 103 to have a low on-resistance, e.g., less than 10 Ω. Another transistor 102 (e.g., the Miller-clamped transistor described above) may be optimized to shut down or reduce the voltage bias of the power HEMT gate when the device is short-circuited, to protect the device as described in the aforementioned example. In this case, it may be desirable for transistor 102 to have a higher on-resistance (e.g., greater than 10 Ω) compared to transistor 103 designed for normal operation. This may be to slow down the turn-off speed of the power HEMT and avoid overvoltages in the power HEMT (e.g., between its drain and source terminals) caused by parasitic effects in the circuit (e.g., due to the L*dI / dt voltage generated on the parasitic inductance of the power loop).

[0278] Figure 60 An example configuration of the auxiliary gate interface circuit 200S is shown, which is part of the semiconductor switch described in the previous embodiments. The integrated auxiliary gate interface module 200S includes an auxiliary GaN HEMT 201, which is preferably a low-voltage device, wherein the gate of the sensing HEMT is connected to the source of the integrated auxiliary GaN HEMT, and the drain of the auxiliary GaN HEMT is connected to a control terminal. The auxiliary GaN HEMT is configured to adjust the drive voltage of the control terminal to a voltage suitable for and allowing the sensing HEMT to use. The auxiliary gate interface 200 of the power HEMT 101 may also have a similar implementation to the auxiliary gate interface circuit 200S described herein.

[0279] An integrated voltage limiting module 202S is connected between the gate of the auxiliary HEMT and the source of the sensing HEMT. The voltage drop across the auxiliary gate interface module 200S is non-linear as the control voltage signal increases linearly. Low gate leakage current of the sensing HEMT can be achieved by limiting the potential at the gate of the sensing HEMT. This is accomplished by allowing a voltage drop across the integrated auxiliary gate interface module. The limitation of the sensing HEMT gate potential is defined by appropriately designing the voltage limiting circuit module so that the gate of the auxiliary GaN HEMT is pulled down when the control gate signal of the semiconductor switch exceeds a certain level. Therefore, the gate voltage operating window of the semiconductor switch (i.e., the voltage operating window applied to the control terminal) is increased compared to a conventional GaN HEMT. The voltage limiter of the sensing HEMT can be designed to be slower so that the pull-down mechanism does not activate during switching.

[0280] In addition to the voltage limiter, additional circuitry can be provided, such as a current control circuit connected between the drain and gate terminals of the auxiliary GaN HEMT 201. The current control module has a connection to a control terminal. The current control module may be or include resistive elements. Alternatively, the current control circuit may be or include a current source, such as... Figure 61 As shown.

[0281] Alternatively, or as an alternative, a current source can be connected in series with a threshold multiplier to drive the gate of the sensing HEMT, such as... Figure 62 As shown in (a), the threshold multiplier configuration includes a voltage divider (R6 and R7) and a pull-down enhancement-type HEMT 204, with the midpoint of the voltage divider connected to the gate of the pull-down HEMT 204. In this embodiment, the top of the voltage divider is connected to the drain of the pull-down enhancement-type HEMT 204 and the gate of the auxiliary GaN HEMT 201. The gate potential of the HEMT 204 is controllable, used to set the voltage drop across the pull-down HEMT 204, which can be controlled by selecting the resistors in the voltage divider. This limits the gate voltage of the auxiliary GaN HEMT 201 and the voltage drop across the auxiliary gate module. This feature protects the gate of the sensing HEMT from overvoltage events. Figure 62 (b) shows another configuration example of the auxiliary gate interface circuit 200S. In this case, the auxiliary GaN HEMT 201 can be omitted, and the gate of the power HEMT 101 can be directly connected to the node where the current source is connected to the threshold multiplier. This is a simplified solution for driving the gate of the sensing HEMT. Since the sensing HEMT does not require similar driving capability as the power HEMT, Figure 62 The simplified solution in (b) should still achieve the functionality of a sensing HEMT. However, this is only one configuration example described, and other circuit designs can be used instead or in conjunction with a current source. For simplicity, Figure 62 The current control module is not shown.

[0282] Since auxiliary GaN HEMTs are preferably low-voltage devices, their source and drain terminals can be interchanged because they are typically manufactured in a symmetrical (or similar) manner. Low-voltage devices generally refer to those with a rated breakdown voltage below 20V and limited current capability (below 100 mA). However, it should be understood that the auxiliary gate can also be a high-power or high-voltage device, although this may increase cost and complexity.

[0283] The auxiliary gate interface 200 of the power HEMT 101 can also have a similar implementation to the auxiliary gate interface circuit 200S described herein. Figure 63 An implementation example is shown.

[0284] Figure 63 An implementation example of the auxiliary gate interface module 200 is shown when it operates based on a short-circuit detection signal (SCD), i.e., a sensed voltage signal. The auxiliary gate interface module 200 includes an additional HEMT 205 connected in parallel with a voltage limiter. The gate of this additional HEMT 205 is connected to the short-circuit detection signal SCD or a regulated version of SCD (SCDC). When a short circuit is detected (i.e., the SCD / SCDC signal exceeds a threshold), HEMT 205 turns on, pulling the gate of the auxiliary GaN HEMT 201_1 to ground. This turns off the auxiliary GaN HEMT, effectively electrically isolating the power HEMT gate from the control terminal. In this situation, if the bias voltage of the power HEMT gate is reduced or grounded, a high-level signal from the control terminal will no longer result in a high-level signal on the power HEMT gate.

[0285] Figure 64 Another implementation example of the proposed sensing and protection mechanism in the semiconductor switch is shown. The Miller clamp 105 sensing the HEMT gate can be clamped to the main power supply, i.e., the low-voltage terminal T1 (instead of sensing the HEMT source node A). The signal conditioning circuitry may include a resistive element R1 (a capacitor can be added separately in parallel with the resistor) used in conjunction with a level shifter. A clamping transistor 106 can be provided in parallel with R1 to protect the sensing node A. The gates of the Miller-clamped HEMTs 103, 105, and 106 can be connected to a main Miller clamp driver, which can be integrated as part of an auxiliary gate interface circuit 200.

[0286] Figure 65Another implementation example of a semiconductor switch sensing HEMT-side sensing mechanism is shown. The sensing interface circuit includes a voltage divider consisting of resistors R2 and R3 connected to the drain of the power HEMT. An additional high-voltage HEMT 107 (also referred to herein as "the other transistor") is integrated, with its drain connected to the other end of the voltage divider. The drain of the sensing HEMT 104 is connected to the midpoint of the voltage divider consisting of R2 and R3. Thus, the source terminal of the sensing HEMT receives a portion of the drain voltage of the power HEMT through the voltage divider, generating an SCD signal to drive the gate of pull-down transistor 102 (or its driver and / or auxiliary gate interface) directly or via a level shifter. In this embodiment, the voltage VS is generated through the voltage divider on the drain side of the sensing HEMT, rather than through the source side of the source HEMT. This requires two high-voltage HEMTs (107 and 104) connected to the voltage divider to ensure that no high voltage is applied across the resistors when the device is in blocking mode (however, a high voltage may exist between the resistors and the substrate).

[0287] The sensing HEMT 104 and the additional HEMT 107 can be driven by the same auxiliary gate interface circuit, or they can have independent connections.

[0288] One advantage of this method is that the sensing HEMT 104 is connected to ground, so in the event of an overcurrent, the drain and source voltages of the sensing HEMT 104 are at a lower potential relative to the second master terminal T2. For the sensing HEMT 104 to be fully turned on and to achieve sensing, the gate voltage of the sensing HEMT is preferably at least a threshold voltage higher than its source and drain voltages. Therefore, even with lower source and drain voltages, a given gate potential referenced to the first master terminal T1 can still allow the sensing HEMT 104 to be fully turned on at a higher short-circuit drain voltage. Alternatively, independent auxiliary gate interfaces using different suitable reference voltages can be implemented for the sensing HEMT 104. Another advantage is that the VS ratio is reduced compared to the drain voltage. This will protect other circuitry connected to the source of the sensing HEMT from high voltage effects.

[0289] Resistors R2 and R3 can be monolithically integrated with the semiconductor switch. In some cases, these resistors may be externally supplied. Furthermore, the conductivity of the 2DEG resistors may decrease when the device is in blocking mode. To address this issue, a voltage divider can be constructed using resistors made of silicon-chromium (SiCr), metal, or other suitable materials.

[0290] As an alternative to the previously implemented one, the sensing HEMT can be driven by an integrated gate driver powered by a voltage source VDD, and its input signal level is shifted by the main interface circuitry.

[0291] In some cases, the generation of the sensed voltage signal can be disabled and / or reset by a reset signal, for example, through... Figure 16 and 18 The blanking time module shown in the diagram and / or a reset signal from an external driver are implemented. For example, the signal conditioning circuit can set a reset HEMT, which is connected between the source of the sensing HEMT and the first master terminal, in parallel with other circuitry of the signal conditioning circuit. The gate of this reset HEMT can be connected to a reset signal, which can be controlled by timing or logic circuitry, an external driver, or a combination thereof. Therefore, when the reset signal is high, the reset HEMT will be short-circuited to ground, and the output of the signal conditioning circuit 300 will be disabled by the short circuit of the reset HEMT.

[0292] Timing or logic circuits can be part of signal conditioning circuits.

[0293] As mentioned above, Figure 20 An example of a Miller clamp driver (MCD) block 400a is shown, which may correspond to Figure 54 , 55 The Miller clamp driver blocks 400 and 400S are shown in Figure 56.

[0294] The Miller clamp driver 400a includes a logic inverter 401 configured to operate an actively switched Miller clamp transistor 102, which acts as a pull-down network. The logic inverter 401 may consist of a resistor or resistive element (i.e., a load transistor or current source) and an enhancement-mode transistor. Figure 21 An example implementation of logic inverter 401 in module 400a is shown. However, this is merely a configuration example, and other logic inverter designs can be substituted or supplemented. Figure 21 An example.

[0295] During operation, the logic inverter is operatively connected to a control signal from either the control terminal or an external gate terminal (i.e., the terminal connected to the gate driver). When the control signal is high, the gate bias of the active switching transistor in Miller clamp 102 is low (and therefore its resistance is high), and vice versa.

[0296] Re-reference Figure 22The figure illustrates an example implementation of a Miller clamp driver (MCD) module 400b (possibly corresponding to modules 400, 400S described and shown herein), which operates based on a short-circuit detection signal (SCD) (i.e., a sensed voltage signal) or a regulated signal SCDC. The Miller clamp driver 400b includes a logic inverter 404 and a logic gate (NAND gate) 405. The logic inverter digitizes the SCD / SCDC signal. In this case, the Miller clamp driver 400b has two input signals—a control signal and a short-circuit detection signal SCD or its regulated version SCDC. When the SCD / SCDC signal is "high" or the control signal is "low," the driver module 400b outputs a high signal, activating the Miller clamp transistor 102, which pulls down the gate of the power HEMT 101.

[0297] Refer again Figure 23 The figure shows Figure 22 This is an example implementation of the Miller clamp driver module 400b. However, this is merely a configuration example and can be replaced or supplemented by other circuit designs. Figure 23 An example.

[0298] Figure 66 This diagram illustrates a schematic example of a power integrated circuit (semiconductor switch) connected to a gate driver. The gate driver is configured to provide a gate drive signal (control signal) to the control terminal of the power IC. Both the gate driver and the power IC can be powered by a voltage source VDD. In this example, the gate driver provides a DESAT pin, offering desaturation protection. This feature is typically found in gate drivers used in automotive inverter applications. When the voltage at the DESAT pin exceeds a threshold voltage, the driver initiates a safe shutdown procedure to protect the power semiconductor switch. A short-circuit detection signal SCD can be connected to the DESAT input of the gate driver. When a short-circuit event occurs, the SCD signal exceeds the threshold, acting on the auxiliary gate interface circuitry and / or the Miller clamp driver to internally protect the power HEMT as shown in the above embodiment. Simultaneously, this signal also triggers a fault detection on the DESAT pin, causing the driver to initiate a safe shutdown.

[0299] Figure 67Another example of a power integrated circuit is shown, in which the power HEMT switch is replaced by a combination switch comprising a high-voltage transistor 40 connected in parallel with the high-voltage power HEMT device 101. The high-voltage transistor device 40 may comprise a non-III-nitride material or material system. In some examples, the high-voltage transistor device may be a silicon and / or silicon carbide transistor, such as, but not limited to, a silicon IGBT, a silicon MOSFET, a SiC MOSFET, or a superjunction MOSFET. Generally, these devices have a long short-circuit withstand time (also known as endurance time), typically in the range of a few microseconds, while GaN HEMTs only last for a few hundred nanoseconds (especially if the rail voltage and DC connection are close to the rated voltage). A short-circuit detection circuit (including a sensing HEMT, a sensing interface circuit, and a signal conditioning circuit) is connected to the power HEMT device and outputs an SCD signal in the event of a short circuit, as shown in the previous embodiment. The SCD signal is input to an auxiliary gate interface and / or a Miller clamp driver to turn off or regulate the gate voltage of the power HEMT until the external driver turns off the control terminal. Reducing the bias voltage at the gate of a power HEMT can help extend its withstand time during a short-circuit event, as a lower gate bias voltage reduces the saturation current of the power HEMT under short-circuit conditions. Therefore, the short-circuit detection and protection circuitry of an HEMT device can extend the overall short-circuit withstand time of the combination switch.

[0300] The following are further examples based on this disclosure, which may be described by one or more of the following non-limiting items, numbered C1 to C26:

[0301] C1. A semiconductor switch, comprising a first main terminal, a second main terminal, and a control terminal, wherein the semiconductor switch further comprises:

[0302] A group III nitride high electron mobility transistor (HEMT) includes a first source terminal, a first drain terminal, and a first gate terminal;

[0303] A first interface circuit, operably connected to the control terminal and the first gate terminal; and

[0304] A short-circuit detection circuit, operably connected to the first drain terminal and the first source terminal, is configured to:

[0305] Detecting a short circuit between the first drain terminal and the first source terminal; and

[0306] A short-circuit detection signal is sent to the first interface circuit, which is configured to turn off the group III nitride HEMT and / or reduce the voltage at the first gate terminal upon receiving the short-circuit detection signal.

[0307] C2. The semiconductor switch as described in item C1, wherein the first interface circuit includes a pull-down transistor, the pull-down transistor including a second source terminal and a second drain terminal;

[0308] Wherein, the second drain terminal is operatively connected to the first gate terminal;

[0309] Wherein, the second source terminal is operatively connected to the first source terminal; and

[0310] The pull-down transistor is configured to turn on when the first interface circuit receives the short-circuit detection signal.

[0311] C3. The semiconductor switch as described in item C2, wherein the pull-down transistor includes a second gate terminal, wherein the first interface circuit is configured to receive the short-circuit detection signal at the second gate terminal.

[0312] C4. The semiconductor switch as described in item C2, wherein the pull-down transistor includes a second gate terminal, wherein the first interface circuit further includes a pull-down transistor gate driver operatively connected to and configured to drive the second gate terminal;

[0313] The first interface circuit is configured to receive the short-circuit detection signal at the gate driver of the pull-down transistor.

[0314] C5. The semiconductor switch as described in any one of items C1 to C4, wherein the first interface circuit includes an auxiliary gate interface circuit, the auxiliary gate interface circuit including a voltage limiter and an auxiliary group III nitride HEMT, the auxiliary group III nitride HEMT comprising:

[0315] A third source terminal, which is operatively connected to the first gate terminal;

[0316] A third drain terminal, operatively connected to the control terminal; and

[0317] A third gate terminal, which is operatively connected to the voltage limiter;

[0318] The voltage limiter can be configured to limit the voltage between the first gate terminal and the first source terminal.

[0319] C6. The semiconductor switch as described in item C5, wherein the first interface circuit is configured to receive the short-circuit detection signal at the auxiliary gate interface circuit; and

[0320] The first interface circuit is configured to reduce the voltage at the first gate terminal when the short-circuit detection signal is received.

[0321] C7. The semiconductor switch as described in item C5, wherein the auxiliary gate interface circuit can be configured to adjust the voltage applied to the control terminal to be operatively compatible with the first gate terminal.

[0322] C8. A semiconductor switch as described in any one of items C1 to C7, the semiconductor switch including a latching circuit configured to adjust the short-circuit detection signal such that the short-circuit detection signal remains in a given state until one or more release conditions are met.

[0323] C9. The semiconductor switch as described in item C8, wherein the one or more release conditions include the expiration of a time period.

[0324] C10. A semiconductor switch as described in any one of items C1 to C9, the semiconductor switch including a regulating circuit configured to regulate the short-circuit detection signal.

[0325] C11. The semiconductor switch as described in item C10, wherein the regulating circuit includes one or more of the following:

[0326] diode;

[0327] Resistor;

[0328] Capacitor;

[0329] Logic inverter;

[0330] Buffer; and / or

[0331] Level converter.

[0332] C12. The semiconductor switch of any one of items C1 to C11, wherein the short-circuit detection circuit includes a desaturation circuit configured to detect a voltage drop between the first drain terminal and the first source terminal.

[0333] C13. The semiconductor switch as described in item C12, wherein the voltage drop is between 5 V and 30 V.

[0334] C14. The semiconductor switch as described in any one of items C1 to C13, wherein the short-circuit detection circuit includes a resistor-capacitor network and a sensing HEMT, the sensing HEMT comprising:

[0335] A fourth source terminal, which is operatively connected to the RC network;

[0336] A fourth drain terminal, operatively connected to the first drain terminal; and

[0337] A fourth gate terminal, which is operatively connected to the first gate terminal.

[0338] C15. The semiconductor switch as described in any one of items C1 to C14, wherein the short-circuit detection circuit comprises:

[0339] A voltage detection circuit, configured to compare the voltage between the first drain terminal and the first source terminal with a reference voltage, and to output a high-voltage detection signal when the voltage between the first drain terminal and the first source terminal is higher than the reference voltage; and

[0340] A blanking time circuit, which is configured to output a blanking time signal after a blanking time period has elapsed;

[0341] The short-circuit detection circuit is configured to send the short-circuit detection signal based on the high-voltage detection signal and the blanking time signal.

[0342] C16. The semiconductor switch as described in item C15, wherein the voltage detection circuit is configured to operate upon receiving the blanking time signal.

[0343] C17. The semiconductor switch as described in item C15, wherein the short-circuit detection circuit further includes a logic combination circuit configured to receive the high-voltage detection signal and the blanking time signal, and to output the short-circuit detection signal based on a combination of the high-voltage detection signal and the blanking time signal.

[0344] C18. The semiconductor switch as described in any one of items C1 to C17, wherein the short-circuit detection circuit is monolithically integrated with the group III nitride HEMT.

[0345] C19. The semiconductor switch as described in item C2, the semiconductor switch further comprising an additional pull-down transistor, the additional pull-down transistor comprising a fifth source terminal and a fifth drain terminal;

[0346] The fifth drain terminal is operably connected to the first gate terminal;

[0347] Wherein, the fifth source terminal is operatively connected to the first source terminal; and

[0348] The additional pull-down transistor is configured to control the group III nitride HEMT in the absence of a short-circuit detection signal.

[0349] C20. The semiconductor switch of claim C19, comprising an additional pull-down transistor gate driver, wherein the additional pull-down transistor includes a fifth gate terminal, wherein the additional pull-down transistor gate driver is operatively connected to the fifth gate terminal and the control terminal.

[0350] C21. The semiconductor switch according to any one of items C1 to C20, comprising a second short-circuit detection circuit, wherein the second short-circuit detection circuit is configured to detect a positive change in voltage between the first drain terminal and the first source terminal over time; and

[0351] The second short-circuit detection circuit is configured to send a second short-circuit detection signal when the positive change in voltage over time exceeds a reference rate.

[0352] C22. The semiconductor switch as described in item C21, wherein the second short-circuit detection circuit is configured to send the second short-circuit detection signal to the first interface circuit.

[0353] C23. A semiconductor switch as described in any one of items C1 to C22, wherein the semiconductor switch comprises one or more of the following:

[0354] Common source cascode devices; and / or

[0355] A combination switch comprising a group III nitride switch connected in parallel with a high-voltage transistor switch, the high-voltage transistor switch being made of a material other than group III nitrides.

[0356] C24. A system comprising a semiconductor switch as described in any one of items C1 to C23, the system further comprising an external gate driver operably connected to the control terminal, wherein the short-circuit detection circuit is configured to send a short-circuit detection signal to the external gate driver;

[0357] The external gate driver is configured to turn off the semiconductor switch upon receiving the short-circuit detection signal.

[0358] C25. The semiconductor switch as described in item 8 or 24, wherein one of the one or more release conditions includes receiving a reset signal from the external gate driver by the short-circuit detection circuit.

[0359] C26. A system comprising a plurality of semiconductor switches as described in any one of items C1 to C23 connected in parallel;

[0360] The first semiconductor switch among the plurality of semiconductor switches includes a first parallel mode detection circuit;

[0361] The second semiconductor switch among the plurality of semiconductor switches includes a second parallel mode detection circuit; and

[0362] Wherein, the short-circuit detection circuit of the first semiconductor switch is configured to send the short-circuit detection signal to the first parallel mode detection circuit, wherein the first parallel mode detection circuit is configured to send a detection signal to the second parallel mode detection circuit upon receiving the short-circuit detection signal; and

[0363] The second parallel mode detection circuit is configured to turn off the second semiconductor switch when the detection signal is received.

[0364] It should also be understood that terms such as “top” and “bottom”, “above” and “below”, “horizontal” and “vertical”, “below” and “above”, “front” and “rear”, “below”, etc., may be used in this specification in accordance with convention, and do not imply a particular physical orientation of the entire device.

[0365] While this disclosure has been described by way of the preferred embodiments described above, it should be understood that these embodiments are illustrative in nature only, and the claims are not limited to these embodiments. Those skilled in the art will be able to make modifications and substitutions based on this disclosure, and such modifications and substitutions are considered to fall within the scope of the appended claims. Each feature disclosed or shown in this specification may be incorporated individually into the common disclosure, or used in any suitable combination with any other features disclosed or shown in this specification.

[0366] References

[0367] [1]https: / / www.powerelectronicsnews.com / ultrafast-discrete-short-circuit-protection-for-gan-hemts

[0368] [2] https: / / ieeexplore.ieee.org / document / 9861995

[0369] [3] US Patent No. 10818786

[0370] [4] US 2023 / 0131602 A1

Claims

1. A semiconductor switch, characterized in that, The semiconductor switch includes a first main terminal, a second main terminal, and a control terminal, wherein the semiconductor switch further includes: A III-nitride high electron mobility transistor, the III-nitride high electron mobility transistor including a first source terminal, a first drain terminal and a first gate terminal; A first interface circuit is operatively connected to the control terminal and the first gate terminal; A sensing transistor, wherein the sensing transistor includes a sensing source terminal, a sensing drain terminal, and a sensing gate terminal; and The second interface circuit is operably connected to the control terminal and the sensing gate terminal; The sensing transistor is configured to sense the drain voltage of the III-nitride high electron mobility transistor in its on-state. The second interface circuit is configured to transmit a sensed voltage signal to the first interface circuit, wherein the sensed voltage signal is based on the drain voltage of the III-nitride high electron mobility transistor in its on-state; and The first interface circuit is configured to turn off the III-nitride high electron mobility transistor and / or reduce the voltage at the first gate terminal when the sensed voltage signal exceeds a threshold level.

2. The semiconductor switch according to claim 1, characterized in that, The system includes a signal conditioning circuit, wherein the signal conditioning circuit is configured to adjust the drain voltage in the on-state to generate the sensed voltage signal.

3. The semiconductor switch according to claim 2, characterized in that, The signal conditioning circuit is operatively connected between the sensing source end and the first main terminal.

4. The semiconductor switch according to claim 2, characterized in that, The signal conditioning circuit is operatively connected between the sensing drain terminal and the second main terminal.

5. The semiconductor switch according to any one of claims 2 to 4, characterized in that, The signal conditioning circuit is part of the second interface circuit.

6. The semiconductor switch according to any one of claims 2 to 5, characterized in that, The signal conditioning circuit includes a resistor divider.

7. The semiconductor switch according to any one of claims 2 to 6, characterized in that, The signal conditioning circuit includes a level shifter.

8. The semiconductor switch according to any one of the preceding claims, characterized in that, The first interface circuit includes a first pull-down device operably connected to the first gate terminal and configured to turn on when the sensed voltage signal exceeds the threshold level.

9. The semiconductor switch according to claim 8, characterized in that, The first interface circuit includes a second pull-down device, wherein the second pull-down device is operatively connected to the first gate terminal; The second pull-down device is configured to control shutdown and / or prevent the III-nitride high electron mobility transistor from being mis-turned on in the absence of a short circuit.

10. The semiconductor switch according to claim 9, characterized in that, The on-state resistance of the second pull-down device is lower than that of the first pull-down device.

11. The semiconductor switch according to any one of the preceding claims, characterized in that, The first interface circuit includes a first auxiliary gate interface circuit.

12. The semiconductor switch according to claim 11, characterized in that, The first auxiliary gate interface circuit is configured to reduce the bias of the first gate terminal when the sensed voltage signal exceeds the threshold level.

13. The semiconductor switch according to claim 11 or 12, characterized in that, The first interface circuit is configured to adjust the voltage applied to the control terminal to make it operatively compatible with the first gate terminal.

14. The semiconductor switch according to any one of claims 11 to 13, characterized in that, The first auxiliary gate interface circuit includes: The first auxiliary transistor includes a source terminal, a drain terminal, and a gate terminal. Wherein, the source terminal of the first auxiliary transistor is operatively connected to the first gate terminal; and The drain terminal of the first auxiliary transistor is operatively connected to the control terminal.

15. The semiconductor switch according to claim 14, characterized in that, Includes a first voltage limiter, wherein the first voltage limiter is configured to limit the potential applied to the gate terminal of the first auxiliary transistor.

16. The semiconductor switch according to claim 14 or 15, characterized in that, The first auxiliary gate interface circuit includes an auxiliary transistor pull-down device; Wherein, the auxiliary transistor pull-down device is configured to turn on when the sensed voltage signal exceeds the threshold level; and When the auxiliary transistor pull-down device is turned on, the auxiliary transistor pull-down device is configured to reduce the voltage at the gate terminal of the first auxiliary transistor.

17. The semiconductor switch according to any one of the preceding claims, characterized in that, The second interface circuit includes a sensing pull-down device, wherein the sensing pull-down device is operatively connected to the sensing gate terminal.

18. The semiconductor switch according to claim 17, which is dependent on claim 8, characterized in that, Both the first pull-down device and the sensing pull-down device are configured to be powered by the same driving circuit.

19. The semiconductor switch according to any one of the preceding claims, characterized in that, The second interface circuit includes a second auxiliary gate interface circuit operatively connected to the sensing gate terminal, wherein the second auxiliary gate interface circuit is configured to adjust the voltage applied to the control terminal to make it operatively compatible with the sensing gate terminal.

20. The semiconductor switch according to claim 19, characterized in that, The second auxiliary gate interface circuit includes a second auxiliary transistor, wherein the second auxiliary transistor includes a source terminal, a drain terminal, and a gate terminal; Wherein, the source terminal of the second auxiliary transistor is operatively connected to the sensing gate terminal; and The drain terminal of the second auxiliary transistor is operatively connected to the control terminal.

21. The semiconductor switch according to claim 20, characterized in that, Includes a second voltage limiter, wherein the second voltage limiter is configured to limit the potential applied to the gate terminal of the second auxiliary transistor.

22. The semiconductor switch according to claim 21, characterized in that, The second voltage limiter includes a threshold multiplier.

23. The semiconductor switch according to claim 4, characterized in that, The sensing drain terminal is connected to the first drain terminal via a second voltage divider, such that the sensing transistor receives a portion of the drain voltage of the III-nitride high electron mobility transistor.

24. The semiconductor switch according to claim 23, characterized in that, It includes an additional transistor configured to limit the voltage on the second voltage divider when the III-nitride high electron mobility transistor is caused to turn off or when the voltage on the first gate terminal is caused to decrease.

25. The semiconductor switch according to any one of the preceding claims, characterized in that, The second interface circuit is configured to make the switching of the sensing transistor independent of the switching of the III-nitride high electron mobility transistor.

26. The semiconductor switch according to any one of the preceding claims, characterized in that, The generation of the sensed voltage signal is configured to be disabled and / or reset by a reset signal.

27. The semiconductor switch according to claim 26, characterized in that, The reset signal is provided by an external driver.

28. The semiconductor switch according to claim 26 or 27, characterized in that, The signal conditioning circuit includes a timing or logic circuit, wherein the timing or logic circuit is configured to control the reset signal.

29. The semiconductor switch according to any one of the preceding claims, characterized in that, The sensing transistor, the first interface circuit, and the second interface circuit are monolithically integrated with the III-nitride high electron mobility transistor.

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