Circuit board and semiconductor package
By setting a resin layer and groove structure on the surface of the circuit board insulation layer, the problem of insulation layer damage during the descaling process is solved, thus achieving insulation layer protection and improving circuit board reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LG INNOTEK CO LTD
- Filing Date
- 2024-12-20
- Publication Date
- 2026-07-31
AI Technical Summary
During the circuit board manufacturing process, the surface of the insulating layer is easily damaged by chemicals in the descaling process, which can lead to the exposure of glass fibers and affect the appearance and reliability of the circuit board.
By applying a resin layer to the surface of the insulation layer to form a groove structure, the insulation layer is protected from chemical corrosion and the glass fiber is prevented from being exposed during the descaling process.
It effectively protects the surface of the insulation layer, prevents glass fiber exposure, improves the appearance and reliability of the circuit board, and reduces chemical damage to the insulation layer.
Smart Images
Figure CN122498239A_ABST
Abstract
Description
Technical Field
[0001] This embodiment relates to a circuit board and a semiconductor package. Background Technology
[0002] Recently, electronic product technology has been developing towards greater multifunctionality and higher speed, and semiconductor chip manufacturing technology is also developing rapidly to meet this trend.
[0003] In particular, the thickness of circuit boards used to miniaturize finished electronic products is constantly decreasing, and the technology of multilayer circuit boards, which contain more circuit layers in a circuit board of the same thickness, is being actively researched.
[0004] A circuit board is formed by printing circuit patterns on an electrically insulating substrate using a conductive material (such as copper); a circuit board is a general term for the circuit substrate before electronic components are mounted. In order to densely mount various types of electronic components on a plane, it is necessary to determine the mounting position of each component and print and fix the circuit patterns connecting the components on the plane.
[0005] These circuit boards typically include single-layer PCBs and multilayer PCBs, which are formed by manufacturing multiple layers of PCBs. By individually manufacturing and evaluating the quality of each layer, multilayer PCBs and multilayer boards can improve the overall yield of multilayer PCBs. Furthermore, by precisely connecting the wiring between the layers, high-density, miniaturized PCB production is possible. In this multilayer process, wiring connections are formed between the layers, and these connections are made through vias. To form these vias, lasers are used instead of traditional mechanical drilling to create very small diameters.
[0006] In the circuit board manufacturing process, a desmearing process is included to remove foreign matter from the board surface and provide roughness. In this case, because the chemicals used in the desmearing process are injected through vias, they damage the surface of the insulating layer, resulting in areas such as glass fibers inside the insulating layer being exposed to the outside. Summary of the Invention
[0007] Technical issues
[0008] This embodiment aims to provide a circuit board and semiconductor package that can improve appearance characteristics by protecting the surface of the insulating layer during surface treatment processes such as desmearing.
[0009] Technical solution
[0010] According to this embodiment, a circuit board includes: a first insulating layer; a first resin layer disposed on the upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first resin layer; a cavity penetrating the second insulating layer; a first circuit pattern disposed on the lower surface of the first insulating layer; a second circuit pattern disposed on the bottom surface of the cavity, i.e., the upper surface of the first resin layer; and a via hole penetrating the first resin layer and the first insulating layer and connecting the first circuit pattern and the second circuit pattern.
[0011] The material of the first insulating layer may be different from the material of the first resin layer.
[0012] The first insulating layer may be a prepreg (PPG) containing glass fibers in a resin, and the first resin layer may be made of a resin material.
[0013] The second insulating layer can be a photosensitive dielectric material (PID).
[0014] The second insulating layer may include a first through-hole extending from one side surface to the other side surface, and at least a portion of the upper surface of the first resin layer may be exposed above the second insulating layer through the first through-hole.
[0015] At least a portion of the second circuit pattern may be disposed on the upper surface of the first resin layer exposed through the first through-hole.
[0016] A groove with a more recessed shape than that in other areas can be formed on the upper surface of the second insulating layer.
[0017] A groove that is more recessed than other areas can be formed on the upper surface of the first resin layer exposed upward through the first through hole.
[0018] The circuit board may also include a protective layer disposed on the upper surface of the second insulating layer.
[0019] According to this embodiment, a semiconductor package includes: a first insulating layer; a first resin layer disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first resin layer; a cavity penetrating the second insulating layer; an electronic component disposed within the cavity; and a first circuit pattern disposed on a lower surface of the first insulating layer. A second circuit pattern is disposed on the bottom surface of the cavity, i.e., the upper surface of the first resin layer; and a via is disposed through the first resin layer and the first insulating layer and connecting the first circuit pattern and the second circuit pattern.
[0020] Beneficial effects
[0021] In this embodiment, by using a first resin layer to cover the surface of the first insulating layer exposed upward through the cavity, damage to the surface of the first insulating layer caused by contact with chemicals during the descaling process can be prevented, thereby preventing the glass fibers inside the first insulating layer from being exposed to the outside. Attached Figure Description
[0022] Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present disclosure.
[0023] Figures 2 to 11 This is a view illustrating the manufacturing process of a circuit board according to an embodiment of the present disclosure. Detailed Implementation
[0024] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0025] However, the technical concept of this disclosure is not limited to the described embodiments, but can be implemented in various different forms, and one or more components between the embodiments can be selectively combined or substituted within the scope of the technical concept of this disclosure.
[0026] Furthermore, the terms (including technical and scientific terms) used in the embodiments of this disclosure, unless explicitly and specifically defined and described, may be interpreted as having meanings that would be commonly understood by a person of ordinary knowledge in the art to which this disclosure pertains, and common terms (e.g., terms defined in a dictionary) may be interpreted in conjunction with the contextual meaning of the relevant art.
[0027] Furthermore, the terminology used in the embodiments of this disclosure is for describing the various embodiments and is not intended to limit the disclosure. In this specification, unless expressly stated otherwise in the phrase, the singular form may also include the plural form, and when described as "at least one (or one or more) of A, B, and C", it may include one or more of all combinations that can be combined with A, B, and C.
[0028] Furthermore, when describing the components of this embodiment of the present disclosure, terms such as first, second, A, B, (a), (b) may be used.
[0029] These terms are intended only to distinguish each component from the others, not to limit the nature, order, or sequence of the components.
[0030] Furthermore, when a component is described as being “connected,” “coupled,” or “accessed” to another component, this includes not only cases where the component is directly “connected,” “coupled,” or “accessed” to the other component, but also cases where the component is “connected,” “coupled,” or “accessed” through another component between the component and the other component.
[0031] Furthermore, when describing components as being formed or positioned "above" or "below," "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or positioned between the two components. Additionally, when expressed as "above" or "below," it may also include the meaning of a downward direction and an upward direction based on a component.
[0032] Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present disclosure. Figures 2 to 11 This is a view illustrating the manufacturing process of a circuit board according to an embodiment of the present disclosure.
[0033] Reference Figures 1 to 11 According to one embodiment of the present disclosure, the circuit board 10 may include a core layer 110, a first stacked layer 112 disposed on one side of the core layer 110, and a second stacked layer 114 disposed on the other side of the core layer 110. Here, "disposed on one side and the other side" should not be understood merely as a configuration in direct contact with one side and the other side, but can also be understood as having other configurations between one side and the first stacked layer 112 and between the other side and the second stacked layer 114.
[0034] The core layer 110 can be a component that forms the basis of the circuit board 10. The core layer 110 can be an insulating layer embedded with glass fiber or a metal material.
[0035] For example, the core layer 110 can be any insulating material, such as photocurable and / or thermosetting materials. As a thermosetting insulating material, it can be an insulating material in which inorganic and / or organic fillers are dispersed in the resin, such as Ajinomoto ABF (Ajinomoto Build-up Film), or a prepreg (PPG) containing glass fibers in the resin. Furthermore, the aforementioned resin can be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers can be materials such as silica and plastics. When the insulating resin is used as the core, the insulating resin can contain reinforcing materials incorporating glass fibers or aramid fibers.
[0036] As another example, if the core layer 110 is made of a metallic material, the bending and heat dissipation characteristics may be improved as the rigidity of the circuit board 10 increases. In this case, the material of the core layer 110 may include one or more of copper (Cu), aluminum (Al), magnesium (Mg), titanium (Ti), hafnium (Hf), and zinc (Zn). The material of the core layer 110 may be made of metals including tungsten (W), molybdenum (Mo), and aluminum (Al), or alloys including Invar, Kovar, nickel (Ni), and iron (Fe), as well as ceramics.
[0037] The core layer 110 may include a via, not shown, extending from one side to the other, and a circuit pattern disposed on one side of the core layer 110 and a circuit pattern disposed on the other side may be electrically connected through the via.
[0038] The first build-up layer 112 may be disposed on one side of the core layer 110. The first build-up layer 112 may include a first insulating layer 120, a first resin layer 130, and a second insulating layer 140. The first insulating layer 120, the first resin layer 130, and the second insulating layer 140 may be disposed along the vertical direction of the core layer 110, i.e., the up-down direction.
[0039] The first insulating layer 120 may be disposed on the upper surface of the core layer 110. The first insulating layer 120 may contain any insulating material, such as photocurable and / or thermosetting materials. The first insulating layer 120 may contain a prepreg (PPG) containing glass fibers in a resin. The resin of the first insulating layer 120 may include one or more of epoxy resin, bismaleimide triazine resin (BT resin), and phenolic resin. When the resin of the first insulating layer 120 is used as an insulating layer resin, it may contain reinforcing materials such as glass fibers or aramid fibers.
[0040] The first circuit pattern 161 can be embedded in the lower surface of the first insulating layer 120. The first insulating layer 120 includes a first via 171, which can be formed to penetrate the first insulating layer 120 in the vertical direction. The lower end of the first via 171 can be electrically connected to the first circuit pattern 161.
[0041] The second insulating layer 140 can be disposed on the upper surface of the first insulating layer 120. The second insulating layer 140 can be a thermosetting insulating material. The second insulating layer 140 can be a photosensitive insulating material. The second insulating layer 140 can be a photosensitive dielectric material (PID).
[0042] The second insulating layer 140 may include a first through-hole 152 for forming a portion of a cavity 150 disposed on one side of the circuit board 10. The first through-hole 152 is formed to extend from the upper surface to the lower surface of the second insulating layer 140, and a portion of the upper surface of the first resin layer 130 may be exposed upward through the first through-hole 152.
[0043] The second circuit pattern 162 can be embedded on the lower surface of the second insulating layer 140. The second circuit pattern 162 can be electrically connected to the upper end of the first via 171. The second insulating layer 140 includes a second via 173, which can be formed to penetrate the second insulating layer 140 in the vertical direction. The lower end of the second via 173 can be electrically connected to the second circuit pattern 162.
[0044] The third circuit pattern 163 can be disposed on the upper surface of the second insulating layer 140. The third circuit pattern 163 can be electrically connected to the upper end of the second via 173.
[0045] A recess 142, which is recessed downwards from other areas, can be formed on the upper surface of the second insulating layer 140. Multiple recesses 142 can be provided, and they can be provided in multiple quantities along the upper surface of the second insulating layer 140. The recesses 142 can be covered by a first protective layer 190, which will be described later. A portion of the first protective layer 190 can be embedded in the recesses 142. The recesses 142 can be formed during the descaling process of the circuit board 10, which will be described later.
[0046] A first resin layer 130 may be formed between a first insulating layer 120 and a second insulating layer 140. The first resin layer 130 may be located between the upper surface of the first insulating layer 120 and the lower surface of the second insulating layer 140. The thickness of the first resin layer 130 may be thinner than the thickness of the first insulating layer 120 or the thickness of the second insulating layer 140. For example, the thickness of the first resin layer 130 may be greater than 1 μm and less than 3 μm. The first resin layer 130 may be formed of a resin material. The first resin layer 130 may include a resin and an adhesive coated onto the surface of the resin.
[0047] The material of resin layer 130 may be resin. Resin layer 130 may not contain fillers, but alternatively, resin layer 130 may contain fillers.
[0048] More specifically, the resin layer 130 may be composed of a primer containing isopropanol (IPA) or acrylate silane. Furthermore, the first resin layer 130 may be composed of MPS (3-(trimethoxysilyl)propyl methacrylate) and may contain silane additives.
[0049] The first resin layer 130 may include a third via 172. The third via 172 may be connected to the upper end of the first via 171. The third via 172 may be integrally formed with the first via 171. Since the first via 171 and the third via 172, which connect the first circuit pattern 161 and the second circuit pattern 162, are integrally formed, the combined structure of the first via 171 and the third via 172 can be referred to as a single via. The upper end of the third via 172 may be electrically connected to the second circuit pattern 162.
[0050] A portion of the upper surface of the first resin layer 130 may form the bottom surface of the cavity 150. A portion of the upper surface of the first resin layer 130 may be exposed above the first laminate 112 through the first through-hole 152. A portion of the second circuit pattern 162 may be disposed on the upper surface of the first resin layer 130 exposed through the first through-hole 152. In this case, the second circuit pattern 162 can also be understood as being formed on the upper surface of the first resin layer 130.
[0051] The first resin layer 130 is configured to cover the upper surface of the first insulating layer 120, thereby protecting the upper surface of the first insulating layer 120. Specifically, a portion of the upper surface of the first resin layer 130 may be exposed upwards through the cavity 150. In this case, since the upper surface of the first insulating layer 120 is covered by the first resin layer 130 before the first protective layer 190 is formed, damage to the first insulating layer 120 from chemical spraying during the descaling process can be prevented. Because the first insulating layer 120 comprises resin and glass fiber, there is a risk that the glass fiber may be exposed to the outside of the first insulating layer 120 due to damage to the resin within the first insulating layer 120 when chemicals are sprayed. However, according to this embodiment, the structure of the first resin layer 130 covering the first insulating layer 120 can prevent the glass fiber within the first insulating layer 120 from being exposed to the outside.
[0052] Meanwhile, although not shown, according to the descaling process, one or more recessed grooves may be formed on the upper surface of the first resin layer 130 exposed upward through the cavity 150.
[0053] A first protective layer 190 may be formed on the upper surface of the first layer 112. The first protective layer 190 protects the third circuit pattern 163 from external moisture or contaminants. Furthermore, when semiconductor components are mounted on the circuit board 10 using materials such as solder, the first protective layer 190 prevents short circuits between solders due to low wettability with the solder. The first protective layer 190 may utilize a photocurable insulating material; for example, a solder resist may be used.
[0054] The first protective layer 190 may include a second through-hole 154. The second through-hole 154 may be configured to be opposite to the first through-hole 152 in the vertical direction. A cavity 150 may be formed on the upper surface of the circuit board 10 by the first through-hole 152 and the second through-hole 154. A second circuit pattern 162 may be formed on the bottom surface of the cavity 150. An electronic component (not shown) electrically connected to the second circuit pattern 162 may be disposed in the cavity 150, and a semiconductor package may be realized by combining the electronic component with the circuit board 10. At least a portion of the electronic component may be disposed within the second through-hole 154.
[0055] The second layer 114 can be disposed on the other side of the core layer 110. The second layer 114 may include a third insulating layer 125, a second resin layer 135, and a fourth insulating layer 145. The third insulating layer 125, the second resin layer 135, and the fourth insulating layer 145 can be disposed along the vertical direction of the core layer 110, i.e., the up-down direction.
[0056] The third insulating layer 125 may be disposed on the lower surface of the core layer 110. The third insulating layer 125 may contain any insulating material, such as photocurable and / or thermosetting materials. The third insulating layer 125 may include a prepreg (PPG) containing glass fibers in a resin. The resin of the third insulating layer 125 may contain one or more of epoxy resin, bismaleimide triazine resin (BT resin), and phenolic resin. When the resin of the third insulating layer 125 is used as an insulating layer resin, it may contain reinforcing materials such as glass fibers or aramid fibers.
[0057] The fourth circuit pattern 164 can be embedded on the upper surface of the third insulating layer 125. The third insulating layer 125 includes a fourth via 174, which can be formed to penetrate the third insulating layer 125 in the vertical direction. The upper end of the fourth via 174 can be electrically connected to the fourth circuit pattern 164.
[0058] The fourth insulating layer 145 may be disposed below the third insulating layer 125. The fourth insulating layer 145 may be a thermosetting insulating material. The fourth insulating layer 145 may be a photosensitive insulating material. The fourth insulating layer 145 may be a photosensitive dielectric material (PID).
[0059] A fifth circuit pattern 165 can be embedded on the upper surface of the fourth insulating layer 145. The fifth circuit pattern 165 can be electrically connected to the lower end of the fourth via 174. The fourth insulating layer 145 includes a fifth via 176, which can be formed to penetrate the fourth insulating layer 145 in the vertical direction. The upper end of the fifth via 176 can be electrically connected to the fifth circuit pattern 165.
[0060] The sixth circuit pattern 166 can be disposed on the lower surface of the fourth insulating layer 145. The sixth circuit pattern 166 can be electrically connected to the lower end of the fifth via 176.
[0061] The second resin layer 135 may be formed between the third insulating layer 125 and the fourth insulating layer 145. The second resin layer 135 may be located between the lower surface of the third insulating layer 125 and the upper surface of the fourth insulating layer 145. The thickness of the second resin layer 135 may be thinner than the thickness of the third insulating layer 125 or the fourth insulating layer 145. For example, the thickness of the second resin layer 135 may be more than 1 μm and less than 3 μm. The second resin layer 135 may be formed of a resin material. The second resin layer 135 may include a resin and an adhesive coated on the resin surface.
[0062] More specifically, the second resin layer 135 may be composed of a primer containing isopropanol (IPA) or acrylate silane. Furthermore, the second resin layer 135 may be composed of MPS (3-(trimethoxysilyl)propyl methacrylate) and may contain silane additives.
[0063] The second resin layer 135 may include a sixth via 175. The sixth via 175 may be connected to the lower end of the fourth via 174. The sixth via 175 may be integrally formed with the fourth via 174. Since the fourth via 174 and the sixth via 175 are integrally formed to connect the fourth circuit pattern 164 and the fifth circuit pattern 165, the combined structure of the fourth via 174 and the sixth via 175 can be referred to as a single via. The upper end of the sixth via 175 may be electrically connected to the fifth circuit pattern 165.
[0064] The second protective layer 195 can be formed on the lower surface of the second laminate 114. The second protective layer 195 can protect the sixth circuit pattern 166 from external moisture or contaminants. Furthermore, when semiconductor components are mounted on the lower surface of the circuit board 10 using materials such as solder, the second protective layer 195 can prevent short circuits between solders due to low wettability with the solder. The second protective layer 195 can be made of a photocurable insulating material; for example, the second protective layer 195 can be made of solder resist.
[0065] According to the above structure, by covering the surface of the first insulating layer 120 exposed upward through the cavity 150 with the first resin layer 130, surface damage to the first insulating layer 120 caused by contact with chemicals during the descaling process can be prevented, thereby preventing the glass fiber inside the first insulating layer 120 from being exposed to the outside.
[0066] Reference Figures 2 to 11 The manufacturing process of a circuit board 10 according to an embodiment of the present disclosure will be described.
[0067] First, such as Figure 2 and Figure 3 As shown, a first circuit pattern 161 and a fourth circuit pattern 164 can be formed on the surface of the core layer 110 using a metal foil 160. For example, the first circuit pattern 161 and the fourth circuit pattern 164 can be achieved by etching.
[0068] Next, as Figure 4 As shown, the first insulating layer 120, the first resin layer 130, the third insulating layer 125, and the second resin layer 135 are respectively laminated on one side and the other side of the core layer 110 to realize the first laminate 112 and the second laminate 114. In this case, copper foil 200 can be respectively disposed on the upper surface of the first resin layer 130 and the lower surface of the second resin layer 135.
[0069] Next, as Figure 5As shown, vias 210 are formed in the first insulating layer 120 and the first resin layer 130, as well as the third insulating layer 125 and the second resin layer 135, where copper foil 200 is disposed. Accordingly, in each configuration of the circuit board 10 described above, the first via 171 and the third via 172 are formed simultaneously, and the fourth via 174 and the sixth via 175 can be formed simultaneously.
[0070] Next, as Figure 6 As shown, the copper foil 200 disposed on the upper surface of the first resin layer 130 and the lower surface of the second resin layer 135 can be removed by etching. Subsequently, as Figure 7 and Figure 8 As shown, chemical copper (Cu) 220 for realizing metal patterns in the first via 171 and the third via 172 and the second circuit pattern 162 can be processed on the upper surface of the first resin layer 130 and the lower surface of the second resin layer 135, respectively, as well as chemical copper (Cu) 220 for realizing metal patterns in the fourth via 174 and the sixth via 175 and the fifth circuit pattern 165.
[0071] Next, as Figure 9 As shown, the second insulating layer 140 and the fourth insulating layer 145 can be attached to the upper surface of the first resin layer 130 on which the second circuit pattern 162 is formed, and to the lower surface of the second resin layer 135 on which the fifth circuit pattern 165 is formed. The second insulating layer 140 and the fourth insulating layer 145 can be implemented by a process of attaching PID vacuum to the upper surface of the first resin layer 130 and the lower surface of the second resin layer 135, respectively.
[0072] Next, as Figure 10 As shown, a cavity 230 for forming a first through hole 152 and a through hole 240 for forming a second through hole 173 and a fifth through hole 176 can be formed on the upper surface of the second insulating layer 140 and the lower surface of the fourth insulating layer 145.
[0073] Subsequently, as Figure 11 As shown, a desmearing process can be performed to remove foreign matter from the surfaces of the first stacked layer 112 and the second stacked layer 114. As described above, during the desmearing process, the surfaces of the first insulating layer 120 and the third insulating layer 125 are covered by the first resin layer 130 and the second resin layer 135, respectively, thereby preventing the chemicals used in the desmearing process from damaging the surfaces of the first insulating layer 120 and the third insulating layer 125.
[0074] As described above, during the descaling process, the upper surface of the upward-exposed second insulating layer 140 and the upper surface of the upward-exposed first resin layer 130 through the cavity 230 may respectively form grooves 142 in the resin constituting the second insulating layer 140 and the resin constituting the first resin layer 130 due to contact with the chemicals of the descaling process.
[0075] After the descaling process, a patterning process is performed to form a third circuit pattern 163, a second via 173, a sixth circuit pattern 166, and a fifth via 176 on the upper surface of the first layer 112 and the lower surface of the second layer 114, respectively. A process is also performed to form a first protective layer 190 and a second protective layer 195, thereby manufacturing a product as shown in the image. Figure 1 The circuit board 10 shown.
[0076] While all components constituting embodiments of this disclosure have been described as combining or jointly operating, this disclosure is not necessarily limited to such embodiments. In other words, within the scope of the purposes of this disclosure, all such components can be selectively combined and operated in one or more ways. Furthermore, unless expressly stated otherwise, terms such as “comprising,” “forming,” or “having” described above mean that the relevant component may be built-in; therefore, they should be interpreted as allowing the inclusion of additional components rather than excluding other components. All terms (including technical or scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise defined. Commonly used terms (e.g., predefined terms) should be interpreted according to their meaning in the relevant technical context and should not be interpreted in an ideal or overly formal sense, unless expressly defined in this disclosure.
[0077] The above description is merely an illustrative explanation of the technical concept of this disclosure. Those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of this disclosure. Therefore, the embodiments disclosed herein are intended to explain, not limit, the technical concept of this disclosure, and the scope of the technical concept is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the following claims, and all technical concepts within the equivalent scope should be interpreted as included within the scope of the rights of this disclosure.
Claims
1. A circuit board, comprising: First insulating layer; A first resin layer is disposed on the upper surface of the first insulating layer; A second insulating layer is disposed on the upper surface of the first resin layer; The cavity penetrates the second insulating layer; A first circuit pattern is disposed on the lower surface of the first insulating layer; A second circuit pattern is disposed on the bottom surface of the cavity, wherein the bottom surface is the upper surface of the first resin layer; as well as The via penetrates the first resin layer and the first insulating layer, and connects the first circuit pattern and the second circuit pattern.
2. The circuit board according to claim 1, in, The material of the first insulating layer is different from the material of the first resin layer.
3. The circuit board according to claim 2, in, The first insulating layer is a prepreg, namely PPG, which contains glass fibers in the resin. The first resin layer is formed of resin material.
4. The circuit board according to claim 1, in, The second insulating layer is a photosensitive dielectric material, namely PID.
5. The circuit board according to claim 1, in, The second insulating layer includes a first through-hole that extends from one surface of the second insulating layer to another surface, and At least a portion of the upper surface of the first resin layer is exposed upward from the second insulating layer through the first through-hole.
6. The circuit board according to claim 5, in, At least a portion of the second circuit pattern is disposed on the upper surface of the first resin layer exposed through the first through-hole.
7. The circuit board according to claim 1, in, A groove is formed on the upper surface of the second insulating layer, and the groove is recessed relative to other areas.
8. The circuit board according to claim 5, in, A groove is formed on the upper surface of the first resin layer exposed upward through the first through hole, the groove being recessed relative to other areas.
9. The circuit board according to claim 1, further comprising: A protective layer is disposed on the upper surface of the second insulating layer.
10. A semiconductor package, comprising: First insulating layer; A first resin layer is disposed on the upper surface of the first insulating layer; A second insulating layer is disposed on the upper surface of the first resin layer; The cavity penetrates the second insulating layer; Electronic components are disposed within the cavity; A first circuit pattern is disposed on the lower surface of the first insulating layer; A second circuit pattern is disposed on the bottom surface of the cavity, wherein the bottom surface is the upper surface of the first resin layer; as well as The via penetrates the first resin layer and the first insulating layer, and connects the first circuit pattern and the second circuit pattern.