Multilayer coreless substrate formed from stacked embedded trace substrates

Abstract

An electronic device including a substrate is disclosed. In one aspect, the substrate includes: at least two stacked embedded trace substrates (ETS); a first dielectric layer disposed between an inward-facing surface of a first ETS and an inward-facing surface of a second ETS in the at least two stacked ETS; and a first set of one or more metal connectors extending through the first dielectric layer and coupling a first set of one or more metal structures at the inward-facing surface of the first ETS to a second set of one or more metal structures at the inward-facing surface of the second ETS.

Description

Technical Field

[0001] This disclosure relates generally to electronic packaging, and more specifically to multilayer coreless substrates formed by stacked embedded trace substrates. Background Technology

[0002] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of electronic components. An IC can be implemented as an IC chip on which a set of circuits is integrated. In some implementations, one or more IC chips can be physically carried and protected by an IC package, where the various power and signal nodes of the one or more IC chips can be electrically coupled to corresponding conductive terminals of the IC package via electrical paths formed in the package substrate. Various packaging technologies are found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc. Advanced packaging and processing technologies can be used to realize complex devices such as multi-component devices and system-on-a-chip (SoC) devices, which can include multiple functional blocks, each designed to perform a specific function, such as microprocessor functions, graphics processing unit (GPU) functions, and communication functions (e.g., WiFi, Bluetooth, and other communications).

[0003] Printed circuit boards (PCBs) are an indispensable component in modern electronic packaging, serving as a platform for mounting and interconnecting various electronic components. The evolution of PCB technology is driven by the demands of advanced electronic products, leading to the development of structures that support increased circuit density and reduced form factor. With the trend towards device miniaturization, the requirements for PCBs have become more stringent, including higher interconnect density and precise metallization routing and placement. Summary of the Invention

[0004] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0005] In one aspect, an electronic device includes: a substrate comprising: at least two stacked embedded trace substrates (ETS); a first dielectric layer disposed between an inward-facing surface of a first ETS and an inward-facing surface of a second ETS in the at least two stacked ETS; and a first set of one or more metal connectors extending through the first dielectric layer and coupling the first set of one or more metal structures at the inward-facing surface of the first ETS to a second set of one or more metal structures at the inward-facing surface of the second ETS.

[0006] In one aspect, a substrate includes: at least two stacked embedded trace substrates (ETS) stacked on top of each other; a first dielectric layer that bonds an inward-facing surface of a first ETS to an inward-facing surface of a second ETS; and a first set of one or more metal structures that extend through the first dielectric layer and connect the first set of one or more metal structures at the inward-facing surface of the first ETS to a second set of one or more metal structures at the inward-facing surface of the second ETS.

[0007] In one aspect, a method of manufacturing a substrate includes: aligning at least two stacked embedded trace substrates (ETS) to stack on top of each other, wherein the at least two stacked ETSs include a first ETS and a second ETS, the first ETS having an inward-facing surface having a first set of one or more metal connectors, the second ETS having an inward-facing surface having a first set of one or more metal structures; aligning a first dielectric layer between the inward-facing surfaces of the first ETS and the second ETS; and bonding the inward-facing surfaces of the first ETS and the second ETS to the first dielectric layer, wherein the bonding connects at least one metal structure of the first set of one or more metal connectors at the inward-facing surface of the first ETS to at least one metal structure of the first set of one or more metal structures at the inward-facing surface of the second ETS.

[0008] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0009] When considered in conjunction with the accompanying drawings, a more complete understanding of the various aspects of this disclosure and its many advantages therefrom will become better understood by referring to the following detailed description, which is presented for illustrative purposes only and does not constitute any limitation on this disclosure.

[0010] Figure 1 Example multilayer coreless substrates according to various aspects of this disclosure are shown.

[0011] Figure 2 This is a top plan view of an example multilayer coreless substrate according to various aspects of this disclosure.

[0012] Figure 3 This is an exploded cross-sectional view of the structure of a multilayer coreless substrate according to various aspects of this disclosure.

[0013] Figure 4 This is a cross-sectional view of an example multilayer coreless substrate according to various aspects of this disclosure.

[0014] Figure 5 This is a partial top plan view of an example multilayer coreless substrate according to various aspects of this disclosure.

[0015] Figure 6 Example electronic packages including multilayer coreless substrates are illustrated according to various aspects of this disclosure.

[0016] Figures 7A to 7F Example operations that can be used to manufacture embedded trace substrates (ETS) according to various aspects of this disclosure are shown.

[0017] Figures 8A to 8D Exemplary operations that can be used to form multilayer coreless substrates using stacked ETSs are shown according to various aspects of this disclosure.

[0018] Figure 9 An example operation of a method for manufacturing a substrate according to various aspects of this disclosure is shown.

[0019] Figure 10 Outline diagrams of packages according to various aspects of the present disclosure are illustrated, the packages including multilayer coreless substrates, integrated devices, and integrated passive devices.

[0020] Figure 11 Example methods for providing or manufacturing a package, including an integrated device comprising electronic components, are illustrated according to various aspects of this disclosure.

[0021] Figure 12Examples of various electronic devices that may integrate any of the following: the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC).

[0022] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0023] Various aspects of this disclosure are illustrated in the following description and related figures with respect to specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of this teaching. Furthermore, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted to avoid obscuring the relevant details of the teachings in this disclosure.

[0024] In some of the described example implementations, instances are identified where various component structures and operational parts are available from known conventional techniques and are then arranged according to one or more exemplary embodiments. In such instances, internal details of known conventional component structures and / or operational parts may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary embodiments disclosed herein.

[0025] Coreless PCBs have emerged as an alternative to traditional PCBs. By design, coreless PCBs do not incorporate a central core material. Instead, they are constructed using thin layers of insulating material. The coreless nature helps reduce the overall thickness of the PCB, which is advantageous for applications requiring compact electronic assemblies. The use of coreless structures in PCBs facilitates several functional improvements, including potentially shorter electrical paths and more straightforward trace configurations. These properties can contribute to efficient signal transmission and are advantageous in the context of high-density interconnect (HDI) applications. Additionally, the structure allows for tighter layer stacking, which can be beneficial for creating a greater number of interconnects within a limited space.

[0026] Figure 1An example multilayer coreless substrate 100 according to various aspects of the present disclosure is shown. In this example, the multilayer coreless substrate 100 is a six-layer substrate having six patterned metallization layers 102, 104, 106, 108, 110, and 112 formed over respective dielectric layers 124, 126, 128, 130, and 132. Metallized vias 114, 116, 118, 120, and 122 extend through dielectric layers 124, 126, 128, 130, and 132 to selectively interconnect the patterned metallization layers 102, 104, 106, 108, 110, and 112. The patterned metallization layer 102 includes pads 134 extending beyond the surface of dielectric layer 124. Similarly, the patterned metallization layer 112 includes pads 136 extending beyond the surface of dielectric layer 132. On one hand, pad 136 can be used as a connection point to which components (e.g., integrated circuit dies, passive components, etc.) disposed on the upper surface of the multilayer coreless substrate 100 are soldered. Similarly, pad 134 can be used as a connection point for soldering the multilayer coreless substrate 100 to a printed circuit board or for soldering components disposed on the lower surface of the coreless substrate. Since pad 134 extends beyond the surface of dielectric layer 124, a patterned solder resist layer 138 is formed above the outer surface of dielectric layer 124 and above the portion of pad 134 to be protected from the influence of solder material. Likewise, since pad 136 extends beyond the surface of dielectric layer 132, a patterned solder resist layer 140 is formed above the outer surface of dielectric layer 132 and above the portion of pad 136 to be protected from the influence of any solder material. On one hand, solder resist layers 138 and 140 may have a thickness between 12 and 15 micrometers on each side and the processing cost may be high. According to certain aspects of this disclosure, multilayer coreless substrates that do not require a solder resist layer can be formed, thereby reducing manufacturing costs associated with the solder resist process. Additionally, according to certain aspects of this disclosure, the substrate thickness can be reduced by omitting such a solder resist layer.

[0027] Figure 2 This is a top plan view of an example multilayer coreless substrate 100 according to various aspects of the present disclosure. In this example, the upper surface of the multilayer coreless substrate 100 is covered by a patterned solder mask 140, such that only portions of the pads 136 are exposed during subsequent component soldering to the multilayer coreless substrate 100. Similarly, the lower surface of the multilayer coreless substrate 100 is formed with a patterned solder mask 138, such that only portions of the pads 134 are exposed during subsequent component soldering to the multilayer coreless substrate 100.

[0028] Conventional processes for manufacturing multilayer coreless substrates (e.g., multilayer coreless substrate 100) can be expensive and difficult to implement, especially as the number of layers required increases. They typically involve a complex sequence of dry film resist (DFR) lamination / delamination, laser drilling, seed layer deposition / etching, and electroplating / etching operations. In cases requiring precise alignment and placement of fine metallization lines, achieving the necessary control over the size and spacing of the metallization lines using conventional coreless substrate manufacturing processes can be challenging.

[0029] Figure 3 This is an exploded cross-sectional view of a multilayer coreless substrate structure 300 according to various aspects of the present disclosure. In this example, structure 300 includes at least two embedded trace substrates (ETS) 302 and 304 and a dielectric layer 306. ETS 302 is a three-layer ETS structure having three metallization layers 308, 310, and 312 formed on two dielectric layers 314 and 316. The outer surface 318 of ETS 302 includes a plurality of pads 320 formed by the metallization layers 308 embedded in the dielectric layer 314, wherein the outer surface 322 of the pads 320 is recessed from the outer surface 324 of the dielectric layer 314. Given this relationship between the outer surface 322 of the pads 320 and the outer surface 324 of the dielectric layer 314, the pads 320 may be referred to as “recessed pads”.

[0030] The inward-facing surface 326 of ETS 302 includes a plurality of pads 328 formed by a metallization layer 312 extending above the inner surface 335 of the dielectric layer 316. In one aspect, "inner surface" and / or "inward-facing surface" refers to the surface that will ultimately be located inside the multilayer coreless substrate structure. Given this relationship between the pads 328 and the inner surface 335 of the dielectric layer 316, the pads 328 may be referred to as "bump pads". Some of the bump pads 328 include metallized bumps 333 formed above the upper surface of the bump pad 328, which effectively extend the height of the particular bump pad 328.

[0031] ETS 304 is also a three-layer ETS structure, which has three metallization layers 330, 332, and 334 formed on two dielectric layers 336 and 338. The outer surface 340 of ETS 304 includes a plurality of recessed pads 342 formed by the metallization layers 334 embedded in the dielectric layer 338, wherein the outer surface 344 of the pads 342 is recessed from the outer surface 346 of the dielectric layer 338. The inward-facing surface 348 of ETS 304 includes a plurality of raised pads 350 formed by the metallization layers 330, which extend above the inner surface 352 of the dielectric layer 336.

[0032] Figure 4This is a cross-sectional view of an example multilayer coreless substrate 400 according to various aspects of this disclosure. In this example, the inward-facing surfaces 326 and 348 of ETS 302 and 304 are bonded to dielectric layer 306. A set of metallization structures (e.g., metallization bumps 333) extends through dielectric layer 306 and connects a set of metallization structures (e.g., raised pads 328) at the inward-facing surface 326 of ETS 302 to a set of metallization structures (e.g., raised pads 350) at the inward-facing surface 348 of ETS 304. Specific raised pads (e.g., raised pads 402 and 404) are not associated with corresponding metallization bumps and are therefore electrically isolated from each other by the dielectric material of dielectric layer 306. It will be appreciated that, based on the teachings of this disclosure, metallization bump 333 may be formed on bump pad 328, bump pad 350, or both bump pads 328 and 350, provided that metallization bump 333 has a height sufficient to connect bump pads 328 and 350 through dielectric layer 306.

[0033] Figure 5 This is a partial top plan view 500 of an example multilayer coreless substrate 400 according to various aspects of this disclosure. (See also multilayer coreless substrate 100). Figure 1 and Figure 2 Unlike other substrates, the outer surface 346 of dielectric layer 338 does not need to be covered by a solder mask because the recessed pads 342 are recessed from surface 346 and are unlikely to short-circuit when solder is applied to connect the recessed pads 342 to electronic components mounted to the multilayer coreless substrate 400. According to certain aspects of this disclosure, the metallization lines 502 (e.g., traces) of the interconnecting recessed pads 342 may also be recessed from surface 346 and exposed without the need for a solder mask covering. Without a solder mask, the overall thickness of the substrate can be reduced compared to a substrate with a solder mask. On one hand, both sides of the substrate can be used to fabricate small-pitch flip-chip pads and solder ball pads because solder mask alignment is not considered when fabricating such structures. On the other hand, manufacturing costs can be reduced, and shorter manufacturing lead times can be achieved.

[0034] Figure 6 An example electronic package 600 including a multilayer coreless substrate 400 is illustrated according to various aspects of the present disclosure. In this example, various electronic components are attached to the outer surface 340 of the multilayer coreless substrate 400. In one aspect, the electronic components may include surface-mount ICs 602 and 604 and one or more passive components 606, such as resistors and / or capacitors. In another aspect, the terminals of the electronic components may be connected to recessed pads 342 via solder joints 608. Since the recessed pads 342 are recessed from the outer surface 324 of the dielectric layer 314, it is not necessary to apply solder resist to the outer surface 318.

[0035] According to various aspects of this disclosure, the outer surface 318 of the multilayer coreless substrate 400 includes solder interconnects 610 attached to recessed pads 320. In one aspect, the solder interconnects 610 can be used to electrically connect the electronic package 600 to the package substrate. Figure 6 The corresponding metal structure (not shown in the figure). Since the recessed pad 320 is recessed from the outer surface 346 of the dielectric layer 338, it is not necessary to apply solder mask to the outer surface 340.

[0036] Figures 7A to 7F Example operations that can be used to manufacture embedded trace substrates (ETS) according to various aspects of this disclosure are shown. Figure 7A A structure 700 on which two ETS structures can be formed is shown. As will be apparent from the following operation, a single multilayer ETS structure is formed on each side of the structure 700. Here, the structure 700 includes a dummy copper clad laminate (CCL) having layers of copper carrier layers 702 and 704 disposed on opposite surfaces of a dielectric core 707. The structure 700 also includes seed layers 706 and 708 (e.g., copper seed layers formed above the copper carrier layers 702 and 704).

[0037] Figure 7B Patterned metallization layers 710 and 712 (e.g., copper metallization layers) of the first level are shown formed over seed layers 706 and 708. The patterned metallization layers 710 and 712 can be formed using standard processes, wherein the metallization layers 710 and 712 are electroplated over the seed layers 706 and 708 (e.g., DFR masking, UV exposure, development, electroplating, and stripping operations).

[0038] exist Figure 7C In this process, dielectric layers 714 and 716 are formed above seed layers 706 and 708 and patterned metallization layers 710 and 712. Additionally, seed layers 718 and 720 are formed above the outer surfaces of dielectric layers 714 and 716 to form the next layer of patterned metallization layers.

[0039] exist Figure 7D In this process, a standard electroplating process for metallization layers 722 and 724 is used to form the second-level patterned metallization layers 722 and 724. Once the second-level patterned metallization layers 722 and 724 have been formed, dielectric layers 726 and 728 are formed above the second-level patterned metallization layers 722 and 724. Additionally, seed layers 730 and 732 are formed above the outer surfaces of dielectric layers 726 and 728 to form the next level of patterned metallization layers.

[0040] exist Figure 7EIn this process, a standard electroplating process for metallization layers 734 and 736 has been used to form the third-level patterned metallization layers 734 and 736.

[0041] exist Figure 7F In this process, two ETSs 738 and 740 are formed by separating ETSs 738 and 740 from the copper carrier layers 702 and 704 of the dummy copper-clad laminate. Seed layers 706 and 708 are removed according to the separation process. Additionally, seed layers 730 and 732 are removed during the separation process.

[0042] Figures 8A to 8D Exemplary operations that can be used to form multilayer coreless substrates using stacked ETSs are shown according to various aspects of this disclosure. Figure 8A ETS 802 and 804 are shown to be bonded to form a multilayer coreless substrate.

[0043] exist Figure 8B In this embodiment, metallized bumps 806 are selectively formed over certain raised pads 808 of the ETS 802. In this example, raised pads 810 do not include metallized bumps because they will not be connected to any metal structure of the ETS 804. In one aspect, the metallized bumps 806 can be formed using lithography and metal plating (e.g., copper plating) manufacturing processes. In another aspect, the metallized bumps can be formed using dry film resist (DFR) lithography and copper (Cu) plating. In one aspect, the process flow may include the following operations: 1) DFR lamination on a seed layer; 2) DFR exposure; 3) DFR development; 4) electrolytic copper plating; 5) DFR stripping; and 6) seed layer etching.

[0044] exist Figure 8C In this process, dielectric layer 812 is aligned between inward-facing surfaces 814 and 816 of ETS 802 and 804, and the structure is subjected to a thermo-pressing operation to form Figure 8D The completed multilayer coreless substrate 818 is shown. In this example, the structure of the multilayer coreless substrate 818 may have a connection with... Figure 4 The multilayer coreless substrate 400 described herein has the same structural features.

[0045] Figure 9An example operation of a method 900 for manufacturing a substrate according to aspects of this disclosure is shown. At operation 902, at least two stacked embedded trace substrates (ETS) are aligned and stacked on top of each other, wherein the at least two stacked ETSs include a first ETS and a second ETS, the first ETS having an inward-facing surface having a first set of one or more metal connectors, and the second ETS having an inward-facing surface having a first set of one or more metal structures. At operation 904, a first dielectric layer is aligned between the inward-facing surfaces of the first ETS and the second ETS. At operation 906, the inward-facing surfaces of the first ETS and the second ETS are bonded to the first dielectric layer, wherein the bonding connects at least one metal structure from the first set of one or more metal connectors on the inward-facing surface of the first ETS to at least one metal structure from the first set of one or more metal structures on the inward-facing surface of the second ETS.

[0046] The technical advantage of method 900 lies in its cost-effective use of stacked ETSs to form a multilayer coreless substrate. In one aspect, this method enables the fabrication of substrates with high-density patterning and multiple layers. The ETSs, and thus the coreless substrate formed using both sides of the ETSs, can be manufactured with the fine line dimensions and high-precision line placement required by the increasing demand for package miniaturization, and can be used to manufacture thinner packages by omitting the typically required solder mask layer.

[0047] Figure 10 A contour view of a package 1000 according to various aspects of the present disclosure is illustrated. The package includes a multilayer coreless substrate 1002, an integrated device 1003, and an integrated passive device 1005. The package 1000 can be coupled to a printed circuit board (PCB) 1006 via a plurality of solder interconnects 1010. The PCB 1006 may include at least one board dielectric layer 1060 and a plurality of board interconnects 1062.

[0048] According to various aspects of this disclosure, the multilayer coreless substrate 1002 is formed of a plurality of stacked ETSs. An integrated device 1003 is coupled to the multilayer coreless substrate 1002 via a plurality of solder interconnects 1030. The integrated device 1003 is coupled to the multilayer coreless substrate 1002 via a plurality of solder post interconnects 1032 and a plurality of solder interconnects 1030. An integrated passive device 1005 is coupled to the multilayer coreless substrate 1002 via a plurality of solder interconnects 1050. The integrated passive device 1005 is coupled to the multilayer coreless substrate 1002 via a plurality of solder post interconnects 1052 and a plurality of solder interconnects 1050.

[0049] The package (e.g., 1000) may be implemented in a radio frequency (RF) package. This RF package may be a radio frequency front-end (RFFE) package. The package (e.g., 1000) may be configured to provide wireless fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g., 1000) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE). The package (e.g., 1000) may be configured to transmit and receive signals with different frequencies and / or communication protocols.

[0050] Figure 11 An example method 1100 for providing or manufacturing a package according to various aspects of this disclosure is illustrated, the package including an integrated device comprising electronic components. In some specific embodiments, Figure 11 Method 1100 can be used to provide or manufacture the product described in this disclosure. Figure 10 Package 1000. However, method 1100 can be used to provide or manufacture any package described in this disclosure.

[0051] It should be noted that, according to all aspects of this disclosure, Figure 11 The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package comprising an integrated device having electronic components mounted in a core. In some specific implementations, the order of the processes may be changed or modified.

[0052] The method (at 1105) provides a substrate (e.g., 1002). The substrate 1002 may be supplied by a supplier or manufactured in-house. The substrate 1002 may include stacked ETSs constructed according to various aspects of this disclosure.

[0053] The method (at 1110) couples at least one integrated device (e.g., 1003) to a first surface of a substrate (e.g., 1002). For example, the integrated device 1003 may be coupled to the substrate 1002 via a plurality of solder interconnects 1032 and a plurality of solder interconnects 1030. The plurality of solder interconnects 1032 may be optional. The plurality of solder interconnects 1030 are coupled to a plurality of embedded pads 1022. A solder reflow process may be used to couple the integrated device 1003 to the plurality of interconnects via the plurality of solder interconnects 1030.

[0054] The method (at 1110) also couples at least one integrated passive device (e.g., 1005) to a first surface of a substrate (e.g., 1002). For example, the integrated passive device 1005 may be coupled to the substrate 1002 via a plurality of solder interconnects 1052 and a plurality of solder interconnects 1050. The plurality of solder interconnects 1052 may be optional. The plurality of solder interconnects 1050 are coupled to a plurality of embedded pads 1022. A solder reflow process may be used to couple the integrated passive device 1005 to the plurality of interconnects via the plurality of solder interconnects 1050.

[0055] The method (at 1115) couples a plurality of solder interconnects (e.g., 1010) to a second surface of a substrate (e.g., 1002). A solder reflow process can be used to couple the plurality of solder interconnects 1010 to the substrate.

[0056] Figure 12 Examples of various electronic devices that may integrate any of the following: the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked package (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1202, laptop computer device 1204, fixed-location terminal device 1206, wearable device 1208, or motor vehicle 1214 may include device 1200 as described herein. For example, device 1200 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 12 The illustrated devices 1202, 1204, 1206, and 1208, as well as vehicle 1210, are merely exemplary. Other electronic devices may also feature device 1200, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0057] Specific implementation examples are described in the following numbering section: Aspect 1. An electronic device comprising: a substrate including: at least two stacked embedded trace substrates (ETS); a first dielectric layer disposed between an inward-facing surface of a first ETS and an inward-facing surface of a second ETS in the at least two stacked ETS; and a first set of one or more metal connectors extending through the first dielectric layer and coupling a first set of one or more metal structures at the inward-facing surface of the first ETS to a second set of one or more metal structures at the inward-facing surface of the second ETS.

[0058] Aspect 2. The electronic device according to aspect 1, wherein: the first group of one or more metal structures at the inward-facing surface of the first ETS includes one or more raised pads; and the second group of one or more metal structures at the inward-facing surface of the second ETS includes one or more embedded pads.

[0059] Aspect 3. The electronic device according to aspect 2, wherein the first group of one or more metal structures extending through the first dielectric layer includes: at least one metallized bump disposed between at least one embedded pad in the one or more embedded pads of the second ETS and at least one raised pad in the one or more raised pads of the first ETS.

[0060] Aspect 4. The electronic device according to aspect 3, wherein: the at least one metallized bump is formed of a metal different from the metal used to form the one or more embedded pads and the one or more raised pads.

[0061] Aspect 5. The electronic device according to any one of Aspects 1 to 4, wherein: the first ETS includes a first outer surface, the first outer surface including one or more embedded pads disposed in a second dielectric layer.

[0062] Aspect 6. The electronic device according to aspect 5, further comprising: an integrated circuit (IC) component disposed on the first outer surface of the first ETS and electrically connected to the one or more embedded pads of the first ETS.

[0063] Aspect 7. The electronic device according to aspect 6, wherein: the IC component is disposed on the first outer surface of the first ETS, and there is no solder mask layer on the first outer surface of the first ETS.

[0064] Aspect 8. The electronic device according to any one of Aspects 1 to 7, wherein: the second ETS includes a second outer surface, the second outer surface including one or more exposed embedded pads disposed in a third dielectric layer.

[0065] Aspect 9. The electronic device according to aspect 8, further comprising: one or more solder joints connecting the one or more exposed embedded pads to one or more metal terminals of a printed circuit board.

[0066] Aspect 10. The electronic device according to aspect 9, wherein: the second outer surface of the second ETS is disposed on the printed circuit board, and no intermediate solder mask layer is formed on the second outer surface of the second ETS.

[0067] Aspect 11. The electronic device according to any one of Aspects 1 to 10, wherein: the first ETS and the second ETS are each a multi-layer ETS structure.

[0068] Aspect 12. The electronic device according to aspect 11, wherein: the first ETS is a three-layer ETS structure; the second ETS is a three-layer ETS structure; or a combination thereof.

[0069] Aspect 13. An electronic device according to any one of Aspects 1 to 12, wherein the electronic device comprises at least one of the following: a music player; a video player; an entertainment unit; a navigation device; a communication device; a mobile device; a mobile phone; a smartphone; a personal digital assistant; a fixed-location terminal; a tablet computer; a computer; a wearable device; a laptop computer; a server; an Internet of Things (IoT) device; or a device in a motor vehicle.

[0070] Aspect 14. A substrate comprising: at least two stacked embedded trace substrates (ETS) stacked on top of each other; a first dielectric layer connecting an inward-facing surface of a first ETS to an inward-facing surface of a second ETS of the at least two stacked ETS; and a first set of one or more metal structures extending through the first dielectric layer and connecting the first set of one or more metal structures at the inward-facing surface of the first ETS to a second set of one or more metal structures at the inward-facing surface of the second ETS.

[0071] Aspect 15. The substrate according to aspect 14, wherein: the first group of one or more metal structures at the inward-facing surface of the first ETS includes one or more raised pads; and the second group of one or more metal structures at the inward-facing surface of the second ETS includes one or more embedded pads.

[0072] Aspect 16. The substrate according to aspect 15, wherein the first group of one or more metal connectors extending through the first dielectric layer includes: at least one metallized bump disposed between at least one embedded pad of the one or more embedded pads of the second ETS and at least one raised pad of the one or more raised pads of the first ETS.

[0073] Aspect 17. The substrate according to aspect 16, wherein: the at least one metallized bump is formed of a metal different from the metal used to form the one or more embedded pads and the one or more raised pads.

[0074] Aspect 18. The substrate according to any one of Aspects 14 to 17, wherein: the first ETS includes a first outer surface, the first outer surface including one or more embedded pads disposed in a second dielectric layer.

[0075] Aspect 19. The substrate according to any one of Aspects 14 to 18, wherein: the second ETS includes a second outer surface, the second outer surface including one or more exposed embedded pads disposed in a third dielectric layer.

[0076] Aspect 20. The substrate according to any one of Aspects 14 to 19, wherein: the first ETS and the second ETS are each a multilayer ETS structure.

[0077] Aspect 21. The substrate according to aspect 20, wherein: the first ETS is a three-layer ETS structure; the second ETS is a three-layer ETS structure; or a combination thereof.

[0078] Aspect 22. A method of manufacturing a substrate, the method comprising: aligning at least two stacked embedded trace substrates (ETS) to stack on top of each other, wherein the at least two stacked ETSs include a first ETS and a second ETS, the first ETS having an inward-facing surface having a first set of one or more metal connectors, the second ETS having an inward-facing surface having a first set of one or more metal structures; aligning a first dielectric layer between the inward-facing surfaces of the first ETS and the second ETS; and bonding the inward-facing surfaces of the first ETS and the second ETS to the first dielectric layer, wherein the bonding connects at least one metal structure of the first set of one or more metal connectors at the inward-facing surface of the first ETS to at least one metal structure of the first set of one or more metal structures at the inward-facing surface of the second ETS.

[0079] Aspect 23. The method according to aspect 22, wherein: the first group of one or more metal connectors at the inward-facing surface of the first ETS includes one or more raised pads; and the first group of one or more metal structures at the inward-facing surface of the second ETS includes one or more embedded pads.

[0080] Aspect 24. The method according to aspect 23, the method further comprising: forming at least one metallized bump, the at least one metallized bump being disposed between at least one embedded pad of the second ETS and at least one raised pad of the first ETS.

[0081] Aspect 25. The method according to aspect 24, wherein: the at least one metallized bump is formed of a metal different from the metal used to form the at least one embedded pad of the second ETS and the at least one raised pad of the first ETS.

[0082] Aspect 26. The method according to any one of Aspects 22 to 25, wherein: the first ETS includes a first outer surface having one or more embedded pads disposed in a second dielectric layer.

[0083] Aspect 27. The method according to any one of Aspects 22 to 26, wherein: the second ETS includes a second outer surface having one or more exposed embedded pads disposed in a third dielectric layer.

[0084] Aspect 28. The method according to any one of Aspects 22 to 27, wherein: the first ETS and the second ETS are each a multi-layer ETS structure.

[0085] Aspect 29. The method according to any one of Aspects 22 to 28, the method further comprising: forming the first ETS; and forming the second ETS.

[0086] Aspect 30. As described in aspect 29, wherein: the first ETS is formed as a three-layer ETS structure; the second ETS is formed as a three-layer ETS structure; or the first ETS and the second ETS are each formed as a three-layer structure.

[0087] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. The term “electrical coupling” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term “encapsulation” means that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component may mean that the first component is above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component may be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. The terms "about 'value X'" or "approximately value X" as used in this disclosure mean within 10% of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0088] In some embodiments, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metallization layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0089] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0090] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features in the example aspects than are explicitly mentioned in each aspect. Rather, the various aspects of this disclosure may include fewer features than those in the individual example aspects disclosed. Therefore, the following aspects should be regarded accordingly as incorporated into the description, where each aspect can be considered as a separate example on its own. Although each dependent aspect may refer in the aspect to a particular combination with one aspect of other aspects, the aspect of the dependent aspect is not limited to that particular combination. It should be understood that other example aspects may also include combinations of the subject matter of a dependent aspect with any other dependent or independent aspect, or any feature combined with other dependent and independent aspects. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of an aspect may be included in any other independent aspect, even if that aspect does not directly depend on the independent aspect.

[0091] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless expressly stated as limited to the singular.

Claims

1. An electronic device, the electronic device comprising: A substrate, the substrate comprising: At least two stacked embedded trace substrates (ETS). A first dielectric layer is disposed between an inward-facing surface of a first ETS and an inward-facing surface of a second ETS in the at least two stacked ETSs; and A first set of one or more metal connectors extends through the first dielectric layer and couples a first set of one or more metal structures at the inward-facing surface of the first ETS to a second set of one or more metal structures at the inward-facing surface of the second ETS.

2. The electronic device according to claim 1, wherein: The first group of one or more metal structures at the inward-facing surface of the first ETS includes one or more raised pads; as well as The second group of one or more metal structures at the inward-facing surface of the second ETS includes one or more embedded pads.

3. The electronic device of claim 2, wherein the first group of one or more metal structures extending through the first dielectric layer comprises: At least one metallized bump is disposed between at least one embedded pad in the one or more embedded pads of the second ETS and at least one raised pad in the one or more raised pads of the first ETS.

4. The electronic device according to claim 3, wherein: The at least one metallized bump is formed of a metal different from the metal used to form the one or more embedded pads and the one or more raised pads.

5. The electronic device according to claim 1, wherein: The first ETS includes a first outer surface, which includes one or more embedded pads disposed in a second dielectric layer.

6. The electronic device according to claim 5, further comprising: An integrated circuit (IC) component is disposed on the first outer surface of the first ETS and electrically connected to the one or more embedded pads of the first ETS.

7. The electronic device according to claim 6, wherein: The IC component is disposed on the first outer surface of the first ETS, and there is no solder mask layer on the first outer surface of the first ETS.

8. The electronic device according to claim 1, wherein: The second ETS includes a second outer surface, which includes one or more exposed embedded pads disposed in a third dielectric layer.

9. The electronic device according to claim 8, further comprising: One or more solder joints connect one or more exposed embedded pads to one or more metal terminals on a printed circuit board.

10. The electronic device according to claim 9, wherein: The second outer surface of the second ETS is disposed on the printed circuit board, and no intermediate solder mask layer is formed on the second outer surface of the second ETS.

11. The electronic device according to claim 1, wherein: The first ETS and the second ETS are each multi-layer ETS structures.

12. The electronic device according to claim 11, wherein: The first ETS is a three-layer ETS structure; The second ETS is a three-layer ETS structure; or Their combination.

13. The electronic device of claim 1, wherein the electronic device comprises at least one of the following: Music player; Video player; Entertainment section; Navigation equipment; Communication equipment; mobile device; Mobile phones; Smartphone; Personal digital assistant; Fixed-location terminal; Tablet computers, computers; Wearable devices; Laptop computers; server; Internet of Things (IoT) devices; or Equipment in motor vehicles.

14. A substrate, the substrate comprising: At least two stacked embedded trace substrates (ETS), wherein the at least two stacked embedded trace substrates (ETS) are stacked on top of each other; A first dielectric layer, wherein the first dielectric layer bonds the inward-facing surface of the first ETS of the at least two stacked ETSs to the inward-facing surface of the second ETS of the at least two stacked ETSs. as well as A first group of one or more metal structures extends through the first dielectric layer and connects the first group of one or more metal structures at the inward-facing surface of the first ETS to a second group of one or more metal structures at the inward-facing surface of the second ETS.

15. The substrate according to claim 14, wherein: The first group of one or more metal structures at the inward-facing surface of the first ETS includes one or more raised pads; as well as The second group of one or more metal structures at the inward-facing surface of the second ETS includes one or more embedded pads.

16. The substrate of claim 15, wherein the first group of one or more metal structures extending through the first dielectric layer comprises: At least one metallized bump is disposed between at least one embedded pad in the one or more embedded pads of the second ETS and at least one raised pad in the one or more raised pads of the first ETS.

17. The substrate according to claim 16, wherein: The at least one metallized bump is formed of a metal different from the metal used to form the one or more embedded pads and the one or more raised pads.

18. The substrate according to claim 14, wherein: The first ETS includes a first outer surface, which includes one or more embedded pads disposed in a second dielectric layer.

19. The substrate according to claim 14, wherein: The second ETS includes a second outer surface, which includes one or more exposed embedded pads disposed in a third dielectric layer.

20. The substrate according to claim 14, wherein: The first ETS and the second ETS are each multi-layer ETS structures.

21. The substrate according to claim 20, wherein: The first ETS is a three-layer ETS structure; The second ETS is a three-layer ETS structure; or Their combination.

22. A method for manufacturing a substrate, the method comprising: At least two stacked embedded trace substrates (ETS) are aligned and stacked on top of each other, wherein the at least two stacked ETSs include a first ETS and a second ETS, the first ETS having an inward-facing surface having a first set of one or more metal connectors, and the second ETS having an inward-facing surface having a first set of one or more metal structures. Align the first dielectric layer between the inward-facing surface of the first ETS and the inward-facing surface of the second ETS; as well as The inward-facing surfaces of the first ETS and the second ETS are bonded to the first dielectric layer, wherein the bonding connects at least one metal structure of one or more metal connectors in the first group at the inward-facing surface of the first ETS to at least one metal structure of one or more metal structures in the first group at the inward-facing surface of the second ETS.

23. The method of claim 22, wherein: The first group of one or more metal connectors at the inward-facing surface of the first ETS includes one or more raised pads; as well as The first group of one or more metal structures at the inward-facing surface of the second ETS includes one or more embedded pads.

24. The method according to claim 23, further comprising: At least one metallized bump is formed, the at least one metallized bump being disposed between at least one embedded pad of the second ETS and at least one raised pad of the first ETS.

25. The method of claim 24, wherein: The at least one metallized bump is formed of a metal different from the metal used to form the at least one embedded pad of the second ETS and the at least one raised pad of the first ETS.

26. The method according to claim 22, wherein: The first ETS includes a first outer surface having one or more embedded pads disposed in a second dielectric layer.

27. The method of claim 22, wherein: The second ETS includes a second outer surface having one or more exposed embedded pads disposed in a third dielectric layer.

28. The method according to claim 22, wherein: The first ETS and the second ETS are each multi-layer ETS structures.

29. The method of claim 22, further comprising: Forming the first ETS; as well as The second ETS is formed.

30. The method according to claim 29, wherein: The first ETS is formed as a three-layer ETS structure; The second ETS is formed as a three-layer ETS structure; or The first ETS and the second ETS each form a three-layer structure.

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