Pre-attached engineering solder for ultra-low residue soldering

Abstract

Some embodiments of this disclosure relate to a method comprising: placing a first solder preform and a first adhesive material between a first device and a second device to form a semiconductor assembly, the first adhesive material being configured to adhere a surface of the first device to a first surface of the first solder preform and to adhere a first surface of the second device to a second surface of the first solder preform opposite to the first surface; and reflowing the semiconductor assembly at a temperature above the solidus temperature of the first solder preform to bond the first device to the second device via at least the first solder preform. The first adhesive material has a reflow residual weight of less than 1% of the weight of the first adhesive material before reflowing the semiconductor assembly.

Description

[0001] Cross-references to related applications This application claims the benefit of U.S. Provisional Patent Application No. 63 / 618,800, filed January 8, 2024, entitled "Pre-attached engineered solders for ultra-low residue soldering," the entire contents of which are incorporated herein by reference. Background Technology

[0002] The manufacturing processes for soldering and sintering power modules have a significant impact on product cost, reliability, and lifespan. The adoption and rapid growth of electric vehicles in recent years have led to exponential growth in power module packaging. Semiconductor packagers are seeking innovative ways to meet this demand. As power module designers seek to improve reliability, the reliance on complex and expensive alignment tools is increasing.

[0003] The high-power semiconductor dies required for power modules generate excess heat, which must be transferred away from the dies. Heat is generated at the dies and flows through the component, away from the dies, to the base plate. Thermal interface materials can facilitate heat transfer towards the base plate.

[0004] For high-power, high-performance semiconductor packaging applications, voids in the solder joints should be minimized to prevent hot spots that could cause premature die degradation. Solder paste consists of solder powder, flux, solvent, and thixotropic agent. Using solder paste in these applications can lead to voids because the solvent is removed during the reflow process. Furthermore, volatile components in the solder paste may coat the inside of the furnace during reflow, causing frequent production stops for furnace cleaning. After reflow, if the volatile components of the solder paste are not removed during the reflow process, flux residues may remain on the printed circuit board (PCB), potentially causing short circuits.

[0005] One way to prevent excessive voids during reflow is to use solid, pre-formed solder preforms as an alternative to solder paste application. Typically, the solder preforms may still require a liquid flux coating to remove oxides that could prevent wetting. In this case, the liquid flux may leave undesirable residues on the PCB or on the joined components, which will need to be cleaned before the module is put into use.

[0006] Applying liquid flux to the surface of solid solder preforms during reflow can also contaminate the internal surfaces of the reflow oven. The oven must be periodically shut down to remove these flux residues from the internal surfaces, and no components should be produced during this time. If flux residue remains on the final component after the reflow and cleaning steps, it can bridge parts or connections, leading to short circuits or catastrophic failures during use.

[0007] When fixtures are needed to hold components together during reflow, bulky fixtures can prevent the reducing atmosphere during reflow from penetrating the components to remove oxides from the surfaces to be joined. Furthermore, the footprint required by the fixtures within the reflow oven limits the number of devices that can be reflowed in a single batch. The fixtures also act as heat sinks, requiring longer heating times for the reflow oven to reach peak temperatures.

[0008] Another problem when reflowing the die to the substrate is improper alignment. This can cause the die to tilt, which can be observed when uneven bonding lines appear between the die and the direct copper plating (DBC) after reflow. Other potential defects in the solder joints include mechanical stress, uneven heat transfer, and thermal stress, which can lead to delamination failure and shortened lifespan. Summary of the Invention

[0009] The techniques described in this article relate to ultra-low residue welding systems and methods.

[0010] In one embodiment, a method includes: placing a first solder preform and a first adhesive material between a first device and a second device to form a semiconductor assembly, the first adhesive material being configured to adhere a surface of the first device to a first surface of the first solder preform and to adhere a first surface of the second device to a second surface of the first solder preform opposite to the first surface; and reflowing the semiconductor assembly at a temperature above the solidus temperature of the first solder preform to bond the first device to the second device via at least the first solder preform, wherein the reflow residual weight of the first adhesive material is less than 1% of the weight of the first adhesive material before reflowing the semiconductor assembly.

[0011] In some embodiments, the first device is a semiconductor die; and a first adhesive material is placed between the first solder preform and the semiconductor die.

[0012] In some implementations, the second device is a DBC or a base plate; and the first adhesive material is placed between the first solder preform and the DBC or base plate.

[0013] In some implementations, the first device is a DBC; and a first adhesive material is placed between the first solder preform and the DBC.

[0014] In some implementations, the first component is a base plate; and a first adhesive material is placed between the first solder preform and the base plate.

[0015] In some embodiments, the method further includes: applying pressure to the semiconductor assembly before reflowing the semiconductor assembly to cause the surface of the first device to adhere to a first surface of the first solder preform via a first adhesive material, and causing the surface of the second device to adhere to a second surface of the solder preform via the first adhesive material.

[0016] In some implementations, reflowing the semiconductor assembly includes reflowing the semiconductor assembly without a mechanical clamp holding the semiconductor assembly together.

[0017] In some implementations, reflowing the semiconductor component includes heating the semiconductor component in the presence of an inert gas or a reducing gas.

[0018] In some embodiments, the inert gas or reducing gas includes nitrogen, argon, helium, hydrogen, formic acid, or forming gas.

[0019] In some implementations, reflowing a semiconductor assembly includes heating a first solder preform above its solidus point to metallurgically bond the semiconductor assembly.

[0020] In some implementations, reflowing the semiconductor component includes exposing the semiconductor component to a heat source at 230°C or higher for 20 to 240 seconds.

[0021] In some implementations, the reflow residual weight of the first adhesive material is less than 0.1% of the weight of the first adhesive material before reflowing the semiconductor component.

[0022] In some implementations, the first adhesive material is completely consumed during the reflow of the semiconductor component.

[0023] In some embodiments, the viscosity of the first viscous material is between 6 Kcps and 30 Kcps.

[0024] In some embodiments, the viscosity of the first adhesive material is between 260 grams and 410 grams.

[0025] In some implementations, reflowing a semiconductor assembly includes reflowing the semiconductor assembly without a flux coating on a first solder preform.

[0026] In some implementations, the reflow semiconductor assembly includes reflowing the semiconductor assembly with a low residual flux coating on a first solder preform.

[0027] In some embodiments, the first solder preform includes an internal matrix material whose solidus point is higher than that of the first solder preform.

[0028] In some implementations, the internal matrix material includes copper or silver.

[0029] In some embodiments, the solidus point of the internal matrix material is at least 100°C higher than the solidus point of the first solder preform.

[0030] In some embodiments, the solidus point of the internal matrix material is at least 500°C higher than the solidus point of the first solder preform.

[0031] In some implementations, the internal substrate material includes a coating.

[0032] In some embodiments, the first solder preform includes tin, silver, copper, antimony, lead, or indium.

[0033] In some embodiments, the method further includes placing a second solder preform and a second adhesive material between a second device and a third device to form a semiconductor assembly, the second adhesive material being configured to adhere a second surface of the second device, opposite to a first surface of the second device, to a first surface of the second solder preform, and to adhere a first surface of the third device to a second surface of the second solder preform, opposite to the first surface of the second solder preform.

[0034] In some embodiments, reflowing the semiconductor assembly includes reflowing the semiconductor assembly at temperatures above the solidus temperature of the first solder preform and above the solidus temperature of the second solder preform to bond the first device to the second device via at least the first solder preform, and to bond the second device to the third device via at least the second solder preform; and the reflow residual weight of the second adhesive material is less than 1% of the weight of the second adhesive material before reflowing the semiconductor assembly.

[0035] In one embodiment, a method includes: dispensing a sintering paste on a substrate, the sintering paste comprising a plurality of silver particles or copper particles; drying the sintering paste after dispensing to form a dried sintering paste; depositing an adhesive material on the dried sintering paste; placing a device on the adhesive material after depositing the adhesive material on the dried sintering paste to form a semiconductor assembly; and sintering the semiconductor assembly to form a sintered joint bonding the substrate and the device.

[0036] In one embodiment, a method includes: applying a thermal interface material (TIM) between a first device and a second device to form a semiconductor assembly, wherein a first surface of the TIM is in contact with a surface of the first device and a second surface of the TIM opposite to the first surface is in contact with a surface of the second device, the TIM comprising a flexible sheet material and first and second indium layers, the flexible sheet material comprising a braided layer formed of multiple filaments of metal, glass, or polymer fibers, the first and second indium layers being directly pressed against the braided layer, wherein the braided layer is sandwiched between the first and second indium layers; and applying pressure to the semiconductor assembly to bond the first device to the second device via the flexible sheet material.

[0037] Other features and aspects of the disclosed technology will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate, by way of example, the features of embodiments according to the disclosed technology. The summary is not intended to limit the scope of any invention described herein, which is defined by the claims and their equivalents.

[0038] It should be understood that all combinations of the foregoing concepts (provided that these concepts are not inconsistent with each other) are considered as part of the inventive subject matter disclosed herein. Specifically, all combinations appearing in the claimed subject matter are considered as part of the inventive subject matter disclosed herein. Attached Figure Description

[0039] The present disclosure according to one or more embodiments is described in detail below with reference to the accompanying drawings. The drawings are provided for illustrative purposes only and depict only exemplary embodiments. Furthermore, it should be noted that the elements in the drawings are not necessarily drawn to scale for clarity and ease of explanation.

[0040] The accompanying figures illustrate various embodiments of the disclosed technology from different perspectives. Although the accompanying descriptive text may refer to such views as “top view,” “bottom view,” or “side view,” such references are merely descriptive and, unless expressly stated otherwise, do not imply or require that the disclosed technology be implemented or used in a particular spatial orientation.

[0041] Figure 1 A side view of a semiconductor component according to some embodiments of the present disclosure is shown.

[0042] Figure 2 It shows Figure 1 A top view of the semiconductor components.

[0043] Figure 3 This is an operational flowchart illustrating an example method of assembling a semiconductor component using one or more solder preforms and adhesive materials according to some embodiments of this disclosure.

[0044] Figure 4An example side view of a semiconductor assembly in which a semiconductor die is bonded to a substrate using sintering paste and adhesive materials according to some embodiments of the present disclosure is shown.

[0045] The accompanying drawings are not exhaustive and do not limit this disclosure to the precise form disclosed. Detailed Implementation

[0046] As described above, the use of solid, pre-formed solder preforms during reflow soldering introduces various defects. These defects may include undesirable residues from the liquid flux used to coat the solder preforms, contamination of the reflow oven by the liquid flux, the use of bulky jigs to hold semiconductor components together during reflow, and / or incorrect alignment of the semiconductor die with the substrate. The systems and methods described herein relate to eliminating these defects while simplifying the assembly process and providing greater throughput through the reflow oven. According to some embodiments of this disclosure, a residue-free or low-residue adhesive material applied to the components eliminates the need for custom jigs and tooling during soldering. This adhesive enables excellent soldering and sintering results without post-processing cleaning steps. It is compatible with solder preforms using a nitrogen atmosphere (with or without a reducing atmosphere) and fluxless reflow techniques. Therefore, by utilizing this adhesive material technology, substrates, preforms, and other device components can be pre-attached to the package for later assembly, thereby simplifying the final manufacturing process. These and other embodiments are further described below.

[0047] Figures 1-2 A semiconductor component 600 according to some embodiments of the present disclosure is shown. Figure 1 A side view of the semiconductor component 600 is shown, and Figure 2 A top view of semiconductor component 600 is shown. The semiconductor component can be a part of a power module. Power modules can be used in inverters of electric vehicles, wind turbines, solar panels, or other devices. They can also be used with devices for power conversion, including motor drives, power supplies, etc. Semiconductor component 600 can also be a part of other types of modules.

[0048] Semiconductor assembly 600 includes a semiconductor die 100, a DBC layer 400, a base plate 500, an adhesive material 200 for aligning and / or securing assembly components, a solder preform 300 for bonding the semiconductor die 100 to the DBC layer 400, and a solder preform 350 for bonding the DBC layer 400 to the base plate 500. To eliminate or otherwise reduce the need for custom-made fixtures during soldering and assembly of the semiconductor assembly 600, the semiconductor assembly 600 is assembled using the adhesive material 200, which leaves no residue or minimal residue, and can be configured to temporarily bond and / or align the various components of the semiconductor assembly 600 during reflow.

[0049] The viscous material 200 may be composed of polyethylene glycol ether and / or alcohol. In some embodiments, the viscosity of the viscous material 200 ranges from about 6 Kcps to 30 Kcps. In some embodiments, the viscosity of the viscous material 200 ranges from about 260 g to about 410 g. In some embodiments, the reflow residual weight of the viscous material 200 is less than 1% of the weight of the viscous material before reflow. In some embodiments, the reflow residual weight of the viscous material 200 is less than 0.1%. In some embodiments, the reflow residual weight of the viscous material 200 is approximately zero, provided that a sufficient reflux peak temperature is maintained for a sufficient amount of time. For example, when the reflux peak temperature is maintained in the range of about 20 seconds to 240 seconds, the reflow residual weight can be zero. In some embodiments, the shelf life of the viscous material 200 is greater than 6 months when stored at 0°C–30°C.

[0050] The adhesive material 200 can be compatible with dispensing and other deposition methods. For example, the adhesive material 200 can be applied by screen printing, spin coating, spraying, brushing, or any other method suitable for coating the semiconductor die 100 and other parts of the assembly 600 with the adhesive material 200.

[0051] During operation, the semiconductor die 100 generates heat, which needs to be dissipated away from the die 100 to maximize its efficiency and lifespan. The semiconductor die 100 may be made of materials such as silicon, silicon carbide, gallium arsenide, gallium nitride, gallium oxide, indium phosphide, or germanium selenide. In some embodiments, the semiconductor die 100 may contain a metallization layer. The DBC 400 may be made of a ceramic insulator, such as alumina or aluminum nitride, between two sheets of pure copper that bond together when exposed to sufficient temperatures. The copper sheets can be bonded to the ceramic via diffusion bonding. A pre-bonded DBC 400 can be obtained prior to assembling the semiconductor assembly 600.

[0052] Solder preforms 300 and 350 are used to metallurgically bond semiconductor components 600 together. Solder preforms 300 and 350 may be made of tin, silver, copper, antimony, lead, indium, or combinations or alloys thereof. Examples of such compositions include tin-silver-copper-antimony, tin-antimony, and high-lead alloys. In some embodiments, solder preforms 300 and 350 may be made of different materials.

[0053] In some implementations, such as Figures 1-2As described, solder preforms 300 and 350 may contain a base material 310 whose solidus point is higher than that of the metal or metal alloy constituting solder preforms 300 and 350. The solidus point of the base material 310 may be at least 100°C higher than that of the solder preforms 300 and 350. In some embodiments, the solidus point of the base material 310 may be at least 500°C higher than that of the solder preforms 300 and 350. The base material 310 may be made of copper, silver, or another metal or metal alloy, wherein the solidus point of the material constituting the base material 310 is higher than that of one or more metals constituting the solder preforms 300 and 350. The internal base material 310 may remain solid during reflow. It may be desirable to select a specific height of base material 310 to maintain a desired bond line thickness distance between the two joined components.

[0054] The substrate material 310 can be in the form of a mesh made of wires, braids, strips, or foil, where intersecting nodes form the substrate 310 within solder preforms 300 and 350. The substrate material 310 may have a coating on its outer surface to promote wetting and prevent void formation. In embodiments where the substrate material 310 is in the form of a mesh, the distance between the nodes of the mesh can range from 200 micrometers to 10,000 micrometers. Depending on the overall dimensions of the solder preforms 300 and 350, the width of the substrate material 310 forming the mesh can range from 20 micrometers to several millimeters. The height of the substrate material 310 can range from 30 micrometers to 800 micrometers. In some embodiments, the height of the substrate material 310 can range from 50 micrometers to 250 micrometers, provided that the height is the same within each individual solder preform 300 or 350 to ensure consistent spacing between the parts to be joined. Depending on the total solder volume required to metallurgically bond the surfaces to be joined, solder preforms 300 or 350 may further increase the total height of the part by 50 micrometers or more. In some embodiments, solder preforms 300 and / or solder preforms 350 do not include the base material 310.

[0055] During assembly, semiconductor assembly 600 can be temporarily held together by adhesive material 200 between each layer from semiconductor die 100 to substrate 500. Semiconductor die 100 can be held to solder preform 300. Solder preform 300 can be held to DBC 400. DBC 400 can be held to solder preform 350. Solder preform 350 can be held to substrate 500. While adhesive material 200 may not be configured to provide a conductive or thermal path from semiconductor die 100 to substrate 500, it can temporarily hold assembly 600 together without requiring mechanical clamping during reflow. During reflow, in an inert or reducing atmosphere, after exposure to sufficiently high temperatures (e.g., about 230°C), adhesive material 200 can be completely consumed during the reflow process without residue. Once the furnace temperature reaches a level sufficient to melt solder preforms 300 and 350, the assembly 600 can be removed from the furnace and cooled to below the solidus line of the reflowed solder preforms 300 and 350.

[0056] Although the illustrated example shows a semiconductor assembly 600 having two heat-transferring TIM layers (including TIM1 layer (solder preform 300) and TIM2 layer (solder preform 350)) used with adhesive material 200, it should be understood that the techniques described herein can be used for other semiconductor assemblies. The techniques described herein can be used for semiconductor assemblies having a single TIM. For example, a solder preform can be used as a TIM0 layer to transfer heat generated by a semiconductor die to a heat sink. In such an arrangement, adhesive material can be deposited on both sides of the TIM0 layer and / or the component to which it is attached. Furthermore, although the illustrated example is described in the context of applying adhesive material 200 to two TIM layers (solder preforms 300 or 350), in some embodiments, adhesive material may be applied to only one of the TIM layers.

[0057] Figure 3This is an operational flowchart illustrating an example method of assembling a semiconductor assembly (e.g., semiconductor assembly 600) using one or more solder preforms and adhesive material according to some embodiments of this disclosure. Operation 310 includes placing each solder preform and adhesive material between components of the semiconductor assembly to be bonded. The adhesive material may be applied or otherwise dispensed onto the surface of the solder preform and / or the surface of the semiconductor component on which the solder preform is placed. Before placing each solder preform, the adhesive material may be applied to the surfaces of both the solder preform and the semiconductor component, applied only to the surface of the semiconductor component, or applied only to the surface of the solder preform. In some embodiments, the adhesive material may be used to pre-attach at least some of the solder preforms to the respective semiconductor components for later assembly and reflow of the semiconductor package. Any suitable method may be used to dispense or otherwise apply the adhesive material to the surface, including screen printing, spin coating, spraying, brushing, etc.

[0058] As an example, when assembling the semiconductor assembly 600, a first solder preform 300 and adhesive material 200 can be placed between the back side of the semiconductor chip 100 and the first side of the DBC 400, and a second solder preform 350 and adhesive material 200 can be placed between the DBC 400 and the substrate 500. More specifically, adhesive material 200 can be deposited onto the back side of the semiconductor die 100 and / or the first side of the solder preform 300, and then the back side of the die 100 can be placed near the first side of the solder preform 300 such that the adhesive material 200 is in contact with the back side of the semiconductor die 100 and the first side of the solder preform 300. The adhesive material 200 can then be deposited onto the second side of the solder preform 300 opposite to the first side attached to the semiconductor die 100 and / or the first side of the DBC 400, and the first side of the DBC 400 can be positioned near the second side of the solder preform, such that the adhesive material 200 is in contact with the second side of the solder preform 300 and the first side of the DBC 400. The adhesive material 200 can then be deposited onto the first side of the solder preform 350 and / or the second side of the DBC 400 opposite to the first side attached to the solder preform 300, and the first side of the solder preform 350 can be positioned near the second side of the DBC 400, such that the adhesive material 200 is in contact with the first side of the solder preform 350 and the second side of the DBC 400. The adhesive material 200 can then be deposited onto the second side of the solder preform 350 opposite to the first side attached to the DBC 400 and / or the first side of the base plate 500, and the first side of the base plate 500 can be placed near the second side of the solder preform 350 such that the adhesive material 200 is in contact with the second side of the solder preform 350 and the first side of the base plate 500.

[0059] Operation 320 includes applying pressure to the assembly to connect semiconductor components using an adhesive material. For example, during the assembly of semiconductor assembly 600, pressure may be applied to use adhesive material 200 to connect semiconductor chip 100 to a first side of solder preform 300, a second side of solder preform 300 to a first side of DBC 400, a second side of DBC 400 to a first side of solder preform 350, and a second side of solder preform 350 to a first side of substrate 500.

[0060] Operation 330 includes reflowing solder preforms of the semiconductor assembly to bond components of the semiconductor assembly together. For example, semiconductor assembly 600 may be placed in a furnace to reflow first and second solder preforms 300 and 350 to metallurgically bond semiconductor assembly 600 together. The semiconductor assembly may be placed in an inert or reducing atmosphere furnace. The inert or reducing atmosphere may consist of nitrogen, argon, helium, hydrogen, formic acid, forming gases, or combinations thereof. During reflow, the adhesive material holds the components of the semiconductor assembly in place, ensuring proper alignment of the components and eliminating the need for mechanical clamps to hold the assembly together.

[0061] The reflow temperature can be higher than the solidus point of one or more solder preforms. In a specific embodiment, the semiconductor component is exposed to a heat source at 230°C or higher for 20 to 240 seconds. After the component is exposed to a heat source higher than the solidus point of the solder preform, the component can be metallurgically bonded. The solder preform of the component may have no flux coating on its surface or have a low residual flow coating on its surface.

[0062] Therefore, by using the adhesive material 200 to hold the various components of the semiconductor assembly 600 in place during reflow, proper alignment of the components of the semiconductor assembly 600 can be ensured, and the need for mechanical fixtures can be eliminated. Using the adhesive material 200 instead of bulky fixtures can significantly increase the throughput of devices sent through the reflow oven in a given time. In some embodiments, the adhesive material 200 can be formulated such that it is completely consumed during the reflow process, leaving no adhesive material-related residue on the semiconductor assembly 600.

[0063] Because the viscous material 200 eliminates the need for mechanical clamps during reflow, reducing atmospheric gas can easily penetrate the clamp-free assembly 600 to remove oxides from the surfaces to be joined during reflow. This, in turn, eliminates the need for a liquid flux coating on the solder preforms 300 and 350. The reflow assembly 600, operating without flux or with ultra-low flux residue, reduces or eliminates the need for a cleaning assembly 600 to remove any flux residue after reflow, and eliminates many of the aforementioned problems associated with flux residue.

[0064] In some implementations, solder preforms can be pre-attached to components of a semiconductor device prior to final package assembly using the adhesive materials described herein. Specifically, by utilizing this adhesive material technology, substrates, preforms, and other device components can be pre-attached to the package for later assembly, thereby simplifying the final manufacturing process.

[0065] Indium-woven fabrics - Indium TIM In some implementations, indium-braided indium-indium TIM can be used to assemble semiconductor components, which can be manufactured in foil form. Thermally conductive indium-braided indium-indium TIM can be used in place of solder preforms to assemble semiconductor components. One such example of a foil is described with reference to U.S. Patents 4,968,550 and 5,052,611. The thermally conductive foil can be assembled as follows: A braid, i.e., a woven or woven filament sheet of metal, glass, or polymer fibers, can be appropriately cleaned and pretreated, and coated with upper and lower layers of indium strips. The assembly of the braid with the upper and lower indium strips can be performed between upper and lower pressure rollers to produce an indium / braided / indium sandwich structure. The thickness of the resulting sandwich structure can be greater than, equal to, or less than the thickness of the original braid. The indium in the strips can be self-soldering. That is, material processing between the rollers causes indium to flow through the gaps and spaces between the filaments of the braid, and then the indium from the strip is combined with the indium from the strip. This completely embeds the filaments in indium. The sandwich structure can have a smooth indium surface. Furthermore, when cutting the sandwich structure, indium flows at the edges to cover any filament ends at the edges. Indium braided sandwich structures can be used as conductive foil strips.

[0066] The thermally conductive foil can be pre-attached to one of the TIM locations in the semiconductor component. It can be pre-attached using an adhesive material (e.g., adhesive material 200) or by pressure application utilizing the adhesive properties of indium. The thermally conductive foil is not reflowed but is applied via pressure. In embodiments where an adhesive material is used in combination with a thermally conductive material, adhesive material residue will remain during device use due to the non-reflow property.

[0067] sintering In some embodiments, the adhesive material described herein can be used in combination with a sintering paste to sinter semiconductor components. The sintering paste may contain a solvent and metal sintering particles, such as silver particles, copper particles, or some combination thereof. The sintering paste may also contain spacer particles having an average particle size or diameter within the target bond line thickness range. Specific examples of sintering pastes that can be used in combination with adhesive materials are described with reference to U.S. Patent Application No. 15 / 460,023, which is incorporated herein by reference.

[0068] For example, a sintering paste can be formed by combining spacer particles with Ag particles and a solvent, such that the spacer particles constitute more than 0 wt% to less than 4 wt% of the composition. The average particle size or diameter of the Ag particles can be from 10 nm to 100 μm. The Ag particles can constitute 50 wt% to 95 wt% of the sintering paste mixture. The solvent can be polyethylene glycol solvent or other suitable sintering solvent.

[0069] The target bonding line thickness range can be achieved by adding spacer particles having an average particle size or diameter within the target bonding line thickness range. The target bonding line thickness of the silver junction can be between 30 μm and 500 μm. In a preferred embodiment, the bonding line thickness is 50 μm to 300 μm, and more specifically 60 μm to 100 μm.

[0070] The spacer particles can be single-component metal particles, such as gold, silver, or copper. In alternative embodiments, the spacer particles are provided by means of solder balls. In these embodiments, the solder balls can be Sn-Pb or lead-free solder balls, such as, for example, Sn-Ag-Cu solder balls, such as SAC 105, SAC 205, SAC 305, SAC 387, etc. In further embodiments, the spacer particles are inorganic particles, such as boron nitride (BN), silicon dioxide (SiO2), aluminum oxide (Al2O3), etc.

[0071] Figure 4An example side view of a semiconductor assembly 800 is shown, in which a semiconductor die 810 is bonded to a substrate 840 using sintering paste 830 and adhesive material 820. During assembly, sintering paste 830 may be deposited (e.g., printed) onto the substrate 840. The sintering paste 830 may then be dried at a sufficient temperature (e.g., about 40°C) for a sufficient amount of time (e.g., about 30 minutes). Adhesive material 820 may be added to the dried sintering paste 830. Subsequently, the semiconductor die 810 may be placed onto the adhesive material 820 to hold the die in place. The sintering paste 830 may be sintered using pressure alone (without heating) at about room temperature (e.g., about 25°C) to form a bond between the die 810 and the substrate 840. In some embodiments, the assembly is sintered at a pressure between 5 and 35 psi. In embodiments, a pick-and-place tool may be used to apply pressure. In the case of sintering at room temperature, adhesive material residue may remain when the device is used. In some implementations, the components can be sintered at a target sintering temperature and then cooled.

[0072] One advantage of using the adhesive material described above during the sintering process is that it avoids the defect risk associated with potential movement / misalignment of semiconductor components after the sintering paste 830 has dried but before pressure is applied to the assembly. Such movement of components can be caused by normal handling of the components, including, for example, transport on a conveyor belt. The sintering paste itself does not prevent this movement before pressure is applied to sinter the components together. By using the adhesive material 820 to adhere the components together, the risk associated with potential movement of the components is eliminated.

[0073] While various embodiments of the disclosed technology have been described above, it should be understood that they have been presented by way of example only and not by way of limitation. Similarly, various diagrams may depict exemplary architectures or other configurations of the disclosed technology, which helps in understanding the features and functionality that may be included in the disclosed technology. The disclosed technology is not limited to the illustrated exemplary architectures or configurations, but various alternative architectures and configurations can be used to implement the desired features. Furthermore, regarding flowcharts, descriptions of operation, and method claims, unless the context otherwise requires, the order in which the steps are presented herein should not compel the various embodiments to perform the described functions in the same order.

[0074] Although the disclosed technology has been described above with reference to various exemplary embodiments and implementations, it should be understood that the various features, aspects, and functionalities described in one or more individual embodiments are not limited to their applicability to the specific embodiments in which they are described, but can be applied individually or in various combinations to one or more other embodiments of the disclosed technology, whether or not those embodiments are described, and whether or not such features are presented as part of the described embodiments. Therefore, the breadth and scope of the technology disclosed herein should not be limited by any of the exemplary embodiments described above.

[0075] Unless otherwise expressly stated, the terms and phrases used in this document and their variations thereof should be interpreted as open-ended rather than restrictive. As examples of the foregoing: the term “including” should be understood to mean “including, but not limited to”, etc.; the term “example” is used to provide exemplary instances of the items discussed, not an exhaustive or restrictive list thereof; the term “a (or an)” should be understood to mean “at least one,” “one or more,” etc.; adjectives such as “conventional,” “traditional,” “normal,” “standard,” “known,” and terms with similar meanings should not be interpreted as limiting the described items to those available up to a given time period, but rather should be understood to cover conventional, traditional, normal, or standard techniques available or known at any time now or in the future. Similarly, where this document relates to techniques obvious or known to a person skilled in the art, such techniques cover those techniques obvious or known to a person skilled in the art at any time now or in the future.

[0076] In some cases, the presence of expanded words and phrases such as “one or more,” “at least,” “but not limited to,” or other similar phrases should not be interpreted as indicating a narrower scope intended or required where such expanded phrases may not exist.

[0077] Furthermore, various embodiments described herein are illustrated with reference to exemplary block diagrams, flowcharts, and other illustrative figures. As will become apparent to those skilled in the art upon reading this document, the illustrated embodiments and various alternatives thereof may be practiced without limitation of the illustrated examples. For instance, the block diagrams and accompanying descriptions should not be construed as requiring a specific architecture or configuration.

[0078] It should be understood that all combinations of the foregoing concepts (provided that these concepts are not inconsistent with each other) are considered as part of the inventive subject matter disclosed herein. Specifically, all combinations of the claimed subject matter appearing in this disclosure are considered as part of the inventive subject matter disclosed herein.

Claims

1. A method comprising: A first solder preform and a first adhesive material are placed between a first device and a second device to form a semiconductor assembly. The first adhesive material is configured to cause the surface of the first device to adhere to a first surface of the first solder preform, and to cause the first surface of the second device to adhere to a second surface of the first solder preform opposite to the first surface. as well as The semiconductor assembly is reflowed at a temperature above the solidus temperature of the first solder preform to bond the first device to the second device via at least the first solder preform, wherein the reflow residual weight of the first adhesive material is less than 1% of the weight of the first adhesive material before reflowing the semiconductor assembly.

2. The method according to claim 1, wherein: The first device is a semiconductor die; and The first adhesive material is placed between the first solder preform and the semiconductor die.

3. The method according to claim 2, wherein: The second device is a DBC or a baseboard; and Furthermore, the first adhesive material is placed between the first solder preform and the DBC or base plate.

4. The method according to claim 1, wherein: The first device is a DBC; and The first adhesive material is placed between the first solder preform and the DBC.

5. The method according to claim 1, wherein: The first device is a base plate; and The first adhesive material is placed between the first solder preform and the base plate.

6. The method of claim 1, further comprising: Before reflowing the semiconductor assembly, pressure is applied to the semiconductor assembly to cause the surface of the first device to adhere to the first surface of the first solder preform via the first adhesive material, and to cause the surface of the second device to adhere to the second surface of the solder preform via the first adhesive material.

7. The method of claim 6, wherein reflowing the semiconductor assembly comprises: The semiconductor components are reflowed without mechanical clamps holding them together.

8. The method of claim 7, wherein reflowing the semiconductor component comprises heating the semiconductor component in the presence of an inert gas or a reducing gas.

9. The method according to claim 8, wherein the inert gas or reducing gas includes nitrogen, argon, helium, hydrogen, formic acid, or a forming gas.

10. The method of claim 6, wherein reflowing the semiconductor component comprises heating the first solder preform above its solidus point to metallurgically bond the semiconductor component.

11. The method of claim 10, wherein reflowing the semiconductor component comprises exposing the semiconductor component to a heat source at 230°C or higher for 20 to 240 seconds.

12. The method of claim 1, wherein the reflow residual weight of the first adhesive material is less than 0.1% of the weight of the first adhesive material before reflowing the semiconductor component.

13. The method of claim 10, wherein the first viscous material is completely consumed during the reflow of the semiconductor component.

14. The method of claim 1, wherein the viscosity of the first viscous material is from 6 Kcps to 30 Kcps.

15. The method of claim 1, wherein the viscosity of the first adhesive material is from 260 g to 410 g.

16. The method of claim 1, wherein reflowing the semiconductor assembly comprises: The semiconductor assembly is reflowed without a flux coating on the first solder preform.

17. The method of claim 1, wherein reflowing the semiconductor assembly comprises: The semiconductor assembly is reflowed with a low residual flux coating on the first solder preform.

18. The method according to claim 1, wherein the first solder preform includes an internal matrix material, the solidus point of the internal matrix material being higher than the solidus point of the first solder preform.

19. The method of claim 18, wherein the internal matrix material comprises copper or silver.

20. The method of claim 18, wherein the solidus point of the internal matrix material is at least 100° higher than the solidus point of the first solder preform.

21. The method of claim 18, wherein the solidus point of the internal matrix material is at least 500°C higher than the solidus point of the first solder preform.

22. The method of claim 18, wherein the internal substrate material comprises a coating.

23. The method of claim 1, wherein the first solder preform comprises tin, silver, copper, antimony, lead, or indium.

24. The method of claim 1, further comprising: A second solder preform and a second adhesive material are placed between the second device and the third device to form the semiconductor assembly. The second adhesive material is configured to adhere the second surface of the second device, which is opposite to the first surface of the second device, to the first surface of the second solder preform, and to adhere the first surface of the third device to the second surface of the second solder preform, which is opposite to the first surface of the second solder preform.

25. The method of claim 24, wherein: Reflowing the semiconductor assembly includes reflowing the semiconductor assembly at temperatures above the solidus temperature of the first solder preform and above the solidus temperature of the second solder preform to bond the first device to the second device via at least the first solder preform, and to bond the second device to the third device via at least the second solder preform; and The reflow residual weight of the second adhesive material is less than 1% of the weight of the second adhesive material before reflowing the semiconductor component.

26. A method comprising: A sintering paste is applied onto a substrate, the sintering paste comprising a plurality of silver or copper particles; After dispensing the sintering paste, the sintering paste is dried to form a dry sintering paste; The viscous material is deposited onto the dried sintering paste; After the adhesive material is deposited on the dried sintering slurry, the device is placed on the adhesive material to form a semiconductor assembly; as well as The semiconductor component is sintered to form a sintered joint that bonds the substrate and the device.

27. A method comprising: A thermal interface material (TIM) is applied between a first device and a second device to form a semiconductor assembly, wherein a first surface of the TIM is in contact with the surface of the first device and a second surface of the TIM opposite to the first surface is in contact with the surface of the second device. The TIM includes a flexible sheet material and first and second indium layers. The flexible sheet material includes a braided layer formed of multiple filaments of metal, glass, or polymer fibers. The first and second indium layers are directly pressed against the braided layer, wherein the braided layer is sandwiched between the first and second indium layers. as well as Pressure is applied to the semiconductor component to bond the first device to the second device via the flexible sheet material.

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