High-transmittance low-emissivity electrically heated low-e glass and method of making same

Abstract

The application discloses high-transmittance low-emissivity electric heating Low-E glass and a preparation method thereof, and belongs to the field of novel glass materials. x The Low-E glass comprises a glass substrate and, in sequence, a bottom medium layer, a first ZnO layer, a patterned Ag layer, a TiO x layer, a second ZnO layer, a SiN x top medium layer, a conductive grid layer and a SiO2 surface protection layer. The patterned Ag layer is a patterned structure formed by laser etching of the Ag layer and composed of a plurality of micron-level independent units, and the electromagnetic shielding loss is significantly reduced to 2-6 dB by cutting off the transverse continuous conductive channel; the conductive grid layer generates Joule heat under an applied voltage, and realizes the glass surface heating function. The application has high visible light transmittance (81%-87%) and low emissivity (0.07-0.14), and can be widely applied to the fields of energy-saving buildings, vehicle-mounted glass, intelligent windows and communication windows.

Description

Technical Field

[0001] This invention relates to the field of novel glass materials, specifically to a high-transmittance, low-emissivity electrically heated Low-E glass and its preparation method. Background Technology

[0002] Low-E glass is a functional glass made by depositing a nanofilm layer with infrared reflective properties on the glass surface. This allows it to reduce the transmission of mid- and far-infrared radiation while maintaining high visible light transmittance, thereby achieving energy-saving and heat-insulating effects. Most existing Low-E glasses use a dielectric layer / silver layer / dielectric layer composite film system. The silver layer, with its low emissivity and good conductivity, is the key functional layer for achieving energy-saving performance.

[0003] With the development of applications such as green buildings, new energy vehicles, rail transit, smart windows, and communication windows, Low-E glass is no longer limited to a single energy-saving function. It needs to possess comprehensive performance characteristics including high light transmittance, low emissivity, defogging and defrosting, electric heating, and wireless signal transmission. Especially in scenarios such as automotive glass, building curtain walls, airports, high-speed rail, and facilities surrounding communication base stations, the glass needs to minimize the attenuation of electromagnetic signals such as 5G, Wi-Fi, Bluetooth, navigation, ETC, and radar. However, the continuous silver layer in traditional Low-E glass, while reflecting infrared thermal radiation, also reflects and absorbs some electromagnetic waves, resulting in high electromagnetic shielding loss and severely affecting the normal transmission of wireless communication signals.

[0004] On the other hand, in environments with low temperature, high humidity, or large temperature differences, glass surfaces are prone to fogging, frosting, or icing, severely affecting lighting, visibility, and safety. Traditional defogging and defrosting methods typically rely on hot air, air conditioning, or external heating wires, which suffer from high energy consumption, slow response, uneven heating, significant visual obstruction, and low structural integration. If transparent electric heating can be achieved by utilizing the inherent conductivity of the Low-E film layer, rapid defogging, defrosting, and de-icing can be achieved without significantly affecting appearance and light transmittance. However, existing electrically heated Low-E glass still faces serious performance synergy challenges. To achieve better heating effects, the film layer needs a low sheet resistance; however, reducing resistance usually requires increasing the thickness of the metal layer or improving its continuity, which can easily lead to a significant decrease in visible light transmittance and significantly enhance the shielding effect against electromagnetic waves. At the same time, some heated glasses using conductive wires, metal meshes, ITO, or thick metal films also suffer from increased haze, visible patterns, complex processes, insufficient adhesion, poor weather resistance, or poor compatibility with Low-E film systems.

[0005] In summary, existing Low-E glass suffers from difficulties in achieving a balance between light transmittance, low emissivity, electromagnetic signal transmission, and electric heating functionality. There is an urgent need to develop a Low-E glass with a simple structure, stable manufacturing process, and synergistic performance, along with its fabrication method. By optimizing the film structure of the dielectric layer, low-emissivity conductive layer, and protective layer, it is possible to significantly reduce electromagnetic shielding losses while ensuring high visible light transmittance and low emissivity. Furthermore, controllable conductivity can be used to achieve low-voltage electric heating functionality, thus meeting the application requirements of energy-efficient buildings, automotive glass, smart windows, communication windows, and anti-fogging and defrosting applications. Summary of the Invention

[0006] The purpose of this invention is to provide a high-transmittance, low-emissivity electrically heated Low-E glass and its preparation method, so as to solve the problem that existing Low-E glass is difficult to coordinate in terms of transmittance, low emissivity, electromagnetic signal transmission and electric heating function.

[0007] To achieve the above objectives, the specific solution adopted by the present invention is as follows: In a first aspect, the present invention provides a high-transmittance, low-emissivity electrically heated Low-E glass, comprising a glass substrate and a composite film system disposed on the surface of the glass substrate, wherein the composite film system comprises sequentially stacked components: SiN x Bottom dielectric layer; The first ZnO layer is disposed on the SiN x Bottom dielectric layer surface; A patterned Ag layer is disposed on the surface of the first ZnO layer. The patterned Ag layer is composed of multiple arrayed, electrically insulated micron-sized independent units, and there are etched trenches between adjacent micron-sized independent units. TiO x A layer is formed by filling the etched trenches of the patterned Ag layer and covering the surface of the patterned Ag layer. The second ZnO layer is disposed on the TiO. x Layer surface; SiN x The top dielectric layer is disposed on the surface of the second ZnO layer; A conductive gate layer is disposed on the SiN x The surface of the top dielectric layer is used to generate Joule heating when a voltage is applied; A SiO2 surface protective layer is filled within the conductive gate layer and covers the surface of the conductive gate layer.

[0008] Furthermore, the SiN x The thickness of the bottom dielectric layer is 25-32 nm; The thickness of the first ZnO layer is 6-8 nm; The patterned Ag layer has a thickness of 8-10 nm, the micron-level independent units are square with a side length of 30-100 μm, and the etched trenches have a width of 1.5-4 μm. The TiO x The thickness of the layer on the surface of the patterned Ag layer is 18-20 nm; The thickness of the second ZnO layer is 8-12 nm; The SiN x The thickness of the top dielectric layer is 25-35 nm; The conductive gate layer is composed of multiple copper wires, and its structure is a crisscrossing grid structure or a parallel bar gate structure; the thickness of the conductive gate layer is 500nm-1μm, the line width of the copper wires is 15-20μm, and the spacing between two adjacent parallel copper wires is 1.8-2.2cm. The thickness of the SiO2 surface protective layer on the upper surface of the conductive gate layer is 18-25 nm.

[0009] Furthermore, the Low-E glass has a visible light transmittance of 81%-87%, an emissivity of 0.07-0.14, and an average electromagnetic shielding loss of 2-6 dB in the frequency range of 0.1-18 GHz.

[0010] Furthermore, the Low-E glass can reach a surface temperature of 45-100°C when driven by a DC voltage of 12-24V.

[0011] Secondly, the present invention provides a method for preparing the above-mentioned Low-E glass, comprising the following steps: Step S1: Clean and surface activate the glass substrate; Step S2: Deposit SiN on the surface of the glass substrate using a magnetron sputtering process. x Bottom dielectric layer; Step S3, in the SiN x The first ZnO layer is deposited on the surface of the bottom dielectric layer using a magnetron sputtering process; Step S4: Deposit an Ag layer on the surface of the first ZnO layer using a magnetron sputtering process; Step S5: The Ag layer is patterned using a laser etching process. The Ag layer is etched into multiple arrayed micron-level independent units that are electrically insulated from each other. An etching trench is formed between adjacent micron-level independent units that penetrates the Ag layer, thus obtaining the patterned Ag layer. Step S6: Deposit TiO2 sequentially on the patterned Ag layer surface using magnetron sputtering. x Layer, second ZnO layer and SiN x Top dielectric layer, the TiO xThe layer fills the etched trenches and covers the surface of the patterned Ag layer; Step S7, in the SiN x A conductive gate layer is fabricated on the surface of the top dielectric layer, wherein the linewidth of the conductive gate layer is 15-20 μm and the spacing between adjacent conductive lines is 1.8-2.2 cm; Step S8: A SiO2 surface protective layer is deposited on the surface of the conductive gate layer using a magnetron sputtering process. The SiO2 surface protective layer fills the conductive gate layer and covers the conductive gate layer.

[0012] Further, in step S2, SiN is deposited. x The process parameters for the bottom dielectric layer are as follows: the target material is Si3N4 target, the sputtering power is 80-120W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:1. In step S3, the process parameters for depositing the first ZnO layer are as follows: the target material is a ZnO target, the sputtering power is 80-120W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 10:1.

[0013] Furthermore, in step S4, the process parameters for depositing the Ag layer are as follows: the target material is an Ag target, the sputtering power is 50-100W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is argon. In step S5, a 355nm ultraviolet nanosecond laser is used to pattern the Ag layer. The laser pulse width is 15-25ns, the repetition frequency is 40-60kHz, the scanning speed is 350-600mm / s, and the single pulse energy is 10-20μJ. The Ag layer is etched into multiple micron-level independent units, the width of the etching trench is 2-4μm, and the etching depth penetrates the entire Ag layer.

[0014] Further, in step S6, TiO is deposited. x The process parameters for the layer are as follows: the target material is TiO2 target, the sputtering power is 30-50W, the working pressure is 0.8-1.2Pa, and the deposition gas is argon. In step S6, the process parameters for depositing the second ZnO layer are as follows: the target material is a ZnO target, the sputtering power is 80-120W, the working pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 10:1. In step S6, SiN is deposited. x The process parameters for the top dielectric layer are as follows: the target material is Si3N4 target, the sputtering power is 80-120W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:1.

[0015] Furthermore, in step S7, the fabrication process of the conductive gate layer is a photolithography-electroplating process or a photolithography-magnetron sputtering lift-off process.

[0016] Furthermore, in step S8, the process parameters for depositing the SiO2 surface protective layer are as follows: the target material is a Si target, the sputtering power is 80-120W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 8:1.

[0017] The functions of each layer in the composite membrane system of this invention are as follows: SiN x Bottom dielectric layer: serves as an antireflective layer, barrier layer, and adhesion enhancement layer. SiN x The bottom dielectric layer can block sodium in the glass + Ions diffuse into the interior of the membrane to prevent Na+ from being absorbed into the membrane. + It causes corrosion and damage to the Ag layer; at the same time, SiN x The bottom dielectric layer, as a bottom antireflective layer, can improve visible light transmittance and enhance the adhesion between the film layer and the glass substrate.

[0018] The first ZnO layer is used to improve the film quality of the Ag layer and regulate optical matching. The first ZnO layer can induce continuous Ag film formation, reduce the surface roughness of the Ag layer, and improve the interaction between the Ag layer and SiN. x The interface matching between the bottom dielectric layers provides a good wetting surface for the uniform growth of the Ag layer.

[0019] Patterned Ag layer: As the core low-emissivity functional layer of Low-E glass, it reflects mid- and far-infrared thermal radiation and reduces the glass's emissivity. By laser etching the Ag layer, continuous Ag layers are formed into micron-sized independent units that are insulated from each other. This cuts off the lateral continuous conductive channels of the Ag layer, reducing the film's reflection and shielding effect on electromagnetic waves, and improving electromagnetic wave transmittance. The etching trenches between adjacent micron-sized independent units penetrate the entire Ag layer without damaging the first ZnO layer.

[0020] TiO x Layer: Used to protect the patterned Ag layer, preventing Ag from being oxidized, bombarded, or agglomerated during subsequent sputtering. TiO x The layer fills the etched trenches of the patterned Ag layer and covers the surface of the patterned Ag layer, thus providing comprehensive protection for the patterned Ag layer.

[0021] Second ZnO layer: with TiO x Layer, SiN xThe top dielectric layer together constitutes a multi-layer dielectric system above the patterned Ag layer. The multi-layer anti-reflection design improves optical matching, increases visible light transmittance, and modulates the film color.

[0022] SiN x Top dielectric layer: Used to further improve the mechanical stability, environmental stability, and optical matching effect of the film. SiN x The top dielectric layer serves as an outer protective layer, enhancing the film's wear resistance and environmental corrosion resistance.

[0023] Conductive grid layer: Used to form a low-resistance transparent electric heating path, generating Joule heating under an applied voltage to achieve defogging, defrosting, de-icing, and auxiliary thermal management functions on the glass surface. The conductive grid layer consists of multiple copper wires, with a crisscrossing grid structure or parallel bar grid structure. Due to the small linewidth (15-20μm) and large spacing (1.8-2.2cm) of the copper wires, it has little impact on visible light transmittance and electromagnetic wave transmittance. In use, the bus electrodes at both ends of the conductive grid layer are connected to an external power supply. Driven by an applied DC voltage, current is introduced into the conductive grid layer through the bus electrodes, generating Joule heating to achieve the heating function of the glass surface.

[0024] SiO2 surface protective layer: As a surface antireflection layer and protective layer, it is used to improve visible light transmittance, improve the neutrality of film color, and provide antioxidant and environmental corrosion protection for the conductive gate layer. The SiO2 surface protective layer fills the spaces between the conductive lines of the conductive gate layer and covers the surface of the conductive gate layer.

[0025] The composite film system of this invention has a clear stacking order, and from the surface of the glass substrate outwards, the layers are: SiN x Bottom dielectric layer, first ZnO layer, patterned Ag layer, TiO x Layer 1, second ZnO layer, SiN x The sequence consists of a top dielectric layer, a conductive gate layer, and a SiO2 surface protective layer. This order is based on the synergistic optimization of the functions of each layer, and the selection of the position of each layer is governed by strict physical and functional criteria. The reasons for these constraints on the position of each layer are explained in detail below.

[0026] Among them, SiN x The bottom dielectric layer must be located on the surface of the glass substrate. First, SiN x The bottom dielectric layer, acting as a barrier layer, must be in direct contact with the glass substrate to effectively block sodium from the glass. + Ions diffuse into the interior of the film; secondly, SiN x The bottom dielectric layer, acting as an adhesion enhancement layer, must be in direct contact with the glass substrate to achieve optimal adhesion; finally, SiN... xThe bottom dielectric layer, as the bottom antireflection layer, must be located at the bottom layer to form a complete optical interference match with the subsequent film layers.

[0027] The first ZnO layer must be located on SiN. x Between the bottom dielectric layer and the patterned Ag layer. The first ZnO layer's function is to induce continuous Ag film formation and provide a good wetting surface; therefore, it must be located immediately below the patterned Ag layer. If the first ZnO layer is placed elsewhere (such as above or far from the patterned Ag layer), it cannot effectively control the quality of the patterned Ag film formation. Simultaneously, the first ZnO layer cannot directly contact the glass substrate because it does not block Na+. + The diffusion function, if in direct contact with the glass substrate, allows Na in the glass to diffuse. + It will penetrate through the first ZnO layer to reach the patterned Ag layer, causing corrosion to the patterned Ag layer.

[0028] The patterned Ag layer must be located between the first ZnO layer and the TiO layer. x Between layers. The patterned Ag layer is a low-emissivity functional layer, and TiO2 is required above it. x The first layer provides protection against oxidation and bombardment damage, and a first ZnO layer is required below it to induce film formation; TiO x The first ZnO layer and the second ZnO layer protect and optimize the patterned Ag layer from the top and bottom directions, respectively. If either of these layers is missing, the low-emissivity performance and stability of the patterned Ag layer will deteriorate.

[0029] TiO x The layer must be immediately above the patterned Ag layer. TiO x The function of the layer is to protect the patterned Ag layer, preventing Ag from being oxidized, bombarded, or agglomerated during subsequent sputtering. Therefore, it must be in direct contact with the patterned Ag layer to exert its protective effect; TiO x The layer should not be placed far from the patterned Ag layer, otherwise the patterned Ag layer will not be effectively protected when depositing subsequent film layers.

[0030] The second ZnO layer must be located on TiO. x Layers and SiN x Between the top dielectric layers. On one hand, the second ZnO layer is used to improve the optical matching between the dielectric layers above the patterned Ag layer, and needs to be close to the patterned Ag layer (separated only by TiO). x Only by having a first ZnO layer can the optical modulation function be effectively exerted; on the other hand, the second ZnO layer cannot directly contact the patterned Ag layer, otherwise it will have an adverse effect on the patterned Ag layer. Therefore, it must be located on TiO. x Above the layer.

[0031] SiN xThe top dielectric layer must be located between the second ZnO layer and the conductive gate layer. (SiN) x The top dielectric layer is used to improve the mechanical and environmental stability of the film, and also serves as the support layer for the conductive gate layer; therefore, it must be located below the conductive gate layer. Meanwhile, SiN… x The top dielectric layer cannot directly contact the patterned Ag layer (a second ZnO layer is required in between), otherwise it will affect the optical matching effect.

[0032] The conductive gate layer must be located on SiN x Above the top dielectric layer and below the SiO2 surface protective layer, the conductive gate layer, as the electrothermal functional layer, needs to be located near the surface of the film system to facilitate heat transfer to the glass surface. Simultaneously, the conductive gate layer cannot be directly exposed to the environment, otherwise it is prone to oxidation and corrosion; therefore, a SiO2 surface protective layer must be placed above it. The conductive gate layer cannot be placed inside the film system (such as near the patterned Ag layer), otherwise, although its heating function will not be affected, it will severely interfere with the optical performance of the film system, and the gate pattern will fail visual inspection.

[0033] The SiO2 surface protective layer must be located on the outermost layer. As both an anti-reflective layer and a protective layer, the SiO2 surface protective layer must be positioned above and completely cover the conductive gate layer to provide antioxidant and environmental corrosion protection. If the SiO2 surface protective layer is located below the conductive gate layer, it cannot provide protection. Therefore, the order of the layers in the composite film system of this invention is determined by the functional requirements of each layer, and adjacent layers cannot be interchanged. Interchanging the positions of any two adjacent layers will result in the loss or severe degradation of at least one core function. Furthermore, each layer is an essential functional layer; removing any one of them would prevent the synergistic integration of high light transmittance, low emissivity, high electromagnetic wave transmittance, and electric heating functions of this invention.

[0034] This invention precisely defines the thickness of each layer in the composite film system, based on a comprehensive consideration of the functional requirements and synergistic optimization of each layer. The selection of the thickness of each layer has clear technical significance. Among them, SiN x The thickness of the bottom dielectric layer is limited to 25-32 nm, which is based on a comprehensive optimization of antireflection effect and barrier capability. When SiN... x When the thickness of the bottom dielectric layer is less than 25 nm, the effect on Na in the glass + The blocking effect of ions is insufficient, Na + Easy to penetrate SiN x The bottom dielectric layer reaches the Ag layer, causing corrosion and reducing its anti-reflection effect. When the thickness exceeds 32 nm, although the blocking ability is further improved, the excessively thick dielectric layer produces significant optical interference shifts, leading to reduced visible light transmittance, and increased film stress may affect adhesion performance. Therefore, SiN... xThe thickness of the bottom dielectric layer is limited to the range of 25-32 nm to ensure good Na2+ blocking. + To achieve optimal antireflection and film adhesion while maintaining diffusion capability, the thickness of the first ZnO layer is limited to 6-8 nm, based on a comprehensive consideration of controlling the Ag layer film formation quality and optical matching. If the thickness of the first ZnO layer is too small (less than 6 nm), it cannot achieve good adhesion to SiN. x A continuous and dense wetting layer forms on the surface of the bottom dielectric layer, making it difficult to effectively induce continuous Ag film formation. The Ag layer tends to grow in an island-like pattern, leading to increased surface roughness and decreased conductivity. While excessive thickness (greater than 8 nm) can improve the film quality of the Ag layer, it alters the optical matching state of the film system, affecting visible light transmittance. Therefore, limiting the thickness of the first ZnO layer to the range of 6-8 nm ensures high-quality Ag film formation while maintaining optimal optical performance.

[0035] The thickness of the patterned Ag layer is limited to 8-10 nm based on a balance between low emissivity and visible light transmittance. The patterned Ag layer is the core low-emissivity functional layer of Low-E glass, and its thickness directly affects emissivity and visible light transmittance. When the patterned Ag layer thickness is less than 8 nm, its reflectivity for mid- and far-infrared thermal radiation is insufficient, resulting in high emissivity and making it difficult to meet the energy-saving requirements of Low-E glass. When the patterned Ag layer thickness is greater than 10 nm, although the emissivity further decreases, the visible light transmittance drops significantly, and the continuous conductivity of the patterned Ag layer becomes too strong, increasing electromagnetic shielding loss. Therefore, limiting the patterned Ag layer thickness to the range of 8-10 nm ensures both low emissivity and high visible light transmittance, as well as low electromagnetic shielding loss. TiO2 x The layer thickness is limited to 18-20 nm, based on a comprehensive consideration of both the protective effect on the Ag layer and optical compatibility. TiO x As a protective layer for the patterned Ag layer, the TiO2 layer must be thick enough to completely cover the surface of the patterned Ag layer and prevent Ag from being oxidized or damaged by bombardment during subsequent sputtering processes. When the thickness is less than 18 nm, it is difficult to form a complete protective layer, and the Ag layer is prone to oxidation or damage in subsequent processes. When the thickness is greater than 20 nm, although it can provide more adequate protection, TiO2... x The refractive index of the layer is high, and the TiO layer is too thick. x The layer alters the optical interference conditions of the film system, leading to a decrease in visible light transmittance or color shift on the film surface. Therefore, TiO2... x The thickness of the first layer is limited to 18-20 nm to ensure adequate protection of the patterned Ag layer while maintaining excellent optical performance. The thickness of the second ZnO layer is limited to 8-12 nm, based on considerations of optical matching effect and film structure integrity. The second ZnO layer and TiO2... x Layer, SiNx The top dielectric layer together constitutes the multilayer dielectric system above the Ag layer, and its thickness plays a regulatory role in the optical interference matching of the film system. When the thickness of the second ZnO layer is less than 8 nm, the optical matching effect is insufficient, and the visible light transmittance is difficult to achieve optimal results; when the thickness is greater than 12 nm, it will disrupt the optical interference matching of the film system, similarly leading to a decrease in transmittance or color shift on the film surface. Therefore, limiting the thickness of the second ZnO layer to the range of 8-12 nm can obtain the best anti-reflection effect and color neutrality. x The thickness of the top dielectric layer is limited to 25-35 nm, based on a comprehensive consideration of the film's mechanical stability and optical compatibility. (SiN) x The top dielectric layer, serving as both the carrier layer for the conductive gate layer and the protective layer for the film system, requires sufficient thickness to ensure mechanical and environmental stability. A thickness below 25 nm results in insufficient wear resistance and environmental corrosion resistance; a thickness above 35 nm increases internal stress, potentially affecting adhesion. Furthermore, excessively thick SiN... x The layer alters the optical interference conditions of the film system, affecting the visible light transmittance. Therefore, SiN... xThe thickness of the top dielectric layer is limited to 25-35 nm to ensure excellent optical performance while maintaining the mechanical stability of the film. The thickness of the conductive gate layer is limited to 500 nm-1 μm, based on a balance between electrothermal efficiency and transparency. The thickness of the conductive gate layer directly determines its resistance and heating power: when the thickness is less than 500 nm, the resistance of the copper wire is relatively high, resulting in limited Joule heating under the same voltage, making it difficult to achieve efficient defogging and defrosting; when the thickness is greater than 1 μm, although the resistance decreases and the heating efficiency increases, the excessively thick copper wire will enhance the scattering and blocking of visible light, leading to increased haze, decreased light transmittance, and increased visual visibility of the lines, affecting the appearance of the glass. Therefore, limiting the thickness of the conductive gate layer to 500 nm-1 μm ensures sufficient electrothermal power while minimizing the impact on light transmittance and appearance. The linewidth of the conductive gate layer is limited to 15-20 μm, and the spacing between adjacent conductive lines is limited to 1.8-2.2 cm, based on a comprehensive optimization of heating uniformity and visual concealment. Excessively narrow linewidths or excessively large spacing can lead to uneven heating; excessively wide linewidths or excessively small spacing can increase the obstruction of visible light and reduce visual visibility. The thickness of the SiO2 surface protective layer is limited to 18-25 nm, based on a comprehensive consideration of antireflection and protection. As the outermost antireflection and protective layer, the thickness of the SiO2 surface protective layer needs to form optical interference matching with the underlying dielectric layers to achieve optimal anti-reflection performance. A thickness below 18 nm results in insufficient antireflection and limited antioxidant protection for the conductive gate layer; a thickness above 25 nm disrupts the antireflection matching of the film system, leading to a decrease in visible light transmittance. Therefore, limiting the thickness of the SiO2 surface protective layer to the range of 18-25 nm achieves optimal antireflection and anti-reflection performance while providing sufficient protection for the conductive gate layer.

[0036] Furthermore, the side length of the micron-sized independent units in the patterned Ag layer, the width of the etched trenches, and the linewidth and spacing of the copper lines in the conductive gate layer also have clear functional significance. The side length of the micron-sized independent units in the patterned Ag layer is limited to 30-100 μm, based on a balance between electromagnetic wave transmission performance and low emissivity. The side length of the micron-sized independent units determines the unit size after the Ag layer is divided: the smaller the side length, the weaker the macroscopic continuous conductivity of the Ag layer, and the lower the reflection and shielding loss of electromagnetic waves; however, when the side length is too small (less than 30 μm), the dense etched trenches will significantly reduce the effective coverage area of ​​the Ag layer, decrease the Ag layer's ability to reflect mid- and far-infrared thermal radiation, and increase the emissivity. When the side length is too large (greater than 100 μm), although a high Ag layer coverage and low emissivity can be maintained, the area of ​​the micron-sized independent units is too large, and there are still long continuous conductive paths within the units, which enhances the shielding effect of electromagnetic waves. Therefore, limiting the side length of the micron-level independent units to the range of 30-100 μm ensures low electromagnetic shielding loss while maintaining low emissivity. The width of the etched trenches is limited to 1.5-4 μm, based on a comprehensive consideration of electrical insulation and the effective coverage of the Ag layer. The etched trenches must have sufficient width to ensure electrical insulation between adjacent micron-level independent units, avoiding incomplete etching or residual conductive material at the edges due to excessively narrow trenches, which would affect the effectiveness of cutting off the transverse continuous conductive channels. However, excessively wide trenches (greater than 4 μm) would over-occupy the Ag layer's coverage area, leading to a decrease in low-emissivity performance and potentially causing unnecessary damage to the first ZnO layer. Therefore, limiting the width of the etched trenches to the range of 1.5-4 μm ensures sufficient electrical insulation between adjacent micron-level independent units while maximizing the effective coverage area and low-emissivity of the Ag layer. The linewidth of the copper wires in the conductive gate layer is limited to 15-20 μm, and the spacing between adjacent conductive lines is limited to 1.8-2.2 cm, based on a comprehensive optimization of heating uniformity, transparency, and visual concealment. The width of the copper wire determines the resistance and heating power of the conductive grid layer: A narrow wire width (less than 15μm) results in high resistance and limited Joule heating when voltage is applied, making efficient defogging and defrosting difficult. While a wide wire width (greater than 20μm) reduces resistance and improves heating efficiency, it also increases the visual visibility of the copper wire, affecting the glass's appearance and increasing its blocking effect on visible light. The spacing between adjacent conductive wires determines the uniformity of heating and the visual concealment effect: An excessively large spacing (greater than 2.2cm) leads to uneven heating, creating alternating hot and cold areas on the glass surface, affecting defogging and defrosting. An excessively small spacing (less than 1.8cm) results in overly dense copper wire arrangement, significantly obstructing light transmittance and enhancing the visual cumulative effect of the metal lines, thus affecting the glass's transparent appearance.Therefore, limiting the copper wire width and spacing to the range of 15-20μm and 1.8-2.2cm respectively can minimize the impact on visible light transmittance, appearance and electromagnetic wave transmittance while ensuring heating uniformity and sufficient heating power.

[0037] This invention constructs a composite film structure on the surface of a glass substrate that combines optical control, low radiation performance, high electromagnetic wave transmittance, and electric heating functions through the above-mentioned technical solutions. Among them, (1) the patterned Ag layer, as the core low-radiation functional layer, has high reflectivity to mid- and far-infrared thermal radiation. When the thickness of the patterned Ag layer is 8-10 nm, it can effectively reflect mid- and far-infrared radiation while maintaining high visible light transmittance, thereby reducing the glass emissivity to 0.07-0.14; (2) by laser etching the continuous Ag layer, it is divided into micron-level independent units, and etching trenches that penetrate the Ag layer are formed between adjacent micron-level independent units, completely cutting off the transverse continuous conductive channels of the Ag layer. After the Ag layer is divided, a large-area continuous conductive network is no longer formed macroscopically, which significantly reduces the reflection and shielding effect on electromagnetic signals such as 5G, Wi-Fi, Bluetooth, navigation, ETC and radar, and reduces the electromagnetic shielding loss from 20dB of the traditional continuous Ag layer to 2-6dB; (3) The conductive grid layer is composed of multiple copper wires, and bus electrodes are set at both ends of the conductive grid layer. When in use, the bus electrodes are connected to an external DC power supply, and the current is introduced into the conductive grid layer through the bus electrodes. Joule heating is generated in the conductive grid layer, and the heat is conducted to the glass surface through the film layer to realize the functions of defogging, defrosting and de-icing. Since the copper wires are only 15-20μm wide and 1.8-2.2cm apart, they have little effect on visible light transmittance and electromagnetic wave transmittance; (4) SiN x Bottom dielectric layer, first ZnO layer, second ZnO layer, TiO x Layer, SiN x The top dielectric layer and the SiO2 surface protective layer work together to achieve antireflection enhancement in the visible light wavelength range of 380-780nm through a multi-layer antireflection design. The thickness of each dielectric layer is optimized to achieve a visible light transmittance of 81%-87%, while the film surface color is controlled to be neutral.

[0038] Beneficial effects Compared with the prior art, the present invention has the following advantages: (1) This invention constructs a composite film system comprising a glass substrate and a composite film system (the composite film system includes SiN) x / ZnO / Ag / TiO x / ZnO / SiN xThe Low-E glass (with a conductive gate layer and SiO2) achieves a synergistic integration of high light transmittance, low emissivity, high electromagnetic wave transmittance, and electric heating function. Through a reasonable film structure design, each functional layer has a clear division of labor and does not interfere with each other: the Ag layer provides low emissivity, the patterned processing ensures high electromagnetic wave transmittance, the conductive gate layer independently realizes the electric heating function, and the dielectric layer realizes optical control and protection.

[0039] (2) This invention utilizes SiN x Bottom dielectric layer, first ZnO layer, second ZnO layer, TiO x Layer, SiN x The top dielectric layer and the SiO2 surface protective layer, among other dielectric layers, optically match and interface-controlled the patterned Ag layer, improving visible light transmittance (81%-87%) while maintaining low emissivity (0.07-0.14), thus achieving an excellent balance between high transmittance and low emissivity.

[0040] (3) The present invention divides the continuous Ag layer into micron-level independent units by laser etching, and completely cuts off the lateral continuous conductive channel of the Ag layer while maintaining low radiation performance. This significantly reduces the average electromagnetic shielding loss in the 0.1-18GHz frequency range from 20dB of the traditional continuous Ag layer to 2-6dB, greatly improving the transmission capability of electromagnetic signals such as 5G, Wi-Fi, Bluetooth, navigation, ETC and radar.

[0041] (4) The present invention sets the conductive grid layer as an independent electric heating structure. When in use, only the bus electrodes at both ends of the conductive grid layer need to be connected to an external DC power supply. It can generate Joule heat at low voltage (12-24V) to achieve the functions of defogging, defrosting and de-icing on the glass surface. The glass surface temperature can be raised to 45-100℃. Because the copper wires in the conductive grid layer have a small line width (15-20μm) and a large spacing (1.8-2.2cm), they have little impact on visible light transmittance, appearance and electromagnetic wave transmission, and completely avoid the problems of visual obstruction, uneven heating and complex structure of traditional heating wires.

[0042] (5) This invention utilizes SiN x Bottom dielectric layer blocks Na in glass + Ion diffusion, through TiO x The patterned Ag layer is protected from oxidation by a protective layer, and the conductive gate layer is protected against oxidation by a SiO2 surface protective layer. The synergistic effect of the protective layers gives the film excellent adhesion, mechanical stability and environmental corrosion resistance.

[0043] (6) The preparation method of the present invention is based on magnetron sputtering, laser etching and metal mesh preparation process. The process is simple, the film thickness is controllable and the repeatability is good. It is compatible with existing Low-E glass coating production lines and has good prospects for industrial application. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the cross-sectional structure of the glass prepared according to the present invention. Detailed Implementation

[0045] The technical solution of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0046] This invention provides a high-transmittance, low-emissivity electrically heated Low-E glass, such as... Figure 1 As shown, the Low-E glass includes a glass substrate and a composite film system sequentially deposited on the surface of the glass substrate. From the surface of the glass substrate outwards, the composite film system consists of: SiN... x Bottom dielectric layer, first ZnO layer, patterned Ag layer, TiO x Layer 1, second ZnO layer, SiN x The composite film system consists of a top dielectric layer, a conductive gate layer, and a SiO2 surface protective layer, and is composed of SiN. x / ZnO / Ag / TiO x / ZnO / SiN x / Conductive gate layer / SiO2.

[0047] Wherein, the SiN x The thickness of the bottom dielectric layer is 25-32 nm; the thickness of the first ZnO layer is 6-8 nm; the thickness of the patterned Ag layer is 8-10 nm, and the patterned Ag layer is composed of multiple arrayed, electrically insulated micron-sized independent units. Each micron-sized independent unit is square with a side length of 30-100 μm, and there are etching trenches between adjacent micron-sized independent units, with a width of 1.5-4 μm. The TiO2 layer... x The thickness of the layer on the patterned Ag layer is 18-20 nm; the thickness of the second ZnO layer is 8-12 nm; the SiN... x The thickness of the top dielectric layer is 25-35 nm; the conductive gate layer is composed of multiple copper wires, and its structure is a crisscrossing grid structure or a parallel bar grid structure. The thickness of the conductive gate layer is 500 nm-1 μm, the linewidth of the copper wires is 15-20 μm, and the spacing between two adjacent parallel copper wires is 1.8-2.2 cm (if it is a grid structure, the spacing between two adjacent parallel copper wires in both the longitudinal and transverse directions is preferably 1.8-2.2 cm); the thickness of the SiO2 surface protective layer on the upper surface of the conductive gate layer is 18-25 nm.

[0048] The method for preparing Low-E glass according to the present invention includes the following steps: Step S1: Clean and surface activate the glass substrate to remove surface oil, particulate matter and organic contaminants, and improve the adhesion of subsequent film layers. Cleaning can be carried out by ultrasonic cleaning with neutral detergent, deionized water and anhydrous ethanol in sequence, followed by drying with high-purity nitrogen and ultraviolet ozone treatment. Step S2: Deposit SiN on the glass substrate surface using a magnetron sputtering process. x Bottom dielectric layer: Si3N4 target material (purity 99.99%) is used, sputtering power is 80-120W, working gas pressure is 0.8-1.2Pa, deposition gas is a mixture of argon and nitrogen with an argon to nitrogen flow ratio of 10:1, and deposition thickness is 25-32nm; this step forms an antireflection layer, a barrier layer and an adhesion enhancement layer on the surface of the glass substrate; Step S3, in SiN x The first ZnO layer is deposited on the surface of the bottom dielectric layer using a magnetron sputtering process: a ZnO target (purity 99.99%) is used, the sputtering power is 80-120W, the working pressure is 0.8-1.2Pa, the deposition gas is a mixture of argon and oxygen with an argon to oxygen flow ratio of 10:1, and the deposition thickness is 6-8nm; this step forms a seed layer that induces continuous Ag film formation, reduces the surface roughness of the Ag layer, and improves interface matching; Step S4: Deposit an Ag layer on the surface of the first ZnO layer using a magnetron sputtering process: use an Ag target (purity 99.99%), sputtering power of 50-100W, working pressure of 0.8-1.2Pa, deposition gas of argon, and deposition thickness of 8-10nm; this step forms the core low-emissivity functional layer of the Low-E glass. Step S5: Patterning the Ag layer using laser etching: A 355nm ultraviolet nanosecond laser is used with a pulse width of 15-25ns, a repetition frequency of 50kHz, a scanning speed of 350-600mm / s, and a single pulse energy of 10-20μJ. The Ag layer is etched into a patterned Ag layer containing multiple arrayed, electrically insulated micron-sized independent units. Etching trenches are formed between adjacent micron-sized independent units, penetrating the Ag layer. The width of the etching trenches is 2-3μm, and the etching depth penetrates the entire Ag layer. This step cuts off the lateral continuous conductive channels of the Ag layer, significantly reducing the reflection and shielding loss of the film layer to electromagnetic waves and improving the electromagnetic wave transmission capability. Step S6: Deposit TiO2 sequentially on the patterned Ag layer surface using magnetron sputtering. x Layer, second ZnO layer and SiN x Top dielectric layer: TiO xThe deposition conditions for the layer are as follows: TiO2 target material is used, sputtering power is 30-50W, working pressure is 0.8-1.2Pa, deposition gas is argon, and deposition thickness is 18-20nm. This step forms a protective layer for the patterned Ag layer to prevent Ag from being oxidized or damaged by bombardment during subsequent sputtering processes. The deposition conditions for the second ZnO layer are as follows: ZnO target material is used, sputtering power is 80-120W, working gas pressure is 0.8-1.2Pa, deposition gas is a mixture of argon and oxygen with an argon to oxygen flow ratio of 10:1, and deposition thickness is 8-12nm; this step improves optical matching and increases visible light transmittance. SiN x The deposition conditions for the top dielectric layer are as follows: Si3N4 target material is used, sputtering power is 80-120W, working gas pressure is 0.8-1.2Pa, deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:1, and deposition thickness is 25-35nm; this step improves the mechanical stability, environmental stability and optical matching effect of the film layer. Step S7, in SiN x A conductive gate layer is fabricated on the surface of the top dielectric layer: the linewidth of the conductive gate layer is 15-20 μm, the spacing between adjacent conductive lines is 1.8-2.2 cm, and the thickness is 500 nm-1 μm; the fabrication process of the conductive gate layer is photolithography-electroplating or photolithography-magnetron sputtering lift-off; it should be noted that these two processes are common methods for fabricating mesh structures or parallel strip gate structures in the prior art, and will not be described in detail in this invention. This step forms a low-resistance transparent electric heating path; Step S8: Deposit a SiO2 surface protective layer on the conductive gate layer using magnetron sputtering: Use a Si target, sputtering power of 80-120W, working gas pressure of 0.8-1.2Pa, and deposition gas of a mixture of argon and oxygen with a flow ratio of 8:1. The deposition thickness is 18-25nm. This step forms a surface antireflection layer and a protective layer, which provides antioxidant and environmental corrosion protection for the conductive gate layer.

[0049] The present invention will be further illustrated below with reference to specific embodiments and comparative examples. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0050] The glass substrate used in the following embodiments of the present invention is sodium-calcium-silicon float glass with a thickness of 5-6 mm. The specific operations for cleaning and surface activation of the glass substrate are as follows: it is cleaned sequentially with a neutral detergent, deionized water, anhydrous ethanol, and then deionized water, with ultrasonic cleaning time of 10 min for each step. Subsequently, it is dried with high-purity nitrogen gas and treated with ultraviolet ozone for 10-15 min. All magnetron sputtering deposition processes are performed at room temperature with a base vacuum level below 5.0 × 10⁻⁶. -4Pa, target-substrate distance of 70-90mm, substrate rotation speed of 10-20rpm. Visible light transmittance (integrated transmittance test in the wavelength range of 380-780nm using a UV-Vis-NIR spectrophotometer), emissivity (tested according to conventional Low-E glass testing methods), electromagnetic shielding loss (tested in the frequency range of 0.1-18GHz), and electrothermal performance (applied DC voltage to a 100mm×100mm sample, and the glass surface temperature change was recorded using an infrared thermal imager) were tested on the glass obtained in the examples and comparative examples.

[0051] Example 1

[0052] The Low-E glass prepared in this embodiment includes a glass substrate and a composite film system disposed on the surface of the glass substrate. The composite film system is: SiN x (28nm) / ZnO (7nm) / Ag (9nm) / TiO x (19nm) / ZnO (10nm) / SiN x (30nm) / Conductive gate layer / SiO2 (22nm).

[0053] The specific preparation steps for this Low-E glass are as follows: Step S1: Clean and surface activate the glass substrate; Step S2: Deposit SiN on the cleaned glass substrate surface. x The bottom dielectric layer uses a Si3N4 target with a purity of 99.99%, a sputtering power of 100W, a working gas pressure of 1.0Pa, and a deposition gas of argon and nitrogen with a flow ratio of 10:1. The deposition thickness is 28nm. Step S3, in SiN x The first ZnO layer is deposited on the surface of the bottom dielectric layer using a ZnO target with a purity of 99.99%, a sputtering power of 100W, a working gas pressure of 1.0Pa, and a deposition gas of argon and oxygen with a flow ratio of 10:1. The deposition thickness is 7nm. Step S4: Deposit an Ag layer on the surface of the first ZnO layer using an Ag target with a purity of 99.99%, a sputtering power of 70W, a working pressure of 1.0Pa, and argon as the deposition gas. The deposition thickness is 9nm. Step S5: The Ag layer is patterned by a 355nm ultraviolet nanosecond laser with a pulse width of 15ns, a repetition frequency of 50kHz, a scanning speed of 350mm / s, and a single pulse energy of 10μJ. The Ag layer is etched into multiple square micron-sized independent units with a side length of 60μm. The width of the etching trench is 2μm, and the etching depth penetrates the entire Ag layer to obtain a patterned Ag layer. Step S6: Deposit TiO2 sequentially on the patterned Ag layer surface using magnetron sputtering. x Layer, second ZnO layer and SiN x Top dielectric layer; TiO x The deposition conditions were as follows: TiO2 target material was used, sputtering power was 40W, working pressure was 1.0Pa, deposition gas was argon, and deposition thickness was 19nm. The deposition conditions for the second ZnO layer are as follows: ZnO target material is used, sputtering power is 100W, working pressure is 1.0Pa, deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 10:1, and deposition thickness is 10nm. SiN x The deposition conditions for the top dielectric layer are as follows: Si3N4 target material is used, sputtering power is 100W, working gas pressure is 1.0Pa, the deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:1, and the deposition thickness is 30nm. Step S7, in SiN x A conductive gate layer is fabricated on the surface of the top dielectric layer. First, a positive photoresist is spin-coated at 3000 rpm for 30 seconds, followed by pre-baking at 95℃ for 90 seconds. After mask exposure and development, a grid pattern is formed. Subsequently, a Cu seed layer is deposited and thickened by electroplating. The electroplating solution is a copper sulfate system with a CuSO4 concentration of 200 g / L, an H2SO4 concentration of 50 g / L, and a Cl... - The concentration is 60 mg / L, and the current density is 5 mA / cm². 2 The electroplating time is 5 minutes, the resulting conductive gate layer has a line width of 18 μm, a thickness of 800 nm, a spacing of 2.0 cm between adjacent conductive lines, and bus electrodes with a width of 3 mm are set at both ends of the conductive gate layer for external voltage input. Step S8: Deposit a SiO2 surface protective layer on the conductive gate layer surface using Si target reactive sputtering with a sputtering power of 100W and a working gas pressure of 1.0Pa. The deposition gas is a mixture of argon and oxygen with a flow ratio of 8:1 and a deposition thickness of 22nm.

[0054] The Low-E glass obtained in this embodiment has a visible light transmittance of 84%, an emissivity of 0.10, and an average electromagnetic shielding loss of 4 dB in the 0.1-18 GHz range. When a 12V DC voltage is applied, the glass surface temperature can rise to 55°C; when a 24V voltage is applied, the surface temperature can rise to 85°C, enabling defogging, defrosting, and auxiliary de-icing functions.

[0055] Example 2

[0056] This embodiment prepares a Low-E glass with a composite film system of SiN. x(32nm) / ZnO (6nm) / Ag (8nm) / TiO x (18nm) / ZnO (8nm) / SiN x (35nm) / Conductive gate layer / SiO2 (25nm).

[0057] The specific preparation steps are as follows: Step S1: Clean and surface activate the glass substrate; Step S2: Deposit SiN on the cleaned glass substrate surface. x The bottom dielectric layer uses a Si3N4 target with a purity of 99.99%, a sputtering power of 90W, a working gas pressure of 0.9Pa, and a deposition gas mixture of argon and nitrogen with a flow ratio of 10:1. The deposition thickness is 32nm. Step S3, in SiN x The first ZnO layer is deposited on the surface of the bottom dielectric layer using a ZnO target with a purity of 99.99%, a sputtering power of 90W, a working gas pressure of 0.9Pa, and a deposition gas mixture of argon and oxygen with a flow ratio of 10:1. The deposition thickness is 6nm. Step S4: Deposit an Ag layer on the surface of the first ZnO layer using an Ag target with a purity of 99.99%, a sputtering power of 60W, a working gas pressure of 0.9Pa, and argon as the deposition gas. The deposition thickness is 8nm. Step S5: The Ag layer is patterned by a 355nm ultraviolet nanosecond laser with a pulse width of 15ns, a repetition frequency of 60kHz, a scanning speed of 550mm / s, and a single pulse energy of 20μJ. The Ag layer is etched into square micron-scale independent units with a side length of 50μm. The width of the etching trench is 3μm, and the etching depth penetrates the entire Ag layer to obtain a patterned Ag layer. Step S6: Deposit TiO2 sequentially on the patterned Ag layer surface using magnetron sputtering. x Layer, second ZnO layer and SiN x Top dielectric layer; in which TiO x The deposition conditions were as follows: TiO2 target material was used, sputtering power was 35W, working pressure was 1.0Pa, deposition gas was argon, and deposition thickness was 18nm. The deposition conditions for the second ZnO layer are as follows: ZnO target material is used, sputtering power is 90W, working pressure is 1.0Pa, deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 10:1, and deposition thickness is 8nm. SiN xThe deposition conditions for the top dielectric layer are as follows: Si3N4 target material is used, sputtering power is 90W, working gas pressure is 1.0Pa, the deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:1, and the deposition thickness is 35nm. Step S7, in SiN x A conductive gate layer is fabricated on the surface of the top dielectric layer using a photolithography-magnetron sputtering lift-off process: first, a photoresist pattern is formed, then Cr / Cu metal layers are sputtered sequentially, with the Cr layer having a thickness of 8 nm as an adhesion layer and the Cu layer having a thickness of 500 nm. Finally, the photoresist is lifted off to obtain the conductive gate layer, which has a linewidth of 15 μm, a thickness of 500 nm, and a spacing of 2.2 cm between adjacent conductive lines. Bus electrodes with a width of 3 mm are set at both ends of the conductive gate layer for external voltage input. Step S8: Deposit a SiO2 surface protective layer on the conductive gate layer surface using Si target reactive sputtering with a sputtering power of 100W, a working gas pressure of 1.0Pa, and a deposition gas mixture of argon and oxygen with an argon to oxygen flow ratio of 8:1. The deposition thickness is 25nm.

[0058] The Low-E glass obtained in this embodiment has a visible light transmittance of 87%, an emissivity of 0.14, and an average electromagnetic shielding loss of 3dB in the 0.1-18GHz range. When a 24V voltage is applied, the glass surface temperature can rise to 65°C. This embodiment is suitable for building windows, communication windows, and smart windows that require high light transmission and color neutrality, while also needing low electromagnetic shielding loss and basic electric heating functionality.

[0059] Example 3

[0060] This embodiment prepares a Low-E glass with a composite film system of SiN. x (25nm) / ZnO (8nm) / Ag (10nm) / TiO x (20nm) / ZnO (12nm) / SiN x (35nm) / Conductive gate layer / SiO2 (18nm).

[0061] The specific preparation steps are as follows: Step S1: Clean and surface activate the glass substrate; Step S2: Deposit SiN on the cleaned glass substrate surface. x The bottom dielectric layer uses a Si3N4 target with a purity of 99.99%, a sputtering power of 110W, a working gas pressure of 1.1Pa, and a deposition gas mixture of argon and nitrogen with a flow ratio of 10:1. The deposition thickness is 25nm. Step S3, in SiN xThe first ZnO layer is deposited on the surface of the bottom dielectric layer using a ZnO target with a purity of 99.99%, a sputtering power of 110W, a working gas pressure of 1.1Pa, and a deposition gas mixture of argon and oxygen with a flow ratio of 10:1. The deposition thickness is 8nm. Step S4: Deposit an Ag layer on the surface of the first ZnO layer using an Ag target with a purity of 99.99%, a sputtering power of 80W, a working pressure of 1.0Pa, and argon as the deposition gas. The deposition thickness is 10nm. Step S5: The Ag layer is patterned by a 355nm ultraviolet nanosecond laser with a pulse width of 25ns, a repetition frequency of 50kHz, a scanning speed of 400mm / s, and a single pulse energy of 15μJ. The Ag layer is etched into square micron-scale independent units with a side length of 100μm. The width of the etching trench is 2.0μm, and the etching depth penetrates the entire Ag layer to obtain a patterned Ag layer. Step S6: Deposit TiO2 sequentially on the patterned Ag layer surface using magnetron sputtering. x Layer, second ZnO layer and SiN x Top dielectric layer; in which TiO x The deposition conditions were as follows: TiO2 target material was used, sputtering power was 45W, working pressure was 1.0Pa, deposition gas was argon, and deposition thickness was 20nm. The deposition conditions for the second ZnO layer are as follows: ZnO target material is used, sputtering power is 110W, working pressure is 1.0Pa, deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 10:1, and deposition thickness is 12nm. SiN x The deposition conditions for the top dielectric layer are as follows: Si3N4 target material is used, sputtering power is 110W, working gas pressure is 1.0Pa, the deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:1, and the deposition thickness is 25nm. Step S7, in SiN x A conductive gate layer is fabricated on the surface of the top dielectric layer using a photolithography-electroplating process. The resulting conductive gate layer has a linewidth of 20 μm, a thickness of 1.0 μm, and a spacing of 1.8 cm between adjacent conductive lines. Bus electrodes with a width of 4 mm are set at both ends of the conductive gate layer for external voltage input. Step S8: Deposit a SiO2 surface protective layer on the conductive gate layer surface using Si target reactive sputtering with a sputtering power of 90W, a working gas pressure of 1.0Pa, and a deposition gas mixture of argon and oxygen with an argon to oxygen flow ratio of 8:1. The deposition thickness is 18nm.

[0062] The Low-E glass obtained in this embodiment has a visible light transmittance of 81%, an emissivity of 0.07, and an average electromagnetic shielding loss of 6 dB in the 0.1-18 GHz range. Due to the large Ag layer thickness and the large side length of the micron-level independent units, this embodiment has a lower emissivity. When a 12V voltage is applied, the glass surface temperature can rise to 60°C; when a 24V voltage is applied, the glass surface temperature can rise to 95°C, making it suitable for building doors and windows in cold regions, automotive defrosting glass, and scenarios with high energy-saving requirements.

[0063] Example 4

[0064] This embodiment prepares a Low-E glass with a composite film system of SiN. x (30nm) / ZnO (6nm) / Ag (8.5nm) / TiO x (18nm) / ZnO (9nm) / SiN x (32nm) / Conductive gate layer (parallel bar gate structure) / SiO2 (24nm).

[0065] The specific preparation steps are as follows: Step S1: Clean and surface activate the glass substrate; Step S2: Deposit SiN on the cleaned glass substrate surface. x The bottom dielectric layer uses a Si3N4 target with a purity of 99.99%, a sputtering power of 100W, a working gas pressure of 1.0Pa, and a deposition gas mixture of argon and nitrogen with a flow ratio of 10:1. The deposition thickness is 30nm. Step S3, in SiN x The first ZnO layer is deposited on the surface of the bottom dielectric layer using a ZnO target with a purity of 99.99%, a sputtering power of 100W, a working gas pressure of 1.0Pa, and a deposition gas mixture of argon and oxygen with a flow ratio of 10:1. The deposition thickness is 6nm. Step S4: Deposit an Ag layer on the surface of the first ZnO layer using an Ag target with a purity of 99.99%, a sputtering power of 65W, a working pressure of 1.0Pa, and argon as the deposition gas. The deposition thickness is 8.5nm. Step S5: The Ag layer is patterned by using a 355nm ultraviolet nanosecond laser with a pulse width of 20ns, a repetition frequency of 60kHz, a scanning speed of 600mm / s, and a single pulse energy of 20μJ. The Ag layer is etched into square micron-scale independent units with a side length of 30μm. The width of the etching trench is 4μm, and the etching depth penetrates the entire Ag layer to obtain a patterned Ag layer. Step S6: Deposit TiO2 sequentially on the patterned Ag layer surface using magnetron sputtering. x Layer, second ZnO layer and SiN xTop dielectric layer; TiO x The deposition conditions were as follows: TiO2 target material was used, sputtering power was 40W, working pressure was 1.0Pa, deposition gas was argon, and deposition thickness was 18nm. The deposition conditions for the second ZnO layer are as follows: ZnO target material is used, sputtering power is 100W, working pressure is 1.0Pa, deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 10:1, and deposition thickness is 9nm. SiN x The deposition conditions for the top dielectric layer are as follows: Si3N4 target material is used, sputtering power is 100W, working gas pressure is 1.0Pa, the deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:1, and the deposition thickness is 32nm. Step S7, in SiN x A conductive gate layer is fabricated on the surface of the top dielectric layer using a photolithography-electroplating process. The conductive gate layer adopts a parallel bar grid structure, resulting in a conductive gate layer with a linewidth of 15μm, a thickness of 600nm, and a spacing of 2.2cm between adjacent conductive lines. Bus electrodes with a width of 3mm are set at both ends of the conductive gate layer for external voltage input. Step S8: Deposit a SiO2 surface protective layer on the conductive gate layer surface using Si target reactive sputtering with a sputtering power of 100W, a working gas pressure of 1.0Pa, and a deposition gas mixture of argon and oxygen with an argon to oxygen flow ratio of 8:1. The deposition thickness is 24nm.

[0066] The Low-E glass obtained in this embodiment has a visible light transmittance of 83%, an emissivity of 0.13, and an average electromagnetic shielding loss of 2dB in the 0.1-18GHz range. When a 24V voltage is applied, the glass surface temperature can rise to 60°C. This embodiment is suitable for communication building curtain walls, vehicle communication windows, ETC windows, navigation signal windows, and applications with high requirements for wireless signal transmittance.

[0067] Example 5

[0068] This embodiment prepares a Low-E glass with a composite film system of SiN. x (28nm) / ZnO (7nm) / Ag (9nm) / TiO x (19nm) / ZnO (10nm) / SiN x (30nm) / Conductive gate layer / SiO2 (20nm).

[0069] The specific preparation steps are as follows: Step S1: Clean and surface activate the glass substrate; Step S2: Deposit SiN on the cleaned glass substrate surface. xThe bottom dielectric layer uses a Si3N4 target with a purity of 99.99%, a sputtering power of 100W, a working gas pressure of 1.0Pa, and a deposition gas of argon and nitrogen with a flow ratio of 10:1. The deposition thickness is 28nm. Step S3, in SiN x The first ZnO layer is deposited on the surface of the bottom dielectric layer using a ZnO target with a purity of 99.99%, a sputtering power of 100W, a working gas pressure of 1.0Pa, and a deposition gas of argon and oxygen with a flow ratio of 10:1. The deposition thickness is 7nm. Step S4: Deposit an Ag layer on the surface of the first ZnO layer using an Ag target with a purity of 99.99%, a sputtering power of 70W, a working pressure of 1.0Pa, and argon as the deposition gas. The deposition thickness is 9nm. Step S5: The Ag layer is patterned by a 355nm ultraviolet nanosecond laser with a pulse width of 25ns, a repetition frequency of 50kHz, a scanning speed of 500mm / s, and a single pulse energy of 20μJ. The Ag layer is etched into square micron-scale independent units with a side length of 60μm. The width of the etching trench is 2μm, and the etching depth penetrates the entire Ag layer to obtain a patterned Ag layer. Step S6: Deposit TiO2 sequentially on the patterned Ag layer surface using magnetron sputtering. x Layer, second ZnO layer and SiN x Top dielectric layer; TiO x The deposition conditions were as follows: TiO2 target material was used, sputtering power was 40W, working pressure was 1.0Pa, deposition gas was argon, and deposition thickness was 19nm. The deposition conditions for the second ZnO layer are as follows: ZnO target material is used, sputtering power is 100W, working pressure is 1.0Pa, deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 10:1, and deposition thickness is 10nm. SiN x The deposition conditions for the top dielectric layer are as follows: Si3N4 target material is used, sputtering power is 100W, working gas pressure is 1.0Pa, the deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:1, and the deposition thickness is 30nm. Step S7, in SiN xA conductive gate layer was fabricated on the surface of the top dielectric layer using a photolithography-electroplating process. The resulting conductive gate layer has a linewidth of 20 μm, a thickness of 1.0 μm, and a spacing of 1.8 cm between adjacent conductive lines. Cu bus electrodes with a width of 5 mm were connected to both ends of the conductive gate layer. The external wires of the bus electrodes were reinforced with conductive silver paste. The curing temperature was 120℃ and the curing time was 20 min. To improve heating uniformity, the conductive gate layer adopted a crisscross grid structure with a spacing of 1.8 cm between horizontal and vertical lines. Step S8: Deposit a SiO2 surface protective layer on the conductive gate layer surface using Si target reactive sputtering with a sputtering power of 110W and a working gas pressure of 1.0Pa. The deposition gas is a mixture of argon and oxygen with a flow ratio of 8:1 and a deposition thickness of 20nm.

[0070] The Low-E glass obtained in this embodiment has a visible light transmittance of 83%, an emissivity of 0.10, and an average electromagnetic shielding loss of 4 dB in the 0.1-18 GHz range. It exhibits strong electrothermal performance; when tested on a 100 mm × 100 mm sample, applying 6 V raised the temperature to 45 °C, applying 12 V raised it to 70 °C, and applying 24 V raised it to 100 °C; the time to reach stable temperature was 60-120 s. After 100 on-off cycles, the resistance change rate was less than 5%, indicating good electrothermal stability.

[0071] Comparative Example 1 The film structure of this comparative example is basically the same as that of Example 1, except that step S5 is not included, that is, the Ag layer is not laser etched and the Ag layer remains a continuous film.

[0072] The comparative sample had a visible light transmittance of 83% and an emissivity of 0.08, but its average electromagnetic shielding loss increased significantly in the 0.7-6 GHz range, reaching 20 dB. Compared to Example 1, although the comparative sample maintained a lower emissivity, its continuous Ag layer formed a large-area conductive channel, resulting in strong reflection and shielding of radio electromagnetic signals, which is detrimental to the transmission of 5G, Wi-Fi, Bluetooth, navigation, ETC, and radar signals. This demonstrates that etching the Ag layer into micron-sized independent units can significantly reduce electromagnetic shielding loss while maintaining Low-E functionality.

[0073] The performance test results of Examples 1-5 and Comparative Example 1 show that all embodiments of the present invention achieve a synergistic integration of high visible light transmittance (81%-87%), low emissivity (0.07-0.14), and low electromagnetic shielding loss (2-6dB). The electromagnetic shielding loss in the comparative example is as high as 20dB, indicating that the continuous Ag layer causes severe reflection and shielding of electromagnetic waves. In contrast, Examples 1-5, by patterning the Ag layer, significantly reduce the electromagnetic shielding loss to 2-6dB, while maintaining excellent visible light transmittance and emissivity. This demonstrates the effectiveness of the patterned Ag layer design in significantly improving electromagnetic wave transmission while maintaining Low-E functionality.

[0074] Furthermore, the performance differences among the various embodiments reflect the influence of different film layer parameters on various performance characteristics: Embodiment 2 uses a thinner Ag layer (8nm), achieving the highest visible light transmittance (87%), but with a relatively high emissivity (0.14); Embodiment 3 uses a thicker Ag layer (10nm) and a larger micrometer-level independent unit side length (100μm), resulting in the lowest emissivity (0.07), but with slightly higher electromagnetic shielding loss (6dB); Embodiment 4 uses the smallest micrometer-level independent unit side length (30μm) and the densest etched trenches, achieving the lowest electromagnetic shielding loss (2dB), suitable for scenarios with extremely high communication signal transmittance requirements. These characteristics demonstrate that by reasonably adjusting the Ag layer thickness and patterning parameters, targeted optimization can be achieved between visible light transmittance, emissivity, and electromagnetic wave transmittance according to different application requirements.

[0075] Meanwhile, regarding the electrothermal performance, under a DC voltage of 12-24V, the glass surface temperature in each embodiment can rise to 45-100℃, and the heating rate is fast (reaching a stable temperature in 60-120s), indicating that the conductive grid layer can effectively generate Joule heat and conduct it to the glass surface. Among them, Embodiment 5, due to its larger conductive grid layer thickness (1.0μm), wider linewidth (20μm), and smaller spacing (1.8cm), has the lowest resistance and the highest heating power, exhibiting the strongest electrothermal performance. Furthermore, after 100 on-off cycles, the resistance change rate of Embodiment 5 is less than 5%, demonstrating the excellent heating stability of the conductive grid layer of this invention.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the invention in any way. All equivalent transformations or modifications made in accordance with the essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-transmittance, low-emissivity electrically heated Low-E glass, comprising a glass substrate and a composite film system disposed on the surface of the glass substrate, characterized in that, The composite membrane system comprises layers stacked sequentially: SiN x Bottom dielectric layer; The first ZnO layer is disposed on the SiN x Bottom dielectric layer surface; A patterned Ag layer is disposed on the surface of the first ZnO layer. The patterned Ag layer is composed of multiple arrayed, electrically insulated micron-sized independent units, and there are etched trenches between adjacent micron-sized independent units. TiO x A layer is formed by filling the etched trenches of the patterned Ag layer and covering the surface of the patterned Ag layer. The second ZnO layer is disposed on the TiO. x Layer surface; SiN x The top dielectric layer is disposed on the surface of the second ZnO layer; A conductive gate layer is disposed on the SiN x The surface of the top dielectric layer is used to generate Joule heating when a voltage is applied; A SiO2 surface protective layer is filled within the conductive gate layer and covers the surface of the conductive gate layer.

2. The Low-E glass according to claim 1, characterized in that, The SiN x The thickness of the bottom dielectric layer is 25-32 nm; The thickness of the first ZnO layer is 6-8 nm; The patterned Ag layer has a thickness of 8-10 nm, the micron-level independent units are square with a side length of 30-100 μm, and the etched trenches have a width of 1.5-4 μm. The TiO x The thickness of the layer on the surface of the patterned Ag layer is 18-20 nm; The thickness of the second ZnO layer is 8-12 nm; The SiN x The thickness of the top dielectric layer is 25-35 nm; The conductive gate layer is composed of multiple copper wires, and its structure is a crisscrossing grid structure or a parallel bar gate structure; the thickness of the conductive gate layer is 500nm-1μm, the line width of the copper wires is 15-20μm, and the spacing between two adjacent parallel copper wires is 1.8-2.2cm. The thickness of the SiO2 surface protective layer on the upper surface of the conductive gate layer is 18-25 nm.

3. The Low-E glass according to claim 1, characterized in that, The Low-E glass has a visible light transmittance of 81%-87%, an emissivity of 0.07-0.14, and an average electromagnetic shielding loss of 2-6 dB in the frequency range of 0.1-18 GHz.

4. The Low-E glass according to claim 3, characterized in that, The Low-E glass can reach a surface temperature of 45-100℃ when driven by a DC voltage of 12-24V.

5. A method for preparing Low-E glass as described in any one of claims 1-4, characterized in that, Includes the following steps: Step S1: Clean and surface activate the glass substrate; Step S2: Deposit SiN on the surface of the glass substrate using a magnetron sputtering process. x Bottom dielectric layer; Step S3, in the SiN x The first ZnO layer is deposited on the surface of the bottom dielectric layer using a magnetron sputtering process; Step S4: Deposit an Ag layer on the surface of the first ZnO layer using a magnetron sputtering process; Step S5: The Ag layer is patterned using a laser etching process to etch the Ag layer into multiple micron-sized independent units that are electrically insulated from each other. An etching trench is formed between adjacent micron-sized independent units that penetrate the Ag layer, thus obtaining the patterned Ag layer. Step S6: Deposit TiO2 sequentially on the patterned Ag layer surface using magnetron sputtering. x Layer, second ZnO layer and SiN x Top dielectric layer, the TiO x The layer fills the etched trenches and covers the surface of the patterned Ag layer; Step S7, in the SiN x A conductive gate layer is fabricated on the surface of the top dielectric layer, wherein the linewidth of the conductive gate layer is 15-20 μm and the spacing between adjacent conductive lines is 1.8-2.2 cm; Step S8: A SiO2 surface protective layer is deposited on the surface of the conductive gate layer using a magnetron sputtering process. The SiO2 surface protective layer fills the conductive gate layer and covers the conductive gate layer.

6. The preparation method according to claim 5, characterized in that, In step S2, SiN is deposited. x The process parameters for the bottom dielectric layer are as follows: the target material is Si3N4 target, the sputtering power is 80-120W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:

1. In step S3, the process parameters for depositing the first ZnO layer are as follows: the target material is a ZnO target, the sputtering power is 80-120W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 10:

1.

7. The preparation method according to claim 5, characterized in that, In step S4, the process parameters for depositing the Ag layer are: the target material is an Ag target, the sputtering power is 50-100W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is argon. In step S5, a 355nm ultraviolet nanosecond laser is used to pattern the Ag layer. The laser pulse width is 15-25ns, the repetition frequency is 40-60kHz, the scanning speed is 350-600mm / s, and the single pulse energy is 10-20μJ. The Ag layer is etched into multiple arrayed micron-level independent units. The width of the etching trench is 2-4μm, and the etching depth penetrates the entire Ag layer.

8. The preparation method according to claim 5, characterized in that, In step S6, TiO2 is deposited. x The process parameters for the layer are as follows: the target material is TiO2 target, the sputtering power is 30-50W, the working pressure is 0.8-1.2Pa, and the deposition gas is argon. In step S6, the process parameters for depositing the second ZnO layer are as follows: the target material is a ZnO target, the sputtering power is 80-120W, the working pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 10:

1. In step S6, SiN is deposited. x The process parameters for the top dielectric layer are as follows: the target material is Si3N4 target, the sputtering power is 80-120W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and nitrogen with a flow ratio of argon to nitrogen of 10:

1.

9. The preparation method according to claim 5, characterized in that, In step S7, the conductive gate layer is prepared by photolithography-electroplating or photolithography-magnetron sputtering lift-off.

10. The preparation method according to claim 5, characterized in that, In step S8, the process parameters for depositing the SiO2 surface protective layer are as follows: the target material is a Si target, the sputtering power is 80-120W, the working gas pressure is 0.8-1.2Pa, and the deposition gas is a mixture of argon and oxygen with a flow ratio of argon to oxygen of 8:1.

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