Wide-band silicon photonic wafer-level multi-channel coupling error calibration structure and method

Abstract

The application discloses a wide-band silicon light wafer-level multi-channel coupling error calibration structure and method, and relates to the technical field of silicon light integrated chip wafer-level testing. The structure comprises at least one set of passive straight-through reference gratings; the design parameters of the set of passive straight-through reference gratings are respectively one-to-one corresponding to the design parameters of all working channel coupling gratings in a Die on a wafer, and are completely consistent with the channel number and channel pitch of a fiber array; for each shot: the set of passive straight-through reference gratings are arranged in the non-silicon light chip area in each shot, and are at the same plane height as the coupling gratings on the wafer, and the coupling additional loss matrix of the shot is obtained through testing; the coupling additional loss matrix is used for calibrating the actual measured insertion loss by channel and wavelength, and wafer-level median normalization optimization is carried out to obtain the calibrated insertion loss. The application can eliminate the inter-channel coupling additional loss, improve the calibration accuracy and the accuracy of silicon light wafer testing.

Description

Technical Field

[0001] This application relates to the field of silicon photonics integrated chip wafer-level testing technology, and in particular to a wideband silicon photonics wafer-level multi-channel coupling error calibration structure and method. Background Technology

[0002] Silicon photonics chips, with their advantages of high integration, low power consumption, and low cost, have become core components of optical communication systems, widely used in various scenarios such as 1310nm short-range communication, 1550nm long-range transmission, coarse wavelength division multiplexing (WDM), and dense wavelength division multiplexing (DDM). Silicon photonics chips generally employ grating coupling structures to couple on-chip optical signals to optical fibers. During the wafer-level testing phase, multi-channel fiber arrays (FAs) are used to test the key performance indicators of thousands of chips on the entire wafer. Among these, insertion loss (IL) is a core indicator for evaluating chip performance and selecting qualified chips.

[0003] Currently, there are two unavoidable sources of error in wafer-level testing: First, the fiber optic array (FA) itself has processing errors such as fiber core diameter eccentricity, array pitch deviation, and inconsistent end-face angles; second, there are cumulative assembly and adjustment errors during the installation of the testing system, such as lateral offset, angular sway, pitch tilt, and height defocus. These two types of errors combine to form additional inter-channel coupling losses, causing false inter-channel differences in the measured IL data. This makes it impossible to accurately reflect the process consistency of the silicon photonics chip itself, and may even lead to the mis-screening of qualified chips and the misplacement of unqualified chips. Summary of the Invention

[0004] The purpose of this application is to provide a wideband silicon photonics wafer-level multi-channel coupling error calibration structure and method, which can eliminate the additional loss of inter-channel coupling and improve the calibration accuracy and the accuracy of silicon photonics wafer testing.

[0005] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a wideband silicon photonics wafer-level multi-channel coupling error calibration structure, comprising: at least one set of passive through-reference gratings; A set of passive through-reference gratings has design parameters that correspond one-to-one with the design parameters of the coupling gratings of all working channels in the die on the wafer; the design parameters include layout parameters and process parameters. The number of channels in a set of passive through-reference gratings is the same as the number of channels in the fiber array in the test system, and the channel pitch of a set of passive through-reference gratings is exactly the same as the channel pitch of the fiber array in the test system. When performing wafer-level testing on silicon photonics chips using a testing system, for each shot on the wafer: a set of passive through-reference gratings is used to lay out the non-silicon photonics chip area within each shot, and is at the same plane height as the coupling grating on the wafer. The coupling additional loss matrix of the shot is obtained through testing by the testing system. The coupling additional loss matrix is ​​used to calibrate the measured insertion loss of each die within the shot at each working channel and each working wavelength, and wafer-level median normalization optimization is performed to obtain the calibrated insertion loss. The non-silicon photonics chip area includes the BB region within the shot, the non-functional region within the die, and the dicing slot.

[0006] Optionally, the passive through-reference grating includes: an input reference grating, a passive single-mode straight waveguide, and an output reference grating; The input reference grating and the output reference grating are connected by a passive single-mode straight waveguide; the passive single-mode straight waveguide is a straight waveguide without bending, splitting, resonance, or filtering structure; All layout and process parameters of the input and output reference gratings are perfectly matched with the coupling gratings of the working channels in the die on the wafer; The input reference grating is used to receive the optical signal input from the fiber array in the test system and transmit it to the output reference grating through a passive single-mode straight waveguide; the output reference grating is used to output the optical signal transmitted by the passive single-mode straight waveguide to the optical power meter in the test system to obtain the coupling additional loss.

[0007] Optionally, the length of the passive single-mode straight waveguide ranges from 100μm to 200μm.

[0008] Optionally, the passive through-reference grating includes: a single grating and a reflective structure; All layout and process parameters of the single grating are perfectly matched with the coupling grating of the working channel in the die on the wafer; A single grating is used to receive optical signals input from the fiber optic array in the test system; The reflective structure is used to reflect the optical signal back to the single grating after it is transmitted through the straight waveguide, and output it to the optical power meter in the test system to obtain the coupling additional loss.

[0009] Optionally, the layout parameters include: grating period, duty cycle, and waveguide width; The process parameters include: etching depth and core layer thickness; Based on the same layout parameters and process parameters, the passive through-reference grating and the coupled grating have the same center wavelength, coupling angle and bandwidth.

[0010] Optionally, the layout of a set of passive through-reference gratings in the non-silicon photonic chip regions within each shot includes: a fixed layout of the BB region; a distributed layout of the BB region; a layout of the non-dicing region at the edge of the shot; a layout of the non-functional area within the die; a segmented layout of the dicing slot; and a combined layout of the dicing slot and the BB region.

[0011] Secondly, this application provides a wideband silicon photonics wafer-level multi-channel coupling error calibration method, wherein the method employs the aforementioned wideband silicon photonics wafer-level multi-channel coupling error calibration structure, and the method includes: Test a set of passive through-reference gratings within each shot to obtain the coupling additional loss matrix of the shot; The actual loss of each working channel and each working wavelength is calibrated channel by channel and wavelength by using the coupling additional loss matrix to obtain the calibrated chip intrinsic true insertion loss of each working channel and each working wavelength. The intrinsic true insertion loss of the calibrated chip is optimized by wafer-level median normalization to obtain the final insertion loss.

[0012] Optionally, a set of passive through-reference gratings within each shot is tested to obtain the coupling-added loss matrix of the shot, including: Align the fiber array in the test system with a set of passive through-reference gratings, perform coarse and fine alignment, find the peak coupling power point of the working wavelength, and lock the Z-axis height and coupling angle of the fiber array. A set of passive through-reference gratings was scanned using an optical fiber array, and the measured insertion loss of the passive through-reference gratings at each working channel and each working wavelength was recorded. Based on the measured insertion loss of the passive through-reference grating at each working channel and wavelength, using the formula... The coupling loss at each working channel and at each working wavelength is determined, and the coupling loss matrix of the shot is constructed; where, For work passage and operating wavelength The coupling-related additional losses, For passive through-reference grating in the working channel and operating wavelength The measured insertion loss is as follows. For passive through-reference grating at operating wavelength The intrinsic fixed transmission loss is as follows.

[0013] Optionally, the calibration formula for the actual loss is: ; In the formula, For work passage and operating wavelength The intrinsic true insertion loss of the chip after calibration. For work passage and operating wavelength The measured insertion loss is as follows. For work passage and operating wavelength The coupling loss is added below; Based on the coupling additional loss matrix, using the formula The measured insertion loss is optimized and calibrated using wafer-level median normalization to obtain the final wafer-level insertion loss; where, This represents the final insertion loss at the wafer level. These are the weighting coefficients. For all dies of the wafer of the median.

[0014] Optionally, the intrinsic true insertion loss of the calibrated chip is optimized by wafer-level median normalization to obtain the final insertion loss, including: The median of the coupling loss of all dies on the entire wafer at each working channel and each working wavelength was calculated. Based on the median, the calibrated intrinsic true insertion loss of the chip is subjected to 3σ outlier removal or interquartile range outlier removal to obtain the final insertion loss.

[0015] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a wideband silicon photonics wafer-level multi-channel coupling error calibration structure and method. By deploying a passive through-reference grating in the non-silicon photonic chip region within the shot, the coupling-added loss matrix of the shot is measured. Since the design parameters of the passive through-reference grating correspond one-to-one with the design parameters of the coupling gratings of all working channels in the die on the wafer, all coupling-added losses, including those caused by fiber array processing errors, assembly and adjustment cumulative errors, and wavelength-related coupling deviations, are completely of the same origin as the systematic errors of the working channels. After calibrating the measured insertion loss channel by channel and wavelength by wavelength, the systematic errors are completely eliminated, truly restoring the intrinsic channel consistency of the silicon photonic chip, and improving the calibration accuracy and the accuracy of silicon photonics wafer testing.

[0016] The passive through-band reference grating is bend-free and beam-splitting, completely solving the problems of additional losses and inaccurate error calibration introduced by previous bent waveguides. The design parameters of a set of passive through-band reference gratings correspond one-to-one with the design parameters of the coupling gratings for all working channels within the die on the wafer. This ensures that the wavelength of the passive through-band reference grating corresponds one-to-one with the wavelength of the coupling gratings for all working channels, eliminating band limitations and adapting to all optical communication bands, breaking the limitations of single-band adaptation in previous inventions. The non-silicon photonic chip area includes the BB region within the shot, the non-functional area within the die, and the dicing slot. It does not occupy the effective area of ​​the die and requires no modification to the chip layout, solving the shortcomings of previous inventions such as occupying chip area and high costs for modifying existing chips. The passive through-band reference grating adopts a purely passive structure with no additional active components. Since the design parameters of the reference grating and the coupling grating are the same, they can share the same photomask and etching process, requiring no additional process steps. This avoids the problems of additional process optimization required for bent waveguides and increased fabrication costs for active structures in previous inventions. By using the coupled additional loss matrix to calibrate the measured insertion loss of each die within the shot at each working channel and each working wavelength, and performing wafer-level median normalization optimization, temperature drift and random alignment errors can be verified. This solves the problem that previous inventions could only subtract errors based on the basic values ​​and could not suppress drift, improve the consistency of wafer-level global calibration, avoid calibration deviations caused by environmental and process fluctuations, and make the test data more stable and reliable. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the overall layout of the silicon photonics wafer provided in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the calibration structure of the BB area within a single shot and the layout of the working channel within the die, provided in an embodiment of this application.

[0020] Figure 3 This is a schematic diagram of the passive through-type reference grating pair structure provided in an embodiment of this application.

[0021] Figure 4 This is a schematic flowchart of a wideband silicon photonics wafer-level multichannel coupling error calibration method provided in an embodiment of this application.

[0022] Figure 5 This is a schematic diagram of the wafer-level testing and calibration process provided in an embodiment of this application.

[0023] Figure 6 This is a schematic diagram of the IL comparison curves before and after multi-channel system error calibration and verification provided in the embodiments of this application.

[0024] Figure 7 A schematic diagram of the median of the calibrated FA system additional loss curve provided for embodiments of this application.

[0025] Figure reference numerals: shot outline-1, coupled grating array-2, BB region-3, passive through reference grating pair-4, passive single-mode straight waveguide-5, input reference grating-6, output reference grating-7. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The wafer, as the carrier of silicon photonics chips, has multiple shot units uniformly distributed on its surface for mass production of chips. A shot unit (or reticle) is the basic exposure unit on the wafer, containing multiple dies and a BB region. A die is a single chip unit after dicing on the wafer, and is the smallest functional unit of a silicon photonics chip. The calibration structure in this application does not occupy the effective area of ​​the die and can be placed in the non-functional area within the die. The non-functional area within the die is an idle area within the die unit that is not used for the core chip function, and can be used as one of the layout locations for the calibration structure, adapting to ultra-high precision calibration scenarios. BB: English full name Building Block, Chinese annotation: process monitoring unit, an idle area within the shot used to monitor chip process quality (BB process monitoring area), is the preferred layout location for the calibration structure in this application. A dicing groove is a groove on the silicon photonics wafer used to divide different dies, i.e., a narrow area between dies. In this application, it can be used as one of the layout locations for the calibration structure, using a segmented layout to avoid dicing damage. The overall layout of the silicon photonics wafer is as follows. Figure 1 As shown.

[0029] In the wafer-level testing stage: 1. Chips not yet diced: At this stage, front-end processes such as photolithography, etching, and deposition have been completed on the wafer, forming thousands of independent chips (dies), but the chips are still connected together by the wafer. 2. Probe testing: Probe cards in the testing system are used to contact the test pads of each chip on the wafer to perform electrical tests. 3. Defect screening: Unqualified chips are marked by testing to avoid wasting costs in subsequent packaging. 4. Wafer map generation: The test results of each chip are recorded for subsequent processes. During wafer-level testing, the probes directly test the performance of the silicon photonics chip on each die.

[0030] There can be multiple working channels within a die. During wafer-level testing, the performance of all working channels within the die is tested simultaneously or sequentially using multi-channel FA to determine the overall die's qualification.

[0031] The existing patents related to wafer-level testing are described below: US Patent Publication No. US2023384516A1, entitled "Loopback waveguide," has the following core technical solution (based on the full text of the publication): 1. Core Structure: A curved waveguide loop structure is adopted to connect the first optoelectronic circuit (optical emitter, including laser, modulator, etc.) and the second optoelectronic circuit (optical receiver, including photodetector, etc.) on the chip through the curved waveguide to form a closed-loop optical path.

[0032] 2. Test principle: By contacting the pads on the chip with an electrical probe, the optical emitting circuit is electrically activated to generate an optical signal. The optical signal is transmitted to the optical receiving circuit through the loop waveguide. The electrical signal output by the receiving circuit is then measured by the electrical probe, thereby evaluating the optoelectronic function and performance of the chip.

[0033] 3. Layout features: Supports two layout methods: 1) Loopback waveguide is laid out inside the same die; 2) Loopback waveguide is laid out in the non-functional area of ​​an adjacent die and is removed during the dicing process after testing.

[0034] 4. Process Implementation: The loopback waveguide and other optical waveguides on the chip are fabricated simultaneously using the same process and can be integrated into the interposer structure.

[0035] 5. Core Innovation: Proposes a scheme to place the loop waveguide on adjacent dies, reducing the occupation of the effective area of ​​the die under test.

[0036] The core flaws of this patent are: 1. Unable to calibrate fiber array coupling loss: The loopback waveguide in this patent is only used to test the functional integrity of the internal optoelectronic circuit of the chip, and does not involve the calibration of coupling loss between the FA and the chip grating. Therefore, it cannot solve the problem of FA processing error and assembly and adjustment cumulative error targeted by this application.

[0037] 2. Calibration accuracy is severely limited: The U-shaped / bent waveguide loop structure introduces non-negligible bending loss, mode conversion loss and propagation loss. Moreover, these losses are greatly affected by process fluctuations and cannot be accurately calibrated in advance, resulting in test errors that are usually greater than 0.5dB.

[0038] 3. Wasted chip area: Even with an adjacent die layout, a large area of ​​adjacent dies is still required, and the existing process monitoring area (BB area) on the wafer cannot be utilized, resulting in limited improvement in overall wafer utilization.

[0039] 4. Unable to compensate for process fluctuations between shots: It only supports one-time calibration of a single die or the entire wafer, does not take into account the process differences between different exposure units (shots), cannot compensate for the fluctuations in grating coupling characteristics between shots, and the calibration accuracy is inconsistent across the entire wafer.

[0040] 5. Poor band compatibility: It mainly focuses on fixed adaptation of single bands and lacks a universal design for multi-wavelength and multi-channel scenarios of CWDM (Coarse Wavelength Division Multiplexing) / DWDM (Dense Wavelength Division Multiplexing). A set of calibration structures can only adapt to a single band, resulting in poor reusability.

[0041] 6. Low testing efficiency: Each die needs to be individually contacted and tested with electrical probes, making it impossible to achieve shot-level calibration and full shot reuse. The testing speed is slow and cannot meet the mass production testing needs of thousands of chips on a 12-inch wafer.

[0042] 7. Cannot achieve pure optical calibration: It must rely on active optoelectronic devices (lasers, photodetectors) on the chip to work, and cannot perform coupling loss calibration on passive silicon photonic chips, thus limiting its applicability.

[0043] Chinese patent CN110988646A, entitled "A Calibration Structure and Method for Wafer-Level Testing of Silicon Photonics Chips," has the following core technical solution: Core structure: A multi-channel calibration structure is integrated within the wafer dicing groove, including an optical switch, a beam splitter, and a reference waveguide.

[0044] Test principle: By switching different channels through an optical switch, the transmission loss of the reference waveguide is measured, and the test system error is calibrated.

[0045] Layout features: The entire calibration structure is arranged within the dicing slot, without occupying the effective area of ​​the die.

[0046] Core innovation: A scheme to integrate calibration structures within the dicing groove is proposed, avoiding the occupation of chip area.

[0047] The core flaws of this patent are: 1. The layout of the dicing slot poses a process risk: The entire calibration structure is located within the dicing slot, occupying a large amount of dicing slot space. This is incompatible with advanced narrow dicing slot designs and can easily damage the calibration structure during the dicing process, leading to calibration failure.

[0048] 2. Unable to compensate for process fluctuations between shots: It only supports one-time calibration of the entire wafer and does not take into account the process differences between different shots, resulting in inconsistent calibration accuracy across the entire wafer.

[0049] 3. Active structures increase cost and complexity: The use of active / passive complex devices such as optical switches and beam splitters increases the cost of fabrication and process complexity. In addition, active devices themselves have performance deviations, introducing additional calibration errors.

[0050] 4. Single-band compatibility: Designed only for 1550nm single-band, it is not compatible with 1310nm and CWDM / DWDM multi-wavelength scenarios.

[0051] Chinese patent application CN119738693A, entitled "A Wafer-Level Testing and Calibration Structure, System, and Method for Silicon Photonics Chips," has the following core technical solution: Core structure: An active calibration module is integrated at the chip edge, which includes an optical switch array, a power beam splitter, and a standard reference unit.

[0052] Test principle: By selecting different calibration channels through an active optical switch, the automatic calibration of multi-channel system errors can be achieved.

[0053] Layout features: The calibration module is located in the edge area inside the die.

[0054] Core innovation: Propose a fully automated test and calibration scheme that integrates an active calibration module.

[0055] The aforementioned publicly disclosed patent solutions all have obvious technical defects and cannot meet the requirements of low cost, high compatibility, and high precision for mass production testing of full-band silicon photonics chips.

[0056] The core flaws of this patent application are: 1. Occupying valuable die area: The calibration module is located in the inner edge area of ​​the die, occupying valuable chip area and increasing chip size and manufacturing cost.

[0057] 2. High cost of active structure: Integrating a large number of active optical switches and power beam splitters significantly increases the cost of fabrication and power consumption, and the yield of active devices will affect the overall test yield.

[0058] 3. Unable to achieve shot-level calibration: Only supports single-die calibration, resulting in low testing efficiency and failing to meet the mass production requirements of 12-inch wafers.

[0059] 4. No BB area layout scheme: The layout method of monitoring the area using wafer BB process is not mentioned, which makes it impossible to achieve zero-modification cost adaptation of existing chips.

[0060] The core gaps in the existing solutions are as follows: 1. None of the published patents propose a "calibration structure layout scheme based on the monitoring area of ​​the building block (BB) process within the wafer shot / reticle", which cannot simultaneously meet the core mass production requirements of "not occupying die area, not affecting the dicing process, shot-level accurate calibration, high efficiency in mass production, and zero chip modification cost".

[0061] 2. Existing solutions are mostly single-band fixed adaptations, lacking universal wide-band compatible designs, and cannot simultaneously cover all scenarios of 1310nm, 1550nm, CWDM, and DWDM. They have poor reusability and high mass production adaptation costs.

[0062] To overcome the aforementioned deficiencies of the prior art, in an exemplary embodiment, such as Figure 2 As shown, a wideband silicon photonics wafer-level multi-channel coupling error calibration structure is provided, comprising: at least one set of passive through-reference gratings. The design parameters of the set of passive through-reference gratings correspond one-to-one with the design parameters of the coupling gratings of all working channels within the die on the wafer; the design parameters include layout parameters and process parameters. The number of channels in the set of passive through-reference gratings is the same as the number of channels in the fiber array of the test system, and the channel pitch of the set of passive through-reference gratings is completely consistent with the channel pitch of the fiber array of the test system.

[0063] When performing wafer-level testing on silicon photonics chips using a testing system, for each shot on the wafer: a set of passive through-reference gratings is used to lay out the non-silicon photonics chip area within each shot, and is at the same plane height as the coupling grating on the wafer. The coupling additional loss matrix of the shot is obtained through testing by the testing system. The coupling additional loss matrix is ​​used to calibrate the measured insertion loss of each die within the shot at each working channel and each working wavelength, and obtain the calibrated insertion loss. The non-silicon photonics chip area includes the BB region within the shot, the non-functional region within the die, and the dicing slot.

[0064] The calibration structure described in this application is characterized by its universality across all wavelengths, minimalist design, complete passivity, no additional processing costs, and compatibility with existing mass production testing platforms. It supports three flexible layouts: in-die, shot-level BB area, and dicing slot. It can completely eliminate the coupling losses introduced by FA processing errors and assembly / adjustment cumulative errors, accurately restoring the intrinsic inter-channel IL consistency of silicon photonics chips. Simultaneously, it is fully compatible with all scenarios including 1310nm, 1550nm, CWDM, and DWDM, completely circumventing the protection scope of existing core patents. This application is applicable to silicon photonics chips in the 1310nm O-band, 1550nm C / L-band, and CWDM / DWDM all-optical communication bands, used to eliminate multi-channel IL caused by FA processing errors and assembly / adjustment cumulative errors.

[0065] Figure 2 The shot outline 1 and the coupled grating array 2 consisting of multiple coupled gratings are also shown.

[0066] As an optional implementation method, such as Figure 3 As shown, the passive through reference grating is a passive through reference grating pair 4 (referred to as the reference grating pair) that is completely matched with the operating band of the chip under test. It consists of an input reference grating 6, an output reference grating 7, and a passive single-mode straight waveguide 5 connecting the two.

[0067] Core matching constraints (universal across all bands, the core of calibration effectiveness): All layout and process parameters of the input reference grating 6 and the output reference grating 7 are perfectly matched 1:1 with the coupling grating (part of the silicon photonics chip) of the working channel within the die under test. This includes, but is not limited to, center wavelength, grating period, duty cycle, etching depth, coupling angle, 3dB bandwidth, mode field diameter, waveguide core layer thickness, and process layer. This ensures that the coupling characteristics of the two are completely consistent, and the system errors are completely homogeneous, adapting to any band scenario of 1310nm, 1550nm, CWDM, and DWDM. Among them, the grating period, duty cycle, and waveguide width are layout parameters, the etching depth and waveguide core layer thickness are process parameters, and the center wavelength, coupling angle, and 3dB bandwidth are the result of the interaction between layout and process parameters. Based on the same layout and process parameters, the passive through-reference grating and the coupling grating have the same center wavelength, coupling angle, and bandwidth.

[0068] Without changing the core principle of "no additional cost", the passive through reference grating and the coupling grating of the working channel are fabricated with the same photomask, or they can be fabricated with different photomasks using the same process (same source photomask), ensuring that the layout and process parameters are completely consistent, adapting to scenarios where photomask design is limited, without increasing additional process costs.

[0069] Alternative waveguide fabrication process: The original solution is a standard etching process, which can be replaced by a combination of dry etching and wet polishing, further reducing the intrinsic transmission loss of the straight waveguide (which can be reduced to ≤0.08dB) and improving the upper limit of calibration accuracy.

[0070] Waveguide Constraints: The passive single-mode straight waveguide 5 is a straight-through waveguide without bending, beam splitting, resonance, or filtering structures. Its length is controlled between 100μm and 200μm, and the intrinsic transmission loss within the target operating band is less than or equal to 0.1dB, a fixed value that can be calibrated in advance through simulation and sample testing. Without changing the core "passive straight-through" design, the length of the passive single-mode straight waveguide 5 can also be between 80μm and 220μm. For example, the material of the passive single-mode straight waveguide 5 can be replaced with a silicon nitride waveguide based on existing silicon-based waveguides to adapt to higher precision and wider band scenarios without changing the core constraints of "no bending and no beam splitting".

[0071] Arrangement constraints: The channel pitch of the passive through-type reference grating pair 4 is completely consistent with the channel pitch of the test FA (composed of multiple optical fibers arranged at a fixed pitch, used to couple on-chip optical signals with external test equipment in wafer-level testing). The number of channels corresponds one-to-one with the number of FA channels. All reference gratings and the coupling gratings of the working channels are at the same height on the wafer plane to ensure that the Z-axis defocusing amount is completely consistent during coupling.

[0072] The input reference grating 6 is used to receive the optical signal input from the fiber array in the test system and transmit it to the output reference grating 7 through the passive single-mode straight waveguide 5; the output reference grating 7 is used to output the optical signal transmitted by the passive single-mode straight waveguide 5 to the optical power meter in the test system to obtain the coupling additional loss.

[0073] As an alternative implementation, the passive through-reference grating includes a single grating and a reflective structure. This structure adds a small reflector to the passive through-reference grating pair 4 and eliminates the output reference grating 7. The optical signal is transmitted via a straight waveguide and then reflected back to the input. While simplifying the structure, it still enables system error calibration and is suitable for ultra-narrow black-and-white (BB) areas and ultra-small shot sizes.

[0074] All layout and process parameters of the single grating are perfectly matched to the coupling gratings of the working channels within the die on the wafer. The single grating is used to receive the optical signal input from the fiber array in the test system. The reflective structure is used to reflect the optical signal back to the single grating after transmission through the straight waveguide, and output it to the optical power meter in the test system to obtain the coupling loss.

[0075] As an optional implementation method, multi-band dedicated adaptation is available: For CWDM / DWDM multi-wavelength multi-channel chips, passive direct-pass reference grating pairs with the same wavelength can be designed one-to-one according to the working wavelength channel to achieve precise calibration wavelength by wavelength and channel by channel; For wide-band working chips, broadband reference grating pairs with the same bandwidth as the working grating can be designed to achieve continuous calibration throughout the entire working band.

[0076] To achieve multi-band adaptation, without changing the core of "full-band compatibility", a "wideband reference grating + wavelength compensation algorithm" can be used for multi-wavelength reference gratings. Only one set of wideband reference gratings is designed to cover the entire 1310nm-1610nm band. The algorithm compensates for coupling deviations at different wavelengths, reduces the number of reference grating pairs, simplifies layout design, and reduces process complexity.

[0077] For broadband reference gratings: Broadband reference gratings are designed with a fixed bandwidth, but they can also be replaced with tunable broadband gratings. By fine-tuning the grating etching parameters, the bandwidth can be adapted to be compatible with CWDM / DWDM chips of different frequency bands, thus improving the reusability of the solution.

[0078] As an alternative implementation, without altering the core principle of "not occupying the effective die area," the layout of a set of passive through-reference gratings within the non-silicon photonic chip region of each shot includes: ① Fixed layout of the BB area; ② Distributed layout of the BB area, distributing passive through-type reference grating pairs across multiple idle points in the BB area, adapting to scenarios with small BB area space and irregular shape; ③ Layout of non-scribing areas at the shot edge, further avoiding the risk of scribing damage; ④ Layout of non-functional areas within the die; ⑤ Segmented layout of the scribe groove; ⑥ Combined layout of the scribe groove and BB area, in narrow scribe groove scenarios, reserving only a few points in the scribe groove, combined with the passive through-type reference grating pairs in the BB area, balancing medium-low precision and mass production efficiency, avoiding the damage risk of a single scribe groove layout.

[0079] The beneficial effects of the calibration structure in this application are: 1. High calibration accuracy: Universal across the entire band, it can suppress the IL test deviation caused by the cumulative error of FA processing and assembly to within ±0.1dB, completely eliminate systematic errors, and truly restore the intrinsic channel consistency of the chip; 2. Extremely strong compatibility across all scenarios: No band limitations, perfectly adaptable to 1310nm short-range communication, 1550nm long-range transmission, CWDM, DWDM and all scenarios, one solution covers all silicon photonics chip testing needs; 3. Maximizes mass production compatibility: The optimal solution for the BB area does not occupy the effective die area at all, requires no modification to the chip layout itself, has zero cost for modifying existing chips, does not affect the dicing process, is compatible with all advanced processes, allows for shot-level calibration and full shot reuse, and improves testing efficiency by tens of times. 4. Extremely low cost: Pure passive structure, no additional active components, no additional fabrication process steps, no need to modify existing mass production testing platforms, and can be reused throughout the entire R&D and mass production process; 5. Thorough patent avoidance: The core BB area layout scheme and the universal calibration logic for the entire band are both blanks in existing patents. The structure and method are significantly different from existing core patents, which can form a complete independent intellectual property protection.

[0080] Based on the same inventive concept, this application also provides a wideband silicon photonics wafer-level multichannel coupling error calibration method employing the wideband silicon photonics wafer-level multichannel coupling error calibration structure described above. The solution provided by this method is similar to the solution described above; therefore, the specific limitations in one or more method embodiments provided below can be found in the limitations of the wideband silicon photonics wafer-level multichannel coupling error calibration structure described above, and will not be repeated here.

[0081] In one exemplary embodiment, such as Figure 4 As shown, a wideband silicon photonics wafer-level multi-channel coupling error calibration method is provided, including the following steps 101 to 103.

[0082] Step 101: Test a set of passive through-reference gratings within each shot to obtain the coupling additional loss matrix of the shot.

[0083] Step 102: Use the coupling additional loss matrix to calibrate the actual loss of each working channel and each working wavelength channel by channel and wavelength to obtain the calibrated intrinsic true insertion loss of the chip at each working channel and each working wavelength.

[0084] Step 103: Perform wafer-level median normalization optimization on the intrinsic true insertion loss of the calibrated chip to obtain the final insertion loss.

[0085] Based on steps 101 to 103 above, the calibration structure undergoes a three-step calibration: first, homogeneous error calibration; second, channel-by-channel subtraction; and third, wafer-level median normalization optimization. See steps 1 to 3 for details.

[0086] Step 1: Based on the calibration structure, calibrate the system coupling additional loss to obtain the system coupling additional loss as follows: .

[0087] For work channels Passive through-reference grating in the working channel and operating wavelength The measured insertion loss is as follows: The passive through-reference grating at the operating wavelength The intrinsic fixed transmission loss is as follows: (After prior calibration through simulation and sample testing), then in the working channel and operating wavelength Coupled additional loss for: ; in It fully encompasses all the additional coupling losses caused by the processing error, assembly and adjustment cumulative error, and wavelength-related coupling deviation of the nth fiber in the FA, and is completely of the same origin as the system error of the working channel.

[0088] Step 2: Based on the coupling additional loss obtained above, calibrate the actual loss of the working channel to obtain the result in the working channel. and operating wavelength The intrinsic true insertion loss of the chip after calibration .

[0089] For work channels and operating wavelength Below, the measured insertion loss is The intrinsic true insertion loss of the calibrated chip is: .

[0090] Step 3: Perform wafer-level median normalization optimization on the calibrated intrinsic true insertion loss of the chip to obtain the final insertion loss.

[0091] Based on the characteristic that the median difference is extremely small among thousands of chips on the same wafer and under the same wavelength channel, statistics were compiled for all shots / dies on the entire wafer, and for each channel and wavelength. the median of Perform 3 calibrations on single-shot / single-die data. σ Outlier removal and optimization of the calibration formula are as follows: ; in This is a weighting coefficient, typically ranging from 0.8 to 1.0, which balances the local calibration accuracy of a single shot / die with the global consistency of the wafer, further suppressing the effects of random alignment errors, temperature drift, and wavelength-dependent drift. It can be an adaptive weighting coefficient (automatically adjusted based on the process fluctuations between shots). Value, when it fluctuates greatly Take a value of 0.8-0.9, for small fluctuations. (Take a value of 0.9-1.0) to improve the adaptive capability of calibration and adapt to wafers with different process stability.

[0092] 3σ outlier removal can be replaced by interquartile range (IQR) outlier removal, which is suitable for scenarios with large dispersion of test data and can also ensure the accuracy of calibration data.

[0093] Based on the above, the execution process of the first step may include steps 201 to 203.

[0094] Step 201: Align the fiber array in the test system with a set of passive through reference gratings, perform coarse and fine alignment, find the peak coupling power point of the working wavelength, and lock the Z-axis height and coupling angle of the fiber array.

[0095] Step 202: Use an optical fiber array to scan all channels of a set of passive through-reference gratings and record the measured insertion loss of the passive through-reference gratings at each working channel and each working wavelength.

[0096] Step 203: Based on the measured insertion loss of the passive through-reference grating at each working channel and working wavelength, use the formula... The coupling loss of each working channel and each working wavelength is determined, and the coupling loss matrix of the shot is constructed.

[0097] In another exemplary embodiment of this application, step 101 performs shot calibration, and steps 102 and 103 perform calibration. Without changing the core of "error stripping", the execution order of steps 102 and 103 can be: "calibrate once per shot" and then calibrate once, or it can be a combination of "shot calibration + timed calibration". For example, after every 5 to 15 shots, a BB area calibration is performed. It is not necessary to calibrate every shot, which further improves the testing efficiency and suppresses the effects of temperature drift and drift during long-term testing.

[0098] The following examples, using typical single-band implementation (1310nm as an example) and multi-wavelength division multiplexing implementation (1550nm CWDM / DWDM) to fully cover all scenarios, such as adapting to the mass production testing of 8-inch or 12-inch silicon photonic wafers, illustrate in detail the calibration structure and calibration method of this application.

[0099] Example 1: Mass production scenario of 1310nm band single channel (typical example) This embodiment is suitable for mass production scenarios with 12-inch silicon photonics wafers, 8-channel FA, 250μm channel pitch, and 1310nm O-band grating coupling. The core adopts a BB area layout scheme. 1. Layout design and implementation: The coupling grating parameters of the working channel (1310nm adaptation): grating period 500nm, duty cycle 0.5, etching depth 70nm, coupling angle 12° (specifically determined according to FA angle), 3dB bandwidth ≥40nm, single-mode waveguide width 400nm, SOI core layer thickness 220nm, adapted for 1310nm wavelength single-mode transmission. Reference grating parameters: 1:1 complete replica of the coupling grating with the working channel, straight waveguide length 150μm, simulated intrinsic transmission loss of 0.03dB at 1310nm band, i.e. ; BB area layout design: Each shot of the 12-inch wafer is 26mm×33mm in size, and each shot contains 8×12 dies. The upper left corner of the shot reserves a fixed BB process monitoring area with a size of 2mm×5mm. An 8-channel reference grating pair is laid out in the BB area with a channel pitch of 127μm, which is fully matched with the test FA. The Y-axis height of the reference grating pair is completely consistent with the Y-axis height of the coupling gratings (referred to as working gratings) of the working channels of all dies in the shot, ensuring the matching of coupling defocus.

[0100] 2. Chip fabrication implementation: The reference grating and the coupling grating of the working channel are fabricated simultaneously using the same photomask and etching process, without additional photolithography or etching steps, without increasing the cost of wafer fabrication, and are fully compatible with standard silicon photonics wafer fabrication processes.

[0101] 3. Test Implementation: The test platform employs a commercial silicon photonics probe station, a 1310nm broadband light source, and a multi-channel optical power meter. The fiber optic array (FA) is an 8-channel single-mode fiber array with a 127μm pitch. The optical signal transmission process is: FA → coupling grating → on-chip waveguide / device → output grating → FA → power meter. The multi-channel power meter simultaneously measures the output power of all 8 channels to calculate the insertion loss. Figure 5 As shown, the specific testing process is as follows: 1) FA Pre-installation and Initial Calibration: Fix the FA to the probe station optical adjustment frame, complete the connection between the 1310nm optical path and the test equipment, and confirm that the optical power of all channels is normal; select the BB area of ​​the first shot of the wafer, align the FA with the reference grating pair, complete coarse alignment and fine alignment, find the peak coupling power point of the 1310nm wavelength, and lock the Z-axis height and coupling angle of the FA; scan the entire channel reference grating pair and record the initial... Calculate the initial The matrix is ​​used to pre-calibrate the inherent processing errors of the FA (Fabrication Equipment). The process of finding the peak coupling power point at 1310nm wavelength through coarse alignment and fine alignment is as follows: A two-dimensional coordinate system, the xoy coordinate system, is constructed, where the x-axis represents the current coordinates of the FA and the y-axis represents the coupling power. Generally, the curve corresponding to coarse or fine alignment resembles a downward-facing parabola, and the peak value of this curve is the optimal coupling power point. The coordinates of the optimal coupling power point are the final position of the FA. The coarse alignment stage quickly finds the vicinity of the optimal coupling power point, with a relatively large movement range and step size. The fine alignment stage finds the optimal coupling power point, with a relatively small movement range and finer step size.

[0102] Insertion loss The calculation formula is: ; in, This refers to the input optical power (the power before it enters the device under test). This refers to the output optical power (the power after passing through the device under test). The unit is dB (decibels).

[0103] 2) Shot-level calibration and die-by-die testing: The probe station moves the wafer stepper. Upon entering a new shot, it first locates the BB region of that shot, tests the reference grating pair, and updates the shot-specific calibration. Matrix; then sequentially locate all dies under test within that shot, without needing to re-align, and directly test all working channels. It calculates and outputs the calibrated value in real time using the calibration formula. Synchronously store measured values, calibrated values, and error matrix to complete a single die test; 3) Drift compensation and global consistency verification: After every 10 shots, return to the BB area of ​​the first shot, recalibrate the error matrix, and verify the effects of FA assembly drift and temperature drift; if the deviation exceeds 0.2dB, update the wafer global consistency verification. Drift compensation is performed for subsequent tests. After the whole wafer test is completed, the median IL of each channel after calibration is calculated. If the difference between the medians of the channels is ≤0.1dB, the calibration is deemed effective and the system error has been completely eliminated.

[0104] Example 2: 1550nm CWDM / DWDM multi-wavelength scenario This embodiment is suitable for mass production scenarios of 12-inch silicon photonics wafers, 16-channel FA, 127μm channel pitch, 1550nm C-band 8-channel CWDM chip (wavelength range 1470nm-1610nm, channel spacing 20nm), and the core adopts the BB area layout scheme.

[0105] Map design and implementation: Coupling grating parameters for the working channel: 8 CWDM wavelength channels correspond to 8 dedicated gratings, with center wavelengths of 1470nm, 1490nm, 1510nm, 1530nm, 1550nm, 1570nm, 1590nm, and 1610nm respectively. The grating period, duty cycle, and etching depth are designed according to the corresponding center wavelengths. The 3dB bandwidth is ≥25nm, the channel pitch is 127μm, and it is matched with a 16-channel FA. Reference grating pair parameters: Eight sets of reference grating pairs with identical parameters are designed for each of the eight CWDM wavelength channels, and the coupling gratings of the corresponding working channels are completely replicated 1:1. The straight waveguide length is 120μm, and the simulated intrinsic transmission loss across the entire wavelength band is ≤0.07dB. The intrinsic transmission loss at each wavelength is pre-calibrated. ; BB area layout design: In the BB area of ​​each shot, 8 sets of 16-channel reference grating pairs are arranged in wavelength order, which are completely matched with the arrangement direction, pitch and height of the working channel. The system error calibration of all 8 wavelength channels can be completed in one alignment. Tape-out and testing implementation: The reference grating is fabricated using the same process as the coupling grating of the working channel, incurring no additional cost. During testing, a tunable laser is used to cover the entire 1470nm-1610nm wavelength band, and system error calibration and working channel calibration are completed wavelength by wavelength. The calibration logic is completely consistent with that of Example 1, which can achieve system error stripping across the entire wavelength channel. After calibration, the inter-channel IL difference is ≤0.15dB, which fully meets the mass production testing requirements of CWDM / DWDM chips.

[0106] At the 1310nm wavelength, the IL comparison curves before and after multi-channel system error calibration are as follows: Figure 6 As shown, the calibrated additional loss curve of the FA system - median is as follows: Figure 7 As shown.

[0107] Regarding the core patents in this field, the core inventive point of this application (the passive grating calibration structure based on the BB region within the shot and the wavelength-by-wave calibration method across the entire band) has not been disclosed by any existing patents, and belongs to the technical gap in this field.

[0108] 1. Comparison with US2023384516A1: This patent's core protection is a curved waveguide loop structure and adjacent die layout scheme used for testing internal optoelectronic circuits of chips. Its core feature is: "A photonic integrated circuit, comprising: a first optoelectronic circuit; a second optoelectronic circuit; and a loop waveguide, wherein the loop waveguide optically couples the first optoelectronic circuit and the second optoelectronic circuit, wherein at least a portion of the loop waveguide is located on a die different from the first optoelectronic circuit and the second optoelectronic circuit." The core of this application's solution is a passive through-type straight waveguide grating pair used for calibrating FA coupling loss, which does not contain any "optoelectronic circuit" or "loop waveguide on different dies" features. Its core function, structure, and layout are completely different. The functions differ: the proposed solution calibrates the coupling loss between the FA and the chip grating, while the existing solution tests the integrity of the internal optoelectronic link function of the chip; The structures are different: the solution in this application adopts a pure optical structure of "input reference grating + passive single-mode straight waveguide + output reference grating", while the existing solution adopts an optoelectronic hybrid structure of "active light emission + curved waveguide loop return + active light reception". Different layouts: The core layout of this application is located in the BB process monitoring area within the shot, while the existing solution is located within the die or in the non-functional area adjacent to the die. It is evident that although both this application and the patent operate in the technical field of silicon photonic integrated chip wafer-level testing technology, and both aim to achieve wafer-level optoelectronic performance testing and error calibration, and both employ on-chip waveguide structures as the testing carrier, the technical problems addressed by the patent and this application are fundamentally different. The patent does not address the core technical issue of FA coupling error calibration, which is the focus of this application.

[0109] 2. Comparison with CN110988646A: This patent's core protection is a calibration structure and method for integrating an active optical switch within a grating slot. The core of this application's solution is a pure passive grating pair structure with a BB area layout, without any active optical switches or beam splitters, and the layout positions are completely different.

[0110] 3. Comparison with CN119738693A: The core of that patent is a scheme that integrates an active calibration module within the inner edge of the die. The core of this application's solution is a purely passive structure with a BB area layout, which does not occupy the die area and has no active components, thus being fundamentally different from that patent.

[0111] 4. Multi-band compatible design: Existing patents do not have a universal wavelength-by-wavelength calibration design for CWDM / DWDM scenarios. The multi-band adaptation logic of this application further strengthens the difference between this application and existing patents.

[0112] The core technical effects of this application compared to previous inventions are as follows: 1. Calibration accuracy is significantly improved Technical means: A passive straight-through single-mode straight waveguide is adopted (no bending, no beam splitting, length 100μm-200μm, intrinsic transmission loss ≤0.1dB can be pre-calibrated), the reference grating and the working grating are perfectly matched 1:1, and it supports shot-level calibration + 3σ outlier removal.

[0113] Technical effect: It completely solves the problems of additional loss and inaccurate error calibration introduced by the bending waveguide in the past, and suppresses the IL test deviation caused by FA processing and assembly error to within ±0.1dB, accurately restores the intrinsic channel consistency of silicon photonic chip, and the calibration accuracy far exceeds that of previous inventions.

[0114] 2. Significantly improved full-band compatibility Technical means: The reference grating can be designed according to the one-to-one correspondence of multiple wavelengths in CWDM / DWDM, or a broadband reference grating can be used, without band limitation, and is compatible with the 1310nm and 1550nm all-optical communication bands.

[0115] Technical benefits: Breaking the limitations of previous inventions that only adapt to a single band, a single solution covers all scenarios including short-range, long-range, coarse wavelength division multiplexing (CWDM), and dense wavelength division multiplexing (DWDM), significantly improving reusability. It eliminates the need to design separate calibration structures for different bands, reducing mass production adaptation costs.

[0116] 3. A leap forward in mass production compatibility and testing efficiency Technical means: The core adopts the in-shot BB process monitoring area layout, which does not occupy the effective area of ​​the die and does not require modification of the chip layout; the reference grating and the working grating are fabricated in the same process and simultaneously, and the one-time calibration at the shot level can be reused to all dies in the shot.

[0117] Technical benefits: It overcomes the shortcomings of previous inventions, such as occupying chip area, high cost of modifying existing chips, and low testing efficiency, and achieves zero modification cost, does not affect the dicing process, improves testing efficiency by tens of times, and is fully adapted to the mass production needs of 12-inch silicon photonic wafers.

[0118] 4. Significantly reduced process costs Technical approach: It adopts a pure passive structure with no additional active components. The reference grating and the working grating share the same photomask and etching process, with no additional process steps.

[0119] Technical benefits: It avoids the problems of needing to optimize the process and increase the cost of fabrication due to active structures in the past, and achieves zero additional cost in the entire process of R&D and mass production, which greatly improves the economic efficiency of the solution.

[0120] 5. Improved calibration stability and global consistency Technical approach: A three-step method of "homogeneous error calibration - channel-by-channel deduction - wafer-level median normalization optimization" is adopted, and a weighting coefficient α is introduced to verify temperature drift and random alignment errors.

[0121] Technical effects: It solves the problem that previous inventions could only deduct errors and could not suppress drift, improve the consistency of wafer-level global calibration, avoid calibration deviations caused by environmental and process fluctuations, and make test data more stable and reliable.

[0122] 6. Enhance technological competitiveness Technical means: The core adopts a straight-through structure + BB area layout, which is significantly different from previous core patents (circular and dicing groove layout).

[0123] Technical benefits: It fills the gap in existing patents regarding BB area layout and universal calibration across all bands, thereby enhancing technological competitiveness.

[0124] All embodiments of this application follow the principle of "unchanged core inventive points"—that is, the core of "passive structure, error calibration from the same source, not occupying the effective area of ​​the die, and full-band compatibility" remains unchanged, and only the specific implementation details are optimized. This not only preserves the original technical effect, but also adapts to the mass production needs of different processes and scenarios, while not falling within the scope of existing patent protection.

[0125] Explanation of Chinese terminology: Reference grating pair: The core calibration structure, consisting of an input reference grating, an output reference grating, and a passive single-mode straight waveguide connecting the two, is used to calibrate the system coupling loss. Its parameters are matched 1:1 with the coupling grating of the working channel.

[0126] Wavelength compensation algorithm: In multi-band adaptation alternatives, it is used in conjunction with a broadband reference grating to compensate for coupling deviations at different wavelengths and achieve accurate calibration across the entire band.

[0127] Passive single-mode straight waveguide: The core component connecting the reference grating pair, without bending, beam splitting, resonance, or filtering structure, with a length controlled between 100μm and 200μm (the alternative range is 80μm to 220μm), intrinsic transmission loss in the target band ≤0.1dB, and can be accurately calibrated in advance.

[0128] Passive through-type reference grating pair: The core calibration structure of this application, which is different from the loop structure of the prior art, consists of an input reference grating, an output reference grating and a passive single-mode straight waveguide. It has no bending loss and can accurately calibrate system errors.

[0129] Loop grating pair: The core structure closest to the prior art (US2023384516A1) is that the input grating and the output grating are connected by a bent waveguide to form a closed-loop optical path, which has additional bending loss and limited calibration accuracy.

[0130] Calibration accuracy: The core indicator for measuring calibration effectiveness, which means that this application can suppress the insertion loss test deviation caused by FA processing and assembly errors to within ±0.1dB, accurately restoring the intrinsic performance of the chip.

[0131] Calibration logic: The core logic used to obtain the additional losses of system coupling. This application supports shot-level dedicated calibration, which can generate a dedicated error matrix for each shot and adapt to process fluctuations between shots.

[0132] Waveguide: A core component used to transmit optical signals, mainly referring to passive single-mode straight waveguides, which are divided into silicon-based waveguides, silicon nitride waveguides, etc. The core requirements are low transmission loss and no additional interference structure.

[0133] Additional system coupling loss: The additional loss formed by the superposition of fiber array processing error, assembly and adjustment cumulative error and wavelength-related coupling deviation is the core error that needs to be removed in this application, and can be calculated by calibration through reference grating.

[0134] Intrinsic chip consistency: The consistency of the chip's manufacturing process, which is not affected by external testing system errors, refers to the true consistency of the insertion loss of each channel of the chip after calibration.

[0135] Chip layout: A planar layout diagram of the chip design, including the position, size and process parameters of all components such as gratings and waveguides. The calibration structure of this application does not require modification of the existing chip layout.

[0136] Active devices: Optoelectronic devices that require external power to operate. As mentioned in the prior art, this increases chip area, tape-out cost and power consumption. This application uses a purely passive structure to avoid this problem.

[0137] Active structure: A calibration structure that includes active devices. Existing technologies (such as CN119738693A) use this structure, but it has drawbacks such as high cost and large error.

[0138] Photomask: A template used in the photolithography process during chip manufacturing. The reference grating and the working grating can share the same photomask or be prepared using the same photomask, without additional process costs.

[0139] Process parameters: Key parameters in chip manufacturing, mainly referring to grating etching depth, waveguide core layer thickness, etc. The process parameters of the reference grating and the working grating need to be matched 1:1.

[0140] Process cost: The cost incurred during chip manufacturing. This application adopts a pure passive structure and is prepared using the same process, resulting in no additional process cost, which is superior to existing technologies.

[0141] Process fluctuations: minor deviations in process parameters during chip manufacturing, mainly referring to process fluctuations between shots. This application can compensate for the errors caused by these fluctuations through shot-level calibration.

[0142] Optical power meter: A test device used to measure the power of optical signals. It is used to test the optical power of reference grating pairs and working channels, and to calculate insertion loss.

[0143] Fiber optic array: Composed of multiple optical fibers arranged at a fixed pitch, used in wafer-level testing to couple on-chip optical signals with external testing equipment, but it has processing errors.

[0144] Passive structure: A structure that can operate without external power supply. This application adopts this structure, which has no additional power consumption, low cost, and is compatible with mass production testing of passive silicon photonics chips.

[0145] Coupling angle: The angle between the grating and the optical fiber is one of the key layout parameters of the grating. The coupling angles of the reference grating and the working grating must be matched 1:1 to ensure consistent coupling characteristics.

[0146] Coupling bias: The bias generated during the coupling process of optical signals, mainly referring to wavelength-dependent coupling bias, is a component of the additional coupling loss of the system.

[0147] Coupling loss: The power loss generated during the coupling process of optical signals is an important indicator for evaluating chip performance. This application can accurately calibrate and remove the additional coupling loss of the system.

[0148] Mode field diameter: A key parameter of gratings and waveguides, which determines the transmission characteristics of optical signals. The mode field diameters of the reference grating and the working grating must be matched 1:1 to ensure that system errors originate from the same source.

[0149] Weighting coefficient: marked as α The value ranges from 0.8 to 1.0 (which can be replaced by adaptive weights) and is used to balance the single-shot calibration accuracy with the wafer-wide consistency, thereby optimizing the calibration effect.

[0150] Narrow scriber slot: The narrow scriber slot used in advanced silicon photonics processes cannot be adapted to the calibration structure of the scriber slot layout in the prior art. The BB area layout of this application can avoid this problem.

[0151] Etching depth: A key process parameter in grating fabrication. The etching depths of the reference grating and the working grating must be matched 1:1 to ensure consistent coupling characteristics.

[0152] Broadband reference grating: A multi-band adaptable reference grating that can cover the entire 1310nm-1610nm band, eliminating the need for wavelength-by-wavelength design of reference grating pairs and simplifying layout design.

[0153] Ion etching + wet polishing combined process: an alternative process for waveguide fabrication. Compared with standard etching process, it can further reduce the intrinsic transmission loss of straight waveguides and improve the upper limit of calibration accuracy.

[0154] Ion etching process: a core process used in chip manufacturing to etch gratings and waveguides. Reference gratings and working gratings are fabricated simultaneously using this process.

[0155] Tape-out cost: The cost incurred during the mass production (tape-out) of chips. This application has no additional active devices or additional process steps, which can reduce tape-out cost.

[0156] Testing efficiency: For wafer-level testing, this application improves testing efficiency by tens of times through shot-level calibration and full shot reuse, which is suitable for mass production requirements.

[0157] Test platform: Equipment combination used for wafer-level testing, mainly refers to commercial silicon photonics probe stations, broadband light sources, multi-channel optical power meters, etc. This application is compatible with existing test platforms and does not require modification.

[0158] Interquartile range outlier removal: An alternative method for outlier removal, suitable for scenarios with large dispersion of test data, with the same effect as 3σ outlier removal, ensuring the accuracy of calibration data.

[0159] Tunable broadband grating: An alternative type of broadband reference grating, it achieves bandwidth adaptability by fine-tuning the grating etching parameters and is compatible with CWDM / DWDM chips of different frequency bands.

[0160] Tunable lasers: Light source devices used in multi-wavelength scene testing, covering the entire 1470nm-1610nm band, used to complete system error calibration and working channel calibration wavelength by wavelength.

[0161] Same process but different photomasks (homogeneous photomasks): Alternative solutions for fabricating reference gratings and working gratings, ensuring that the layout and process parameters of the two are completely consistent, adapting to scenarios where photomask design is limited, without additional cost.

[0162] Same-source error calibration: The first step of the calibration method in this application is to ensure accurate error calibration by calibrating the additional loss of the system through a reference grating pair (which is of the same source as the working grating).

[0163] 3 σ Outlier removal: A method for processing calibration data, used to remove outlier calibration data to ensure the accuracy of shot-level calibration data. It can be used as an alternative to interquartile range outlier removal.

[0164] BB process monitoring area: abbreviated as BB area, located within each shot, is an idle area used to monitor chip process quality. In this application, the calibration structure is preferably laid out here, without occupying the effective area of ​​the die.

[0165] FA assembly drift: a slight shift in the position of the fiber array assembly during testing. This application can verify the error caused by this drift through timed calibration, thereby improving calibration stability.

[0166] FA processing error: Errors generated during the manufacturing process of fiber arrays, including fiber core diameter eccentricity, array pitch deviation, and inconsistent end face angles, are one of the sources of additional coupling loss in the system.

[0167] Shot-level calibration: The core calibration method of this application is to use a shot as a unit. When entering a new shot, the reference grating pair in the BB area is calibrated first to generate a dedicated error matrix to adapt to process fluctuations between shots.

[0168] Silicon Nitride waveguides: an alternative to passive single-mode straight waveguides, suitable for testing scenarios with higher precision and wider bands compared to silicon-based waveguides.

[0169] SOI core layer thickness: The thickness of the core layer in the SOI (silicon-on-insulator) structure of a silicon photonic chip is a key process parameter for waveguides and gratings. The reference grating and the working grating must match this parameter.

[0170] IL test deviation: The deviation generated during the insertion loss test is mainly caused by FA processing error and cumulative assembly error. This application can suppress the deviation to within ±0.1dB.

[0171] Layout parameters: Key parameters in chip layout design, mainly referring to grating period, duty cycle, coupling angle, 3dB bandwidth, etc. The layout parameters of the reference grating and the working grating must be matched 1:1.

[0172] Calibration submatrix: An error matrix generated during shot-level calibration, containing the system coupling additional loss of each channel and wavelength within the shot, used for calibration of all dies within the shot.

[0173] Wafer-level global optimization: The third step of the calibration method in this application improves wafer-level calibration consistency by statistically analyzing the median error of the entire wafer, eliminating outliers, and optimizing the calibration formula.

[0174] Wafer-level testing: Testing performed before the entire wafer is divided into individual dies, used for batch screening of qualified chips. This application is adapted to this testing scenario, improving testing efficiency and accuracy.

[0175] Temperature drift: Test deviation caused by changes in ambient temperature during the test. This application can suppress this deviation and improve calibration stability through wafer-level global optimization.

[0176] Active calibration module: The module used in the prior art (such as CN119738693A) is used to input standard optical signals to multiple channels. It has the disadvantages of high cost and large error. This application does not use it.

[0177] Duty cycle: A key layout parameter of the grating, referring to the ratio of the grating notch width to the grating period. The duty cycles of the reference grating and the working grating must be matched 1:1 to ensure consistent coupling characteristics.

[0178] Straight waveguide length: The key parameter for passive single-mode straight waveguides is 100μm-200μm or 80μm-220μm. The core requirement is that the intrinsic transmission loss of the target band is ≤0.1dB.

[0179] Channel-by-channel deduction: In the second step of the calibration method of this application, the system coupling additional loss is deducted from the measured insertion loss of each working channel by a shot-level calibration submatrix to obtain the chip intrinsic IL.

[0180] Wavelength-by-wavelength calibration: A calibration method for multi-wavelength scenarios (CWDM / DWDM) that calibrates system errors and working channels one by one according to the working wavelength to ensure accurate calibration across all wavelengths.

[0181] Array pitch: The spacing between adjacent channels in a fiber array or grating array. The array pitch of the reference grating pair must be exactly the same as that of the FA to ensure accurate coupling alignment.

[0182] Refractive structure: An alternative structure to the reference grating pair, a small reflector is added, the output grating is eliminated, and the optical signal is reflected back to the input end after being transmitted through a straight waveguide, simplifying the structure without affecting the error calibration.

[0183] Refractor: The core component in a reflective reference grating alignment, used to reflect the optical signal transmitted through a straight waveguide back to the input end, replacing the function of the output grating.

[0184] Input reference grating: A component of the reference grating pair used to receive the optical signal input to the fiber array, and its parameters are matched 1:1 with the input grating of the working channel.

[0185] Output reference grating: A component of the reference grating pair, used to output the optical signal transmitted through the straight waveguide to the optical power meter. Its parameters are matched 1:1 with the output grating of the working channel and can be replaced by a mirror.

[0186] Coupled optical path: The transmission path of optical signals from the fiber array to the grating and then to the waveguide. It is used to clarify the coupling alignment relationship and ensure that the coupling conditions of the calibration structure and the working channel are consistent.

[0187] Coupling angle: The angle between the grating and the optical fiber is one of the key layout parameters of the grating. The coupling angles of the reference grating and the working grating must be matched 1:1 to ensure consistent coupling characteristics.

[0188] Coupling defocus: The vertical distance deviation between the fiber array and the grating. The reference grating and the working grating must be at the same height on the same plane of the wafer to ensure consistent coupling defocus and improve calibration accuracy.

[0189] Accumulated installation and adjustment error: Errors generated during the installation and debugging of the test system, including lateral offset, angular sway, pitch tilt, and height defocus, are one of the sources of additional system coupling losses.

[0190] 3dB bandwidth: A key layout parameter of the grating, referring to the wavelength range corresponding to a 3dB power attenuation when the grating transmits optical signals. The 3dB bandwidth of the reference grating and the working grating must be matched to ensure full-band compatibility.

[0191] Die internal layout: The calibration structure is laid out within the die unit. This method is used in the prior art (US2023384516A1), which occupies the effective area of ​​the die. This application can replace this layout.

[0192] Silicon-based waveguide: The conventional type of passive single-mode straight waveguide, which was used in the original solution, can be replaced by silicon nitride waveguide.

[0193] Silicon photonics chips: Optoelectronic chips based on silicon have the advantages of high integration, low power consumption and low cost, and are the target of this application, and are widely used in optical communication scenarios.

[0194] Silicon photonics integrated chip wafer-level testing technology: The technical field to which this application pertains refers to the technology of batch testing chips on a whole wafer before the silicon photonics wafer is diced, with the core being the accurate testing of key chip indicators.

[0195] Silicon photonics probe station: a core piece of equipment for wafer-level testing, used to fix wafers, adjust the position of fiber arrays, and achieve precise coupling between gratings and optical fibers.

[0196] Grating: The core component in silicon photonics chips that realizes optical signal coupling and transmission. It is divided into reference grating and working grating. The parameters of the reference grating and working grating must be matched 1:1.

[0197] Grating period: A key layout parameter of the grating, referring to the spacing between two adjacent grating scribes. The grating periods of the reference grating and the working grating must be matched 1:1 to ensure consistent coupling characteristics.

[0198] Grating coupling structure: The structure that realizes the coupling of on-chip optical signals with optical fibers in silicon photonics chips is the key to optical signal transmission in wafer-level testing. The reference grating pair in this application is designed based on this structure.

[0199] Photolithography: A process used in chip manufacturing to transfer a layout pattern to a chip substrate. Reference gratings and working gratings are fabricated simultaneously through this process.

[0200] Optical switch: A component used in existing technologies (such as CN119738693A) to switch multi-channel optical signals. It is an active structure and is not used in this application.

[0201] Optical signal: The core signal used for transmission and testing of silicon photonic chips. It is transmitted through gratings and waveguides, and its power is measured by an optical power meter to calculate the insertion loss.

[0202] Broadband light source: The light source equipment used in single-band testing. This equipment is used in 1310nm band testing to provide a stable broadband optical signal.

[0203] English terms and abbreviations: 3σ: The full English name is Three Sigma. The Chinese annotation is the 3σ principle, which is used for outlier removal. It uses the mean and standard deviation of statistical data to remove outliers that deviate from the mean by more than three times the standard deviation.

[0204] CWDM: An optical communication technology that multiplexes optical signals of different wavelengths into a single optical fiber for transmission. This application is compatible with chip testing for this technology.

[0205] DWDM: An optical communication technology that, compared to CWDM, has smaller wavelength spacing and larger capacity. This application is applicable to chip testing for this technology.

[0206] FA: Composed of multiple optical fibers arranged at a fixed pitch, used in wafer-level testing to couple on-chip optical signals with external testing equipment, and is subject to processing and assembly errors.

[0207] IQR: An alternative method for outlier removal, which removes outliers that are outside the reasonable range by calculating the interquartile range of the data.

[0208] IL: refers to the power loss of optical signals when they pass through a chip, waveguide, or coupling structure. It is a core indicator for evaluating the performance of silicon photonics chips and screening qualified chips.

[0209] O-band: The full English name is O-band. The Chinese annotation is: one of the optical communication bands, with a center wavelength of about 1310nm. It is mainly used for short-range optical communication. This application can be adapted to chip testing in this band.

[0210] Reticle: Chinese annotation: exposure plate, mask plate, synonym of shot, refers to the basic exposure unit on the wafer, and each reticle contains multiple dies.

[0211] SOI: Silicon On Insulator, a substrate structure for silicon photonic chips. The thickness of the SOI core layer is a key process parameter for gratings and waveguides.

[0212] α (alpha): Chinese annotation: weighting coefficient, with a value range of 0.8-1.0, used to balance the single-shot calibration accuracy and the wafer-wide consistency, and can be replaced by an adaptive weighting coefficient.

[0213] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0214] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A wideband silicon photonics wafer-level multi-channel coupling error calibration structure, characterized in that, include: At least one set of passive through-reference gratings; A set of passive through-reference gratings has design parameters that correspond one-to-one with the design parameters of the coupling gratings of all working channels in the die on the wafer; the design parameters include layout parameters and process parameters. The number of channels in a set of passive through-reference gratings is the same as the number of channels in the fiber array in the test system, and the channel pitch of a set of passive through-reference gratings is exactly the same as the channel pitch of the fiber array in the test system. When performing wafer-level testing on silicon photonics chips using a testing system, for each shot on the wafer: a set of passive through-reference gratings is used to lay out the non-silicon photonics chip area within each shot, and is at the same plane height as the coupling grating on the wafer. The coupling additional loss matrix of the shot is obtained through testing by the testing system. The coupling additional loss matrix is ​​used to calibrate the measured insertion loss of each die within the shot at each working channel and each working wavelength, and wafer-level median normalization optimization is performed to obtain the calibrated insertion loss. The non-silicon photonics chip area includes the BB region within the shot, the non-functional region within the die, and the dicing slot.

2. The wideband silicon photonics wafer-level multi-channel coupling error calibration structure according to claim 1, characterized in that, The passive through-reference grating includes: an input reference grating, a passive single-mode straight waveguide, and an output reference grating; The input reference grating and the output reference grating are connected by a passive single-mode straight waveguide; the passive single-mode straight waveguide is a straight waveguide without bending, splitting, resonance, or filtering structure; All layout and process parameters of the input and output reference gratings are perfectly matched with the coupling gratings of the working channels in the die on the wafer; The input reference grating is used to receive the optical signal input from the fiber array in the test system and transmit it to the output reference grating through a passive single-mode straight waveguide; the output reference grating is used to output the optical signal transmitted by the passive single-mode straight waveguide to the optical power meter in the test system to obtain the coupling additional loss.

3. The wideband silicon photonics wafer-level multi-channel coupling error calibration structure according to claim 2, characterized in that, The length of the passive single-mode straight waveguide ranges from 100μm to 200μm.

4. The wideband silicon photonics wafer-level multi-channel coupling error calibration structure according to claim 1, characterized in that, The passive through-reference grating includes: a single grating and a reflective structure; All layout and process parameters of the single grating are perfectly matched with the coupling grating of the working channel in the die on the wafer; A single grating is used to receive optical signals input from the fiber optic array in the test system; The reflective structure is used to reflect the optical signal back to the single grating after it is transmitted through the straight waveguide, and output it to the optical power meter in the test system to obtain the coupling additional loss.

5. The wideband silicon photonics wafer-level multi-channel coupling error calibration structure according to claim 1, characterized in that, The layout parameters include: grating period, duty cycle, and waveguide width; The process parameters include: etching depth and core layer thickness; Based on the same layout parameters and process parameters, the passive through-reference grating and the coupled grating have the same center wavelength, coupling angle and bandwidth.

6. The wideband silicon photonics wafer-level multi-channel coupling error calibration structure according to claim 1, characterized in that, The layout of a set of passive through-reference gratings in the non-silicon photonic chip regions within each shot includes: fixed layout of the BB region; distributed layout of the BB region; layout of the non-dicing region at the edge of the shot; layout of the non-functional area within the die; segmented layout of the dicing slot; and combined layout of the dicing slot and the BB region.

7. A wideband silicon photonics wafer-level multi-channel coupling error calibration method, characterized in that, The method employs the wideband silicon photonics wafer-level multi-channel coupling error calibration structure as described in any one of claims 1-6, and the method includes: Test a set of passive through-reference gratings within each shot to obtain the coupling additional loss matrix of the shot; The actual loss of each working channel and each working wavelength is calibrated channel by channel and wavelength by using the coupling additional loss matrix to obtain the calibrated chip intrinsic true insertion loss of each working channel and each working wavelength. The intrinsic true insertion loss of the calibrated chip is optimized by wafer-level median normalization to obtain the final insertion loss.

8. The wideband silicon photonics wafer-level multi-channel coupling error calibration method according to claim 7, characterized in that, Test a set of passive through-reference gratings within each shot to obtain the coupling-added loss matrix of the shot, including: Align the fiber array in the test system with a set of passive through-reference gratings, perform coarse and fine alignment, find the peak coupling power point of the working wavelength, and lock the Z-axis height and coupling angle of the fiber array. A set of passive through-reference gratings was scanned using an optical fiber array, and the measured insertion loss of the passive through-reference gratings at each working channel and each working wavelength was recorded. Based on the measured insertion loss of the passive through-reference grating at each working channel and wavelength, using the formula... The coupling loss at each working channel and at each working wavelength is determined, and the coupling loss matrix of the shot is constructed; where, For work passage and operating wavelength The coupling-related additional losses, For passive through-reference grating in the working channel and operating wavelength The measured insertion loss is as follows. For passive through-reference grating at operating wavelength The intrinsic fixed transmission loss is as follows.

9. The wideband silicon photonics wafer-level multi-channel coupling error calibration method according to claim 7, characterized in that, The calibration formula for actual loss is: ； In the formula, For work passage and operating wavelength The intrinsic true insertion loss of the chip after calibration. For work passage and operating wavelength The measured insertion loss is as follows. For work passage and operating wavelength The coupling loss is added below; Based on the coupling additional loss matrix, using the formula The measured insertion loss is optimized and calibrated using wafer-level median normalization to obtain the final wafer-level insertion loss; where, This represents the final insertion loss at the wafer level. These are the weighting coefficients. For all dies of the wafer of the median.

10. The wideband silicon photonics wafer-level multi-channel coupling error calibration method according to claim 7, characterized in that, The intrinsic true insertion loss of the calibrated chip is optimized by wafer-level median normalization to obtain the final insertion loss, including: The median of the coupling loss of all dies on the entire wafer at each working channel and each working wavelength was calculated. Based on the median, the intrinsic true insertion loss of the calibrated chip is calculated using a 3... σ Outlier removal or interquartile range outlier removal yields the final insertion loss.

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