Dual pulse testing apparatus and method for power semiconductor

Abstract

The application discloses a double-pulse testing device and method of a power semiconductor, and belongs to the technical field of power semiconductors. The device comprises a global control module, which is used for generating a parameter package according to a testing task and characteristic parameters of a target device when the double-pulse testing of the target device is to be performed, sending the parameter package to a target local execution module, iteratively adjusting the parameter package according to a double-pulse testing result of the target device fed back by the target local execution module, and sending the iteratively adjusted parameter package to the target local execution module until the double-pulse testing result of the target device fed back by the target local execution module meets a testing target. The target local execution module is used for performing the double-pulse testing of the target device according to the parameter package issued by the global control module, and feeding back the double-pulse testing result of the target device to the global control module. The device can improve the efficiency and precision when the double-pulse testing of the power semiconductor is performed.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a dual-pulse testing device and method for power semiconductors. Background Technology

[0002] Double-pulse testing (DPT) is a crucial method for evaluating the turn-on loss, turn-off loss, reverse recovery characteristics, delay time, overshoot, and ringing behavior of power semiconductors. Therefore, DPT is extremely important during the R&D, screening, and packaging verification stages of power semiconductors. With the continuous development of power semiconductors, their conduction time has been reduced from tens of nanoseconds to a few nanoseconds. This has led to an exponential increase in the sensitivity of power semiconductors to parasitic parameters, and the failure time of power semiconductors has also decreased from the microsecond level to the nanosecond level. Against this backdrop, more stringent requirements have been placed on the double-pulse testing platform for power semiconductors.

[0003] In existing technologies, dual-pulse test platforms typically employ a centralized main control architecture to perform dual-pulse testing on power semiconductors. That is, the main control board generates a unified test parameter package to perform dual-pulse testing on the power semiconductor. After the power semiconductor is tested, the test parameters are manually analyzed by testers to correct the test parameters. This dual-pulse testing method is not only inefficient, but the accuracy of the test parameter package corrections also heavily relies on human experience, making it impossible to guarantee the accuracy and reliability of the power semiconductor dual-pulse test results. Furthermore, there is a certain communication delay between the main control board and the power semiconductor, which further reduces the accuracy and reliability of the power semiconductor dual-pulse test results. Currently, there is no effective solution to this technical problem. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a double-pulse testing device and method for power semiconductors, so as to solve the technical problems of low efficiency and poor accuracy in the prior art when performing double-pulse testing on power semiconductors. The specific solution is as follows: To address the aforementioned technical problems, the present invention provides a dual-pulse testing device for power semiconductors, comprising: A global control module is used to generate a parameter package based on the test task and the characteristic parameters of the target device when a double-pulse test is to be performed on the target device. This parameter package is then sent to the target local execution module. The module iteratively adjusts the parameter package based on the double-pulse test results of the target device fed back by the target local execution module, and simultaneously sends the iteratively adjusted parameter package back to the target local execution module, until the double-pulse test results of the target device fed back by the target local execution module meet the test objective. The target local execution module is any one of N local execution modules; N≥1. The target local execution module is used to perform a double-pulse test on the target device according to the parameter package issued by the global control module or the parameter package after iterative adjustment, and to feed back the double-pulse test result of the target device to the global control module.

[0005] Preferably, the global control module includes: The first communication unit is used to transmit communication data; High-voltage power supply control interface, used for communication with external high-voltage power supply modules; The main contactor control unit is used to control the on / off state of the external high-voltage power supply module; The parameter calculation unit, connected to the first communication unit, the high-voltage power supply control interface, and the main contactor control unit, is used to generate a parameter package based on the test task and the characteristic parameters of the target device when a double-pulse test is to be performed on the target device. The parameter package is then sent to the target local execution module via the first communication unit. Simultaneously, the double-pulse test result of the target device fed back by the target local execution module is obtained through the first communication unit. The parameter package is iteratively adjusted based on the double-pulse test result of the target device fed back by the target local execution module, and the iteratively adjusted parameter package is sent to the target local execution module until the double-pulse test result of the target device fed back by the target local execution module meets the test objective.

[0006] Preferably, the target local execution module includes: A proximity energy storage unit, located within a preset range, is used to provide an energy source for the target device; the preset range is set according to the arrangement position of the target device. The bus pre-charge branch is used to charge the voltage of the near-load energy storage unit to the target bus voltage using the external high-voltage power supply module according to the instructions issued by the global control module. A low-parasitic bus circuit is connected between the target device and the near-load energy storage unit; wherein, the low-parasitic bus circuit is a bus connection structure designed to shorten the main power current path between the near-load energy storage unit, the target device and the load circuit, and to reduce the area of ​​the main power circuit. The second communication unit is used to generate a corresponding drive signal according to the parameter package issued by the global control module or the iteratively adjusted parameter package when the charging voltage of the near-load energy storage unit reaches the preset charging range, and to feed back the double-pulse test result of the target device to the global control module through the first communication unit; the preset charging range is set according to the target bus voltage. A signal driving unit is used to perform a double-pulse test on the target device using the driving signal generated by the second communication unit; The signal sampling unit is used to acquire the double-pulse test results of the target device in real time.

[0007] Preferably, the target local execution module further includes: A local hardware protection chain is used to control the target local execution module to lock out and / or soft shut down when an abnormality is detected in the target device and / or the target local execution module and / or the global control module, and to prompt the corresponding fault information.

[0008] To address the aforementioned technical problems, this invention also provides a double-pulse testing method for power semiconductors, applied to a global control module in a double-pulse testing device, comprising: When performing a double-pulse test on the target device, a parameter packet is generated based on the test task and the characteristic parameters of the target device, and the parameter packet is sent to the target local execution module; the target local execution module is any one of N local execution modules; N≥1; The parameter package is iteratively adjusted based on the double-pulse test result of the target device fed back by the target local execution module, and the iteratively adjusted parameter package is sent back to the target local execution module until the double-pulse test result of the target device fed back by the target local execution module meets the test target; wherein, when the target local execution module receives the parameter package or the iteratively adjusted parameter package issued by the global control module, it performs a double-pulse test on the target device based on the parameter package issued by the global control module or the iteratively adjusted parameter package, and feeds back the double-pulse test result of the target device to the global control module.

[0009] Preferably, when performing a double-pulse test on the target device, a parameter package is generated based on the test task and the characteristic parameters of the target device, and the parameter package is sent to the target local execution module, including: When a double-pulse test is to be performed on the target device, the bus voltage, drive bias, protection threshold, first pulse width, dead time, and second pulse time corresponding to the double-pulse test are determined according to the test task and the characteristic parameters of the target device, and the bus voltage, drive bias, protection threshold, first pulse width, dead time, and second pulse time corresponding to the double-pulse test are sent to the target local execution module.

[0010] Preferably, the iterative adjustment of the parameter package based on the double-pulse test results of the target device fed back by the target local execution module includes: The bus voltage corresponding to the double-pulse test of the target device is iteratively adjusted according to the target model; The expression for the target model is: ; In the formula, To perform the first step on the target device The bus voltage corresponding to the second double-pulse test. To perform the first step on the target device The bus voltage corresponding to the second double-pulse test. For compensation coefficient, To perform the first step on the target device The difference between the expected voltage value and the actual voltage value when the target device is turned off during the double-pulse test.

[0011] To address the aforementioned technical problems, this invention also provides a double-pulse testing method for power semiconductors, applied to a target local execution module in a double-pulse testing device, wherein the target local execution module is any one of N local execution modules; N≥1; comprising: The global control module is monitored. When the global control module needs to perform a double-pulse test on the target device, it generates a parameter package based on the test task and the characteristic parameters of the target device, sends the parameter package to the target local execution module, and iteratively adjusts the parameter package based on the double-pulse test result of the target device fed back by the target local execution module. At the same time, the iteratively adjusted parameter package is sent to the target local execution module until the double-pulse test result of the target device fed back by the target local execution module meets the test target. When the parameter package or the iteratively adjusted parameter package issued by the global control module is received, the target device is subjected to a double-pulse test according to the parameter package issued by the global control module or the iteratively adjusted parameter package, and the double-pulse test result of the target device is fed back to the global control module.

[0012] Preferably, the step of performing a double-pulse test on the target device based on the parameter package issued by the global control module or the iteratively adjusted parameter package, and feeding back the double-pulse test result of the target device to the global control module, includes: Generate corresponding drive signals based on the parameter package issued by the global control module or the iteratively adjusted parameter package; The target device is subjected to a double-pulse test using the generated drive signal, and the double-pulse test result of the target device is fed back to the global control module.

[0013] Preferably, the step of feeding back the double-pulse test result of the target device to the global control module includes: When the double-pulse test result of the target device is detected, the waveform feature parameters corresponding to the double-pulse test result of the target device are extracted to obtain the target waveform parameters; The target waveform parameters are fed back to the global control module.

[0014] Beneficial Effects: Compared to existing technologies, the dual-pulse testing device provided by this invention allows the global control module to automatically and iteratively adjust the parameter package based on the dual-pulse test results fed back by the target local execution module until the dual-pulse test results of the target device fed back by the target local execution module meet the test objectives. This completely eliminates the drawbacks of manual parameter package adjustment by testers relying on their own experience. Since this method can simultaneously perform parallel batch dual-pulse testing on multiple power semiconductors, it not only improves the efficiency of dual-pulse testing of power semiconductors but also ensures the consistency and reliability of test results. Furthermore, in this invention, the dual-pulse test of the target device is performed by the target local execution module, which is closer to the target device. This shortens the communication link between the global control module and the target device, eliminating the need for the global control module to directly address nanosecond-level timing challenges. This effectively avoids test errors caused by long-distance communication delays, thereby further improving the accuracy and reliability of power semiconductor dual-pulse test results.

[0015] Correspondingly, the dual-pulse testing method for power semiconductors provided by this invention also has the above-mentioned beneficial effects. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is a structural diagram of a dual-pulse testing device for power semiconductors provided in an embodiment of the present invention; Figure 2 This is a structural diagram of another power semiconductor dual-pulse testing device provided in an embodiment of the present invention; Figure 3 This is a structural diagram of a local hardware protection chain provided in an embodiment of the present invention; Figure 4 A flowchart illustrating a dual-pulse testing method for power semiconductors provided in an embodiment of the present invention; Figure 5 A flowchart illustrating another double-pulse testing method for power semiconductors provided in an embodiment of the present invention; Figure 6 This is a timing diagram of a double-pulse test device using power semiconductors provided in an embodiment of the present invention when performing double-pulse testing on a target device. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1 , Figure 1 This is a structural diagram of a double-pulse testing device for power semiconductors provided in an embodiment of the present invention. The device includes: The global control module 11 is used to generate a parameter package based on the test task and the characteristic parameters of the target device when a double-pulse test is to be performed on the target device. It then sends the parameter package to the target local execution module and iteratively adjusts the parameter package based on the double-pulse test results of the target device fed back by the target local execution module. Simultaneously, it sends the iteratively adjusted parameter package to the target local execution module until the double-pulse test results of the target device fed back by the target local execution module meet the test objective. The target local execution module 12 is any one of N local execution modules; N≥1. The target local execution module 12 is used to perform double pulse tests on the target device according to the parameter package issued by the global control module or the parameter package after iterative adjustment, and to feed back the double pulse test results of the target device to the global control module.

[0020] In this embodiment, a double-pulse testing device for power semiconductors is provided. This device can solve the technical problems of low efficiency and poor accuracy in the prior art when performing double-pulse testing on power semiconductors.

[0021] The dual-pulse test device consists of a global control module 11 and N local execution modules. When the device has only one local execution module, it forms a single-channel test device for performing dual-pulse testing on a single power semiconductor; when the device has multiple local execution modules, it forms a multi-channel parallel test device for simultaneously performing dual-pulse testing on multiple power semiconductors. The global control module 11 is the global coordinating node in the entire dual-pulse test device, while the local execution modules are the local execution and self-preservation nodes, forming a logically decoupled cooperative relationship between them.

[0022] To improve the versatility of the dual-pulse testing device described in this application in practical applications, any one of the N local execution modules 12 is named the target local execution module 12. Taking the target local execution module 12 as an example, the information interaction process between the global control module 11 and the target local execution module 12 will be specifically explained.

[0023] Step 1: When the global control module 11 wants to perform a double-pulse test on the target device, it first asks the target local execution module 12 to read the characteristic parameters of the target device and generate a test task in combination with the test target; then, the global control module 11 generates a parameter package based on the test task and the characteristic parameters of the target device and sends the parameter package to the target local execution module 12.

[0024] The test targets include: the actual test voltage and actual test current of the target device when it enters the preset tolerance range during the double-pulse test, and the waveform parameters corresponding to the waveform output by the target device when it can reach a stable state during the double-pulse test.

[0025] Step 2: After the target local execution module 12 receives the parameter packet sent by the global control module 11, it will perform a double-pulse test on the target device according to the parameter packet sent by the global control module 11, and will feed back the double-pulse test results of the target device to the global control module 11. The double-pulse test results of the target device include: the voltage waveform, current waveform, and drive timing waveform corresponding to the target device during the double-pulse test.

[0026] Step 3: When the global control module 11 receives the double pulse test result of the target device fed back by the target local execution module 12, it will iteratively adjust the parameter package according to the double pulse test result of the target device fed back by the target local execution module 12, and send the iteratively adjusted parameter package to the target local execution module 12.

[0027] Step 4: After the target local execution module 12 receives the iteratively adjusted parameter packet issued by the global control module 11, it will perform a double-pulse test on the target device according to the iteratively adjusted parameter packet issued by the global control module 11, and will feed back the double-pulse test result of the target device to the global control module 11. Then, the global control module 11 will continue to execute Step 4 until the double-pulse test result of the target device fed back by the target local execution module 12 meets the test target.

[0028] Compared to existing technologies, the dual-pulse testing device provided in this embodiment eliminates the drawbacks of manual parameter adjustment by testers relying on their experience. This is because the global control module automatically iteratively adjusts the parameter package based on the dual-pulse test results fed back by the target local execution module until the dual-pulse test results of the target device meet the test objectives. Since this method can simultaneously perform parallel batch dual-pulse testing on multiple power semiconductors, it not only improves the efficiency of dual-pulse testing of power semiconductors but also ensures the consistency and reliability of the test results. Furthermore, in this embodiment, the dual-pulse test of the target device is performed by the target local execution module, which is closer to the target device. This shortens the communication link between the global control module and the target device, eliminating the need for the global control module to directly address nanosecond-level timing challenges. This effectively avoids test errors caused by long-distance communication delays, thereby further improving the accuracy and reliability of the power semiconductor dual-pulse test results.

[0029] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. Please refer to [link / reference]. Figure 2 , Figure 2 This is a structural diagram of another power semiconductor dual-pulse testing device provided in an embodiment of the present invention. In a preferred embodiment, the global control module 11 includes: The first communication unit 101 is used to transmit communication data; The high-voltage power supply control interface 102 is used to communicate with an external high-voltage power supply module; The main contactor control unit 103 is used to control the on / off state of the external high-voltage power supply module; The parameter calculation unit 104 is connected to the first communication unit 101, the high-voltage power supply control interface 102, and the main contactor control unit 103. When a double-pulse test is to be performed on the target device, it generates a parameter package based on the test task and the characteristic parameters of the target device, and sends the parameter package to the target local execution module through the first communication unit 101. At the same time, it obtains the double-pulse test result of the target device fed back by the target local execution module through the first communication unit 101, it iteratively adjusts the parameter package based on the double-pulse test result of the target device fed back by the target local execution module, and sends the iteratively adjusted parameter package to the target local execution module until the double-pulse test result of the target device fed back by the target local execution module meets the test target.

[0030] In this embodiment, the functional components inside the global control module 11 are described in detail. Specifically, the global control module 11 includes a first communication unit 101, a high-voltage power supply control interface 102, a main contactor control unit 103, and a parameter calculation unit 104.

[0031] The first communication unit 101 is used to transmit communication data, including sending parameter packets to the target local execution module 12, receiving status information and event notifications fed back by the target local execution module 12, etc. The first communication unit 101 and the second communication unit 204 in the target local execution module 12 form a high-speed isolated communication relationship.

[0032] The high-voltage power supply control interface 102 is used to communicate with the external high-voltage power supply module 14 to enable, interlock, and coordinate the state of the high-voltage energy source. The high-voltage power supply control interface 102 itself does not directly generate high-voltage pulse energy; instead, it acts as a control channel to coordinate the external high-voltage power supply module 14 to provide energy to the bus pre-charge branch 202 of the target local execution module 12. It should be noted that the external high-voltage power supply module 14 can be either an external high-voltage DC power supply or an independent high-voltage charging subsystem that works in conjunction with the global control module 11.

[0033] The main contactor control unit 103 is used to control the on / off state of the external high-voltage power supply module 14. Furthermore, the main contactor control unit 103 can perform global interlocking or bus disconnection operations on the double pulse test device under conditions such as failure of the double pulse test device, abnormal termination of the test, and test exit. This enables the global control module 11 to form a layered protection system together with the local hardware protection chain 207 in the target local execution module 12.

[0034] The parameter calculation unit 104 is used to store the characteristic parameters of the target device and to perform test parameter generation, closed-loop compensation calculation, and degradation decision-making after a fault. When the global control module 11 needs to perform a double-pulse test on the target device, the parameter calculation unit 104 generates a parameter package based on the test task and the characteristic parameters of the target device, and sends the parameter package to the target local execution module 12 through the first communication unit 101. At the same time, it obtains the double-pulse test result of the target device fed back by the target local execution module 12 through the first communication unit 101 to iteratively adjust the parameter package, and sends the iteratively adjusted parameter package to the target local execution module 12 until the double-pulse test result of the target device fed back by the target local execution module 12 meets the test target.

[0035] It should be noted that the global control module 11 may also include a host computer interface 105, so that the global control module 11 can comprehensively manage the test tasks sent by the host computer 10, the double pulse test results uploaded by the target local execution module 12, and alarm information, and perform better double pulse testing on the target device.

[0036] Clearly, the technical solution provided in this embodiment can ensure the overall reliability of the global control module when performing its corresponding functions.

[0037] Please continue reading Figure 2 The target local execution module 12 includes: The proximity energy storage unit 201, located within a preset range, is used to provide an energy source for the target device 13; the preset range is set according to the arrangement position of the target device 13. The bus pre-charge branch 202 is used to charge the voltage of the near-load energy storage unit 201 to the target bus voltage using the external high-voltage power supply module 14 according to the instructions issued by the global control module. The low parasitic bus loop 203 is connected between the target device 13 and the near-load energy storage unit 201; wherein, the low parasitic bus loop 203 is a bus connection structure designed to shorten the main power current path between the near-load energy storage unit 201, the target device 13 and the load loop, and to reduce the area of ​​the main power loop. The second communication unit 204 is used to generate a corresponding drive signal according to the parameter package issued by the global control module or the parameter package after iterative adjustment when the charging voltage of the near-load energy storage unit 201 reaches the preset charging range, and to feed back the double pulse test result of the target device 13 to the global control module through the first communication unit; the preset charging range is set according to the target bus voltage. The signal driving unit 205 is used to perform a double-pulse test on the target device 13 using the driving signal generated by the second communication unit 204; The signal sampling unit 206 is used to acquire the double-pulse test results of the target device 13 in real time.

[0038] In this embodiment, the functional components inside the target local execution module 12 are described in detail. Specifically, the target local execution module 12 is equipped with a near-load energy storage unit 201, a bus pre-charge branch 202, a low parasitic bus circuit 203, a second communication unit 204, a signal driving unit 205, and a signal sampling unit 206.

[0039] The near-load energy storage unit 201 is preferably located near the target device 13 and the freewheeling branch to shorten the pulse energy release path and reduce stray inductance and bus ringing. The bus pre-charge branch 202 is used to charge the voltage of the near-load energy storage unit 201 to the target bus voltage using the external high-voltage power supply module 14 according to the instructions issued by the global control module, so as to establish the local bus conditions required for the double-pulse test of the target device 13.

[0040] The low parasitic bus loop 203 is a bus connection structure designed to shorten the main power current path between the near-load energy storage unit 201, the target device 13, and the load loop, and to reduce the area of ​​the main power loop. That is, the low parasitic bus loop 203 preferably adopts a design with short path, low loop area, and near-load layout, which can improve the fidelity of the double-pulse test results and the consistency of multiple rounds of testing.

[0041] The second communication unit 204 is used to generate a corresponding drive signal according to the parameter package issued by the global control module or the parameter package after iterative adjustment when the charging voltage of the near-load energy storage unit 201 reaches the preset charging range, and to feed back the double pulse test result of the target device 13 to the global control module through the first communication unit. The preset charging range is set according to the target bus voltage.

[0042] The signal driving unit 205 is used to perform a double-pulse test on the target device 13 according to the driving signal generated by the second communication unit 204, and to generate driving pulses corresponding to the first pulse width, dead time, and second pulse width during the double-pulse test on the target device 13 according to the locally generated timing signal. It is easy to see that since the driving pulses for the double-pulse test on the target device 13 are generated locally in the target local execution module 12, the double-pulse test on the target device 13 can be performed by the target local execution module 12, which is closer to the target device 13. This shortens the communication link between the global control module and the target device 13, and the global control module 11 does not need to directly deal with nanosecond-level timing challenges, effectively avoiding test errors caused by long-distance communication delays.

[0043] The signal sampling unit 206 is used to acquire the double-pulse test results of the target device 13 in real time, and synchronously acquire the voltage, current and key timing waveforms during the test process, providing a data basis for subsequent parameter extraction, fault analysis and closed-loop compensation.

[0044] In a preferred embodiment, the target local execution module 12 further includes: The local hardware protection chain 207 is used to control the target local execution module 12 to lock and / or softly shut down when an abnormality is detected in the target device 13 and / or the target local execution module 12 and / or the global control module, and to prompt the corresponding fault information.

[0045] In this embodiment, a local hardware protection chain 207 is also provided in the target local execution module 12. The local hardware protection chain 207 is used to detect the current values ​​in the main power circuit and current circuit of the target device 13, the global control module 11, and the target local execution module 12, as well as the on-state voltage drop and drive signal of the target device 13. When the local hardware protection chain 207 detects an abnormality in a certain measurement parameter, it will lock out and / or soft-shut down the target local execution module 12. Furthermore, when the local hardware protection chain 207 detects an abnormality in the target device 13 and / or the target local execution module 12, it will also report the corresponding fault information to the global control module 11 through the second communication unit 204.

[0046] In practical applications, if a communication timeout occurs between the global control module 11 and the target local execution module 12, or if the global control module 11 detects that the parameter packet sent to the target local execution module 12 is incomplete, the global control module 11 will stop sending parameter packets to the target local execution module 12. The local hardware protection chain 207 will then lock out and / or soft-shut down the target local execution module 12 to avoid false triggering caused by missing parameters, timing inconsistencies, or state mismatches. If the near-load energy storage unit 201 in the target local execution module 12 does not complete pre-charging within a preset time, or if the measured bus voltage of the target device 13 does not meet the requirements, the target local execution module 12 will not perform a double-pulse test on the target device to prevent waveform distortion caused by forcibly performing a double-pulse test on the target device 13 when the bus voltage does not meet the conditions.

[0047] In addition, to prevent the target local execution module 12 from entering an islanded state due to communication interruption between the global control module 11 and the target local execution module 12, watchdog timers can be configured in both modules. Specifically, after receiving a trigger authorization from the global control module 11 and entering the bus pre-charging or execution preparation phase, the target local execution module 12 needs to maintain heartbeat communication with the global control module 11 within a preset period. If the communication between the target local execution module 12 and the global control module 11 is interrupted during the pre-charging preparation phase or the communication duration exceeds the preset duration, the local hardware protection chain 207 will also trigger a lockout.

[0048] Please see Figure 3 , Figure 3 This is a structural diagram of a local hardware protection chain provided in an embodiment of the present invention. Specifically, the local hardware protection chain 207 includes: a current detection branch 001, a conduction voltage drop detection branch 002, a dead zone time generator 003, a high-speed current comparator 004, a conduction voltage drop comparator 005, a fault logic circuit 006, a duration determination unit 007, a latching block circuit 008, and a soft shutdown control unit 009.

[0049] Among them, the current detection branch 001 collects the current signal of the main circuit, and after signal conditioning, it is sent to the high-speed current comparator 004 for comparison with the preset first fault threshold; the on-state voltage drop detection branch 002 collects the main power terminal voltage signal of the target device 13 in the on state, and after signal conditioning, it is sent to the on-state voltage drop comparator 005 for comparison with the preset second fault threshold; after the gate drive conduction edge of the target device 13 or the local timing start signal of the target local execution module 12 is sent to the dead zone time generator 003, a timing dead zone signal of preset duration will be generated. The timing dead zone signal will temporarily shield the output of the high-speed current comparator 004 and / or the on-state voltage drop comparator 005.

[0050] After the blind zone ends, if the signal output by the high-speed current comparator 004 or the on-state voltage drop comparator 005 meets the fault warning signal and the duration of the output signal exceeds the preset threshold, then the fault logic circuit 006 and the duration determination unit 007 will output a valid fault trigger signal. The fault trigger signal will set the latching latch circuit 008, and the latching latch signal output by the latching latch circuit 008 will be directly sent to the signal driving unit 205 to cut off the drive output of the signal driving unit 205. At the same time, the latching latch signal output by the latching latch circuit 008 will also trigger the soft shutdown control unit 009 to perform controlled shutdown, thereby avoiding damage to the electronic components in the target local execution module 12 caused by the overvoltage generated by hard shutdown. In addition, the latching latch signal output by the latching latch circuit 008 will also be sent to the buffer control unit of the signal sampling unit 206 to freeze the fault waveform, and notify the global control module 11 of the fault event through the asynchronous reporting link. The latching signal output by the latching circuit 008 will remain valid until manually reset, thereby preventing repeated triggering of faults.

[0051] It should be noted that the fault logic circuit 006 also receives a manual reset signal, so that after the fault is manually cleared, the fault logic circuit 006 can resume normal fault judgment logic. The blind zone time generator 003 temporarily blocks the logic signals output by the high-speed current comparator 004 and / or the on-state voltage drop comparator 005 within a preset short time window after the target device 13 is turned on. This is to avoid false triggering of the target device 13 at the moment of turn-on due to parasitic parameter coupling, current spikes, reverse recovery disturbances, Miller coupling, or transient interference from sensors. With this setting, the ability of the local hardware protection chain 207 to distinguish between real faults and transient disturbances can be improved.

[0052] In other words, the blind zone logic generated by the blind zone time generator 003 is not intended to cancel protection, but rather to achieve precise control over the triggering time of the protection mechanism. The blind zone time generator 003 only prevents fault criteria from entering the latching block path during a very brief transient phase (typically a few hundred nanoseconds to a few microseconds) after the target device 13 is turned on; after the blind zone ends, the output signals of the high-speed current comparator 004 and the on-state voltage drop comparator 005 immediately return to their valid state. Once the target device 13 meets the actual fault criteria such as overcurrent, abnormal on-state voltage drop, or continuous exceedance of limits, the protection action of the local hardware protection chain 207 will be triggered. The blind zone duration generated by the blind zone time generator 003 can be flexibly set according to the type of target device 13 and the test conditions.

[0053] It should be noted that in practical applications, the local hardware protection chain 207 can also be configured with other structural forms, as long as the execution logic of the local hardware protection chain 207 can be implemented. The local hardware protection chain 207 does not rely on the judgment logic of the central software to execute the fault triggering action, but is executed by the detected current detection signal, the device on-state voltage drop signal, and the timing dead zone signal. Among them, the current detection signal is used to characterize the current parameter characteristics of the main circuit, and it can be detected by a high-bandwidth shunt, Rogowski coil, or other high-speed current sensor. The device on-state voltage drop signal is used to characterize the voltage characteristic parameters of the target device 13 in the on-state. Specifically, if the target device 13 is an IGBT (Insulated Gate Bipolar Transistor), then the device on-state voltage drop signal is the voltage drop signal between the collector and emitter of the IGBT. If the target device 13 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or GaN (Gallium Nitride), then the device's on-state voltage drop signal is the voltage drop signal between the drain and the source.

[0054] Obviously, the technical solution provided in this embodiment can more promptly eliminate abnormal faults that occur in the dual-pulse testing device.

[0055] Please see Figure 4 , Figure 4 This is a flowchart of a double-pulse testing method for power semiconductors provided in an embodiment of the present invention. The method is applied to the global control module in a double-pulse testing device and includes: Step S11: When performing a double-pulse test on the target device, a parameter packet is generated based on the test task and the characteristic parameters of the target device, and the parameter packet is sent to the target local execution module; the target local execution module is any one of N local execution modules; N≥1; Step S12: Iteratively adjust the parameter package based on the double-pulse test results of the target device fed back by the target local execution module, and send the iteratively adjusted parameter package to the target local execution module until the double-pulse test results of the target device fed back by the target local execution module meet the test target; wherein, when the target local execution module receives the parameter package or the iteratively adjusted parameter package issued by the global control module, it performs a double-pulse test on the target device based on the parameter package issued by the global control module or the iteratively adjusted parameter package, and feeds back the double-pulse test results of the target device to the global control module.

[0056] This embodiment provides a double-pulse testing method for power semiconductors. This method describes the aforementioned double-pulse testing process from the perspective of the global control module within the double-pulse testing device. Specific implementation details can be found in the aforementioned disclosure and will not be repeated here.

[0057] The dual-pulse testing method for power semiconductors provided in this embodiment of the invention has the beneficial effects of the dual-pulse testing device for power semiconductors disclosed above.

[0058] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the above steps include: when a double-pulse test is to be performed on the target device, a parameter packet is generated according to the test task and the characteristic parameters of the target device, and the parameter packet is sent to the target local execution module, including: When a double-pulse test is to be performed on the target device, the bus voltage, drive bias, protection threshold, first pulse width, dead time and second pulse time corresponding to the double-pulse test are determined according to the test task and the characteristic parameters of the target device. The bus voltage, drive bias, protection threshold, first pulse width, dead time and second pulse time corresponding to the double-pulse test are then sent to the target local execution module.

[0059] In this embodiment, after the dual-pulse test device is powered on, the global control module acquires the characteristic parameters of the target device through the target local execution module. These characteristic parameters include at least: the target device's category, rated withstand voltage, rated current, target test current, external load inductance value, target bus voltage upper limit, drive voltage window, test temperature, and permissible safety boundaries.

[0060] When determining the parameter package for performing a double-pulse test on the target device based on the test task and the characteristic parameters of the target device, the global control module uses table lookup and constraint correction to generate the parameter package. Specifically, the global control module first provides the bus voltage, drive bias, protection threshold, first pulse width t1, dead time t2, and second pulse time t3 corresponding to the double-pulse test of the target device according to the type and rated specifications of the target device, and sends these parameters to the target local execution module.

[0061] After the target local execution module performs a double-pulse test on the target device according to the above parameters, it feeds back the double-pulse test results to the global control module. Upon receiving the double-pulse test results from the target local execution module, the global control module iteratively adjusts the parameter package for the next round of double-pulse testing based on the test task, the characteristic parameters of the target device, and the double-pulse test results. The adjusted parameter package is then sent back to the target local execution module, enabling it to perform another double-pulse test on the target device.

[0062] When generating parameter packages based on the test task and the characteristic parameters of the target device, the global control module can generate parameter packages using the following method: Step 1: Select the bus voltage, drive bias, and protection threshold corresponding to the target device when performing a double-pulse test, according to the type and rated withstand voltage of the target device; Step 2: Estimate the width of the first pulse when performing a double-pulse test on the target device based on the target test current of the target device and the external load inductance, so that the target current at the end of the first pulse can reach the preset tolerance range. Specifically, an estimation model can be used to determine the initial value of the first pulse width.

[0063] The expression for the estimation model is as follows: ; In the formula, The width of the first pulse when performing a double-pulse test on the target device. This is the inductance value of the external load. For the target test current, This is the current bus voltage. The compensation amount is set based on the type of the target device, the switching delay, and the system parasitic parameters.

[0064] It should be noted that in practical applications, even if the initial value of the first pulse width is determined using the estimation model, the first pulse width can still be corrected in subsequent processes by combining temperature, measured waveform characteristics, and safety boundaries.

[0065] Step 3: Select the initial value of the dead time according to the type of the target device, the type of the freewheeling path, and the allowable recovery time of the target device; Step 4: Select the initial value of the subpulse width according to the target observation window and the thermal safety boundary of the target device; Step 5: Based on the test temperature and the characteristic parameters obtained in the previous round, constrain and correct the target bus voltage, drive bias, and protection threshold to form a parameter package.

[0066] Obviously, the technical solution provided in this embodiment can accurately generate the parameter package corresponding to the double-pulse test of the target device.

[0067] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the above steps: iteratively adjusting the parameter package according to the double-pulse test results of the target device fed back by the target local execution module, including: The bus voltage corresponding to the target device during double-pulse testing is iteratively adjusted based on the target model; The expression for the target model is: ; In the formula, To perform the first step on the target device The bus voltage corresponding to the second double-pulse test. To perform the first step on the target device The bus voltage corresponding to the second double-pulse test. For compensation coefficient, To perform the first step on the target device The difference between the expected voltage value and the actual voltage value when the target device is turned off during the double-pulse test.

[0068] In this embodiment, after receiving the test results corresponding to the target device when the target local execution module performs a double-pulse test on the target device, the global control module will extract at least the following characteristic parameters from the double-pulse test results of the target device: the actual bus voltage at the moment of the first pulse turn-off, the bus voltage drop, the peak current deviation, the recovery characteristics during the dead zone, the device turn-on delay, the turn-off delay, and the ringing amplitude.

[0069] During the iterative adjustment of the parameter package, the global control module performs closed-loop compensation on the next parameter package sent to the target local execution module based on the double-pulse test results of the target device. The purpose of this closed-loop compensation is not to change the stress level corresponding to the double-pulse test on the target device, but rather to improve the hit rate of test conditions, reduce waveform drift during multiple rounds of testing on the target device, and improve the consistency of extracted feature parameters within the preset safety boundaries and target tolerance range.

[0070] During the iterative adjustment of the parameter package, if the actual bus voltage deviates from the target test voltage window due to a drop at the moment the first pulse is turned off, the global control module will add a target compensation amount in the next iteration to increase the initial bus voltage. Specifically, the bus voltage corresponding to the double-pulse test of the target device can be iteratively adjusted according to the target model.

[0071] If the target tolerance range still fails to converge after multiple rounds of compensation, the dual-pulse test device will exit automatic compensation and switch to alarm or manual confirmation mode. When the peak current deviates from the target value but remains within the safe stress boundary, the width of the first pulse can be finely adjusted to improve the target test current hit rate. When the recovery characteristics during the dead time show insufficient follow current recovery or excessive recovery time, the dead time can be compensated and corrected. It should be noted that each round of compensation is constrained by the upper limit of the step size and the upper limit of the cumulative value.

[0072] Obviously, the technical solution provided in this embodiment allows for more precise adjustment of the bus voltage corresponding to the target device during double-pulse testing.

[0073] Please see Figure 5 , Figure 5 This is a flowchart of another double-pulse testing method for power semiconductors provided in an embodiment of the present invention. The method is applied to a target local execution module in a double-pulse testing device, where the target local execution module is any one of N local execution modules; N≥1; including: Step S21: Monitor the global control module; when the global control module needs to perform a double-pulse test on the target device, it generates a parameter package based on the test task and the characteristic parameters of the target device, sends the parameter package to the target local execution module, and iteratively adjusts the parameter package based on the double-pulse test results of the target device fed back by the target local execution module. At the same time, it sends the iteratively adjusted parameter package to the target local execution module until the double-pulse test results of the target device fed back by the target local execution module meet the test target. Step S22: When the parameter package or the iteratively adjusted parameter package issued by the global control module is received, the target device is subjected to a double pulse test according to the parameter package issued by the global control module or the iteratively adjusted parameter package, and the double pulse test result of the target device is fed back to the global control module.

[0074] This embodiment provides a double-pulse testing method for power semiconductors. This method describes the aforementioned double-pulse testing process from the perspective of the target local execution module within the double-pulse testing device. Specific implementation details can be found in the aforementioned disclosure and will not be repeated here.

[0075] The dual-pulse testing method for power semiconductors provided in this embodiment of the invention has the beneficial effects of the dual-pulse testing device for power semiconductors disclosed above.

[0076] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the above steps: performing a double-pulse test on the target device according to the parameter package issued by the global control module or the iteratively adjusted parameter package, and feeding back the double-pulse test result of the target device to the global control module, include: Generate corresponding drive signals based on the parameter package issued by the global control module or the parameter package after iterative adjustment; The generated driving signal is used to perform a double-pulse test on the target device, and the double-pulse test result of the target device is fed back to the global control module.

[0077] In this embodiment, after receiving the parameter package or the iteratively adjusted parameter package issued by the global control module, the target local execution module generates a corresponding driving signal based on the parameter package or the iteratively adjusted parameter package issued by the global control module, and uses the generated driving signal to perform a double-pulse test on the target device.

[0078] In other words, the driving signal used to perform double-pulse testing on the target device is generated by the target local execution module, which is closer to the target device, and the double-pulse testing on the target device is performed by the target local execution module, which is closer to the target device. This shortens the communication link between the global control module and the target device, and the global control module does not need to directly deal with nanosecond-level timing challenges, thus effectively avoiding the test error caused by long-distance communication delay.

[0079] Clearly, the technical solution provided in this embodiment can further improve the accuracy and reliability of power semiconductor double-pulse test results.

[0080] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the above step of feeding back the double-pulse test results of the target device to the global control module includes: When the double-pulse test result of the target device is detected, the waveform feature parameters corresponding to the double-pulse test result of the target device are extracted to obtain the target waveform parameters; The target waveform parameters are fed back to the global control module.

[0081] In this embodiment, in order to reduce the amount of data transmitted between the global control module and the target local execution module during communication, when the target local execution module detects the double pulse test result of the target device, it will not directly send the double pulse test result of the target device to the global execution module. Instead, it will extract the waveform feature parameters corresponding to the double pulse test result of the target device, obtain the target waveform parameters, and feed the target waveform parameters back to the global control module.

[0082] Obviously, the technical solution provided in this embodiment can reduce the resource overhead required by the target local execution module when interacting with the global control module.

[0083] Please see Figure 6 , Figure 6 This invention provides a timing diagram of a power semiconductor double-pulse test apparatus for performing double-pulse testing on a target device. The double-pulse test of the target device using the power semiconductor double-pulse test apparatus can be roughly divided into three stages: the first stage is the test preparation and pre-charge stage; the second stage is the normal test process stage; and the third stage is the fault isolation stage. The following will combine... Figure 2 and Figure 5 The three stages described above will be explained in detail.

[0084] Phase 1: Step 1: The host computer sends a test task to the global control module to perform a double-pulse test on the target device; Step 2: When the global control module receives the test task issued by the host computer, it sends an enable command to the external high-voltage power supply module and controls the bus pre-charge branch of the target local execution module to charge the near-load energy storage unit to the target bus voltage. Step 3: When the charging voltage of the near-load energy storage unit reaches the preset charging range, the global control module generates a parameter package based on the test task and the characteristic parameters of the target device, and sends the parameter package to the target local execution module; wherein, the preset charging range is set according to the target bus voltage; Step 4: An external high-voltage power supply continuously provides energy to the target local execution module; Step 5: The target local execution module establishes the bus test voltage for the target device through the bus pre-charge branch and the near-load energy storage unit; Step 6: When the target local execution module completes the pre-charging process without any abnormalities, it sends a message to the global control module indicating that execution is ready. Step 7: The global control module sends a trigger authorization message to the target local execution module, so that the target local execution module can perform a double-pulse test on the target device; Phase Two: Step 8: When the target local execution module receives the trigger authorization information sent by the global control module, it generates the bus voltage, drive bias, protection threshold, first pulse width, dead time and second pulse time corresponding to the double pulse test of the target device according to the parameter packet sent by the global control module, and uses these parameters to perform a double pulse test on the target device. Step 9: During the double-pulse test of the target device, the target local execution module extracts the waveform feature parameters corresponding to the double-pulse test results of the target device and reports the extracted waveform feature parameters to the global control module. Step 10: The global control module iteratively adjusts the parameter package based on the waveform characteristic parameters corresponding to the target device during the double-pulse test, and obtains the iteratively adjusted parameter package; Step 11: The global control module sends the iteratively adjusted parameter package to the target local execution module to continue the double-pulse test on the target device; Phase Three: Step 12: When the target local execution module receives the trigger authorization information sent by the global control module, it generates the bus voltage, drive bias, protection threshold, first pulse width, dead time and second pulse time corresponding to the double pulse test of the target device according to the parameter packet sent by the global control module, and uses these parameters to perform double pulse test on the target device. Step 13: The local hardware protection chain in the target local execution module detects that the drive bias of the target device is too high, and the local hardware protection chain locks the target local execution module. Step 14: The target local execution module asynchronously reports fault information to the global control module; Step 15: The global control module revokes the trigger authorization information sent to the target local control module; Step 16: The global control module cuts off the power supply from the external high-voltage power module to the target local execution module through the main contactor control unit; Step 17: The global control module latches the fault information of the target device; Step 18: The global control module sends a fault alarm message to the host computer and waits for manual reset.

[0085] Based on the technical content disclosed in the foregoing embodiments, the technical effects that this application can achieve are summarized and explained below: First, in the double-pulse testing apparatus provided by this invention, the global control module can automatically and iteratively adjust the parameter package based on the double-pulse test results fed back by the target local execution module until the double-pulse test results of the target device fed back by the target local execution module meet the test objective. This completely eliminates the drawbacks of testers relying on their own experience to manually adjust the parameter package. Since this method can simultaneously perform parallel batch double-pulse testing on multiple power semiconductors, it not only improves the efficiency of double-pulse testing of power semiconductors but also ensures the consistency and reliability of the test results.

[0086] Secondly, in this invention, the dual-pulse test of the target device is performed by the target local execution module, which is closer to the target device. This shortens the communication link between the global control module and the target device. The global control module does not need to directly deal with the timing challenges at the nanosecond level, thus effectively avoiding the test error caused by long-distance communication delay. This can further improve the accuracy and reliability of the power semiconductor dual-pulse test results.

[0087] Third, the present invention, through the combined design of near-load energy storage unit, bus pre-charge branch and low parasitic bus circuit, enables the energy required for dual-pulse testing to be established and released close to the target device, which can effectively shorten the pulse energy release path, reduce stray inductance and bus ringing, thereby improving the fidelity of the test waveform and the consistency of multiple rounds of testing.

[0088] Fourth, the present invention sets up a local hardware protection chain in the target local execution module, and combines latching and soft shutdown mechanisms to enable the fault to be suppressed locally first, and then trigger the global control module to implement global linkage handling through asynchronous reporting. This significantly shortens the transmission length of the fault handling link and improves the protection capability of the entire dual-pulse test device.

[0089] Fifth, the present invention also sets up a fault-tolerant and degradation processing mechanism for scenarios such as communication anomalies, pre-charge anomalies, local hard faults, and closed-loop compensation failures. This enables the dual-pulse test device to not only complete dual-pulse testing and closed-loop correction under normal operating conditions, but also to maintain failure safety under abnormal boundary conditions. This further improves the overall reliability when performing dual-pulse testing on target devices.

[0090] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0091] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0092] The above provides a detailed description of the dual-pulse testing device and method for power semiconductors provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A dual-pulse testing device for power semiconductors, characterized in that, include: A global control module is used to generate a parameter package based on the test task and the characteristic parameters of the target device when a double-pulse test is to be performed on the target device. This parameter package is then sent to the target local execution module. The module iteratively adjusts the parameter package based on the double-pulse test results of the target device fed back by the target local execution module, and simultaneously sends the iteratively adjusted parameter package back to the target local execution module, until the double-pulse test results of the target device fed back by the target local execution module meet the test objective. The target local execution module is any one of N local execution modules; N≥1. The target local execution module is used to perform a double-pulse test on the target device according to the parameter package issued by the global control module or the parameter package after iterative adjustment, and to feed back the double-pulse test result of the target device to the global control module. The target local execution module includes: A proximity energy storage unit, located within a preset range, is used to provide an energy source for the target device; the preset range is set according to the arrangement position of the target device. The bus pre-charge branch is used to charge the voltage of the near-load energy storage unit to the target bus voltage using an external high-voltage power supply module, according to the instructions issued by the global control module. A low-parasitic bus circuit is connected between the target device and the near-load energy storage unit; wherein, the low-parasitic bus circuit is a bus connection structure designed to shorten the main power current path between the near-load energy storage unit, the target device and the load circuit, and to reduce the area of ​​the main power circuit. The second communication unit is used to generate a corresponding drive signal according to the parameter package issued by the global control module or the iteratively adjusted parameter package when the charging voltage of the near-load energy storage unit reaches the preset charging range, and to feed back the double-pulse test result of the target device to the global control module; the preset charging range is set according to the target bus voltage. A signal driving unit is used to perform a double-pulse test on the target device using the driving signal generated by the second communication unit; A signal sampling unit is used to acquire the dual-pulse test results of the target device in real time; The target local execution module also includes: A local hardware protection chain is used to control the target local execution module to lock out and / or soft shut down when an abnormality is detected in the target device and / or the target local execution module and / or the global control module, and to prompt the corresponding fault information. In the local hardware protection chain, the current detection branch collects the current signal of the main circuit and sends it to a high-speed current comparator for comparison with a preset first fault threshold; the on-state voltage drop detection branch collects the main power terminal voltage signal of the target device in the on-state and sends it to an on-state voltage drop comparator for comparison with a preset second fault threshold; after the gate drive conduction edge of the target device or the local timing start signal of the target local execution module is sent to the dead zone time generator, a timing dead zone signal of preset duration is generated, which temporarily shields the output of the high-speed current comparator and / or the on-state voltage drop comparator; after the dead zone ends... If the signal output by the high-speed current comparator or the on-state voltage drop comparator meets the fault warning signal and the duration of the output signal exceeds the preset threshold, the fault logic circuit and the duration determination unit will output a valid fault trigger signal. This signal will set the latching latch circuit. The latching latch signal output by the latching latch circuit will be directly sent to the signal driving unit. In addition to triggering the soft shutdown control unit to perform controlled shutdown, the latching latch signal output by the latching latch circuit will also be sent to the buffer control unit of the signal sampling unit to freeze the fault waveform and notify the global control module of the fault event through the asynchronous reporting link.

2. The dual-pulse testing device for power semiconductors according to claim 1, characterized in that, The global control module includes: The first communication unit is communicatively connected to the second communication unit and is used to transmit communication data; A high-voltage power supply control interface is used to communicate with the external high-voltage power supply module; The main contactor control unit is used to control the on / off state of the external high-voltage power supply module; The parameter calculation unit, connected to the first communication unit, the high-voltage power supply control interface, and the main contactor control unit, is used to generate a parameter package based on the test task and the characteristic parameters of the target device when a double-pulse test is to be performed on the target device. The parameter package is then sent to the target local execution module via the first communication unit. Simultaneously, the double-pulse test result of the target device fed back by the target local execution module is obtained through the first communication unit. The parameter package is iteratively adjusted based on the double-pulse test result of the target device fed back by the target local execution module, and the iteratively adjusted parameter package is sent to the target local execution module until the double-pulse test result of the target device fed back by the target local execution module meets the test objective.

3. A double-pulse testing method for power semiconductors, characterized in that, A global control module used in a dual-pulse testing device includes: When performing a double-pulse test on the target device, a parameter packet is generated based on the test task and the characteristic parameters of the target device, and the parameter packet is sent to the target local execution module; the target local execution module is any one of N local execution modules; N≥1; The parameter package is iteratively adjusted based on the double-pulse test results of the target device fed back by the target local execution module, and the iteratively adjusted parameter package is sent back to the target local execution module until the double-pulse test results of the target device fed back by the target local execution module meet the test target; wherein, when the target local execution module receives the parameter package or the iteratively adjusted parameter package issued by the global control module, it performs a double-pulse test on the target device based on the parameter package issued by the global control module or the iteratively adjusted parameter package, and feeds back the double-pulse test results of the target device to the global control module; The target local execution module includes: A proximity energy storage unit, located within a preset range, is used to provide an energy source for the target device; the preset range is set according to the arrangement position of the target device. The bus pre-charge branch is used to charge the voltage of the near-load energy storage unit to the target bus voltage using an external high-voltage power supply module, according to the instructions issued by the global control module. A low-parasitic bus circuit is connected between the target device and the near-load energy storage unit; wherein, the low-parasitic bus circuit is a bus connection structure designed to shorten the main power current path between the near-load energy storage unit, the target device and the load circuit, and to reduce the area of ​​the main power circuit. The second communication unit is used to generate a corresponding drive signal according to the parameter package issued by the global control module or the iteratively adjusted parameter package when the charging voltage of the near-load energy storage unit reaches the preset charging range, and to feed back the double-pulse test result of the target device to the global control module; the preset charging range is set according to the target bus voltage. A signal driving unit is used to perform a double-pulse test on the target device using the driving signal generated by the second communication unit; A signal sampling unit is used to acquire the dual-pulse test results of the target device in real time; The target local execution module also includes: A local hardware protection chain is used to control the target local execution module to lock out and / or soft shut down when an abnormality is detected in the target device and / or the target local execution module and / or the global control module, and to prompt the corresponding fault information. In the local hardware protection chain, the current detection branch collects the current signal of the main circuit and sends it to a high-speed current comparator for comparison with a preset first fault threshold; the on-state voltage drop detection branch collects the main power terminal voltage signal of the target device in the on-state and sends it to an on-state voltage drop comparator for comparison with a preset second fault threshold; after the gate drive conduction edge of the target device or the local timing start signal of the target local execution module is sent to the dead zone time generator, a timing dead zone signal of preset duration is generated, which temporarily shields the output of the high-speed current comparator and / or the on-state voltage drop comparator; after the dead zone ends... If the signal output by the high-speed current comparator or the on-state voltage drop comparator meets the fault warning signal and the duration of the output signal exceeds the preset threshold, the fault logic circuit and the duration determination unit will output a valid fault trigger signal. This signal will set the latching latch circuit. The latching latch signal output by the latching latch circuit will be directly sent to the signal driving unit. In addition to triggering the soft shutdown control unit to perform controlled shutdown, the latching latch signal output by the latching latch circuit will also be sent to the buffer control unit of the signal sampling unit to freeze the fault waveform and notify the global control module of the fault event through the asynchronous reporting link.

4. The double-pulse testing method for power semiconductors according to claim 3, characterized in that, When a dual-pulse test is to be performed on the target device, a parameter packet is generated based on the test task and the characteristic parameters of the target device, and the parameter packet is sent to the target local execution module, including: When a double-pulse test is to be performed on the target device, the bus voltage, drive bias, protection threshold, first pulse width, dead time, and second pulse time corresponding to the double-pulse test are determined according to the test task and the characteristic parameters of the target device, and the bus voltage, drive bias, protection threshold, first pulse width, dead time, and second pulse time corresponding to the double-pulse test are sent to the target local execution module.

5. The double-pulse testing method for power semiconductors according to claim 3, characterized in that, The iterative adjustment of the parameter package based on the double-pulse test results of the target device fed back by the target local execution module includes: The bus voltage corresponding to the double-pulse test of the target device is iteratively adjusted according to the target model; The expression for the target model is: ； In the formula, To perform the first step on the target device The bus voltage corresponding to the second double-pulse test. To perform the first step on the target device The bus voltage corresponding to the second double-pulse test. For compensation coefficient, To perform the first step on the target device The difference between the expected voltage value and the actual voltage value when the target device is turned off during the double-pulse test.

6. A double-pulse testing method for power semiconductors, characterized in that, A target local execution module applied in a double-pulse testing device, wherein the target local execution module is any one of N local execution modules; N≥1; comprising: The global control module is monitored. When the global control module needs to perform a double-pulse test on the target device, it generates a parameter package based on the test task and the characteristic parameters of the target device, sends the parameter package to the target local execution module, and iteratively adjusts the parameter package based on the double-pulse test result of the target device fed back by the target local execution module. At the same time, the iteratively adjusted parameter package is sent to the target local execution module until the double-pulse test result of the target device fed back by the target local execution module meets the test target. When the parameter package or the iteratively adjusted parameter package issued by the global control module is received, the target device is subjected to a double pulse test according to the parameter package issued by the global control module or the iteratively adjusted parameter package, and the double pulse test result of the target device is fed back to the global control module. The target local execution module includes: A proximity energy storage unit, located within a preset range, is used to provide an energy source for the target device; the preset range is set according to the arrangement position of the target device. The bus pre-charge branch is used to charge the voltage of the near-load energy storage unit to the target bus voltage using an external high-voltage power supply module, according to the instructions issued by the global control module. A low-parasitic bus circuit is connected between the target device and the near-load energy storage unit; wherein, the low-parasitic bus circuit is a bus connection structure designed to shorten the main power current path between the near-load energy storage unit, the target device and the load circuit, and to reduce the area of ​​the main power circuit. The second communication unit is used to generate a corresponding drive signal according to the parameter package issued by the global control module or the iteratively adjusted parameter package when the charging voltage of the near-load energy storage unit reaches the preset charging range, and to feed back the double-pulse test result of the target device to the global control module; the preset charging range is set according to the target bus voltage. A signal driving unit is used to perform a double-pulse test on the target device using the driving signal generated by the second communication unit; A signal sampling unit is used to acquire the dual-pulse test results of the target device in real time; The target local execution module also includes: A local hardware protection chain is used to control the target local execution module to lock out and / or soft shut down when an abnormality is detected in the target device and / or the target local execution module and / or the global control module, and to prompt the corresponding fault information. In the local hardware protection chain, the current detection branch collects the current signal of the main circuit and sends it to a high-speed current comparator for comparison with a preset first fault threshold; the on-state voltage drop detection branch collects the main power terminal voltage signal of the target device in the on-state and sends it to an on-state voltage drop comparator for comparison with a preset second fault threshold; after the gate drive conduction edge of the target device or the local timing start signal of the target local execution module is sent to the dead zone time generator, a timing dead zone signal of preset duration is generated, which temporarily shields the output of the high-speed current comparator and / or the on-state voltage drop comparator; after the dead zone ends... If the signal output by the high-speed current comparator or the on-state voltage drop comparator meets the fault warning signal and the duration of the output signal exceeds the preset threshold, the fault logic circuit and the duration determination unit will output a valid fault trigger signal. This signal will set the latching latch circuit. The latching latch signal output by the latching latch circuit will be directly sent to the signal driving unit. In addition to triggering the soft shutdown control unit to perform controlled shutdown, the latching latch signal output by the latching latch circuit will also be sent to the buffer control unit of the signal sampling unit to freeze the fault waveform and notify the global control module of the fault event through the asynchronous reporting link.

7. The double-pulse testing method for power semiconductors according to claim 6, characterized in that, The step of performing a double-pulse test on the target device based on the parameter package issued by the global control module or the iteratively adjusted parameter package, and feeding back the double-pulse test result of the target device to the global control module, includes: Generate corresponding drive signals based on the parameter package issued by the global control module or the iteratively adjusted parameter package; The target device is subjected to a double-pulse test using the generated drive signal, and the double-pulse test result of the target device is fed back to the global control module.

8. The double-pulse testing method for power semiconductors according to claim 6, characterized in that, The step of feeding back the dual-pulse test results of the target device to the global control module includes: When the double-pulse test result of the target device is detected, the waveform feature parameters corresponding to the double-pulse test result of the target device are extracted to obtain the target waveform parameters; The target waveform parameters are fed back to the global control module.

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