Method and system for dynamic adjustment of test vectors based on ATE equipment

Abstract

The application provides a method and system for dynamically adjusting test vectors based on an ATE device, the method comprising: generating a test vector; the ATE device reading the test vector and testing an integrated circuit under test based on the test vector; collecting response data of the integrated circuit under test during the testing process, comparing the response data with expected output signals, and determining whether the test vector is abnormal based on the comparison result; generating a feedback signal when it is detected that the test vector is abnormal; and adjusting the test vector based on the feedback signal. By monitoring the response data of the integrated circuit under test in real time during the testing process and dynamically adjusting the test vector according to real-time feedback, the traditional fixed test vector can quickly discover and cover the fault modes that may be missed. The testing period is shortened, and the testing cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a method and system for dynamically adjusting test vectors based on ATE equipment. Background Technology

[0002] In integrated circuit manufacturing, automated test equipment (ATE) plays a crucial role in verifying chip functionality and performance. Test vectors, as the fundamental instruction set for ATE operations, rely on fixed vector definitions pre-defined and cannot be altered during testing. This static testing model presents several technical challenges: for increasingly complex modern integrated circuits, pre-defined test vectors struggle to effectively identify all potential fault scenarios, leading to incomplete test coverage. Engineers are forced to repeatedly execute tests and manually correct vectors, significantly extending testing cycles and increasing production costs. Furthermore, differences in production batches or process conditions introduce new defect types. Fixed vectors lack adaptability and cannot dynamically optimize test strategies for process fluctuations, resulting in repetitive test plan development and further complicating the testing process. In addition, the lack of real-time data feedback mechanisms prevents the ATE system from adjusting test parameters based on chip responses, making the testing process rigid and unable to meet dynamically changing testing needs, severely limiting overall testing efficiency and adaptability. Summary of the Invention

[0003] This invention provides a method and system for dynamically adjusting test vectors based on ATE equipment, enabling real-time modification of vector parameters during testing, reducing ATE memory usage and test interruption frequency, and enhancing the adaptability and flexibility of testing.

[0004] This invention provides a method for dynamically adjusting test vectors based on ATE equipment, the method comprising: Generate test vectors; The ATE device reads the test vector and performs tests on the integrated circuit under test based on the test vector; During the test, the response data of the integrated circuit under test is collected, and the response data is compared with the expected output signal. Based on the comparison result, it is determined whether the test vector is abnormal. When an anomaly is detected in the test vector, a feedback signal is generated; The test vector is adjusted based on the feedback signal.

[0005] Furthermore, comparing the response data with the expected output signal and determining whether the test vector is abnormal based on the comparison result includes at least one of the following determination methods: Determine whether the difference between the response data of the integrated circuit under test and the expected output signal exceeds a preset threshold; Determine whether the response timing of the integrated circuit under test matches the expected timing; Determine whether the integrated circuit under test has a functional error.

[0006] Furthermore, adjusting the test vector based on the feedback signal includes at least one of the following adjustment methods: adding a new test vector, deleting an existing test vector, adjusting the input signal, timing parameters or test conditions in the test vector, and sorting the test vector.

[0007] Furthermore, adding new test vectors includes: The feedback signal is used to identify fault modes that are not covered by the original test vectors. For uncovered fault modes, new test vectors are automatically generated. Insert the new test vector into the current test sequence and execute it immediately.

[0008] Furthermore, sorting the test vectors includes: The frequency of faults detected by each test vector is statistically analyzed based on the feedback signals. When the frequency of fault detection is greater than or equal to a set threshold, the test vector is executed.

[0009] Furthermore, based on the dependencies between test vectors, precondition test vectors are executed before dependent test vectors.

[0010] Furthermore, the method also includes: recording the current version of the test vector, the historical versions of the test vector, and the adjustments made to the test vector.

[0011] Furthermore, after the test is completed, a test report is generated; wherein the test report includes test coverage, failure modes, and adjusted test vector information.

[0012] In another aspect of the invention, the system includes: The test vector generation module is configured to generate test vectors. The test execution module is configured to perform tests on the integrated circuit under test using the test vector. The real-time feedback analysis module is configured to collect the response data of the integrated circuit under test, compare the response data with the expected output signal, and determine whether the test vector is abnormal based on the comparison result. The feedback signal generation module is configured to generate a feedback signal when an anomaly is detected in the test vector; Test vector adjustment module: configured to adjust the test vector based on the feedback signal.

[0013] Furthermore, the system also includes: The test vector library is configured to store the current version of the test vector, the historical versions of the test vector, and the adjustments made to the test vector. The user interaction module is configured to send the intervention information input by the user to the real-time feedback analysis module.

[0014] Compared with the prior art, the present invention has at least the following technical effects: This invention rapidly identifies and specifically covers fault modes that may be missed by traditional fixed test vectors by monitoring the response data of the integrated circuit under test in real time during the testing process and dynamically adjusting the test vectors based on real-time feedback. This shortens the testing cycle and reduces testing costs. Simultaneously, the dynamic adjustment mechanism allows the test vectors to adapt to the characteristics of integrated circuits in different batches and under different process conditions, improving the flexibility and adaptability of the test, and enhancing the accuracy and reliability of the test results. Attached Figure Description

[0015] Figure 1 This is a simplified flowchart of the method for dynamically adjusting test vectors based on ATE equipment in Embodiment 1 of the present invention; Figure 2 This is a simplified schematic diagram of the structure for dynamically adjusting test vectors based on ATE equipment in Embodiment 2 of the present invention. Detailed Implementation

[0016] The following description, with reference to schematic diagrams, illustrates a method and system for dynamically adjusting test vectors based on an ATE device, according to the present invention. Preferred embodiments of the invention are shown. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0017] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0018] Example 1 Please refer to Figure 1 This embodiment discloses a method for dynamically adjusting test vectors based on ATE equipment, the method comprising: S1. Generate test vectors; The S2.ATE device reads the test vector and performs tests on the integrated circuit under test based on the test vector; S3. During the test, the response data of the integrated circuit under test is collected, and the response data is compared with the expected output signal. Based on the comparison result, it is determined whether the test vector is abnormal. S4. When an anomaly is detected in the test vector, a feedback signal is generated; S5. Adjust the test vector based on the feedback signal.

[0019] In this embodiment, by monitoring the response data of the integrated circuit under test in real time during the testing process and dynamically adjusting the test vector based on real-time feedback, fault modes that may be missed by traditional fixed test vectors can be quickly identified and specifically covered. This shortens the testing cycle and reduces testing costs. Simultaneously, the dynamic adjustment mechanism allows the test vector to adapt to the characteristics of integrated circuits under different batches and process conditions, improving the flexibility and adaptability of the test, and enhancing the accuracy and reliability of the test results.

[0020] In this embodiment, a test vector refers to a set of input stimulus sequences and their corresponding expected output responses used to verify the functionality and performance of an integrated circuit. Each test vector typically contains the following information: the logic level or analog value of the input signal, timing information (such as clock frequency, pulse width, setup time, hold time, etc.), test conditions (such as power supply voltage, temperature, load conditions, etc.), and the expected output response. Test vectors can cover a variety of test scenarios, from simple logic function verification to complex timing analysis and boundary condition testing.

[0021] In this embodiment, ATE (Automatic Test Equipment) refers to an instrument system specifically designed for automated testing of integrated circuits. ATE equipment can apply various input stimuli to the integrated circuit under test according to predefined or dynamically generated test vectors, and collect and analyze the output response of the integrated circuit under test in real time, thereby determining whether its function is normal and whether its performance meets the standards.

[0022] In this embodiment, the feedback signal refers to an indication automatically generated by the system when the real-time feedback analysis module detects a significant deviation or anomaly between the response data of the integrated circuit under test and the expected output signal. This feedback signal includes information such as the specific type of anomaly (e.g., logic error, timing mismatch, functional failure), the location of the anomaly (e.g., specific test vector number, pin number), the magnitude of the deviation, and its statistical characteristics. The function of the feedback signal is to trigger a dynamic adjustment mechanism, providing data support and decision-making basis for subsequent dynamic modification and optimization of test vectors.

[0023] In step S1, the generation of test vectors requires comprehensive consideration of the integrated circuit's design specifications, functional requirements, performance indicators, and potential failure modes. Specifically, test vectors are generated based on the IC (Integrated Circuit) design specifications, which include key information such as the circuit's functional definition, timing requirements, electrical characteristic parameters, and expected operating condition range.

[0024] In step S2, a specific implementation method for the ATE device to read the test vector and perform testing on the integrated circuit under test based on the test vector is as follows: the ATE device applies the input stimulus sequence in the test vector to the input pins of the integrated circuit under test and simultaneously measures the output response of the integrated circuit under test under these stimuli. The ATE device can be configured to execute the test vector in serial or parallel mode to adapt to different testing requirements and the interface characteristics of the integrated circuit under test.

[0025] In step S3, the response data is compared with the expected output signal, and the determination of whether the test vector is abnormal based on the comparison result includes at least one of the following determination methods: Determine whether the difference between the response data of the integrated circuit under test and the expected output signal exceeds a preset threshold.

[0026] Determine whether the response timing of the integrated circuit under test matches the expected timing.

[0027] Determine whether the integrated circuit under test has a functional error.

[0028] The preset threshold can be set according to the specific design specifications, process characteristics, and test accuracy requirements of the integrated circuit. For digital integrated circuits, the preset threshold can be set as the tolerance range of logic levels, such as a high-level threshold of 90%-110% of the nominal value and a low-level threshold of -10% to 10% of the nominal value. For analog integrated circuits, the preset threshold can be set as the allowable percentage deviation of voltage or current, such as ±5% or ±10%. The setting of the preset threshold needs to comprehensively consider the balance between test accuracy, noise tolerance, and fault detection sensitivity.

[0029] For example, a specific implementation of comparing the response data with the expected output signal and determining whether the test vector is abnormal based on the comparison result is as follows: perform a logical XOR operation on the actual response data and the expected output signal; if the result is non-zero, it indicates that a difference exists. Alternatively, the response data can be sampled and compared with the sampled value of the expected output signal.

[0030] In this embodiment, the expected timing refers to the parameters of the ideal response signal in the time dimension, which are predefined according to the design specifications and timing constraints of the integrated circuit. These parameters include, but are not limited to, the rise time, fall time, propagation delay, setup time, hold time, clock cycle, and duty cycle. Expected timing is a benchmark for evaluating the timing performance of the integrated circuit under test. Any significant deviation between the actual timing and the expected timing may lead to circuit malfunction or performance degradation.

[0031] In this embodiment, the functional error refers to a situation where the output of the integrated circuit under test (ICD) is inconsistent with the expected function defined in the design specifications when performing a specific function or logical operation. This includes logic design defects, process defects (such as jamming faults or bridging faults), data errors caused by timing violations, and abnormal states caused by external interference. Typical functional errors include: incorrect logic operation results (such as incorrect adder output), state machine transition errors (such as the FSM entering an illegal state), data transmission errors (such as lost or corrupted bus data), and abnormal control signals (such as a malfunctioning enable signal).

[0032] In step S5, adjusting the test vector based on the feedback signal includes at least one of the following adjustment methods: adding a new test vector, deleting an existing test vector, adjusting the input signal, timing parameters or test conditions in the test vector, and sorting the test vector.

[0033] Specifically, adding new test vectors includes: S41. Identify the fault modes that are not covered by the original test vectors based on the feedback signal; S42. For uncovered fault modes, automatically generate corresponding new test vectors; S43. Insert the new test vector into the current test sequence and execute it immediately.

[0034] Understandably, the feedback signal includes anomaly information exposed by the integrated circuit under test under the current set of test vectors. By analyzing the type, location, and characteristics of these anomalies, the system can infer fault modes that may exist but have not yet been effectively triggered and detected by existing test vectors.

[0035] In a specific example of S42, the new test vectors can be generated automatically by using an automatic test mode generation algorithm (such as the ATPG algorithm) or a rule-based generation strategy.

[0036] In step S43, the insertion position of the new test vector can be determined according to the testing strategy, for example, immediately following the current test vector, or inserted into a priority queue. After insertion, the ATE device immediately executes the new test vector and continues to monitor the response data in real time, thereby achieving dynamic improvement of test coverage.

[0037] The purpose of the above specific operations is to: identify test blind spots in real time and generate targeted test vectors in an instant, so that the testing process can adaptively cover those failure modes that are difficult to foresee or are missed in the initial test design stage, improve the comprehensiveness and effectiveness of testing, and reduce the risk of product defects leaking out due to insufficient testing.

[0038] In this embodiment, deleting the original test vector refers to removing redundant, inefficient, or invalid test vectors, with the aim of optimizing test time and improving test efficiency.

[0039] In this embodiment, adjusting the input signal, timing parameters, or test conditions in the test vector refers to finely modifying the internal parameters of the existing test vector, with the aim of more accurately locating or verifying specific faults.

[0040] In a specific example, adjusting the input signals in the test vector refers to changing the input voltage, current, data mode, etc., to simulate different operating environments or stimulate specific circuit behaviors. Adjusting timing parameters refers to adjusting the clock frequency, pulse width, setup time, hold time, etc., to detect timing-related faults or optimize test speed. Adjusting test conditions refers to changing the temperature, power supply voltage, load conditions, etc., to simulate extreme operating environments or perform reliability testing.

[0041] In this embodiment, sorting the test vectors refers to optimizing the execution order of the test vectors to improve fault detection efficiency or shorten the overall testing time.

[0042] Specifically, sorting the test vectors includes: calculating the frequency of fault detection by each test vector based on the feedback signal; executing the test vector when the frequency of fault detection is greater than or equal to a set threshold; and controlling the execution of precondition test vectors to take precedence over dependent test vectors based on the dependencies between test vectors.

[0043] The setting of the threshold needs to take into account the balance of test objectives, historical test data, and test resources.

[0044] In practical applications, threshold settings can be determined based on statistical analysis of historical test data. For example, a threshold could be set to a fault detection rate ≥ 8%, meaning that when a test vector's fault detection rate reaches or exceeds 8% in historical tests, that test vector will be executed with priority. Another example is setting a threshold to successfully detect faults ≥ 40 times in the last 500 tests, meaning that when a test vector successfully detects faults at least 40 times in the last 500 tests, the system marks it as a high-priority test vector.

[0045] In this embodiment, the dependency relationship refers to the fact that the correct execution of one or more test vectors or their established specific state is a necessary prerequisite for the effective execution and accurate results of another one or more test vectors (i.e., dependent test vectors). For example, a read / write test of a specific register must be performed after its initialization test. Of course, the dependency relationship can also be a logical order set manually during test sequence design; for example, testing a complex module requires completing the testing of its sub-modules first. It is understood that those skilled in the art can determine the dependencies between test vectors based on integrated circuit design documents, test specifications, historical testing experience, and circuit functional logic.

[0046] The purpose of controlling the execution of precondition test vectors before dependent test vectors is to ensure that all precondition test vectors required by any dependent test vectors have been successfully executed before any dependent test vectors are executed.

[0047] Through the above technical solution, this application effectively solves the problem of unreasonable test order that may result from sorting solely based on failure frequency. By identifying and enforcing the dependencies between test vectors, the preconditions required for the execution of all dependent test vectors are met. This not only avoids false failures or inaccurate test results caused by incorrect test order, but also improves the reliability and effectiveness of the test. Furthermore, this mechanism, combined with the failure frequency-based sorting method, enables the testing process to quickly identify common failures.

[0048] In this embodiment, the method further includes: recording the current version of the test vector, the historical versions of the test vector, and the adjustments made to the test vector.

[0049] In this embodiment, comprehensive version management and change tracking of test vectors can be achieved during the dynamic adjustment of test vectors based on feedback signals. By recording the current version, historical versions, and detailed adjustment content of the test vectors, users can clearly understand the evolution of the test vectors and accurately trace the reasons and effects of each adjustment.

[0050] In a specific example, the adjustment of the test vectors includes, but is not limited to, adding new test vectors, deleting existing test vectors, changing the level or waveform of input signals, adjusting timing parameters, and modifying test conditions.

[0051] Furthermore, after the test is completed, a test report is generated; wherein the test report includes test coverage, failure modes, and adjusted test vector information.

[0052] The fault modes list details all fault types, fault locations, fault triggering conditions, and other information found during the testing process, providing a basis for fault analysis and circuit improvement.

[0053] Example 2 Based on the same inventive concept, this embodiment discloses a system for dynamically adjusting test vectors based on ATE equipment, used to implement the method for dynamically adjusting test vectors based on ATE equipment disclosed in Embodiment 1. Please refer to... Figure 2 The system includes: The test vector generation module is configured to generate test vectors. An ATE device is configured to read the test vector; The test execution module is configured to perform tests on the integrated circuit under test using the test vector. The real-time feedback analysis module is configured to collect the response data of the integrated circuit under test, compare the response data with the expected output signal, and determine whether the test vector is abnormal based on the comparison result. The feedback signal generation module is configured to generate a feedback signal when an anomaly is detected in the test vector; Test vector adjustment module: configured to adjust the test vector based on the feedback signal.

[0054] In this embodiment, through the systematic operation of the above modules, the system can respond to abnormal situations of the integrated circuit under test in real time during the testing process, dynamically adjust the test strategy and test vectors, and improve the flexibility, adaptability and efficiency of the test. Furthermore, the entire system forms a closed-loop adaptive testing mechanism, which can continuously optimize the test plan based on real-time test results, thereby performing comprehensive, efficient and reliable quality inspection of the integrated circuit under test.

[0055] Furthermore, the system also includes: The test vector library is configured to store the current version of the test vector, the historical versions of the test vector, and the adjustments made to the test vector. The user interaction module is configured to send the intervention information input by the user to the real-time feedback analysis module.

[0056] In one specific embodiment, the user interaction module provides a graphical or command-line user interface, allowing test engineers to monitor the testing process in real time, view test results, analyze fault information, and manually intervene in the test vector adjustment process when necessary. Users can use this module to manually add, delete, or modify test vectors, set or adjust automatic adjustment rules and thresholds, pause or resume the testing process, and export test data and reports.

[0057] It is evident that the system for dynamically modifying and adjusting test vectors in the aforementioned ATE equipment can fully leverage the system's intelligent adjustment capabilities and the user's judgment to achieve more flexible, efficient, and precise test control.

[0058] Preferably, the user interaction module also supports a variety of alarm and prompt functions. When a serious anomaly or critical fault is detected, it can promptly notify the user for manual intervention and judgment, ensuring the safety and controllability of the testing process.

[0059] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for dynamically adjusting test vectors based on ATE equipment, characterized in that, The method includes: Generate test vectors; The ATE device reads the test vector and performs tests on the integrated circuit under test based on the test vector; During the test, the response data of the integrated circuit under test is collected, and the response data is compared with the expected output signal. Based on the comparison result, it is determined whether the test vector is abnormal. When an anomaly is detected in the test vector, a feedback signal is generated; The test vector is adjusted based on the feedback signal.

2. The method for dynamically adjusting test vectors based on ATE equipment as described in claim 1, characterized in that, Comparing the response data with the expected output signal and determining whether the test vector is abnormal based on the comparison result includes at least one of the following determination methods: Determine whether the difference between the response data of the integrated circuit under test and the expected output signal exceeds a preset threshold; Determine whether the response timing of the integrated circuit under test matches the expected timing; Determine whether the integrated circuit under test has a functional error.

3. The method for dynamically adjusting test vectors based on ATE equipment as described in claim 1, characterized in that, Adjusting the test vector based on the feedback signal includes at least one of the following adjustment methods: adding a new test vector, deleting an existing test vector, adjusting the input signal, timing parameters or test conditions in the test vector, and sorting the test vector.

4. The method for dynamically adjusting test vectors based on ATE equipment as described in claim 3, characterized in that, Adding new test vectors includes: The feedback signal is used to identify fault modes that are not covered by the original test vectors. For uncovered fault modes, new test vectors are automatically generated. Insert the new test vector into the current test sequence and execute it immediately.

5. The method for dynamically adjusting test vectors based on ATE equipment as described in claim 3, characterized in that, Sorting the test vectors includes: The frequency of faults detected by each test vector is statistically analyzed based on the feedback signals. When the frequency of fault detection is greater than or equal to a set threshold, the test vector is executed.

6. The method for dynamically adjusting test vectors based on ATE equipment as described in claim 5, characterized in that, Sorting the test vectors further includes: Based on the dependencies between test vectors, the execution of precondition test vectors is prioritized over dependent test vectors.

7. The method for dynamically adjusting test vectors based on ATE equipment as described in claim 1, characterized in that, The method further includes: recording the current version of the test vector, the historical versions of the test vector, and the adjustments made to the test vector.

8. The method for dynamically adjusting test vectors based on ATE equipment as described in claim 1, characterized in that, The method further includes: generating a test report after the test is completed; wherein the test report includes test coverage, failure modes, and adjusted test vector information.

9. A system for dynamically adjusting test vectors based on ATE equipment, characterized in that, The system includes: The test vector generation module is configured to generate test vectors. An ATE device is configured to read the test vector; The test execution module is configured to perform tests on the integrated circuit under test using the test vector. The real-time feedback analysis module is configured to collect the response data of the integrated circuit under test, compare the response data with the expected output signal, and determine whether the test vector is abnormal based on the comparison result. The feedback signal generation module is configured to generate a feedback signal when an anomaly is detected in the test vector; Test vector adjustment module: configured to adjust the test vector based on the feedback signal.

10. The system for dynamically adjusting test vectors based on ATE equipment as described in claim 9, characterized in that, The system also includes: The test vector library is configured to store the current version of the test vector, the historical versions of the test vector, and the adjustments made to the test vector. The user interaction module is configured to send the intervention information input by the user to the real-time feedback analysis module.

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