A self-test method for wafer probe cards

Abstract

The application relates to the technical field of wafer acceptance test, and discloses a self-checking method of a wafer probe card, which comprises the following steps: marking a probe group with an average resistance greater than a resistance threshold value as an abnormal probe group; electrically short-circuiting each wire corresponding to the abnormal probe group in the test machine to construct a first measurement loop, and measuring a loop resistance value of the first measurement loop; calculating a loop difference value of the average resistance and the loop resistance value; in response to an absolute value of the loop difference value being less than or equal to a loop threshold value, determining that a fault type is poor contact between a probe and a test point interface; and in response to the absolute value of the loop difference value being greater than the loop threshold value, determining that a fault type is an internal link fault. The self-checking method of the wafer probe card can distinguish the fault source of abnormal contact into poor contact between a probe and a test point interface or an internal link fault of the test machine, so that the reliability of wafer probe card self-checking and product yield are ensured.

Description

Technical Field

[0001] This invention relates to the field of wafer acceptance testing technology, and in particular to a self-testing method for a wafer probe card. Background Technology

[0002] Wafer acceptance testing, conducted after wafer fabrication but before quality inspection, involves measuring the electrical parameters of specific test structures using a testing machine to evaluate the quality and stability of the semiconductor manufacturing process. Probe cards are a crucial component of wafer acceptance testing; the testing machine uses these probe cards to attach to test points on the wafer to apply signals and perform measurements.

[0003] During wafer testing, subsequent electrical characteristics, functional, and reliability tests are only valid if the probes make proper contact with the test points. Currently, multiple probe groups are set on the probe card, with each group containing two or more probes. Multiple probes from the same group contact the same test point, and the contact is determined by measuring the resistance between two probes within the same group using a testing machine.

[0004] During wafer testing, it is generally desirable for the contact resistance between the probe and the test point to remain at an extremely low and stable level, such as below 1Ω, to ensure the accuracy of subsequent tests. However, as wafer testing continues, aluminum shavings or oxide particles from the test point surface gradually adhere to the probes due to repeated piercing. This probe contamination leads to increased and unstable contact resistance between the probe and the test point. This not only introduces measurement errors but may also cause test data to deviate from the true value due to excessively high contact resistance. Ultimately, this could result in correctly performing chips being misclassified as defective, or defective chips being allowed to enter the subsequent packaging stage, causing incalculable yield losses and cost waste.

[0005] To address the testing risks posed by poor probe card contact, current methods include maintaining system accuracy through regular calibration of the testing equipment, or by using a manual microscope in conjunction with probe station operation to assess probe contact before testing. For example, the consistency of probe tip height can be indirectly evaluated by calculating the positional differences of the probe station's lifting platform at different probe contact points.

[0006] However, regular equipment calibration is time-consuming, often requiring several hours to calibrate a single tester. Furthermore, calibration only guarantees the accuracy of the tester itself and does not reflect the health of the entire signal path from the tester through wires and connectors to the probe tip. Consequently, when the resistance value of the probe group is abnormal, the specific source of the contact abnormality cannot be determined. Different faults require completely different handling methods. For example, if the fault originates from poor contact between the probe and the test point interface, re-alignment and re-insertion of the probes are necessary; if the fault originates from an internal link failure in the tester, hardware inspection and replacement are required. Failure to pinpoint the source of the fault leads to ineffective repetitive operations and may even mask the true hardware failure, resulting in inaccurate batch test data. Summary of the Invention

[0007] Therefore, the purpose of this invention is to determine whether a contact anomaly originates from poor contact at the probe-test point interface or an internal link failure of the test machine when the probe card contacts the test point. A self-testing method for wafer probe cards is proposed, which involves electrically short-circuiting each wire of the abnormal probe group inside the test machine and measuring the loop resistance under short-circuit conditions. The difference between the loop resistance and the original average resistance of the abnormal probe group is compared to distinguish the source of the contact anomaly as poor contact at the probe-test point interface or an internal link failure of the test machine, thereby ensuring the reliability of the wafer probe card self-testing and product yield.

[0008] To address the aforementioned technical problems, this invention provides a self-testing method for a wafer probe card. After each probe group of the probe card contacts each test point on the wafer, the self-testing method includes: The average resistance of the probe group is obtained, and the probe group with the average resistance greater than the resistance threshold is marked as an abnormal probe group; wherein, each probe group includes at least two probes, each probe is equipped with a wire, one end of the wire is connected to the corresponding probe, and the other end of the wire is connected to the testing machine. The wires corresponding to the abnormal probe group are electrically short-circuited inside the testing machine to construct a first measurement circuit, and the circuit resistance value of the first measurement circuit is measured. Calculate the loop difference between the average resistance value and the loop resistance value: if the absolute value of the loop difference is less than or equal to the loop threshold, the fault type is determined to be poor contact between the probe and the test point interface; if the absolute value of the loop difference is greater than the loop threshold, the fault type is determined to be an internal link fault.

[0009] Preferably, the testing machine includes a switch matrix, the switch matrix including a short-circuit relay; the first input terminal of the short-circuit relay is used to electrically connect to the first wire of the abnormal probe group, and the second input terminal of the short-circuit relay is used to electrically connect to the second wire of the abnormal probe group. When the short-circuit relay is closed, the first wire and the second wire are electrically short-circuited at the common output terminal of the short-circuit relay; and the current path in the first measurement circuit passes sequentially through: the short-circuit point, the first wire, the first probe, the test point, the second probe, and the second wire. When the short-circuit relay is disconnected, the first wire and the second wire are independent of each other.

[0010] Preferably, the resistance threshold is determined based on the contact resistance between the probe and the test point, the probe resistance, the wire resistance, the on-resistance of the switch matrix, and the contact resistance of the connector; The circuit threshold is set to max(average resistance × 10%, 10Ω).

[0011] Preferably, in response to an internal link fault, the self-test method further includes: Disconnect the electrical short circuit, short-circuit the first lead of the abnormal probe group to the system ground inside the tester, inject test current from the second lead, and measure the first one-sided short-circuit resistance value; short-circuit the second lead of the abnormal probe group to the system ground inside the tester, inject test current from the first lead, and measure the second one-sided short-circuit resistance value. Calculate the first difference between the first single-sided short-circuit resistance value and the first line reference value, and the second difference between the second single-sided short-circuit resistance value and the second line reference value, respectively: When the absolute value of the first difference is less than or equal to the first line threshold and the second difference is greater than the second line threshold, the fault is determined to be located on the second conductor side link. When the absolute value of the first difference is greater than the first line threshold and the second difference is less than or equal to the second line threshold, the fault is determined to be located on the first conductor side link. When the absolute value of the first difference is greater than the first line threshold and the second difference is greater than the second line threshold, the fault is determined to be located in the common part of the links on each conductor side.

[0012] Preferably, the testing machine includes a switch matrix, the switch matrix comprising: The first grounding relay has an input terminal for electrically connecting to the first conductor and an output terminal for electrically connecting to the system ground. The second grounding relay has an input terminal for electrically connecting to the second conductor and an output terminal for electrically connecting to the system ground.

[0013] Preferably, the first wire-side link is a signal path that extends from the measurement node corresponding to the first wire inside the test machine along the first wire to the tip of the first probe. The second wire side link is a signal path that extends from the measurement node corresponding to the second wire inside the test machine along the second wire to the tip of the second probe; Each wire side link converges in the probe card substrate circuit and is then connected to the test point.

[0014] Preferably, the method for determining the first line reference value and the second line reference value includes: selecting a probe group with an average resistance value less than a resistance threshold as a first sample probe group; short-circuiting the first lead of the first sample probe group to the system ground inside the testing machine, injecting test current from the second lead, measuring the first one-sided short-circuit resistance value, and using the measured first one-sided short-circuit resistance value as the first line reference value; short-circuiting the second lead of the first sample probe group to the system ground inside the testing machine, injecting test current from the first lead, measuring the second one-sided short-circuit resistance value, and using the measured second one-sided short-circuit resistance value as the second line reference value; The line threshold is defined as min(2 × line reference value, line reference value + 10Ω).

[0015] Preferably, when the fault is determined to be located on any conductor-side link, the self-test method further includes: Disconnect the wire corresponding to the wire side link from the system ground inside the tester. Following the direction from the measurement end inside the tester to the corresponding probe tip, sequentially short-circuit the multi-level electrically accessible nodes on the wire side link to the system ground, and measure the node resistance value between each level of electrically accessible node and the system ground. Compare the node resistance values ​​at each level with the corresponding node reference values: If the absolute value of the difference between the node resistance value of the k-th level electrically accessible node and the corresponding node reference value is less than or equal to the node threshold, and the absolute value of the difference between the node resistance value of the (k+1)-th level and the corresponding node reference value is greater than the node threshold, then the fault is determined to be located in the segment between the k-th level electrically accessible node and the (k+1)-th level electrically accessible node.

[0016] Preferably, the multi-level electrically accessible node includes, in sequence: an ADC output terminal, a switch matrix input terminal, a switch matrix output terminal, and a test machine interface connector; The testing machine includes a switch matrix, which includes a primary relay, a secondary relay, a tertiary relay, and a quaternary relay. The input terminal of the first-level relay is used to electrically connect to the output terminal of the ADC, and the output terminal of the first-level relay is used to electrically connect to the system ground. The input terminal of the secondary relay is used to electrically connect to the input terminal of the switch matrix, and the output terminal of the secondary relay is used to electrically connect to the system ground. The input terminal of the three-stage relay is used to electrically connect to the output terminal of the switch matrix, and the output terminal of the three-stage relay is used to electrically connect to the system ground. The input terminal of the four-stage relay is used to electrically connect to the test machine interface connector, and the output terminal of the four-stage relay is used to electrically connect to the system ground.

[0017] Preferably, the method for determining the node reference value includes: selecting a probe group with an average resistance value less than a resistance threshold as a second sample probe group; sequentially shorting multiple electrically accessible nodes on the first wire-side link or the second wire-side link in the second sample probe group to the system ground in the direction from the measurement end inside the test machine to the corresponding probe tip, measuring the node resistance value between each electrically accessible node and the system ground; and using the node resistance value between each electrically accessible node and the system ground as the corresponding node reference value. The node threshold is defined as min(2 × node baseline value, node baseline value + 10Ω).

[0018] Compared with the prior art, the above-described technical solution of the present invention has the following advantages: The self-testing method of the wafer probe card described in this invention involves electrically short-circuiting each wire of the abnormal probe group inside the test machine and measuring the loop resistance under the short-circuit state. The difference between the loop resistance and the original average resistance of the abnormal probe group is compared to distinguish the source of the contact abnormality fault as poor contact between the probe and the test point interface or internal link failure of the test machine, thereby ensuring the reliability of the wafer probe card self-testing and the product yield.

[0019] Furthermore, when the lead wire is short-circuited inside the testing machine, the measured loop resistance value mainly reflects the contact condition from the probe tip to the test point interface and the resistance of the lead wire, thus eliminating interference from the link between the internal measurement unit of the testing machine and the short-circuit point. By calculating the difference between the loop resistance value and the previously measured average resistance value, and comparing the difference with a preset loop threshold, the root cause of the anomaly can be distinguished: when the difference is small, it indicates that the resistance anomaly mainly stems from poor contact between the probe and the test point interface, such as probe misalignment, insufficient pressure, or failure to effectively pierce the surface oxide layer; while when the difference is significantly large, it indicates that the resistance anomaly mainly comes from the internal link between the testing machine and the short-circuit point, which may be hardware problems such as relay contact oxidation, poor lead wire contact, or loose connectors. Attached Figure Description

[0020] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0021] Figure 1 This is a flowchart illustrating a self-testing method for a wafer probe card in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of another process for the self-testing method of the wafer probe card in an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of a self-testing system for a wafer probe card in an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the structure of a testing machine in an embodiment of the present invention.

[0025] Explanation of the reference numerals in the accompanying drawings: 1. Tester; 2. Probe card; 31. First probe; 32. Second probe; 41. First lead wire; 42. Second lead wire; 5. Wafer; 51. Test point. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0027] Example 1: This example introduces a self-testing method for a wafer probe card.

[0028] The self-test method of the wafer probe card in this embodiment, after each probe group of the probe card 2 contacts each test point 51 of the wafer 5, executes steps SS1 to SS3, referring to... Figure 1 .

[0029] Step SS1: Obtain the average resistance of the probe group and mark the probe group with the average resistance greater than the resistance threshold as an abnormal probe group.

[0030] In application, corresponding to multiple test points 51 on wafer 5, probe card 2 is equipped with multiple probe groups. Each probe group includes at least two probes, and each probe is equipped with a wire. One end of the wire is connected to the corresponding probe, and the other end of the wire is connected to the test machine 1. Further, refer to... Figure 3 Each probe group includes a first probe 31 and a second probe 32. The distance between the first probe 31 and the second probe 32 is less than or equal to the width or diameter of the test point 51, and the first probe 31 and the second probe 32 of the same group simultaneously contact the same test point 51 during needle insertion. In addition, the first probe 31 is equipped with a first lead wire 41, and the second probe 32 is equipped with a second lead wire 42.

[0031] The testing machine 1 can apply voltage or current to the corresponding probes via wires and measure the electrical signals on the probes. (Reference) Figure 4The test machine 1 includes a switch matrix, which is a signal routing network composed of multiple relays arranged in rows and columns. This network routes the voltage source, current source, and measurement unit of the test machine 1 to different test channels. Each relay in the switch matrix can be independently controlled by the test program via a control port. Furthermore, the switch matrix includes different types of relays; for example, it includes short-circuit relays.

[0032] The first input terminal of the short-circuit relay is used to electrically connect to the first wire 41 of the abnormal probe group, and the second input terminal of the short-circuit relay is used to electrically connect to the second wire 42 of the abnormal probe group. Specifically, when the short-circuit relay is closed, the first wire 41 and the second wire 42 are electrically short-circuited at the common output terminal of the short-circuit relay. When the short-circuit relay is open, the first wire 41 and the second wire 42 are independent of each other.

[0033] In practical applications, with the probe group in contact with test point 51 (i.e., probe card 2 remains pressed down and not lifted), a test current is applied between the two probes. The testing machine 1 continuously measures the voltage between the two probes in each probe group multiple times. The sampling frequency is greater than or equal to 10Hz, and the duration is greater than or equal to 1s. Furthermore, according to Ohm's law, the resistance between the two probes is determined using the collected voltage and test current, thereby obtaining a sequence of resistance values ​​for the probe group at multiple time points. For each probe group, the average value of the obtained resistance value sequence is recorded as the average resistance value of the probe group.

[0034] In actual implementation, the resistance threshold is used to distinguish between normal probe groups and abnormal probe groups. Probe groups with an average resistance greater than the resistance threshold are marked as abnormal probe groups, while probe groups with an average resistance less than or equal to the resistance threshold are considered normal probe groups.

[0035] Furthermore, the resistance threshold is determined based on the contact resistance between the probe and test point 51, the probe resistance, the wire resistance, the switching matrix conduction resistance, and the connector contact resistance. The contact resistance between the probe and test point 51 includes the contact resistance between the first probe 31 and test point 51 and the contact resistance between the second probe 32 and test point 51. Further, the resistance threshold can be from 500Ω to 2000Ω. Preferably, the resistance threshold can be 1000Ω.

[0036] Step SS2: Short-circuit each wire corresponding to the abnormal probe group inside the tester 1 to construct a first measurement circuit, and measure the circuit resistance value of the first measurement circuit.

[0037] In application, when the first wire 41 and the second wire 42 corresponding to any abnormal probe group are electrically short-circuited inside the test machine 1: the first input terminal of the short-circuit relay is electrically connected to the first wire 41 of the abnormal probe group, and the second input terminal of the short-circuit relay is electrically connected to the second wire 42 of the abnormal probe group; the first wire 41 and the second wire 42 are electrically short-circuited at the common output terminal of the short-circuit relay, that is, the first wire 41 and the second wire 42 are directly connected inside the test machine 1.

[0038] In practical applications, the common output terminal of the short-circuit relay is used as the short-circuit point. Test current is injected through this point to measure the loop resistance of the first measurement circuit. After obtaining the loop resistance value, a disconnect command is immediately sent to the short-circuit relay, restoring the first conductor 41 and the second conductor 42 to their independent electrical states. Furthermore, the test current is between 1mA and 10mA. Even further, the test current used in each step of this application can be the same to ensure consistent measurement conditions.

[0039] In actual implementation, the current path in the first measurement circuit passes through the following sequence: shorting point, first wire 41, first probe 31, test point 51, second probe 32 and second wire 42. The current flows through the second wire 42 and returns to the shorting point.

[0040] As can be seen, the loop resistance value includes: the resistance of the first wire 41, the resistance of the first probe 31, the contact resistance between the first probe 31 and the test point 51, the bulk resistance of the test point 51, the contact resistance between the second probe 32 and the test point 51, the resistance of the second probe 32, and the resistance of the second wire 42. It is worth noting that, since the shorting point is inside the testing machine 1, the loop resistance value only reflects the resistance of the path from the shorting point outwards to the probe tip and back, and does not include the link resistance from the internal measurement unit of the testing machine 1 to the shorting point.

[0041] Step SS3: Calculate the loop difference between the average resistance value and the loop resistance value: if the absolute value of the loop difference is less than or equal to the loop threshold, the fault type is determined to be poor contact between the probe and the test point 51 interface; if the absolute value of the loop difference is greater than the loop threshold, the fault type is determined to be an internal link fault.

[0042] In application, since the short circuit does not change the physical contact state between the probe and the test point 51 interface, the difference between the average resistance value and the loop resistance value mainly comes from whether or not the internal measurement link resistance of the test machine 1 is included.

[0043] If the absolute value of the loop difference is less than or equal to the loop threshold, it means that the total resistance before and after the short circuit is basically unchanged. This means that the high resistance value in the average resistance mainly comes from the contact resistance between the probe and the test point 51 interface, rather than the internal link of the test machine 1. The fault type is determined to be poor contact between the probe and the test point 51 interface. The corresponding processing measures are then implemented, such as lifting the probe card 2, cleaning the probe, and re-aligning the needle.

[0044] If the absolute value of the loop difference is greater than the loop threshold, it indicates that the resistance decreases significantly after the short circuit, meaning that the average resistance includes the link resistance from the internal measuring unit of tester 1 to the short circuit point. Since the short circuit relay disconnects the link between the internal measuring unit of tester 1 and the short circuit point, the loop resistance value does not include the link resistance. Therefore, when the loop resistance value is significantly less than or equal to the average resistance value, the fault type is determined to be an internal link fault.

[0045] In practical applications, the loop threshold is set to max(average resistance × 10%, 10Ω). Further, the loop threshold is set to 250Ω.

[0046] Example 2: Based on Example 1, this example introduces a self-testing method for a wafer probe card.

[0047] In response to the fault type being an internal link fault, the self-test method of the wafer probe card in this embodiment further includes steps SS4 to SS5 to further determine whether the fault occurs on the link on the first conductor 41 side or the link on the second conductor 42 side.

[0048] Step SS4: Disconnect the electrical short circuit, short-circuit the first lead 41 of the abnormal probe group to the system ground inside the tester 1, inject test current from the second lead 42, and measure the first single-sided short-circuit resistance value; short-circuit the second lead 42 of the abnormal probe group to the system ground inside the tester 1, inject test current from the first lead 41, and measure the second single-sided short-circuit resistance value.

[0049] When applying this method, ensure that the short-circuit relay in step SS2 has been disconnected and that the first wire 41 and the second wire 42 have returned to their independent states.

[0050] In practical applications, the test machine 1 includes a switch matrix, which includes a first grounding relay and a second grounding relay.

[0051] The input terminal of the first grounding relay is used to electrically connect to the first conductor 41, and the output terminal of the first grounding relay is used to electrically connect to the system ground. When the first conductor 41 of the abnormal probe group is short-circuited to the system ground inside the test machine 1: the input terminal of the first grounding relay is electrically connected to the first conductor 41 of the abnormal probe group, and the output terminal of the first grounding relay is electrically connected to the system ground. The second conductor 42 remains independent and is not connected to any additional circuit. The system ground is the zero-potential reference node inside the test machine 1, and the designated test channel can be electrically connected to the system ground through the grounding relays in the switch matrix.

[0052] The measuring unit of tester 1 injects test current through the second lead 42. The current path is as follows: measuring unit of tester 1, second lead 42, second probe 32, test point 51, first probe 31, first lead 41, system ground. Since the first lead 41 is grounded, the first single-sided short-circuit resistance value includes the resistance of the link on the second lead 42 side and the resistance of the link on the first lead 41 side from the tip of the first probe 31 to system ground.

[0053] The input terminal of the second grounding relay is used to electrically connect to the second conductor 42, and the output terminal of the second grounding relay is used to electrically connect to the system ground. When the second conductor 42 of the fault probe group is short-circuited to the system ground inside the testing machine 1: the input terminal of the second grounding relay is electrically connected to the second conductor 42 of the fault probe group, and the output terminal of the second grounding relay is electrically connected to the system ground. The first conductor 41 remains independent and is not connected to any additional circuitry.

[0054] The measuring unit of tester 1 injects test current through the first lead 41. The current path is as follows: tester 1, first lead 41, first probe 31, test point 51, second probe 32, second lead 42, system ground. Since the second lead 42 is grounded, the second single-sided short-circuit resistance value includes the resistance of the link on the first lead 41 side and the resistance of the link on the second lead 42 side from the tip of the second probe 32 to system ground.

[0055] In actual implementation, the first wire 41 side link is a signal path extending from the measurement node corresponding to the first wire 41 inside the test machine 1 along the first wire 41 to the tip of the first probe 31. The second wire 42 side link is a signal path extending from the measurement node corresponding to the second wire 42 inside the test machine 1 along the second wire 42 to the tip of the second probe 32. All wire side links converge in the circuitry of the probe card 2 substrate and are connected to the test point 51.

[0056] Step SS5: Calculate the first difference between the first single-sided short-circuit resistance value and the first line reference value, and the second difference between the second single-sided short-circuit resistance value and the second line reference value, respectively. When the absolute value of the first difference is less than or equal to the first line threshold, and the second difference is greater than the second line threshold, the fault is determined to be located on the link of the second conductor 42 side. When the absolute value of the first difference is greater than the first line threshold, and the second difference is less than or equal to the second line threshold, the fault is determined to be located on the link of the first conductor 41 side. When the absolute value of the first difference is greater than the first line threshold, and the second difference is greater than the second line threshold, the fault is determined to be located in the common part of the links of each conductor side, referencing... Figure 2 .

[0057] In application, the method for determining the first and second line reference values ​​includes: selecting a probe group with an average resistance less than a resistance threshold as the first sample probe group; short-circuiting the first lead 41 of the first sample probe group to the system ground inside the testing machine 1, injecting test current from the second lead 42, measuring the first one-sided short-circuit resistance value, and using the measured first one-sided short-circuit resistance value as the first line reference value; short-circuiting the second lead 42 of the first sample probe group to the system ground inside the testing machine 1, injecting test current from the first lead 41, measuring the second one-sided short-circuit resistance value, and using the measured second one-sided short-circuit resistance value as the second line reference value. Further, the line reference value can be from 1Ω to 10Ω.

[0058] In practical applications, the line threshold is calculated as min(2 × line reference value, line reference value + 10Ω). Furthermore, the line threshold can be between 4Ω and 20Ω.

[0059] In actual implementation, when the first conductor 41 is grounded, the absolute value of the first difference is less than or equal to the first line threshold, indicating that the link on the first conductor 41 side is intact; when the second conductor 42 is grounded, the second difference is greater than the second line threshold, indicating that there is a fault in the link on the second conductor 42 side, so the fault is in the link on the second conductor 42 side.

[0060] When the first conductor 41 is grounded, the absolute value of the first difference is greater than the first line threshold, indicating that there is a fault in the link on the first conductor 41 side; when the second conductor 42 is grounded, the second difference is less than or equal to the second line threshold, indicating that the link on the second conductor 42 side is intact, so the fault is in the link on the first conductor 41 side.

[0061] When the absolute value of the first difference is greater than the first line threshold and the second difference is greater than the second line threshold, the common part of the link on the first conductor 41 side and the link on the second conductor 42 side is investigated first.

[0062] Example 3: Based on Example 2, this example introduces a self-testing method for a wafer probe card.

[0063] When the fault is determined to be located on any conductor-side link, the self-test method of the wafer probe card in this embodiment further includes steps SS6 to SS7 to further locate the fault to a specific segment of the conductor-side link.

[0064] Step SS6: Disconnect the wire corresponding to the wire side link from the system ground inside the tester 1. Following the direction from the measurement end inside the tester 1 to the corresponding probe tip, sequentially short-circuit the multi-level electrically accessible nodes on the wire side link to the system ground, and measure the node resistance value between each electrically accessible node and the system ground.

[0065] When applying this method, ensure that the grounding relay in step SS4 has been disconnected, and that the conductors corresponding to the conductor-side links have been restored to an independent state and are not short-circuited to the system ground.

[0066] In practical applications, the electrically accessible node is an electrical node on the conductor-side link, accessible internally by a switch matrix within the test unit 1, capable of being independently short-circuited to system ground for resistance measurement. Furthermore, the multi-stage electrically accessible node sequentially includes: a first-stage ADC output, a second-stage switch matrix input, a third-stage switch matrix output, and a fourth-stage test unit 1 interface connector. The ADC output is the signal output of the analog-to-digital converter in the measurement unit. The test unit 1 interface connector is the interface connector located on the rear panel of the test unit 1.

[0067] In actual implementation, the test machine 1 includes a switch matrix, which includes a first-level relay, a second-level relay, a third-level relay, and a fourth-level relay.

[0068] The input terminal of the primary relay is used to electrically connect to the output terminal of the ADC, and the output terminal of the primary relay is used to electrically connect to the system ground. When the ADC output terminal is shorted to the system ground: the input terminal of the primary relay is electrically connected to the ADC output terminal, and the output terminal of the primary relay is electrically connected to the system ground; when the short connection between the ADC output terminal and the system ground is broken: the primary relay is disconnected.

[0069] The input terminal of the secondary relay is used to electrically connect to the input terminal of the switch matrix, and the output terminal of the secondary relay is used to electrically connect to the system ground. When the input terminal of the switch matrix is ​​shorted to the system ground: the input terminal of the secondary relay is electrically connected to the input terminal of the switch matrix, and the output terminal of the secondary relay is electrically connected to the system ground; when the short-circuit between the input terminal of the switch matrix and the system ground is disconnected: the secondary relay is disconnected.

[0070] The input terminal of the three-stage relay is used to electrically connect to the output terminal of the switch matrix, and the output terminal of the three-stage relay is used to electrically connect to the system ground. When the output terminal of the switch matrix is ​​short-circuited to the system ground: the input terminal of the three-stage relay is electrically connected to the output terminal of the switch matrix, and the output terminal of the three-stage relay is electrically connected to the system ground; when the short-circuit between the output terminal of the switch matrix and the system ground is disconnected: the three-stage relay is disconnected.

[0071] The input terminal of the four-stage relay is used to electrically connect to the interface connector of the test machine 1, and the output terminal of the four-stage relay is used to electrically connect to the system ground. When the interface connector of the test machine 1 is shorted to the system ground: the input terminal of the four-stage relay is electrically connected to the interface connector of the test machine 1, and the output terminal of the four-stage relay is electrically connected to the system ground; when the interface connector of the test machine 1 is disconnected from the system ground: the four-stage relay is disconnected.

[0072] In some embodiments, relays at corresponding levels are closed sequentially from level 1 to level 4, shorting the corresponding electrically accessible node to system ground. The measurement unit of tester 1 injects test current into the electrically accessible node and measures the node resistance between the electrically accessible node and system ground. After measurement, the relays at the corresponding level are immediately disconnected before proceeding to the next level of measurement.

[0073] Furthermore, the node resistance values ​​include level 1, level 2, level 3, and level 4 node resistance values. The level 1 node resistance value includes the resistance between the ADC output and system ground; the level 2 node resistance value includes the path resistance from the ADC output through internal wires to the switch matrix input; the level 3 node resistance value includes the path resistance from the ADC output through internal wires, switch matrix relay contacts, and to the switch matrix output; and the level 4 node resistance value includes the path resistance from the ADC output through internal wires, switch matrix relay contacts, and internal wiring of the interface connector to the tester 1 interface connector.

[0074] Step SS7: Compare the node resistance values ​​at each level with the corresponding node reference values: If the absolute value of the difference between the node resistance value of the k-th level electrically accessible node and the corresponding node reference value is less than or equal to the node threshold, and the absolute value of the difference between the node resistance value of the (k+1)-th level and the corresponding node reference value is greater than the node threshold, then the fault is determined to be located in the segment between the k-th level electrically accessible node and the (k+1)-th level electrically accessible node. Here, k takes the value 1, 2, 3, or 4.

[0075] When applied, the node threshold is min(2 × node reference value, node reference value + 10Ω).

[0076] In practical applications, the method for determining the node reference value includes: selecting a probe group with an average resistance less than a resistance threshold as the second sample probe group; sequentially shorting the multi-level electrically accessible nodes on the first conductor 41 side link or the second conductor 42 side link in the second sample probe group to the system ground in the direction from the measurement end inside the test machine 1 to the corresponding probe tip, measuring the node resistance value between each electrically accessible node and the system ground; and using the node resistance value between each electrically accessible node and the system ground as the corresponding node reference value. Further, the node reference value corresponding to the node resistance value of the first level is less than or equal to 1Ω; the node resistance value corresponding to the node resistance value of the second level is 1Ω to 5Ω; the node resistance value corresponding to the node resistance value of the third level is 1Ω to 10Ω; and the node resistance value corresponding to the node resistance value of the fourth level is 2Ω to 15Ω.

[0077] In actual implementation, if the absolute value of the difference between the node resistance value of the first stage and the node reference value of the first stage is greater than the corresponding node threshold, the fault is determined to be located before the ADC output terminal, that is, the fault of the analog-to-digital converter in the measurement unit is checked first.

[0078] If the absolute value of the difference between the node resistance value of the kth level and the node reference value of the kth level is less than or equal to the corresponding node threshold, it indicates that the fault point is located after the interface connector of the test machine 1. In other words, the external cable or probe card 2 should be checked first for faults.

[0079] In some embodiments, when there are multiple abnormal probe groups, steps SS2 to SS7 are performed independently on each abnormal probe group in sequence until all abnormal probe groups have completed self-testing.

[0080] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A self-testing method for a wafer probe card, characterized in that, After each probe group of the probe card contacts each test point on the wafer, the self-test method includes: The average resistance of the probe group is obtained, and the probe group with the average resistance greater than the resistance threshold is marked as an abnormal probe group; wherein, each probe group includes at least two probes, each probe is equipped with a wire, one end of the wire is connected to the corresponding probe, and the other end of the wire is connected to the testing machine. The wires corresponding to the abnormal probe group are electrically short-circuited inside the testing machine to construct a first measurement circuit, and the circuit resistance value of the first measurement circuit is measured. Calculate the loop difference between the average resistance value and the loop resistance value: if the absolute value of the loop difference is less than or equal to the loop threshold, the fault type is determined to be poor contact between the probe and the test point interface; if the absolute value of the loop difference is greater than the loop threshold, the fault type is determined to be an internal link fault of the test machine. The testing machine includes a switch matrix, which includes a short-circuit relay; the first input terminal of the short-circuit relay is used to electrically connect to the first wire of the abnormal probe group, and the second input terminal of the short-circuit relay is used to electrically connect to the second wire of the abnormal probe group. When the short-circuit relay is closed, the first wire and the second wire are electrically short-circuited at the common output terminal of the short-circuit relay; and the current path in the first measurement circuit passes sequentially through: the short-circuit point, the first wire, the first probe, the test point, the second probe, and the second wire.

2. The self-testing method for a wafer probe card according to claim 1, characterized in that, When the short-circuit relay is disconnected, the first wire and the second wire are independent of each other.

3. The self-testing method for a wafer probe card according to claim 2, characterized in that, The resistance threshold is determined based on the contact resistance between the probe and the test point, the probe resistance, the wire resistance, the switching matrix conduction resistance, and the connector contact resistance. The circuit threshold is set to max(average resistance × 10%, 10Ω).

4. The self-testing method for a wafer probe card according to claim 1, characterized in that, In response to a fault type of internal link fault in the test machine, the self-test method further includes: Disconnect the electrical short circuit, short-circuit the first lead of the abnormal probe group to the system ground inside the tester, inject test current from the second lead, and measure the first one-sided short-circuit resistance value; short-circuit the second lead of the abnormal probe group to the system ground inside the tester, inject test current from the first lead, and measure the second one-sided short-circuit resistance value. Calculate the first difference between the first single-sided short-circuit resistance value and the first line reference value, and the second difference between the second single-sided short-circuit resistance value and the second line reference value, respectively: When the absolute value of the first difference is less than or equal to the first line threshold and the second difference is greater than the second line threshold, the fault is determined to be located on the second conductor side link. When the absolute value of the first difference is greater than the first line threshold and the second difference is less than or equal to the second line threshold, the fault is determined to be located on the first conductor side link. When the absolute value of the first difference is greater than the first line threshold and the second difference is greater than the second line threshold, the fault is determined to be located in the common part of the links on each conductor side.

5. The self-testing method for a wafer probe card according to claim 4, characterized in that, The testing machine includes a switch matrix, which includes: The first grounding relay has an input terminal for electrically connecting to the first conductor and an output terminal for electrically connecting to the system ground. The second grounding relay has an input terminal for electrically connecting to the second conductor and an output terminal for electrically connecting to the system ground.

6. The self-testing method for a wafer probe card according to claim 4, characterized in that, The first wire side link is a signal path that extends from the measurement node corresponding to the first wire inside the test machine along the first wire to the tip of the first probe; The second wire side link is a signal path that extends from the measurement node corresponding to the second wire inside the test machine along the second wire to the tip of the second probe; Each wire side link converges in the probe card substrate circuit and is then connected to the test point.

7. The self-testing method for a wafer probe card according to claim 4, characterized in that, The method for determining the first line reference value and the second line reference value includes: selecting a probe group with an average resistance value less than a resistance threshold as a first sample probe group; short-circuiting the first lead of the first sample probe group to the system ground inside the testing machine, injecting test current from the second lead, measuring the first one-sided short-circuit resistance value, and using the measured first one-sided short-circuit resistance value as the first line reference value; short-circuiting the second lead of the first sample probe group to the system ground inside the testing machine, injecting test current from the first lead, measuring the second one-sided short-circuit resistance value, and using the measured second one-sided short-circuit resistance value as the second line reference value; The line threshold is defined as min(2 × line reference value, line reference value + 10Ω).

8. The self-testing method for a wafer probe card according to claim 4, characterized in that, When the fault is determined to be located on any conductor-side link, the self-test method further includes: Disconnect the wire corresponding to the wire side link from the system ground inside the tester. Following the direction from the measurement end inside the tester to the corresponding probe tip, sequentially short-circuit the multi-level electrically accessible nodes on the wire side link to the system ground, and measure the node resistance value between each level of electrically accessible node and the system ground. Compare the node resistance values ​​at each level with the corresponding node reference values: If the absolute value of the difference between the node resistance value of the k-th level electrically accessible node and the corresponding node reference value is less than or equal to the node threshold, and the absolute value of the difference between the node resistance value of the (k+1)-th level and the corresponding node reference value is greater than the node threshold, then the fault is determined to be located in the segment between the k-th level electrically accessible node and the (k+1)-th level electrically accessible node.

9. The self-testing method for a wafer probe card according to claim 8, characterized in that, The multi-level electrically accessible nodes sequentially include: an ADC output terminal, a switch matrix input terminal, a switch matrix output terminal, and a test machine interface connector; The testing machine includes a switch matrix, which includes a primary relay, a secondary relay, a tertiary relay, and a quaternary relay. The input terminal of the first-level relay is used to electrically connect to the output terminal of the ADC, and the output terminal of the first-level relay is used to electrically connect to the system ground. The input terminal of the secondary relay is used to electrically connect to the input terminal of the switch matrix, and the output terminal of the secondary relay is used to electrically connect to the system ground. The input terminal of the three-stage relay is used to electrically connect to the output terminal of the switch matrix, and the output terminal of the three-stage relay is used to electrically connect to the system ground. The input terminal of the four-stage relay is used to electrically connect to the test machine interface connector, and the output terminal of the four-stage relay is used to electrically connect to the system ground.

10. The self-testing method for a wafer probe card according to claim 8, characterized in that, The method for determining the node reference value includes: selecting a probe group with an average resistance value less than a resistance threshold as the second sample probe group; sequentially shorting the multi-level electrically accessible nodes on the first wire-side link or the second wire-side link in the second sample probe group to the system ground in the direction from the measurement end inside the test machine to the corresponding probe tip, measuring the node resistance value between each electrically accessible node and the system ground; and using the node resistance value between each electrically accessible node and the system ground as the corresponding node reference value. The node threshold is defined as min(2 × node baseline value, node baseline value + 10Ω).

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