Real-time self-calibrating time-to-digital converter and method

Abstract

The application provides a real-time self-calibration time-to-digital converter and method, and belongs to the technical field of time-to-digital converters.The real-time self-calibration time-to-digital converter comprises: a delay module configured to receive a to-be-tested signal, and perform delay processing on the to-be-tested signal to obtain a delayed to-be-tested signal; a multiplexer configured to respectively receive the delayed to-be-tested signal and a calibration signal, and selectively output the delayed to-be-tested signal or the calibration signal under the control of the to-be-tested signal to obtain an actual output signal; a delay chain comprising a plurality of delay units connected in series, the delay chain being configured to receive the actual output signal and output a plurality of state signals corresponding to the delay units respectively, wherein the state signals are used to represent whether the actual output signal is transmitted to the delay units; and a processor configured to perform data processing on the plurality of state signals to determine a measurement time value corresponding to the to-be-tested signal.

Description

Technical Field

[0001] This invention relates to the field of time-to-digital converter technology, and more specifically, to a real-time self-calibrating time-to-digital converter and method. Background Technology

[0002] Time-to-digital converters (TDCs), as key components for high-precision time measurement, are widely used in industrial automation control, lidar, physics experiments, and quantum communication systems. In these applications, the accuracy of time measurement directly affects the system's performance and reliability.

[0003] Most existing TDC calibration schemes employ offline calibration or static compensation methods. These methods typically perform a calibration before the measurement begins and then rely on the initial calibration parameters throughout the measurement process. This type of calibration is difficult to maintain high accuracy and stability under drastic changes in environmental conditions (such as temperature and voltage). Summary of the Invention

[0004] In view of this, the present invention provides a real-time self-calibrating time-to-digital converter and method.

[0005] One aspect of the present invention provides a real-time self-calibrating time-to-digital converter, comprising: a delay module configured to receive a signal under test and perform delay processing on the signal under test to obtain a delayed signal under test; a multiplexer configured to receive the delayed signal under test and a calibration signal respectively, and selectively output the delayed signal under test or the calibration signal under the control of the signal under test to obtain an actual output signal; a delay chain comprising a plurality of cascaded delay units, the delay chain being configured to receive the actual output signal and output a plurality of status signals corresponding to each of the delay units, wherein the status signals are used to characterize whether the actual output signal is transmitted to the delay unit; and a processor configured to perform data processing on the plurality of status signals to determine a measurement time value corresponding to the signal under test.

[0006] According to an embodiment of the present invention, the multiplexer is configured to output the calibration signal from the output terminal of the multiplexer when the signal under test is at a first level or when the signal under test is not received, and to output the delayed signal under test from the output terminal of the multiplexer when the signal under test is at a second level, so as to obtain the actual output signal.

[0007] According to an embodiment of the present invention, the processor includes: a status readout unit configured to determine a pseudo thermometer code based on a plurality of the aforementioned status signals; a logic operation unit configured to perform a logic operation on the pseudo thermometer code to obtain a pseudo unique thermal code; a decoding unit configured to obtain an actual status code based on the pseudo unique thermal code; and a calculation unit configured to determine a measurement time value corresponding to the measured signal based on the actual status code.

[0008] According to an embodiment of the present invention, the above-mentioned logic operation unit includes a four-input AND gate, which is configured to invert the (i+1)th, (i+2)th, and (i+3)th bits of the pseudo-thermometer code and then perform an AND operation with the i-th bit of the pseudo-thermometer code to obtain the i-th bit of the pseudo-isothermal code, where i is an integer greater than 0.

[0009] According to an embodiment of the present invention, the decoding unit is configured to: filter out bits with a value of 1 from the pseudo-one-hot code to obtain at least one initial target bit; filter out the bit with the lowest preset weight value from the at least one initial target bit to obtain a target bit; set the target bit in the pseudo-one-hot code to 1 and set the remaining bits to 0 to obtain the actual status code corresponding to the pseudo-one-hot code.

[0010] According to an embodiment of the present invention, the above-mentioned calculation unit is configured to: perform data processing on the above-mentioned actual status code to obtain a digital output value corresponding to the above-mentioned actual status code; and determine a measurement time value corresponding to the above-mentioned signal under test based on the above-mentioned digital output value and a preset time resolution value.

[0011] According to an embodiment of the present invention, there are multiple delay chains, each of which is configured to receive the actual output signal, and the processor is configured to determine multiple measurement time values ​​corresponding to each of the delay chains, and calculate an average value of the multiple measurement time values ​​to obtain an average measurement time value.

[0012] According to an embodiment of the present invention, there are multiple measurement time values ​​within one processing cycle of the processor. The processor further includes a first random access memory and a second random access memory. The first random access memory and the second random access memory constitute a ping-pong buffer structure to alternately perform storage and reading operations on the multiple measurement time values.

[0013] Another aspect of the present invention provides a real-time self-calibrating time-to-digital converter method, applied to the time-to-digital converter described above, comprising: receiving a signal to be measured and performing a delay processing on the signal to be measured to obtain a delayed signal to be measured; receiving the delayed signal to be measured and a calibration signal respectively, and selectively deriving the delayed signal to be measured or the calibration signal based on the valid state of the signal to be measured to obtain an actual output signal; receiving the actual output signal using a delay link and outputting multiple status signals; and performing data processing on the multiple status signals to determine a measurement time value corresponding to the signal to be measured.

[0014] According to an embodiment of the present invention, the above-described data processing of multiple state signals to determine the measurement time value corresponding to the signal to be measured includes: determining a pseudo thermometer code based on the multiple state signals; performing logical operations on the pseudo thermometer code to obtain a pseudo unique thermal code; obtaining an actual state code based on the pseudo unique thermal code; and determining the measurement time value corresponding to the signal to be measured based on the actual state code.

[0015] According to embodiments of the present invention, by introducing a delay unit and a multiplexer, when the multiplexer switches from the calibration channel to the measurement channel, the signal under test lags the calibration signal by a fixed time interval. This ensures that the signal under test and the calibration signal in the actual output signal will not collide, enabling the time-to-digital converter to have a highly efficient real-time self-calibration function. It can automatically adapt to environmental changes during the measurement process without manual intervention or external calibration equipment. Subsequently, the processor performs data processing on the actual output signal to determine the measurement time value corresponding to the signal under test, which significantly improves the stability and measurement accuracy of the results during the actual measurement process and reduces maintenance costs. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0017] Figure 1 A schematic diagram of a real-time self-calibrating time-to-digital converter according to an embodiment of the present invention is shown.

[0018] Figure 2 A schematic diagram illustrating the working principle of a processor according to an embodiment of the present invention is shown.

[0019] Figure 3 A flowchart of a real-time self-calibrated time-to-digital conversion method according to an embodiment of the present invention is shown.

[0020] Figure 4 A schematic diagram showing the effect comparison of a real-time self-calibrating time-to-digital converter according to an embodiment of the present Detailed Implementation

[0021] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms "comprising," "including," etc., as used herein indicate the presence of the above-described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0023] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0024] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0025] Existing TDC implementations are primarily based on Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs). Compared to ASICs, FPGA-implemented TDCs offer greater flexibility, lower cost, and shorter development cycles, thus attracting widespread attention in practical applications. However, temperature variations can cause drift in the characteristics of the FPGA's internal delay chain, introducing measurement errors. Furthermore, existing TDC solutions often require manual or external calibration when facing complex and variable measurement environments, a cumbersome and inefficient process.

[0026] Therefore, there is a need to develop a time-to-digital converter (TDC) capable of real-time self-calibration in complex environments. This TDC needs to be able to dynamically adapt to environmental changes to ensure high accuracy and low nonlinearity even under drastic fluctuations in environmental factors such as temperature and voltage. Simultaneously, to meet the demands of high-speed signal measurement, the dead time of the TDC also needs to be as short as possible to improve the overall system efficiency. To address these challenges, this invention proposes a multi-chain real-time self-calibrating time-to-digital converter (TDC) based on FPGA, aiming to overcome the shortcomings of existing technologies and meet the requirements of modern measurement systems for high accuracy, high stability, and real-time calibration.

[0027] Figure 1 A schematic diagram of a real-time self-calibrating time-to-digital converter according to an embodiment of the present invention is shown.

[0028] like Figure 1 As shown, the real-time self-calibrating time-to-digital converter includes a delay module 110, a multiplexer 120, a delay chain 130, and a processor 140.

[0029] The delay module 110 is configured to receive the signal to be tested and perform delay processing on the signal to be tested to obtain the delayed signal to be tested.

[0030] The delay module 110 can integrate timing control components or signal transmission links. After receiving the complete signal under test, it performs uniform timing delay processing on the entire signal under test according to the preset delay parameters. During the processing, the inherent electrical parameters of the signal under test, such as amplitude, waveform shape, and signal frequency, are kept undistorted. Only the output time of the signal under test is changed. The signal is transmitted with a fixed or adjustable duration via the internal signal link. The signal after timing delay is output from the output end of the delay module 110, forming a delayed signal under test with a certain time difference compared to the original signal under test.

[0031] The multiplexer 120 is configured to receive the delayed test signal and the calibration signal respectively, and selectively output the delayed test signal or the calibration signal under the control of the test signal to obtain the actual output signal.

[0032] The multiplexer 120 has two independent signal input ports and one signal output port. The two input ports are respectively connected to the signal output terminal of the delay module 110 and the external calibration signal source, thereby enabling synchronous access to the delayed test signal and the calibration signal generated by the timing delay processing. In addition, the multiplexer 120 is provided with a control signal input terminal, which receives the original test signal. The level transition and timing change of the original test signal itself serve as the trigger for internal channel switching. According to the preset channel switching logic, the multiplexer 120 completes the conduction and shutdown control of the internal path. When switching to the input branch where the delayed test signal is located, the multiplexer 120 outputs the delayed test signal. When switching to the input branch where the calibration signal is located, it outputs the calibration signal. Finally, the actual output signal is continuously output from the common output terminal of the multiplexer 120. By relying on the channel switching method controlled by the test signal in real time, the alternating output of the test signal and the calibration signal is realized.

[0033] The delay chain 130 includes multiple delay units cascaded in sequence. The delay chain 130 is configured to receive the actual output signal and output multiple status signals corresponding to each delay unit. The status signals are used to characterize whether the actual output signal is transmitted to the delay unit.

[0034] In embodiments of the present invention, the delay unit can be a Carry4. Carry4 is originally a dedicated basic circuit module natively integrated into the FPGA, used to help digital circuits perform addition and quickly transmit carry signals. A single module contains four independent signal transmission paths arranged sequentially. After the signal enters from one end of the module, it travels step by step along the four paths. Each small path segment consumes a fixed and uniformly short delay. This stable delay characteristic can be used as a basic benchmark for precise time measurement in a TDC (Time Difference Control). Therefore, Carry4 can serve as the core delay reference for picosecond-level fine-time measurement in an FPGA-based TDC. In the entire measurement architecture of the TDC, multiple Carry4s can be cascaded end-to-end to form a long, continuous path. After the actual output signal is input from the beginning of the entire path, the signal edge slowly moves backward along all the cascaded Carry4s. Each Carry4 corresponds to a very small, fixed time scale. Conventional clocks can only measure large segments of clock cycle duration, providing only rough timing. The entire delay path built using Carry4 modules is specifically designed to fill in the finer details within a single clock cycle that cannot be distinguished by a regular clock. Each Carry4 module has a sampling point at its end. By synchronously capturing the level state (status signal) of each point using a unified standard clock, the exact position of the actual output signal's signal edge within the delay chain can be determined. For example, when the actual output signal reaches the fourth delay unit, the status signals of the first four delay units are all 1, while the status signals of subsequent delay units are all 0 because they have not received the actual output signal. By analyzing the multiple status signals corresponding to each delay unit, time measurement can be achieved.

[0035] Processor 140 is configured to process multiple status signals to determine the measurement time value corresponding to the signal under test.

[0036] Through embodiments of the present invention, by introducing a delay unit and a multiplexer, when the multiplexer switches from the calibration channel to the measurement channel, the signal under test lags the calibration signal by a fixed time interval. This ensures that the signal under test and the calibration signal in the actual output signal will not collide, enabling the time-to-digital converter to have a highly efficient real-time self-calibration function. It can automatically adapt to environmental changes during the measurement process without manual intervention or external calibration equipment. Subsequently, the processor processes the actual output signal to determine the measurement time value corresponding to the signal under test, which significantly improves the stability and measurement accuracy of the results during the actual measurement process and reduces maintenance costs.

[0037] The key to achieving real-time self-calibration is to avoid collisions between the signal under test and the calibration signal. To avoid the above problem, the specific control logic of the multiplexer is as follows: when the signal under test is at the first level, or when no signal under test is received, the calibration signal is exported from the output of the multiplexer. When the signal under test is at the second level, the delayed signal under test is exported from the output of the multiplexer to obtain the actual output signal.

[0038] Specifically, when the signal under test (SUT) is at its first level, or when no SUT is received, it indicates that the SUT is invalid. In this case, the multiplexer opens the calibration channel, and the calibration signal enters the delay chain. The code density continuously accumulates and updates the actual time corresponding to the fine time, achieving efficient real-time self-calibration. When the SUT is at its second level, it indicates that the SUT is valid. In this case, the multiplexer opens the measurement channel, and the signal enters the delay chain after passing through the delay module, thus avoiding collisions between the calibration signal and the SUT. If there is no delay module, when the multiplexer directly switches from the calibration channel to the measurement channel, the SUT will immediately follow the calibration signal into the delay chain. At this time, due to system errors of the multiplexer or other hardware, the SUT and calibration signals are not perfectly connected, but there is some aliasing. In this case, the actual measurement signal output by the multiplexer cannot clearly distinguish the boundary between the SUT and calibration signals, which will affect subsequent data processing and make it impossible to determine the measurement time corresponding to the SUT. Therefore, in order to achieve real-time self-calibration, a delay module is needed to separate the SUT and calibration signals.

[0039] To process multiple state signals to determine the measurement time value corresponding to the signal under test, the processor can be configured as follows: a state readout unit configured to determine a pseudo-thermometer code based on multiple state signals; and a logic operation unit configured to perform logic operations on the pseudo-thermometer code to obtain a pseudo-unique thermal code. The logic operation unit includes a four-input AND gate configured to invert the (i+1)th, (i+2)th, and (i+3)th bits of the pseudo-thermometer code and then perform an AND operation with the (i)th bit of the pseudo-thermometer code to obtain the (i)th bit of the pseudo-unique thermal code, where i is a major constant. The system includes: an integer less than 0; a decoding unit configured to select bits with a value of 1 from the pseudo-one-hot code to obtain at least one initial target bit; select the bit with the lowest preset weight value from the at least one initial target bit to obtain the target bit; set the target bit in the pseudo-one-hot code to 1 and set the remaining bits to 0 to obtain the actual status code corresponding to the pseudo-one-hot code; and a calculation unit configured to perform data processing on the actual status code to obtain a digital output value corresponding to the actual status code; and determine the measurement time value corresponding to the signal under test based on the digital output value and a preset time resolution value.

[0040] In TDC, thermometer code is a specific encoding method used to characterize the actual situation of multiple state signals. For example, when there are 5 delay units in the delay chain, and the actual output signal is transmitted to the 3rd delay unit, the state signals corresponding to the first three delay units are all high level, and the state signals corresponding to the last two delay units are all low level. At this time, the thermometer code can be represented as "11100". Similarly, when the actual output signal is transmitted to the 4th delay unit, the thermometer code can be represented as "11110".

[0041] Generally, since the actual output signal is transmitted sequentially, the thermometer code follows a pattern of consecutive all-1s followed by all-0s. However, during signal transmission, signal level fluctuations can cause a "bubbling" phenomenon, resulting in leading 1s in the thermometer code becoming 0s, forming pseudo-thermometer codes. For example, a normal thermometer code is "11110," but due to the "bubbling" phenomenon, pseudo-thermometer codes such as "10110," "01110," and "10010" may appear. In other words, pseudo-thermometer codes are variant codes obtained by the thermometer code due to device level fluctuations and signal bubbling errors. In practice, the processor needs to process the pseudo-thermometer code to obtain the measurement time.

[0042] In this embodiment of the invention, a pseudo-one-hot code is obtained by performing logical operations on the pseudo thermometer code using a four-input AND gate in the logic operation unit, thereby eliminating the "bubbling" effect. Specifically, for the pseudo thermometer code "101011000000", the 1s in the second and fourth bits become 0s due to level fluctuations. If conventional processing logic is used, it would be assumed that the actual output signal is only transmitted to the first delay unit. However, by performing bit-by-bit operations on the pseudo thermometer code "101011000000" using the four-input AND gate in this embodiment of the invention, the pseudo-one-hot code "000001000000" can be finally obtained, thus clearly indicating that the actual output signal is transmitted to the sixth delay unit. For ease of understanding, the four-input AND gate can be regarded as a lookup device for the "1000" format data in the pseudo thermometer code. At the same time, it should be noted that in actual practice, there will not be a situation where there are three consecutive bubbles, that is, there will not be a situation where the pseudo thermometer code is in the form of "110001000" but the actual output signal has been transmitted to the sixth delay unit.

[0043] Furthermore, since the output signal may simultaneously contain both the measured signal and the calibration signal, a decoding unit is needed to process the pseudo-one-hot code to obtain the actual status code. For example, when the calibration channel is closed and the measurement channel is open, a few low-level signals will enter the delay chain, followed by the measured signal. This will cause the pseudo thermometer code to appear in the form of "1111110000111110", meaning that the pseudo thermometer code contains both the measured signal and the calibration signal. Due to the delay module, the measured signal lags behind the calibration signal. Therefore, the measured signal must be in a lower bit position relative to the calibration signal. Thus, bits 1 to 6 represent the measured signal, and bits 11 to 15 represent the calibration signal. After processing the pseudo-thermometer code "1111110000111110", we obtain the pseudo-one-hot code "0000010000000010". Since the pseudo-one-hot code contains two 1s, we need to extract the sixth 1 bit based on the least significant bit priority principle, keep it unchanged, and set the remaining bits to 0 to obtain the actual status code "0000010000000000". This actual status code truly represents which delay unit the measured signal has passed through. This decoding unit not only ensures the correctness of the output value but also reduces the dead time of the TDC through a pipelined structure, improving the overall efficiency of the system.

[0044] Since the 1 is in the 6th position in the actual status code "0000010000000000", the digital output value obtained by the calculation unit after processing the actual status code is 6. Multiplying the digital output value 6 with the preset time resolution value, the measurement time value corresponding to the signal under test can be determined. The time resolution value is the time taken for the actual output signal to pass through each delay unit.

[0045] Figure 2 A schematic diagram illustrating the working principle of a processor according to an embodiment of the present invention is shown.

[0046] like Figure 2 As shown, both the pseudo-thermometer code and the pseudo-isothermal code are 48 bits. After processing the thermometer code using a four-input AND gate "1000", the pseudo-isothermal code is obtained. Two bits in the pseudo-isothermal code are set to 1. The pseudo-isothermal code is detected using three value detection units. The first detection result is negative, while the latter two result are positive. Subsequently, the discrimination and selection module makes a judgment to obtain the codes corresponding to the signal to be measured and the calibration signal. Finally, the low-order priority decoder is used to determine the low-order signal to be measured, thus obtaining the actual status code.

[0047] In conventional TDC (Time-to-Digital Converter) schemes, the processor processes data from multiple state signals of a delay chain to obtain the measurement time corresponding to that delay chain. Furthermore, multiple delay chains can be configured to operate in parallel, each receiving the same actual output signal. The processor processes data from different delay chains to obtain multiple measurement time values ​​corresponding to each delay chain. The average of these multiple measurement time values ​​is then calculated as the final output. By processing the signal independently for each chain and averaging the results from multiple measurements, the impact of environmental factors on TDC is reduced. Similarly, multiple measurements can be taken on a single delay chain, and the average of the results can be calculated. For example, the real-time self-calibrating time-to-digital converter of this invention may include n delay chains, each measuring the signal under test m times, resulting in n×m measurement time values. The average of these n×m actual measurement time values ​​is then calculated. The final output result is obtained by calculating the average value. . It can be expressed by the following formula:

[0048] (1).

[0049] Where t(m, n) is the original measurement time value, and Tclk is the reference clock period. For the fixed bias delay of the m-th delay chain itself, T OSC (m, n) represents the delay deviation of the m-th delay chain during the nth measurement.

[0050] According to an embodiment of the present invention, multiple time values ​​are measured within one processing cycle of the processor. The processor further includes a first random access memory and a second random access memory, which constitute a ping-pong buffer structure to alternately perform storage and retrieval operations on the multiple measured time values.

[0051] To achieve efficient real-time self-calibration, a ping-pong buffer structure can be constructed using two symmetrical BRAMs (Block Random Access Memory). These two symmetrical BRAMs are BRAM1 and BRAM2. When the calculated measurement time value is stored in BRAM1, BRAM2 outputs the previously stored measurement time value. The next time, the measurement time value is stored in BRAM2, and BRAM1 outputs the previously stored measurement time value; this storage and output process alternates. This ping-pong measurement time value structure not only reduces dead time but also ensures that code density is accumulated using the gap time between measured signals and the fine time of the measured signals without increasing the measurement dead time, thus achieving real-time updates of the true time. Even under drastic changes in ambient temperature, this structure guarantees the reliability of the measured values, enabling the TDC to maintain high accuracy and low nonlinearity measurement performance in various complex environments.

[0052] One calibration requires 8,400,000 clock cycles, with an equivalent update time of 0.048 seconds, far exceeding the rate of change in ambient temperature. Alternating storage and output allows for code density accumulation and real-time self-calibration during the intervals between measured signals without increasing the measurement dead time, thus improving system measurement efficiency. In embodiments of this invention, a code-by-code calibration method can be used. After obtaining the number of occurrences of each fine count, the actual time corresponding to the fine count is calculated using the following formula. This scheme is simple, effective, and easily integrated onto a chip. The formula for the calibrated actual time is as follows:

[0053] (2).

[0054] in, Let i be the actual time corresponding to the i-th fine count. Let i be the number of occurrences of the i-th sub-count. To achieve the maximum value of the fine count, The clock cycle.

[0055] It should be noted that the ping-pong calibration structure includes two or more symmetrical BRAMs to achieve ping-pong calibration, reduce dead time, and improve calibration efficiency. Simultaneously, the calibration structure can be based on other memory structures, such as Read-Only Memory (ROM), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM) or Flash Memory, and other types of memory structures and any combination thereof. Furthermore, the aforementioned real-time self-calibrating time-to-digital converter can also be implemented based on other FPGA models or other microprocessors, such as microcontrollers or Application-Specific Integrated Circuits (ASICs). The multiplexer can also employ one or more input channels for the signal under test and one or more input channels for the calibration signal.

[0056] Figure 3 A flowchart of a real-time self-calibrated time-to-digital conversion method according to an embodiment of the present invention is shown.

[0057] like Figure 3 As shown, the method includes operations S310~S340.

[0058] In operation S310, the signal to be tested is received and the signal to be tested is delayed to obtain the delayed signal to be tested.

[0059] In operation S320, the delayed test signal and the calibration signal are received respectively, and based on the valid state of the test signal, the delayed test signal or the calibration signal is selectively exported to obtain the actual output signal.

[0060] During operation of S330, the actual output signal is received using a delayed link, and multiple status signals are output.

[0061] In operation S340, multiple status signals are processed to determine the measurement time value corresponding to the signal to be measured.

[0062] In one specific embodiment of the present invention, multiple state signals are processed to determine the measurement time value corresponding to the signal to be measured. Specifically, this can be achieved by the following method: determining a pseudo thermometer code based on multiple state signals; performing logical operations on the pseudo thermometer code to obtain a pseudo unique thermal code; obtaining the actual state code based on the pseudo unique thermal code; and determining the measurement time value corresponding to the signal to be measured based on the actual state code.

[0063] To test the performance of the real-time self-calibrating time-to-digital converter in this embodiment of the invention, the time measurement performance of a conventional time-to-digital converter and the real-time self-calibrating time-to-digital converter in this embodiment of the invention were also compared. Figure 4 A schematic diagram showing the effect comparison of a real-time self-calibrating time-to-digital converter according to an embodiment of the present

[0064] like Figure 4 As shown, the horizontal axis represents the temperature range, and the vertical axis represents the root mean square of time jitter, used to characterize the temperature resistance of the time-to-digital converter. Figure 4 As shown, the conventional time-to-digital converter corresponds to Figure 4 In the uncalibrated case, the root mean square fluctuation range of time jitter is relatively large. The real-time self-calibrating time-to-digital converter of this embodiment corresponds to... Figure 4The real-time calibration results show that, within a temperature range of -50℃ to 100℃, the root mean square fluctuation of the time jitter is between [3.2499, 3.6462], with a fluctuation of only 0.3963 ps. This demonstrates that the real-time self-calibrating time-to-digital converter of this embodiment exhibits remarkable resistance to temperature variations. Therefore, the real-time self-calibrating time-to-digital converter of this embodiment has broad application prospects in the field of high-precision time measurement, and is particularly suitable for complex environments with drastic temperature changes.

[0065] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of a real-time self-calibrating time-to-digital converter according to various embodiments of the invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. Furthermore, in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Moreover, each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0066] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0067] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A real-time self-calibrating time-to-digital converter, characterized in that, include: The delay module is configured to receive the signal to be tested and perform delay processing on the signal to be tested to obtain a delayed signal to be tested; A multiplexer is configured to receive the delayed test signal and the calibration signal respectively, and under the control of the test signal, selectively output the delayed test signal or the calibration signal to obtain an actual output signal; A delay chain includes multiple delay units cascaded in sequence. The delay chain is configured to receive the actual output signal and output multiple status signals corresponding to each delay unit. The status signals are used to characterize whether the actual output signal is transmitted to the delay unit. The processor is configured to perform data processing on a plurality of the status signals to determine a measurement time value corresponding to the signal to be measured.

2. The time-to-digital converter according to claim 1, characterized in that, The multiplexer is configured to output the calibration signal from the output of the multiplexer when the signal under test is at a first level, or when the signal under test is not received, and to output the delayed signal under test from the output of the multiplexer when the signal under test is at a second level, so as to obtain the actual output signal.

3. The time-to-digital converter according to claim 1, characterized in that, The processor includes: The status readout unit is configured to determine the pseudo thermometer code based on multiple status signals; The logic operation unit is configured to perform logic operations on the pseudo thermometer code to obtain the pseudo unique thermal code. The decoding unit is configured to obtain the actual status code based on the pseudo-one-hot code; The calculation unit is configured to determine the measurement time value corresponding to the signal under test based on the actual status code.

4. The time-to-digital converter according to claim 3, characterized in that, The logic operation unit includes: A four-input AND gate is configured to invert the (i+1)th, (i+2)th, and (i+3)th bits of the pseudo-thermometer code and then perform an AND operation with the (i)th bit of the pseudo-thermometer code to obtain the (i)th bit of the pseudo-unithermal code, where i is an integer greater than 0.

5. The time-to-digital converter according to claim 3, characterized in that, The decoding unit is configured as follows: In the pseudo-one-hot code, bits with a value of 1 are selected to obtain at least one initial target bit. The target bit is obtained by selecting the bit with the lowest preset weight value from the at least one initial target bit. Set the target bit in the pseudo-one-hot code to 1 and set all other bits to 0 to obtain the actual status code corresponding to the pseudo-one-hot code.

6. The time-to-digital converter according to claim 3, characterized in that, The computing unit is configured as follows: The actual status code is processed to obtain a digital output value corresponding to the actual status code; Based on the digital output value and the preset time resolution value, the measurement time value corresponding to the signal under test is determined.

7. The time-to-digital converter according to claim 1, characterized in that, There are multiple delay chains, each of which is configured to receive the actual output signal. The processor is configured to determine multiple measurement time values ​​corresponding to each delay chain and calculate an average value of the multiple measurement time values ​​to obtain an average measurement time value.

8. The time-to-digital converter according to claim 1, characterized in that, The measured time values ​​are multiple within one processing cycle of the processor, and the processor further includes: A first random access memory and a second random access memory, which together form a ping-pong buffer structure to alternately perform storage and retrieval operations on multiple measured time values.

9. A real-time self-calibrating time-to-digital conversion method, applied to the time-to-digital converter as described in any one of claims 1-8, characterized in that, include: Receive the signal to be tested and perform a delay processing on the signal to be tested to obtain a delayed signal to be tested; The delayed test signal and the calibration signal are received respectively, and based on the valid state of the test signal, the delayed test signal or the calibration signal is selectively exported to obtain the actual output signal; The actual output signal is received using a delayed link, and multiple status signals are output. Data processing is performed on multiple state signals to determine the measurement time value corresponding to the signal to be measured.

10. The time-to-digital conversion method according to claim 9, characterized in that, The step of processing multiple state signals to determine the measurement time value corresponding to the signal to be measured includes: Based on multiple state signals, the pseudo thermometer code is determined; Perform logical operations on the pseudo thermometer code to obtain the pseudo unique thermometer code; Based on the pseudo-one-hot code, the actual status code is obtained; Based on the actual status code, the measurement time value corresponding to the signal to be measured is determined.

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