Data fitting-based electronic timepiece timing accuracy calibration method and system

Abstract

The application relates to the technical field of electronic clocks, and particularly discloses an electronic clock timing precision calibration method and system based on data fitting, which comprises the following steps: based on the time sequence characteristics of an electronic clock, mapping temperature difference to the extreme value offset of a jitter amplitude distribution set, and solving a sensorless temperature estimation; combining the nominal period of an electronic clock real-time pulse segment sequence, matching and calibrating the temperature estimation, and establishing a temperature-offset mapping table; again carrying out temperature difference mapping on a current pulse segment to obtain a real-time temperature estimation, positioning the interval based on the mapping table to obtain an interval reference offset; according to the reference offset, configuring a compensation step length for the jitter amplitude, generating a dynamic compensation step length, adjusting the cumulative count value phase to obtain a single-period refresh value; taking the single-period refresh value as a correction reference, carrying out time sequence calibration on subsequent pulses of the electronic clock, and outputting the final working signal of the electronic clock; and the application can improve the timing precision and temperature tracking response capability of the electronic clock under the condition of no external temperature sensor.

Description

Technical Field

[0001] This invention relates to the field of electronic clock and watch technology, and in particular to a method and system for calibrating the timing accuracy of electronic clocks and watches based on data fitting. Background Technology

[0002] In existing technologies, the accuracy compensation of electronic clocks largely relies on external temperature sensors to collect ambient temperature data, combined with the crystal oscillator frequency-temperature characteristic curve to perform lookup interpolation compensation. This method cannot dynamically correct the thermal conduction delay between the sensor and the crystal oscillator, making it difficult to track temperature changes in real time under rapid temperature variations. The compensation action is delayed, easily causing the accumulation of pulse edge offset, resulting in excessive timing errors. Furthermore, external sensors are significantly limited by power consumption and size, and in miniaturized, sealed electronic clock structures, they also face challenges such as insufficient installation space and high cost.

[0003] In existing technologies, sensorless temperature estimation often employs a linear mapping between extreme value offsets and temperature, lacking a time-weighted attenuation fusion mechanism for jitter amplitude distribution extreme value offsets. This makes it impossible to distinguish between historical extreme values ​​and instantaneous jitter weights, leading to estimation spikes at temperature change inflection points. Furthermore, the absence of sliding window midpoint noise reduction makes it difficult to suppress random jitter interference, resulting in large dispersion in the temperature-offset mapping table, reducing the accuracy of compensation step size assignment, and hindering closed-loop phase adjustment and period refresh. Therefore, there is an urgent need to develop a calibration scheme that, through the coordinated application of temperature difference mapping, interval positioning, and phase adjustment, solves the problems of inaccurate sensorless temperature measurement and compensation lag, thereby improving the full-temperature-range timing accuracy and temperature change response speed of electronic clocks. Summary of the Invention

[0004] This invention provides a method and system for calibrating the timing accuracy of electronic clocks and watches based on data fitting, in order to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides a method for calibrating the timing accuracy of electronic clocks based on data fitting, comprising:

[0006] A1: Based on the timing characteristics of the electronic clock, the extreme value offset of the jitter amplitude distribution set in the electronic clock is mapped by temperature difference to obtain the sensorless temperature estimate of the electronic clock.

[0007] A2: Based on the nominal period of the real-time pulse segment sequence in the electronic clock, the sensorless temperature estimate is matched and calibrated to obtain the temperature-offset mapping table of the sensorless temperature estimate;

[0008] A3: Repeatedly perform temperature difference mapping on the current pulse segment of the electronic clock to obtain the real-time temperature estimate of the current pulse segment, and perform interval positioning on the real-time temperature estimate based on the temperature-offset mapping table to obtain the interval reference offset of the current pulse segment.

[0009] A4: Based on the interval reference offset, the jitter amplitude of the current pulse segment is compensated by a step size to obtain the real-time dynamic compensation step size of the current pulse segment, and the cumulative count value of the electronic clock is phase-adjusted to obtain the single-cycle refresh value of the electronic clock.

[0010] A5: Based on the single-cycle refresh value, the subsequent pulses of the electronic clock are time-calibrated to obtain the final signal of the electronic clock.

[0011] In a preferred embodiment, the step of performing temperature difference mapping on the extreme value offset of the jitter amplitude distribution set of the electronic clock based on the timing characteristics of the electronic clock to obtain the sensorless temperature estimate of the electronic clock includes:

[0012] The edge triggering timing of the original pulse sequence of the electronic clock is obtained by performing time-domain differential mapping on the original pulse sequence;

[0013] Based on the nominal periodic trigger time of the electronic clock, the difference of the edge trigger timing is extracted to obtain the instantaneous offset of the edge trigger timing.

[0014] The instantaneous offset is dynamically captured to obtain extreme value candidate pairs of the edge-triggered timing, and the extreme value candidate pairs include the maximum positive offset and the maximum negative offset;

[0015] The maximum positive offset and the maximum negative offset are fused by time-weighted attenuation to obtain the extreme offset of the jitter amplitude distribution set.

[0016] In a preferred embodiment, the step of performing temperature difference mapping on the extreme value offset of the jitter amplitude distribution set of the electronic clock based on the time-series characteristics of the electronic clock to obtain the sensorless temperature estimate of the electronic clock further includes:

[0017] Based on the timing characteristics of the electronic clock, the extreme value offset is located by neighborhood matching to obtain the temperature candidate range of the extreme value offset.

[0018] Based on the temperature values ​​of the feature points at both ends of the temperature candidate interval, linear weighted interpolation is performed on the extreme value offset to obtain the initial temperature estimate of the extreme value offset.

[0019] Based on the initial temperature estimate sequence of the electronic clock, a sliding window value is selected for the initial temperature estimate to obtain the sensorless temperature estimate of the electronic clock. The calculation formula for the sensorless temperature estimate is as follows:

[0020] ;

[0021] in, For the sensorless temperature estimation, The reference temperature for the electronic clock. The temperature scale factor is the time series characteristic. It is the inverse error function. This is the extreme value offset. The extreme value offset is the minimum value within the statistical period. The extreme value offset is the maximum value within the statistical period. These are the preset nonlinear correction coefficients. The second-order time derivative of the extreme value offset is... With natural constant An exponential function with base 0.

[0022] In a preferred embodiment, the step of performing time-weighted attenuation fusion on the maximum positive offset and the maximum negative offset to obtain the extreme value offset of the jitter amplitude distribution set includes:

[0023] Based on the preset duration level, the maximum positive offset and the maximum negative offset are shifted down to obtain the positive offset value and negative offset value of the jitter amplitude distribution set;

[0024] The positive and negative offset values ​​are stripped to obtain the net offset value of the jitter amplitude distribution set;

[0025] The net offset value is truncated by half-wave to obtain the unidirectional offset amplitude of the jitter amplitude distribution set;

[0026] The unidirectional offset amplitude is latched as the extreme offset of the jitter amplitude distribution set.

[0027] In a preferred embodiment, the step of matching and calibrating the sensorless temperature estimate based on the nominal period of the real-time pulse segment sequence in the electronic clock to obtain a temperature-offset mapping table for the sensorless temperature estimate includes:

[0028] Based on the sensorless temperature estimate and the nominal period of the real-time pulse segment sequence in the electronic clock, the period deviation of the real-time pulse segment sequence is sampled to obtain the measured offset sequence of the real-time pulse segment sequence.

[0029] The measured offset sequence is sorted by temperature dependence to obtain the offset sequence of the measured offset sequence;

[0030] The offset sequence is segmented and aggregated, and the measured offsets falling within the same temperature range are arithmetically averaged and combined to obtain the representative offset of the offset sequence.

[0031] Based on the midpoint value of the temperature range of the electronic clock, the representative offset is discretely paired and bound to obtain the temperature-offset mapping table of the sensorless temperature estimate.

[0032] In a preferred embodiment, the step of repeatedly performing temperature difference mapping on the current pulse segment of the electronic clock to obtain a real-time temperature estimate of the current pulse segment, and then, based on the temperature-offset mapping table, performing interval positioning on the real-time temperature estimate to obtain the interval reference offset of the current pulse segment, includes:

[0033] Differential stripping is performed on the current pulse segment of the electronic clock to obtain the instantaneous periodic jitter sequence of the current pulse segment;

[0034] Based on the aforementioned temporal characteristics, the instantaneous periodic jitter sequence is reverse-matched and located to obtain the real-time temperature estimate of the current pulse segment.

[0035] Based on the temperature-offset mapping table, an interval search is performed on the real-time temperature estimate to obtain the mapping interval of the real-time temperature estimate;

[0036] Boundary locking is performed on the mapping interval to obtain the lower limit temperature node and the upper limit temperature node of the mapping interval;

[0037] Offsets are read for the lower temperature node and the upper temperature node respectively to obtain the lower reference offset and upper reference offset of the mapping interval;

[0038] The lower limit reference offset and the upper limit reference offset are weighted and fused to obtain the interval reference offset of the current pulse segment.

[0039] In a preferred embodiment, the step of assigning a compensation step size to the jitter amplitude of the current pulse segment based on the interval reference offset to obtain the real-time dynamic compensation step size of the current pulse segment, and performing phase adjustment on the cumulative count value of the electronic clock to obtain the single-cycle refresh value of the electronic clock, includes:

[0040] Edge-triggered sampling is performed on the jitter amplitude of the current pulse segment to obtain the instantaneous extreme value of the jitter amplitude;

[0041] Based on the interval reference offset, the instantaneous extreme values ​​are compared differentially to obtain the dynamic error component of the jitter amplitude;

[0042] The dynamic error components are integrated and accumulated to obtain the cumulative phase deviation of the dynamic error components;

[0043] Based on the accumulated phase deviation, the local oscillator of the electronic clock is adjusted by frequency division ratio to obtain the real-time dynamic compensation step size of the current pulse segment.

[0044] In a preferred embodiment, the step of assigning a compensation step size to the jitter amplitude of the current pulse segment based on the interval reference offset to obtain the real-time dynamic compensation step size of the current pulse segment, and performing phase adjustment on the cumulative count value of the electronic clock to obtain the single-cycle refresh value of the electronic clock, further includes:

[0045] Based on the real-time dynamic compensation step size, the cumulative count value of the electronic clock is iteratively accumulated to obtain the accumulated intermediate value of the cumulative count value;

[0046] The overflow truncation of the accumulated intermediate quantity is used to obtain the modulus constraint margin of the accumulated count value;

[0047] The register is overwritten with the modulus constraint margin to obtain the single-cycle refresh value of the electronic clock.

[0048] In a preferred embodiment, the step of timing calibration of subsequent pulses of the electronic clock based on the single-cycle refresh value to obtain the final signal of the electronic clock includes:

[0049] Based on the single-cycle refresh value, the frequency division coefficient is loaded onto the output frequency divider of the electronic clock to obtain the calibrated frequency division ratio of the output frequency divider;

[0050] Based on the calibrated frequency division ratio, the high-frequency reference source of the electronic clock is divided by pulse frequency to obtain the gated pulse beat sequence of the high-frequency reference source;

[0051] Based on the edge reference of the single-cycle refresh value, the gated pulse beat sequence is aligned by rising edge triggering to obtain the phase synchronization pulse train of the electronic clock.

[0052] The phase synchronization pulse train is buffered at the drive stage to obtain the final signal of the electronic clock.

[0053] To address the aforementioned problems, this invention also provides an electronic clock and watch timing accuracy calibration system based on data fitting, the system comprising:

[0054] The temperature difference mapping estimation module is used to perform temperature difference mapping on the extreme value offset of the jitter amplitude distribution set of the electronic clock based on the time sequence characteristics of the electronic clock, so as to obtain the sensorless temperature estimation of the electronic clock.

[0055] The temperature-offset calibration module is used to match and calibrate the sensorless temperature estimate based on the nominal period of the real-time pulse segment sequence in the electronic clock, and obtain the temperature-offset mapping table of the sensorless temperature estimate.

[0056] The temperature range positioning module is used to repeatedly perform temperature difference mapping on the current pulse segment of the electronic clock to obtain the real-time temperature estimate of the current pulse segment, and perform range positioning on the real-time temperature estimate based on the temperature-offset mapping table to obtain the range reference offset of the current pulse segment.

[0057] The dynamic compensation phase adjustment module is used to assign a compensation step size to the jitter amplitude of the current pulse segment based on the interval reference offset, so as to obtain the real-time dynamic compensation step size of the current pulse segment, and to adjust the phase of the cumulative count value of the electronic clock to obtain the single-cycle refresh value of the electronic clock.

[0058] The timing calibration output module is used to perform timing calibration on subsequent pulses of the electronic clock based on the single-cycle refresh value, so as to obtain the final signal of the electronic clock.

[0059] Compared with the prior art, the present invention has the following beneficial effects:

[0060] 1. This invention significantly improves the accuracy and stability of full-temperature-range temperature estimation without relying on an external temperature sensor. By performing time-domain differential mapping and dynamic extreme value capture on the original pulse sequence, and introducing a time-weighted attenuation fusion mechanism to shift the maximum positive and negative offset down by level, stripping differences, and retaining half-waves, it effectively suppresses the residual interference of historical jitter extreme values ​​on the current temperature estimate and solves the problem of estimate jumps at temperature change inflection points. By employing an inverse error function combined with a nonlinear temperature difference mapping formula based on the second-order time derivative and the selection of the sliding window value, it accurately fits the nonlinear region of the quartz crystal thermal frequency characteristic curve, eliminates measurement noise introduced by random jitter, and greatly improves the consistency of the initial temperature estimate sequence, providing low-dispersion, high-confidence input data for constructing the temperature-offset mapping table.

[0061] 2. This invention also significantly enhances timing tracking capability and phase synchronization accuracy under rapid temperature change conditions through a temperature-offset mapping table and closed-loop dynamic compensation. Real-time temperature estimates are obtained by reverse matching and positioning the current pulse segment. Interval reference offsets are obtained using interval retrieval and weighted fusion. Then, real-time dynamic compensation step sizes are generated through instantaneous extreme value sampling, differential comparison, and integral accumulation. Finally, overflow truncation and register overwriting of the accumulated count value complete a single-cycle refresh, overcoming compensation lag caused by thermal conduction delays. Attached Figure Description

[0062] Figure 1This is a flowchart illustrating a data fitting-based method for calibrating the timing accuracy of electronic clocks according to an embodiment of the present invention.

[0063] Figure 2 A functional block diagram of an electronic clock and watch timing accuracy calibration system based on data fitting provided in an embodiment of the present invention;

[0064] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0065] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0066] This application provides a method for calibrating the timing accuracy of electronic clocks based on data fitting. The execution entity of this method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the method can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cluster of cloud servers. The server can be an independent server or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0067] Reference Figure 1 The diagram shown is a flowchart illustrating a data-fit-based electronic clock timing accuracy calibration method according to an embodiment of the present invention. In this embodiment, the data-fit-based electronic clock timing accuracy calibration method includes:

[0068] A1: Based on the timing characteristics of the electronic clock, the extreme value offset of the jitter amplitude distribution set in the electronic clock is mapped by temperature difference to obtain the sensorless temperature estimate of the electronic clock.

[0069] In this embodiment of the invention, the step of performing temperature difference mapping on the extreme value offset of the jitter amplitude distribution set of the electronic clock based on the time-series characteristics of the electronic clock to obtain the sensorless temperature estimate of the electronic clock includes:

[0070] The edge triggering timing of the original pulse sequence of the electronic clock is obtained by performing time-domain differential mapping on the original pulse sequence;

[0071] Based on the nominal periodic trigger time of the electronic clock, the difference of the edge trigger timing is extracted to obtain the instantaneous offset of the edge trigger timing.

[0072] The instantaneous offset is dynamically captured to obtain extreme value candidate pairs of the edge-triggered timing, and the extreme value candidate pairs include the maximum positive offset and the maximum negative offset;

[0073] The maximum positive offset and the maximum negative offset are fused by time-weighted attenuation to obtain the extreme offset of the jitter amplitude distribution set.

[0074] The method of performing temperature difference mapping on the extreme value offset of the jitter amplitude distribution set of the electronic clock based on the time-series characteristics of the electronic clock to obtain the sensorless temperature estimate of the electronic clock also includes:

[0075] Based on the timing characteristics of the electronic clock, the extreme value offset is located by neighborhood matching to obtain the temperature candidate range of the extreme value offset.

[0076] Based on the temperature values ​​of the feature points at both ends of the temperature candidate interval, linear weighted interpolation is performed on the extreme value offset to obtain the initial temperature estimate of the extreme value offset.

[0077] Based on the initial temperature estimate sequence of the electronic clock, a sliding window value is selected for the initial temperature estimate to obtain the sensorless temperature estimate of the electronic clock. The calculation formula for the sensorless temperature estimate is as follows:

[0078] ;

[0079] in, For the sensorless temperature estimation, The reference temperature for the electronic clock. The temperature scale factor is the time series characteristic. It is the inverse error function. This is the extreme value offset. The extreme value offset is the minimum value within the statistical period. The extreme value offset is the maximum value within the statistical period. These are the preset nonlinear correction coefficients. The second-order time derivative of the extreme value offset is... With natural constant An exponential function with base 0.

[0080] The step of performing time-weighted attenuation fusion on the maximum positive offset and the maximum negative offset to obtain the extreme value offset of the jitter amplitude distribution set includes:

[0081] Based on the preset duration level, the maximum positive offset and the maximum negative offset are shifted down to obtain the positive offset value and negative offset value of the jitter amplitude distribution set;

[0082] The positive and negative offset values ​​are stripped to obtain the net offset value of the jitter amplitude distribution set;

[0083] The net offset value is truncated by half-wave to obtain the unidirectional offset amplitude of the jitter amplitude distribution set;

[0084] The unidirectional offset amplitude is latched as the extreme offset of the jitter amplitude distribution set.

[0085] Electronic clocks generate a continuous sequence of raw pulses during operation, with each pulse representing one clock oscillation. Time-domain differential mapping refers to capturing the rising and falling edges of each pulse signal in the raw pulse sequence along the time axis. The rising edge is the instant a pulse transitions from a low level to a high level, and the falling edge is the instant a pulse transitions from a high level to a low level. Using a hardware comparator or level-triggered circuit, each pulse edge is converted into a brief trigger pulse. These trigger pulses are arranged in chronological order, forming an edge-triggered timing sequence. This edge-triggered timing sequence precisely records the times when all transitions occur in the raw pulse sequence.

[0086] The nominal cycle trigger time is the theoretical time at which an electronic clock should produce an edge under ideal temperature and error-free conditions. This series of theoretical times is read from the electronic clock's internal registers or factory calibration records. Then, the time when each actual edge occurs in the edge trigger sequence is subtracted from the corresponding nominal cycle trigger time. The time difference obtained from the subtraction operation is called the instantaneous offset. If the actual edge occurs later than the theoretical time, the instantaneous offset is positive; if it occurs earlier than the theoretical time, the instantaneous offset is negative. Each edge corresponds to one instantaneous offset.

[0087] Dynamic extreme value capture refers to continuously comparing newly generated instantaneous offsets with the currently saved maximum and minimum values ​​within a continuous time window. During initialization, the first instantaneous offset is simultaneously set as both a candidate maximum and a candidate minimum. Subsequently, each new instantaneous offset is compared with a candidate maximum; if larger, the candidate maximum is replaced; similarly, it is compared with a candidate minimum; if smaller, the candidate minimum is replaced. The time window is set to a length according to the actual operating requirements of the electronic clock, for example, covering hundreds of pulse cycles. When the time window ends, the currently captured candidate maximum and candidate minimum are used as the maximum positive offset and maximum negative offset, respectively; these two offsets together constitute an extreme value candidate pair.

[0088] Time-weighted attenuation fusion first relies on preset duration levels. Duration levels are a set of predetermined time length values, such as short, medium, and long, each corresponding to a time span. The maximum positive and maximum negative offsets are shifted downwards according to the current duration level; that is, if the current level is long, the offset is reduced to the offset range corresponding to the medium level; if it is medium, it is reduced to the offset range corresponding to the short level. After shifting down the levels, positive and negative offset values ​​are obtained. Then, difference stripping is performed on the positive and negative offset values, i.e., the negative offset value is subtracted from the positive offset value to obtain a net offset value. The net offset value represents the remaining amplitude after the positive and negative jitter cancel each other out. Next, a half-wave truncation operation is performed on the net offset value. Half-wave truncation refers to judging the sign of the net offset value; if the net offset value is positive, it is retained; if the net offset value is negative, it is set to zero. The value obtained after half-wave truncation is called the unidirectional offset amplitude. Finally, this unidirectional offset amplitude is latched into a register as the extreme offset of the jitter amplitude distribution set. The latching operation ensures that this extreme offset remains unchanged in subsequent processing until the next update.

[0089] Neighborhood matching localization refers to pre-storing a mapping table in the non-volatile memory of the electronic clock. This mapping table records the correspondence between extreme offset values ​​of a series of jitter amplitude distribution sets and temperature values. Using the currently latched extreme offset as the lookup key, the mapping table is searched for the two closest extreme offset entries, corresponding to a lower temperature and a higher temperature, respectively. These two temperature values ​​and their corresponding extreme offsets together constitute the candidate temperature range.

[0090] Linear weighted interpolation refers to using the extreme value offsets and temperature values ​​corresponding to the lower and upper endpoints of a temperature candidate interval, and proportionally allocating temperature values ​​based on the relative position of the current extreme value offset between the upper and lower endpoints. Specifically, the process involves: first calculating the distance from the current extreme value offset to the lower endpoint extreme value offset; then calculating the total distance from the upper endpoint extreme value offset to the lower endpoint extreme value offset; and finally dividing the former by the latter to obtain a weight ratio. This weight ratio is then multiplied by the difference between the upper and lower endpoint temperature values, and finally, the multiplier is added to the lower endpoint temperature value to obtain the initial temperature estimate.

[0091] The initial temperature estimate sequence refers to a series of initial temperature estimates obtained after multiple consecutive neighborhood matching localizations and linear weighted interpolations, arranged in chronological order. The sliding window midpoint selection involves setting a fixed-length window containing several of the most recently generated initial temperature estimates. Whenever a new initial temperature estimate is obtained, the window slides forward, discarding the oldest estimate and adding the new one. Then, all initial temperature estimates within the window are sorted by value, and the middle value is taken as the output. This output value is the sensorless temperature estimate of the electronic clock. The entire process relies solely on the jitter characteristics of the electronic clock's pulse signal, without using any physical temperature sensor, to estimate the temperature.

[0092] During the factory calibration phase, an electronic clock records a reference temperature value, which is stored in the clock's non-volatile memory. The temperature scale factor of the timing characteristics originates from the inherent material properties of the quartz crystal used in the clock. This property is determined by the crystal's cutting angle and aging characteristics, and is measured and fixed in the clock's parameter area after manufacturing. The extreme value offset is derived from the unidirectional offset amplitude latched after time-weighted attenuation fusion of the maximum positive and maximum negative offsets. The minimum and maximum values ​​of the extreme value offset within the statistical period are obtained by real-time comparison and capture of each extreme value offset within the statistical period. The length of the statistical period is set by the clock's internal timer counter. At the end of each statistical period, the currently captured minimum value is stored in the minimum value register, and the maximum value is stored in the maximum value register. The preset nonlinear correction coefficient is derived from the statistical fitting of batch test data of the electronic clock, and this coefficient is pre-written into the clock's read-only memory. The second time derivative of the extreme value offset is derived from the difference operation of the extreme value offsets obtained three times in a row. The first difference yields the first rate of change, and the second difference yields the second rate of change. This second rate of change reflects the acceleration of the change in the extreme value offset, that is, the quantification of the degree of temperature change.

[0093] The formula's significance lies in converting the extreme offset of an electronic clock into a sensorless temperature estimate. The use of the inverse error function allows the normalized position of the extreme offset within the minimum to maximum value range to be mapped to the inverse transform output of the error function. This mapping conforms to the error function distribution characteristics of a quartz crystal oscillator frequency as it changes with temperature. The exponential function term adjusts the output amplitude based on the second-order time derivative of the extreme offset. When temperature changes drastically, the absolute value of the second-order time derivative is large, and the exponential function value decreases accordingly, compressing and correcting the temperature estimate to prevent overshoot caused by transient jitter. A reference temperature serves as a benchmark to ensure the estimate remains within a reasonable range. The temperature scaling factor converts the dimensionless output of the inverse error function into an incremental value with temperature dimensions. The entire formula achieves a non-linear mapping from jitter amplitude to temperature, while introducing a dynamic correction term to improve the estimation accuracy in scenarios with rapid temperature changes.

[0094] The formula exhibits the following trends: When the extreme value offset approaches the minimum value within the statistical period, the input of the inverse error function approaches zero, and the output approaches negative infinity. Multiplying by the temperature scaling factor results in an increment approaching negative infinity, but the actual temperature estimate is limited by the temperature scaling factor, causing the sensorless temperature estimate to shift below the reference temperature, reflecting a low-temperature state. When the extreme value offset approaches the maximum value within the statistical period, the input of the inverse error function approaches one, and the output approaches positive infinity. The sensorless temperature estimate shifts above the reference temperature, reflecting a high-temperature state. When the extreme value offset equals the midpoint between the minimum and maximum values, the input and output of the inverse error function are both zero, and the sensorless temperature estimate equals the reference temperature. When the second time derivative of the extreme value offset is zero, indicating uniform temperature change, the exponential function value equals one, and the formula degenerates into a pure error function mapping. When the absolute value of the second time derivative increases, indicating accelerated temperature change, the exponential function value is less than one, the overall product decreases, and the temperature estimate contracts relative to the pure error function mapping result towards the reference temperature, resulting in a trend where the estimate becomes more conservative as the rate of temperature change increases.

[0095] The beneficial effects include the ability to accurately obtain temperature estimates by directly analyzing the jitter characteristics of the original pulse sequence of electronic clocks, eliminating the need for external temperature sensors and effectively reducing hardware costs and circuit complexity. By performing time-weighted attenuation fusion, matching positioning, and interpolation processing on extreme value offsets, the internal temperature drift state of the crystal oscillator is accurately restored. Combined with the use of a sliding window to select a smooth estimate sequence, instantaneous jitter interference is eliminated, improving the continuity and stability of the estimate. This enables self-calibration of the electronic clock's timing accuracy across the entire temperature range, ensuring long-term stable operation of the device.

[0096] A2: Based on the nominal period of the real-time pulse segment sequence in the electronic clock, the sensorless temperature estimate is matched and calibrated to obtain the temperature-offset mapping table of the sensorless temperature estimate;

[0097] In this embodiment of the invention, the step of matching and calibrating the sensorless temperature estimate based on the nominal period of the real-time pulse segment sequence in the electronic clock to obtain the temperature-offset mapping table of the sensorless temperature estimate includes:

[0098] Based on the sensorless temperature estimate and the nominal period of the real-time pulse segment sequence in the electronic clock, the period deviation of the real-time pulse segment sequence is sampled to obtain the measured offset sequence of the real-time pulse segment sequence.

[0099] The measured offset sequence is sorted by temperature dependence to obtain the offset sequence of the measured offset sequence;

[0100] The offset sequence is segmented and aggregated, and the measured offsets falling within the same temperature range are arithmetically averaged and combined to obtain the representative offset of the offset sequence.

[0101] Based on the midpoint value of the temperature range of the electronic clock, the representative offset is discretely paired and bound to obtain the temperature-offset mapping table of the sensorless temperature estimate.

[0102] A continuous pulse sequence is extracted from the real-time operation of an electronic clock as a real-time pulse segment sequence. Simultaneously, the nominal period value stored internally in the clock is read; this nominal period is the theoretical pulse interval of the clock at a reference temperature. The sensorless temperature estimate is used as a reference label and aligned with the actual occurrence time of each pulse in the real-time pulse segment sequence. A hardware comparison circuit records the time difference between the actual time and the theoretical time of the nominal period pulse pulse by pulse, and these differences are arranged according to the corresponding sensorless temperature estimates, ultimately forming a table recording the correspondence between temperature values ​​and pulse offsets.

[0103] The specific operation of period deviation sampling is as follows: The electronic clock contains a high-speed counter that operates at a frequency much higher than the nominal period. When the rising edge of each pulse in the real-time pulse segment sequence arrives, the hardware latch circuit immediately captures the current count value of the high-speed counter, which represents the actual arrival time of the pulse. Simultaneously, the theoretical count value that the pulse should have appeared is read from the nominal period register of the electronic clock. Subtracting the theoretical count value from the actual count value yields the period deviation value of the pulse. All period deviation values ​​are sequentially stored in a first-in-first-out (FIFO) memory according to the order of the pulses in the sequence, forming a measured offset sequence.

[0104] The specific operation of temperature-dependent sorting is as follows: Each measured offset corresponds to a sensorless temperature estimate at the time of its generation. This temperature estimate is bound to the measured offset as a data pair. Then, all data pairs are arranged in ascending order of temperature estimates, with smaller temperature estimates placed first and larger ones placed last. The binding relationship between the temperature estimate and the measured offset within each data pair is not changed during the sorting process. After sorting, the measured offset portion is extracted separately from the sorted data pairs and arranged in a new order to form an offset sequence. The offsets in this offset sequence are now arranged in ascending order of their corresponding temperatures.

[0105] The specific operation of segmented interval aggregation is as follows: The entire possible range of sensorless temperature estimates is divided into several continuous and non-overlapping temperature intervals, each with a fixed width. Each offset in the offset sequence is traversed, and its temperature interval is determined based on the temperature estimate it is bound to. The offset is then placed into the corresponding interval bucket. Each interval bucket may contain multiple offsets. An arithmetic mean is performed on all offsets within each interval bucket, i.e., the values ​​of all offsets in the bucket are summed, and then divided by the number of offsets in the bucket. The quotient is used as the representative offset for that temperature interval. If no offset falls within a certain temperature interval, no representative offset is generated for that interval.

[0106] The specific operation of discrete point pair binding is as follows: For each temperature interval that generates a representative offset, firstly, calculate the midpoint value of that temperature interval. The midpoint value is calculated by summing the lower and upper temperature limits of the interval and then dividing by two. Then, use this midpoint value as the x-axis and the corresponding representative offset as the y-axis, combining them into a point pair. Write all the point pairs obtained from all temperature intervals into the non-volatile memory of the electronic clock in ascending order of their midpoint values, forming a two-column table. The first column represents the midpoint value of the temperature interval, and the second column represents the representative offset. This table is the temperature-offset mapping table for sensorless temperature estimation.

[0107] The beneficial effects include: by matching and calibrating the sampling period deviation, the sensorless temperature estimate is correlated with the nominal pulse period to generate an accurate temperature-offset mapping table, which truly reflects the temperature change offset pattern of electronic clocks and watches, providing solid data support for timing calibration. Temperature sorting, interval aggregation, and mean integration eliminate random fluctuations in single measurements, improving the stability of the mapping table. The discrete point binding constructs a regular lookup table mapping relationship, enabling autonomous temperature calibration without external sensors, strengthening the device's resistance to environmental temperature changes, and continuously ensuring stable and reliable timing accuracy.

[0108] A3: Repeatedly perform temperature difference mapping on the current pulse segment of the electronic clock to obtain the real-time temperature estimate of the current pulse segment, and perform interval positioning on the real-time temperature estimate based on the temperature-offset mapping table to obtain the interval reference offset of the current pulse segment.

[0109] In this embodiment of the invention, the step of repeatedly performing temperature difference mapping on the current pulse segment of the electronic clock to obtain a real-time temperature estimate of the current pulse segment, and then performing interval positioning on the real-time temperature estimate based on the temperature-offset mapping table to obtain the interval reference offset of the current pulse segment, includes:

[0110] Differential stripping is performed on the current pulse segment of the electronic clock to obtain the instantaneous periodic jitter sequence of the current pulse segment;

[0111] Based on the aforementioned temporal characteristics, the instantaneous periodic jitter sequence is reverse-matched and located to obtain the real-time temperature estimate of the current pulse segment.

[0112] Based on the temperature-offset mapping table, an interval search is performed on the real-time temperature estimate to obtain the mapping interval of the real-time temperature estimate;

[0113] Boundary locking is performed on the mapping interval to obtain the lower limit temperature node and the upper limit temperature node of the mapping interval;

[0114] Offsets are read for the lower temperature node and the upper temperature node respectively to obtain the lower reference offset and upper reference offset of the mapping interval;

[0115] The lower limit reference offset and the upper limit reference offset are weighted and fused to obtain the interval reference offset of the current pulse segment.

[0116] A continuous pulse signal is extracted from the current operating state of the electronic clock as the current pulse segment. The same series of operations as the aforementioned temperature difference mapping are performed on this segment, namely, obtaining the estimated temperature corresponding to this segment by capturing the pulse edge and extracting the offset. Then, this temperature estimate is used as a query key to find its corresponding temperature range in the pre-constructed temperature-offset mapping table. The boundary nodes of this range are determined, and the offset values ​​corresponding to the boundary nodes are read. Finally, the two boundary offsets are merged to obtain a reference offset representing the current pulse segment's value within that temperature range.

[0117] The specific operation of differential stripping is as follows: The high-speed counter inside the electronic clock latches the current count value at the arrival of each rising edge of the current pulse segment, which is taken as the actual arrival time of that pulse. Simultaneously, the theoretical arrival time of the pulse is read from the nominal period register. The theoretical arrival time is calculated by adding the nominal period to the actual arrival time of the previous pulse. Subtracting the theoretical arrival time from the actual arrival time yields a time difference. This difference reflects the degree to which the pulse is ahead or behind the ideal period, and is called instantaneous period jitter. Following the order of the pulses in the segment, all instantaneous period jitter values ​​are sequentially stored in a register chain, forming an instantaneous period jitter sequence.

[0118] The specific operation of reverse matching localization is as follows: Each jitter value in the instantaneous jitter sequence is compared point-by-point with a time-series feature template pre-stored in the electronic clock. The time-series feature template is a reference data set established during the factory calibration phase of the electronic clock by testing jitter patterns at different temperatures. The comparison process uses the nearest neighbor matching principle, that is, calculating the overall degree of difference between the current jitter sequence and the jitter pattern corresponding to each temperature in the template. The degree of difference is quantified by summing the absolute values ​​of the point-by-point subtractions. The temperature value corresponding to the temperature pattern with the smallest degree of difference is selected as the real-time temperature estimate of the current pulse segment.

[0119] The specific operation of interval retrieval is as follows: The temperature-offset mapping table is a list arranged in ascending order of temperature values. Each row in the table records the midpoint value of a temperature interval and its corresponding representative offset. The real-time temperature estimate is compared with the midpoint value of each row in the table. The first row where the midpoint value is greater than the real-time temperature estimate, and the last row where the midpoint value is less than the real-time temperature estimate, are found. The range between the midpoint values ​​of the temperature intervals corresponding to these two rows is the mapping interval in which the real-time temperature estimate lies. This mapping interval is jointly defined by the lower limit temperature and the upper limit temperature.

[0120] The specific operation of boundary locking is as follows: Extract the lower and upper boundaries of the mapped interval from the temperature-offset mapping table. The lower boundary is the minimum value among all temperature values ​​within the mapped interval; the table row corresponding to this minimum value is called the lower limit temperature node. The upper boundary is the maximum value among all temperature values ​​within the mapped interval; the table row corresponding to this maximum value is called the upper limit temperature node. These two nodes represent the two endpoints of the temperature interval retrieved from the mapping table, and each node contains both a temperature value and a corresponding offset value.

[0121] The specific operation for reading the offset is as follows: Locate the offset column corresponding to the row containing the lower limit temperature node in the temperature-offset mapping table, extract the value from that column, and store it in the lower limit reference offset register. Similarly, locate the offset column corresponding to the row containing the upper limit temperature node, extract the value from that column, and store it in the upper limit reference offset register. These two offsets represent the pulse offset characteristics that the electronic clock should exhibit at the lowest and highest temperatures within the mapping range, respectively.

[0122] The specific operation of weighted fusion is as follows: First, calculate the ratio of the difference between the real-time temperature estimate and the lower limit temperature node to the total width of the mapping interval; this ratio serves as the weight of the lower limit reference offset. Then, calculate the ratio of the difference between the real-time temperature estimate and the upper limit temperature node to the total width of the mapping interval; this ratio serves as the weight of the upper limit reference offset. The sum of the two weights equals one. Multiply the lower limit reference offset by its corresponding weight, multiply the upper limit reference offset by its corresponding weight, and then add the two products together. The sum obtained is the interval reference offset for the current pulse segment. The entire weighted fusion process allows the interval reference offset to continuously change according to the relative position of the real-time temperature estimate within the mapping interval, avoiding abrupt boundary changes.

[0123] The beneficial effects include obtaining real-time temperature estimates by repeatedly mapping the current pulse segment using temperature difference, and quickly locating the mapping range of the current temperature by combining a temperature-offset mapping table for range retrieval and boundary locking. By weighted fusion of the lower and upper limit reference offsets to obtain the range reference offset, the continuous transition of the offset within the temperature range is ensured, avoiding calibration errors caused by boundary jumps. This scheme enables dynamic tracking of the real-time operating status of electronic clocks, allowing timing accuracy calibration to adapt to changes in ambient temperature, significantly improving the real-time performance and smoothness of calibration.

[0124] A4: Based on the interval reference offset, the jitter amplitude of the current pulse segment is compensated by a step size to obtain the real-time dynamic compensation step size of the current pulse segment, and the cumulative count value of the electronic clock is phase-adjusted to obtain the single-cycle refresh value of the electronic clock.

[0125] In this embodiment of the invention, the step of assigning a compensation step size to the jitter amplitude of the current pulse segment based on the interval reference offset to obtain the real-time dynamic compensation step size of the current pulse segment, and performing phase adjustment on the cumulative count value of the electronic clock to obtain the single-cycle refresh value of the electronic clock, includes:

[0126] Edge-triggered sampling is performed on the jitter amplitude of the current pulse segment to obtain the instantaneous extreme value of the jitter amplitude;

[0127] Based on the interval reference offset, the instantaneous extreme values ​​are compared differentially to obtain the dynamic error component of the jitter amplitude;

[0128] The dynamic error components are integrated and accumulated to obtain the cumulative phase deviation of the dynamic error components;

[0129] Based on the accumulated phase deviation, the local oscillator of the electronic clock is adjusted by frequency division ratio to obtain the real-time dynamic compensation step size of the current pulse segment.

[0130] The step of assigning a compensation step size to the jitter amplitude of the current pulse segment based on the interval reference offset to obtain the real-time dynamic compensation step size of the current pulse segment, and adjusting the phase of the cumulative count value of the electronic clock to obtain the single-cycle refresh value of the electronic clock, further includes:

[0131] Based on the real-time dynamic compensation step size, the cumulative count value of the electronic clock is iteratively accumulated to obtain the accumulated intermediate value of the cumulative count value;

[0132] The overflow truncation of the accumulated intermediate quantity is used to obtain the modulus constraint margin of the accumulated count value;

[0133] The register is overwritten with the modulus constraint margin to obtain the single-cycle refresh value of the electronic clock.

[0134] The jitter amplitude value generated during the current pulse segment's operation is obtained, and then combined with the previously obtained interval reference offset. The difference between the two is compared to determine the required compensation step size. After the compensation step size is assigned, it is applied to the accumulated count value of the electronic clock to adjust the phase direction of the accumulated count value, ultimately obtaining a refresh value after single-cycle correction. This value is used to drive the next timing action of the electronic clock.

[0135] The specific operation of edge-triggered sampling is as follows: An edge detection circuit is installed inside the electronic clock. This circuit monitors the rising and falling edges of each pulse in the current pulse segment in real time. When a rising edge is detected, the edge detection circuit outputs a trigger signal, which enables a sample-and-hold circuit. Driven by the trigger signal, the sample-and-hold circuit immediately captures the offset of the pulse arrival time relative to the nominal period; this offset is the jitter amplitude. Within a fixed time window, the jitter amplitudes of multiple pulses are continuously captured, and the largest value is latched into a maximum value register; this maximum value is called the instantaneous extreme value.

[0136] The specific operation of differential comparison is as follows: The instantaneous extreme value is read from the maximum value register, and the interval reference offset is read from the interval reference offset register. The instantaneous extreme value is input to one input of the subtractor, and the interval reference offset is input to the other input. The subtractor performs a subtraction operation, subtracting the interval reference offset from the instantaneous extreme value. If the difference obtained from the subtraction operation is positive, it indicates that the current jitter amplitude exceeds the allowable range of the reference; if it is negative, it indicates that the current jitter amplitude is below the allowable range of the reference. This difference is named the dynamic error component and stored in the dynamic error register.

[0137] The specific operation of integration and accumulation is as follows: An accumulator register is set up, with an initial value of zero. Whenever a new dynamic error component is obtained, the accumulator adds this dynamic error component to the existing value in the accumulator register, and the result is written back to the accumulator register. This process is repeated with each new pulse, and the value in the accumulator register continuously increases or decreases, reflecting the cumulative effect of the dynamic error component over time. The final output value of the accumulator register is called the cumulative phase deviation, which represents the total phase shift caused by continuous jitter.

[0138] The specific operation of frequency division ratio adjustment is as follows: The local oscillator of the electronic clock generates a high-frequency clock signal. This signal passes through a programmable frequency divider and outputs a reference clock for timing. The programmable frequency divider contains a frequency division ratio register, the value of which determines the frequency division factor. The accumulated phase deviation is converted into a frequency division ratio correction amount; the sign of the correction amount determines whether the frequency division factor is increased or decreased. The correction amount is added to the current frequency division ratio to obtain a new frequency division ratio value, which is then written to the frequency division ratio register. After the value of the frequency division ratio register changes, the output frequency of the local oscillator changes accordingly. This change is converted into a compensation step size within each pulse period, which is the real-time dynamic compensation step size.

[0139] The specific operation of iterative accumulation is as follows: The electronic clock has an internal cumulative count register that records the total number of timing pulses from the start time to the current time. At the beginning of each new pulse cycle, the value of the real-time dynamic compensation step size is read from the step size register and added to the current value in the cumulative count register. The sum is called the intermediate accumulation value. This intermediate accumulation value is temporarily stored in an intermediate register for use in subsequent operations.

[0140] The specific operation of overflow truncation is as follows: The bit width of the cumulative count value in an electronic clock is fixed, for example, 3 bits. When the value of the accumulated intermediate quantity exceeds the maximum value that 3 bits can represent, overflow occurs. The overflow truncation circuit detects the most significant bit of the accumulated intermediate quantity. If this bit is 0 and there is a carry output, the carry part is discarded, and only the low-order bits are retained. The retained low-order bits are the modulo constraint margin. The value of this margin is always less than the modulo constraint value, ensuring that the cumulative count value will not grow indefinitely and exceed the register range.

[0141] The register overwrite operation involves retrieving the modulus constraint margin from the intermediate register and writing it directly into the cumulative count register, overwriting the old value. After the overwrite operation, the cumulative count register stores the updated count value, which is called the single-cycle refresh value. The timing display module of the electronic clock reads this single-cycle refresh value and uses it to drive the carry-over and display of seconds, minutes, and hours. Throughout the process, the real-time dynamic compensation step size may vary in each pulse cycle, achieving dynamic tracking and compensation for jitter and ensuring the timing accuracy of the electronic clock.

[0142] The beneficial effect is that by assigning a compensation step size to the jitter amplitude using an interval reference offset, the precise generation of the real-time dynamic compensation step size is achieved. The accumulated phase deviation is obtained through the integration and accumulation of dynamic error components, and the frequency division ratio of the local oscillator is adjusted to ensure that the compensation step size follows jitter changes in real time. A single-cycle refresh value is obtained through iterative accumulation, overflow truncation, and register overwriting, completing the precise phase adjustment for each pulse cycle. This scheme effectively eliminates the accumulated phase deviation, ensuring the continuity and stability of the electronic clock's timing output under dynamic temperature conditions, and significantly improving the timing accuracy over long-term operation.

[0143] A5: Based on the single-cycle refresh value, the subsequent pulses of the electronic clock are time-calibrated to obtain the final signal of the electronic clock.

[0144] In this embodiment of the invention, the step of performing timing calibration on subsequent pulses of the electronic clock based on the single-cycle refresh value to obtain the final signal of the electronic clock includes:

[0145] Based on the single-cycle refresh value, the frequency division coefficient is loaded onto the output frequency divider of the electronic clock to obtain the calibrated frequency division ratio of the output frequency divider;

[0146] Based on the calibrated frequency division ratio, the high-frequency reference source of the electronic clock is divided by pulse frequency to obtain the gated pulse beat sequence of the high-frequency reference source;

[0147] Based on the edge reference of the single-cycle refresh value, the gated pulse beat sequence is aligned by rising edge triggering to obtain the phase synchronization pulse train of the electronic clock.

[0148] The phase synchronization pulse train is buffered at the drive stage to obtain the final signal of the electronic clock.

[0149] Using the previously obtained single-cycle refresh value as the calibration benchmark, the frequency division coefficient of the output frequency divider is set sequentially, the high-frequency reference source is processed by pulse frequency division, the edge alignment of the generated gated pulse beat sequence is performed, and finally the final signal sequence that can be used to drive the display or timing of electronic clocks is obtained through the driver-level buffer output.

[0150] The output frequency divider is a programmable digital frequency divider circuit with an internal frequency division factor register. The single-cycle refresh value is read from the cumulative count register and directly written into the frequency division factor register of the output frequency divider, completing the frequency division factor loading operation. After loading, the value stored in the frequency division factor register is called the calibrated frequency division ratio, which determines the subsequent frequency division factor of the input clock by the output frequency divider.

[0151] A high-frequency reference source is a highly stable oscillator inside an electronic clock, generating a continuous pulse signal at a fixed frequency. The pulse signal output from this high-frequency reference source is connected to the clock input of an output frequency divider. The output frequency divider counts and divides the input high-frequency pulses according to an internally stored calibrated division ratio. Each time the count reaches a number of pulses equal to the division ratio, a pulse is output. This series of continuously output pulses is arranged in chronological order, forming a gated pulse beat sequence. The time interval between each pulse in this sequence is determined by the calibrated division ratio.

[0152] The edge reference for a single-cycle refresh value refers to the rising or falling edge signal generated at the update time of the single-cycle refresh value. This signal serves as a reference for phase alignment. The rising edge of each pulse in the gated pulse beat sequence is compared with the edge reference. If a time offset exists, the entire gated pulse beat sequence is shifted using an adjustable delay chain, ensuring that the rising edge of the first pulse in the sequence is perfectly aligned with the edge reference. The resulting pulse sequence after alignment is called a phase-synchronized pulse train, which is strictly synchronized in phase with the single-cycle refresh value.

[0153] A driver-stage buffered output refers to feeding a phase synchronization pulse train into an output buffer amplifier circuit. This buffer amplifier has sufficient driving capability to convert weak digital pulse signals into strong signals suitable for driving external loads. The output of the buffer amplifier is directly connected to the timing display module or signal output pin of the electronic clock. The signal output after buffering and amplification is the final signal of the electronic clock, which is used to drive the second hand, refresh the digital display, or serve as a timing reference output to other circuits.

[0154] The beneficial effect is that the division coefficient is loaded onto the output divider based on the single-cycle refresh value, achieving precise calibration of the division ratio. A gated pulse beat sequence is obtained by pulse division of the high-frequency reference source, and then aligned with the rising edge trigger using the edge reference of the single-cycle refresh value, ensuring strict phase synchronization between the output pulse and the calibration reference. The final signal obtained from the driver-stage buffer output possesses sufficient driving capability and timing stability, eliminating accumulated errors in subsequent pulse outputs of the electronic clock and ensuring accurate and continuous timing display.

[0155] like Figure 2 The diagram shown is a functional block diagram of an electronic clock and watch timing accuracy calibration system based on data fitting, provided in an embodiment of the present invention.

[0156] The data fitting-based electronic clock timing accuracy calibration system 100 of this invention can be installed in an electronic device. Depending on the functions implemented, the data fitting-based electronic clock timing accuracy calibration system 100 may include a temperature difference mapping estimation module 101, a temperature-offset calibration module 102, a temperature range positioning module 103, a dynamic compensation phase adjustment module 104, and a timing calibration output module 105. The module described in this invention can also be called a unit, referring to a series of computer program segments that can be executed by the processor of an electronic device and perform a fixed function, stored in the memory of the electronic device.

[0157] In this embodiment, the functions of each module / unit are as follows:

[0158] The temperature difference mapping estimation module 101 is used to perform temperature difference mapping on the extreme value offset of the jitter amplitude distribution set of the electronic clock based on the time sequence characteristics of the electronic clock, so as to obtain the sensorless temperature estimation of the electronic clock.

[0159] The temperature-offset calibration module 102 is used to match and calibrate the sensorless temperature estimate based on the nominal period of the real-time pulse segment sequence in the electronic clock, so as to obtain the temperature-offset mapping table of the sensorless temperature estimate.

[0160] The temperature range positioning module 103 is used to repeatedly perform temperature difference mapping on the current pulse segment of the electronic clock to obtain the real-time temperature estimate of the current pulse segment, and perform range positioning on the real-time temperature estimate based on the temperature-offset mapping table to obtain the range reference offset of the current pulse segment.

[0161] The dynamic compensation phase adjustment module 104 is used to assign a compensation step size to the jitter amplitude of the current pulse segment based on the interval reference offset, so as to obtain the real-time dynamic compensation step size of the current pulse segment, and to adjust the phase of the cumulative count value of the electronic clock to obtain the single-cycle refresh value of the electronic clock.

[0162] The timing calibration output module 105 is used to perform timing calibration on subsequent pulses of the electronic clock based on the single-cycle refresh value, so as to obtain the final signal of the electronic clock.

[0163] In the several embodiments provided by this invention, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0164] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0165] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0166] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0167] The embodiments of this application can acquire and process relevant data based on an artificial intelligence technology. Artificial intelligence is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0168] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for calibrating the timing accuracy of electronic clocks and watches based on data fitting, characterized in that, The method includes: A1: Based on the timing characteristics of the electronic clock, the extreme value offset of the jitter amplitude distribution set in the electronic clock is mapped by temperature difference to obtain the sensorless temperature estimate of the electronic clock. A2: Based on the nominal period of the real-time pulse segment sequence in the electronic clock, the sensorless temperature estimate is matched and calibrated to obtain the temperature-offset mapping table of the sensorless temperature estimate; A3: Repeatedly perform temperature difference mapping on the current pulse segment of the electronic clock to obtain the real-time temperature estimate of the current pulse segment, and perform interval positioning on the real-time temperature estimate based on the temperature-offset mapping table to obtain the interval reference offset of the current pulse segment. A4: Based on the interval reference offset, the jitter amplitude of the current pulse segment is compensated with a step size to obtain the real-time dynamic compensation step size of the current pulse segment, and the cumulative count value of the electronic clock is phase-adjusted to obtain the single-cycle refresh value of the electronic clock. A5: Based on the single-cycle refresh value, the subsequent pulses of the electronic clock are time-calibrated to obtain the final signal of the electronic clock.

2. The method for calibrating the timing accuracy of electronic clocks and watches based on data fitting as described in claim 1, characterized in that, The method of using the time-series characteristics of electronic clocks to perform temperature difference mapping on the extreme value offset of the jitter amplitude distribution set in the electronic clocks to obtain the sensorless temperature estimate of the electronic clocks includes: The edge triggering timing of the original pulse sequence of the electronic clock is obtained by performing time-domain differential mapping on the original pulse sequence; Based on the nominal periodic trigger time of the electronic clock, the difference of the edge trigger timing is extracted to obtain the instantaneous offset of the edge trigger timing. The instantaneous offset is dynamically captured to obtain extreme value candidate pairs of the edge-triggered timing, and the extreme value candidate pairs include the maximum positive offset and the maximum negative offset; The maximum positive offset and the maximum negative offset are fused by time-weighted attenuation to obtain the extreme offset of the jitter amplitude distribution set.

3. The method for calibrating the timing accuracy of electronic clocks and watches based on data fitting as described in claim 1, characterized in that, The method of performing temperature difference mapping on the extreme value offset of the jitter amplitude distribution set of the electronic clock based on the time-series characteristics of the electronic clock to obtain the sensorless temperature estimate of the electronic clock also includes: Based on the timing characteristics of the electronic clock, the extreme value offset is located by neighborhood matching to obtain the temperature candidate range of the extreme value offset. Based on the temperature values ​​of the feature points at both ends of the temperature candidate interval, linear weighted interpolation is performed on the extreme value offset to obtain the initial temperature estimate of the extreme value offset. Based on the initial temperature estimate sequence of the electronic clock, a sliding window value is selected for the initial temperature estimate to obtain the sensorless temperature estimate of the electronic clock. The calculation formula for the sensorless temperature estimate is as follows: ； in, For the sensorless temperature estimation, The reference temperature for the electronic clock. The temperature scale factor is the time series characteristic. It is the inverse error function. This is the extreme value offset. The extreme value offset is the minimum value within the statistical period. The extreme value offset is the maximum value within the statistical period. These are the preset nonlinear correction coefficients. The second time derivative of the extreme value offset is... With natural constant An exponential function with base 0.

4. The method for calibrating the timing accuracy of electronic clocks and watches based on data fitting as described in claim 2, characterized in that, The step of performing time-weighted attenuation fusion on the maximum positive offset and the maximum negative offset to obtain the extreme value offset of the jitter amplitude distribution set includes: Based on the preset duration level, the maximum positive offset and the maximum negative offset are shifted down to obtain the positive offset value and negative offset value of the jitter amplitude distribution set; The positive and negative offset values ​​are stripped to obtain the net offset value of the jitter amplitude distribution set; The net offset value is half-wave truncation to obtain the unidirectional offset amplitude of the jitter amplitude distribution set; The unidirectional offset amplitude is latched as the extreme offset of the jitter amplitude distribution set.

5. The method for calibrating the timing accuracy of electronic clocks and watches based on data fitting as described in claim 1, characterized in that, The process of matching and calibrating the sensorless temperature estimate based on the nominal period of the real-time pulse segment sequence in the electronic clock to obtain a temperature-offset mapping table for the sensorless temperature estimate includes: Based on the sensorless temperature estimate and the nominal period of the real-time pulse segment sequence in the electronic clock, the period deviation of the real-time pulse segment sequence is sampled to obtain the measured offset sequence of the real-time pulse segment sequence. The measured offset sequence is sorted by temperature dependence to obtain the offset sequence of the measured offset sequence; The offset sequence is segmented and aggregated, and the measured offsets falling within the same temperature range are arithmetically averaged and combined to obtain the representative offset of the offset sequence. Based on the midpoint value of the temperature range of the electronic clock, the representative offset is discretely paired and bound to obtain the temperature-offset mapping table of the sensorless temperature estimate.

6. The method for calibrating the timing accuracy of electronic clocks and watches based on data fitting as described in claim 3, characterized in that, The process of repeatedly performing temperature difference mapping on the current pulse segment of the electronic clock to obtain a real-time temperature estimate of the current pulse segment, and then performing interval positioning on the real-time temperature estimate based on the temperature-offset mapping table to obtain the interval reference offset of the current pulse segment, includes: Differential stripping is performed on the current pulse segment of the electronic clock to obtain the instantaneous periodic jitter sequence of the current pulse segment; Based on the aforementioned temporal characteristics, the instantaneous periodic jitter sequence is reverse-matched and located to obtain the real-time temperature estimate of the current pulse segment. Based on the temperature-offset mapping table, an interval search is performed on the real-time temperature estimate to obtain the mapping interval of the real-time temperature estimate; Boundary locking is performed on the mapping interval to obtain the lower limit temperature node and the upper limit temperature node of the mapping interval; Offsets are read for the lower temperature node and the upper temperature node respectively to obtain the lower reference offset and upper reference offset of the mapping interval; The lower limit reference offset and the upper limit reference offset are weighted and fused to obtain the interval reference offset of the current pulse segment.

7. The method for calibrating the timing accuracy of electronic clocks and watches based on data fitting as described in claim 1, characterized in that, The process of assigning a compensation step size to the jitter amplitude of the current pulse segment based on the interval reference offset to obtain the real-time dynamic compensation step size of the current pulse segment, and adjusting the phase of the cumulative count value of the electronic clock to obtain the single-cycle refresh value of the electronic clock, includes: Edge-triggered sampling is performed on the jitter amplitude of the current pulse segment to obtain the instantaneous extreme value of the jitter amplitude; Based on the interval reference offset, the instantaneous extreme values ​​are compared differentially to obtain the dynamic error component of the jitter amplitude; The dynamic error components are integrated and accumulated to obtain the cumulative phase deviation of the dynamic error components; Based on the accumulated phase deviation, the local oscillator of the electronic clock is adjusted by frequency division ratio to obtain the real-time dynamic compensation step size of the current pulse segment.

8. The method for calibrating the timing accuracy of electronic clocks and watches based on data fitting as described in claim 1, characterized in that, The step of assigning a compensation step size to the jitter amplitude of the current pulse segment based on the interval reference offset to obtain the real-time dynamic compensation step size of the current pulse segment, and adjusting the phase of the cumulative count value of the electronic clock to obtain the single-cycle refresh value of the electronic clock, further includes: Based on the real-time dynamic compensation step size, the cumulative count value of the electronic clock is iteratively accumulated to obtain the accumulated intermediate value of the cumulative count value; The overflow truncation of the accumulated intermediate quantity is used to obtain the modulus constraint margin of the accumulated count value; The register is overwritten with the modulus constraint margin to obtain the single-cycle refresh value of the electronic clock.

9. The method for calibrating the timing accuracy of electronic clocks and watches based on data fitting as described in claim 1, characterized in that, The step of timing calibration of subsequent pulses of the electronic clock based on the single-cycle refresh value to obtain the final signal of the electronic clock includes: Based on the single-cycle refresh value, the frequency division coefficient is loaded onto the output frequency divider of the electronic clock to obtain the calibrated frequency division ratio of the output frequency divider; Based on the calibrated frequency division ratio, the high-frequency reference source of the electronic clock is divided by pulse frequency to obtain the gated pulse beat sequence of the high-frequency reference source; Based on the edge reference of the single-cycle refresh value, the gated pulse beat sequence is aligned by rising edge triggering to obtain the phase synchronization pulse train of the electronic clock. The phase synchronization pulse train is buffered at the drive stage to obtain the final signal of the electronic clock.

10. A timekeeping accuracy calibration system for electronic clocks and watches based on data fitting, characterized in that, The system for implementing the data fitting-based electronic clock timing accuracy calibration method of claim 1 includes: The temperature difference mapping estimation module is used to perform temperature difference mapping on the extreme value offset of the jitter amplitude distribution set of the electronic clock based on the time sequence characteristics of the electronic clock, so as to obtain the sensorless temperature estimation of the electronic clock. The temperature-offset calibration module is used to match and calibrate the sensorless temperature estimate based on the nominal period of the real-time pulse segment sequence in the electronic clock, and obtain the temperature-offset mapping table of the sensorless temperature estimate. The temperature range positioning module is used to repeatedly perform temperature difference mapping on the current pulse segment of the electronic clock to obtain the real-time temperature estimate of the current pulse segment, and perform range positioning on the real-time temperature estimate based on the temperature-offset mapping table to obtain the range reference offset of the current pulse segment. The dynamic compensation phase adjustment module is used to assign a compensation step size to the jitter amplitude of the current pulse segment based on the interval reference offset, so as to obtain the real-time dynamic compensation step size of the current pulse segment, and to adjust the phase of the cumulative count value of the electronic clock to obtain the single-cycle refresh value of the electronic clock. The timing calibration output module is used to perform timing calibration on subsequent pulses of the electronic clock based on the single-cycle refresh value, so as to obtain the final signal of the electronic clock.

Images