An LDO voltage regulator circuit

Abstract

The application relates to the technical field of voltage stabilizing circuits, and discloses an LDO voltage stabilizing circuit which comprises an error amplifier, a buffer, a current amplifier, a power tube Mp, a feedback capacitor Cf and an output voltage detection unit; when in use, the change condition of the stabilized voltage is detected through the feedback capacitor Cf and the current amplifier, and is fed back to the input end of the buffer; on the one hand, a relatively large off-chip capacitor does not need to be arranged, and integration and manufacturing are facilitated; on the other hand, the transient response performance and the AC stability of the LDO voltage stabilizing circuit can be ensured; in addition, the buffer can be arranged to play a role in matching the front and rear impedance matching, so that the power tube Mp can work better, the load capacity of the power tube Mp is improved, and therefore the use requirement of a large-current load can be met.

Description

Technical Field

[0001] This invention relates to the field of voltage regulator circuit technology, and more specifically to an LDO voltage regulator circuit. Background Technology

[0002] With the rapid expansion of PoE power supply systems, there is a growing demand for internal power management systems capable of lower voltage startup, as well as higher accuracy, faster response, higher efficiency, and greater load drive capability. Low-dropout regulators (LDOs), with their superior performance in terms of temperature control, low noise, and high power supply rejection ratio, are widely used in various power management systems. Furthermore, compared to high-voltage output switching power supplies, LDOs offer a unique size advantage in portable electronic device applications.

[0003] The structure of existing LDO voltage regulator circuits used in PoE power supply systems is as follows: Figure 1 As shown, it mainly includes an error amplifier, a power transistor Mp, a feedback network composed of resistors R1 and R2, and a load capacitor Cout. Figure 1 The working process of the structure shown is as follows: When the input signal Vin changes, the power transistor acts as a variable resistor. The voltage feedback signal is obtained through the feedback network, and then compared with the reference voltage Vref through the error amplifier. The power transistor is controlled by the output signal, thereby achieving the effect of outputting a stable voltage.

[0004] for Figure 1 The structure shown has the following problems in practical use: because it requires an external capacitor, Cout, the entire circuit structure is not easy to integrate, and it also affects the manufacturing speed of the circuit. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the present invention provides an LDO voltage regulator circuit. The technical problem to be solved is that the existing LDO circuits require the use of off-chip capacitors, which is not conducive to integration and has a slow manufacturing speed.

[0006] To solve the above technical problems, the present invention provides the following technical solution: an LDO voltage regulator circuit, including an error amplifier, a buffer, a current amplifier, a power transistor Mp, a feedback capacitor Cf, and an output voltage detection unit;

[0007] The source of the power transistor Mp is used to input the external signal Vin, and the drain of the power transistor Mp is used to output the regulated voltage. The output voltage detection unit is used to detect the magnitude of the regulated voltage and input the detected voltage to the negative input terminal of the error amplifier. The positive input terminal of the error amplifier is used to input the reference voltage Vref. The output terminal of the error amplifier is electrically connected to the input terminal of the buffer, and the output terminal of the buffer is electrically connected to the gate of the power transistor Mp. One end of the feedback capacitor Cf is electrically connected to the drain of the power transistor Mp, and the other end is electrically connected to the current amplifier; the current amplifier is used to amplify the current input to the feedback capacitor Cf and feed it back to the input of the buffer.

[0008] In one embodiment, the error amplifier includes MOS transistors M1-M10; The source of MOSFET M1 and the source of MOSFET M3 are used to input bias current I1; the gate of MOSFET M1 is used to input reference voltage Vref, and the gate of MOSFET M3 is used to input detection voltage; the drain of MOSFET M1 is electrically connected to the drain of MOSFET M2, the gate of MOSFET M2, and the gate of MOSFET M7, respectively, and the source of MOSFET M7 and the source of MOSFET M2 are both grounded; the drain of MOSFET M3 is electrically connected to the drain of MOSFET M4, the gate of MOSFET M4, and the gate of MOSFET M10, respectively, and the source of MOSFET M4 and the source of MOSFET M10 are both grounded; The drain of MOSFET M7 is electrically connected to the source of MOSFET M6. The gate of MOSFET M6 is electrically connected to the drain of MOSFET M6, the drain of MOSFET M5, the gate of MOSFET M5, the gate of MOSFET M8, and the gate of MOSFET M9. The source of MOSFET M9 is electrically connected to the drain of MOSFET M10, and the drain of MOSFET M9 is electrically connected to the drain of MOSFET M8. This is the output terminal of the error amplifier. The sources of MOSFET M8 and MOSFET M5 are used to input the external signal Vin.

[0009] In one embodiment, the MOS transistors M1, M3, M5, and M8 are PMOS transistors; The MOS transistors M2, M4, M6, M7, M9, and M10 are NMOS transistors.

[0010] In one embodiment, the buffer includes a MOSFET M11 and a capacitor Cc. The source of the MOSFET M11 is used to input the bias current I3, which is the output terminal of the buffer, and is also electrically connected to one end of the capacitor Cc. The gate of the MOSFET M11 is the input terminal of the buffer and is electrically connected to the other end of the capacitor Cc. The drain of the MOSFET M11 is grounded.

[0011] In one implementation, MOS transistor M11 is a PMOS transistor.

[0012] In one embodiment, the current amplifier includes MOS transistors M12-M15 and a resistor Rf. The gate of MOS transistor M15 is electrically connected to one end of resistor Rf and the other end of feedback capacitor Rf, respectively. The other end of resistor Rf is electrically connected to the drain of MOS transistor M15, the source of MOS transistor M14, and the gate of MOS transistor M13, respectively. The source of MOS transistor M13 and the source of MOS transistor M15 are both grounded. The drain of MOS transistor M14 is electrically connected to the gate of MOS transistor M12 and the gate of MOS transistor M14 respectively, and is used to input bias current I2. The drain of MOS transistor M12 is electrically connected to the drain of MOS transistor M13, and the source of MOS transistor M12 is electrically connected to the input terminal of the buffer.

[0013] In one embodiment, MOS transistor M12 is a PMOS transistor, and MOS transistors M13, M14 and M15 are NMOS transistors.

[0014] In one embodiment, the present invention further includes a bandgap reference circuit for generating a reference voltage Vref, a bias current I1, a bias current I2, and a bias current I3, comprising MOSFETs M21-M38, transistors Q1-Q3, resistors R3 and R4. The source of MOSFET M31 is electrically connected to the sources of MOSFET M21, MOSFET M25, MOSFET M29, MOSFET M36, MOSFET M37 and MOSFET M38 respectively, for inputting drive power. The gate of MOSFET M31 is electrically connected to the drain of MOSFET M31 and the source of MOSFET M32. The gate of MOSFET M32 is electrically connected to the drain of MOSFET M32 and the drain of MOSFET M33. The gate of MOSFET M33 is electrically connected to the gate of MOSFET M35, the source of MOSFET M33, and the drain of MOSFET M34. The gate of MOSFET M34 is used to input the reference voltage Vref. The sources of MOSFET M34 and MOSFET M35 are both grounded. The drain of MOSFET M35 is electrically connected to the gate of MOSFET M21, the gate of MOSFET M25, the drain of MOSFET M25, the source of MOSFET M26, the gate of MOSFET M29, the gate of MOSFET M36, the gate of MOSFET M37, and the gate of MOSFET M38. The drain of MOSFET M21 is electrically connected to the source of MOSFET M22. The gate of MOSFET M22 is electrically connected to the gate of MOSFET M26, the drain of MOSFET M26, the drain of MOSFET M27, and the gate of MOSFET M30. The drain of MOSFET M22 is electrically connected to the drain of MOSFET M23, the gate of MOSFET M23, and the gate of MOSFET M27. The source of MOSFET M23 is electrically connected to the drain of MOSFET M24, the gate of MOSFET M24, and the gate of MOSFET M28. The drain of MOSFET M28 is electrically connected to the source of MOSFET M27. The source of MOSFET M24 is electrically connected to the emitter of transistor Q1. The source of MOSFET M28 is electrically connected to the emitter of transistor Q2 through resistor R3. The base and collector of transistor Q1, the base and collector of transistor Q2 are all grounded. The source of the MOSFET M30 is electrically connected to the drain of the MOSFET M29. The drain of the MOSFET M30 is electrically connected to the emitter of the transistor Q3 through resistor R4, which is used to output the reference voltage Vref. The base and collector of the transistor Q3 are both grounded. The drain of MOSFET M36 is used to output bias current I1, the drain of MOSFET M37 is used to output bias current I2, and the drain of MOSFET M38 is used to output bias current I3.

[0015] In one embodiment, the output voltage detection unit includes resistors R1 and R2. One end of resistor R1 is electrically connected to the drain of the power transistor Mp, and the other end of resistor R1 is grounded through resistor R2, and outputs the detection voltage.

[0016] In one embodiment, the other end of the resistor R1 is also grounded through a capacitor C2.

[0017] The beneficial effects of this invention compared to the prior art are: Firstly, this invention detects changes in the regulated voltage by setting a feedback capacitor Cf and a current amplifier, and feeds the feedback to the input of the buffer. On the one hand, it eliminates the need for a large external capacitor, which facilitates integration and manufacturing; on the other hand, it ensures the transient response performance and AC stability of the LDO regulator circuit. Secondly, by setting up a buffer, impedance matching can be achieved, enabling the power transistor Mp to work better and improving its load capacity, thereby meeting the requirements of high-current loads. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an existing LDO voltage regulator circuit; Figure 2 This is a schematic diagram of the structure of the present invention in the embodiments; Figure 3 This is a circuit diagram of the present invention as shown in the embodiments; Figure 4 This is a circuit diagram of the bandgap reference circuit in the embodiment; Figure 5 for Figure 4 Simulation diagrams of the circuit's input and output under different process angles; Figure 6 This is a loop STB simulation diagram of the circuit of the present invention under different load currents; Figure 7 The image shows the PSRR curves of the circuit of this invention under different loads. Detailed Implementation

[0019] The illustrative embodiments of this application include, but are not limited to, an LDO voltage regulator circuit.

[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0021] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. Words such as “comprising” or “including” mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and does not exclude other elements or objects. Words such as “connected” or “linked” are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0022] like Figure 2 As shown, this embodiment provides an LDO voltage regulator circuit, including an error amplifier 4, a buffer 1, a current amplifier 2, a power transistor Mp, a feedback capacitor Cf, and an output voltage detection unit 3; The source of the power transistor Mp is used to input the external signal Vin, and the drain of the power transistor Mp is used to output the regulated voltage. The output voltage detection unit 3 is used to detect the magnitude of the regulated voltage and input the detected voltage to the negative input terminal of the error amplifier. The positive input terminal of the error amplifier 4 is used to input the reference voltage Vref. The output terminal of the error amplifier 4 is electrically connected to the input terminal of the buffer 1, and the output terminal of the buffer 1 is electrically connected to the gate of the power transistor Mp. One end of the feedback capacitor Cf is electrically connected to the drain of the power transistor Mp, and the other end is electrically connected to the current amplifier 2; the current amplifier 2 is used to amplify the current input by the feedback capacitor Cf and feed it back to the input of the buffer 1.

[0023] In practical use, this invention detects changes in the regulated voltage by setting a feedback capacitor Cf and a current amplifier 2, and feeds the feedback to the input of the buffer 1. On the one hand, it eliminates the need for a large external capacitor, which is convenient for integration and manufacturing; on the other hand, it ensures the transient response performance and AC stability of the LDO voltage regulator circuit. Secondly, by setting buffer 1, impedance matching can be achieved before and after the circuit, enabling the power transistor Mp to work better and improving its load capacity, thereby meeting the requirements of high current loads.

[0024] Furthermore, regarding the feedback capacitor Cf and current amplifier 2, when the LDO voltage regulator circuit of this invention is used, the output voltage will rise as the load current increases. The current amplifier 2 senses the change in output voltage through the current of the feedback capacitor Cf, and then feeds the change in output voltage back to the output terminal of the error amplifier 1, thereby affecting the gate voltage of the power transistor Mp and stabilizing the output voltage. At the same time, the current amplifier 2 and the feedback capacitor Cf, as auxiliary circuits, can also improve the internal structure of the LDO voltage regulator circuit, widening the gap between the major and minor poles of the circuit and effectively enhancing loop stability.

[0025] In this embodiment, the implementation circuit diagram of the LDO voltage regulator circuit is as follows: Figure 3 As shown, in Figure 3 In the middle, error amplifier 4 includes MOS transistors M1-M10; The source of MOSFET M1 and the source of MOSFET M3 are used to input the bias current I1; the gate of MOSFET M1 is used to input the reference voltage Vref, and the gate of MOSFET M3 is used to input the detection voltage; the drain of MOSFET M1 is electrically connected to the drain of MOSFET M2, the gate of MOSFET M2, and the gate of MOSFET M7, respectively, and the source of MOSFET M7 and the source of MOSFET M2 are both grounded; the drain of MOSFET M3 is electrically connected to the drain of MOSFET M4, the gate of MOSFET M4, and the gate of MOSFET M10, respectively, and the source of MOSFET M4 and the source of MOSFET M10 are both grounded; The drain of MOSFET M7 is electrically connected to the source of MOSFET M6. The gate of MOSFET M6 is electrically connected to the drain of MOSFET M6, the drain of MOSFET M5, the gate of MOSFET M5, the gate of MOSFET M8, and the gate of MOSFET M9. The source of MOSFET M9 is electrically connected to the drain of MOSFET M10. The drain of MOSFET M9 is electrically connected to the drain of MOSFET M8. This is the output terminal of the error amplifier. The sources of MOSFET M8 and MOSFET M5 are used to input the external signal Vin.

[0026] In addition, in this embodiment, MOS transistors M1, M3, M5 and M8 are PMOS transistors; MOSFETs M2, M4, M6, M7, M9, and M10 are NMOS transistors.

[0027] for Figure 3 Error amplifier 4 in the circuit is a three-current-mirror operational transconductance amplifier. The low-impedance internal nodes of the error amplifier drive parasitic poles to higher frequencies, thus giving the circuit good loop stability and not significantly affecting the overall performance of the LDO.

[0028] exist Figure 3 In this configuration, the buffer includes a MOSFET M11 and a capacitor Cc. The source of MOSFET M11 is used to input the bias current I3, serving as the output terminal of the buffer, and is also electrically connected to one end of capacitor Cc. The gate of MOSFET M11 is the input terminal of the buffer and is electrically connected to the other end of capacitor Cc. The drain of MOSFET M11 is grounded. Furthermore, MOSFET M11 is a PMOS transistor.

[0029] In practical applications, MOSFET M11 enhances the high-current load capacity of the LDO regulator circuit and matches the impedance of error amplifier 4 and power transistor Mp, thereby improving loop stability. The introduction of buffer 1 adds a low-frequency pole to the circuit, namely the secondary pole at the output of buffer 1, the size of which is determined by the dimensions of MOSFET M11 and power transistor Mp. The presence of capacitor Cc effectively enhances the circuit's linear transient response, stabilizing the circuit during step changes in input voltage, reducing output fluctuations, and improving transient recovery speed.

[0030] Specifically, in Figure 3 In the middle, the current amplifier 2 includes MOSFETs M12-M15 and resistor Rf. The gate of MOSFET M15 is electrically connected to one end of resistor Rf and the other end of feedback capacitor Rf, respectively. The other end of resistor Rf is electrically connected to the drain of MOSFET M15, the source of MOSFET M14 and the gate of MOSFET M13, respectively. The source of MOSFET M13 and the source of MOSFET M15 are both grounded. The drain of MOSFET M14 is electrically connected to the gate of MOSFET M12 and the gate of MOSFET M14 respectively, and is used to input bias current I2. The drain of MOSFET M12 is electrically connected to the drain of MOSFET M13, and the source of MOSFET M12 is electrically connected to the input terminal of buffer 1.

[0031] In addition, MOSFET M12 is a PMOS transistor, while MOSFETs M13, M14, and M15 are NMOS transistors.

[0032] In operation, resistor Rf enhances the circuit's load transient response. It converts the current signal into a voltage signal through feedback capacitor Cf, and simultaneously provides DC bias for MOSFETs M13 and M15, reducing input impedance and making the internal poles of current amplifier 2 greater than the loop's unity-gain frequency. Current amplifier 2 accumulates the signal to the output of error amplifier 4 through MOSFETs M8 and M13. MOSFETs M12 and M14 reduce system offset, improving the accuracy of the current mirror.

[0033] Specifically, in this embodiment, the present invention further includes a bandgap reference circuit, which is used to generate a reference voltage Vref, a bias current I1, a bias current I2, and a bias current I3, and its circuit is as follows: Figure 4 As shown, it includes MOSFETs M21-M38, transistors Q1-Q3, resistors R3 and R4; The source of MOSFET M31 is electrically connected to the sources of MOSFET M21, MOSFET M25, MOSFET M29, MOSFET M36, MOSFET M37 and MOSFET M38 respectively, for input drive power supply VDD; The gate of MOSFET M31 is electrically connected to the drain of MOSFET M31 and the source of MOSFET M32. The gate of MOSFET M32 is electrically connected to the drain of MOSFET M32 and the drain of MOSFET M33. The gate of MOSFET M33 is electrically connected to the gate of MOSFET M35, the source of MOSFET M33, and the drain of MOSFET M34. The gate of MOSFET M34 is used to input the reference voltage Vref. The sources of MOSFET M34 and MOSFET M35 are both grounded. The drain of MOSFET M35 is electrically connected to the gate of MOSFET M21, the gate of MOSFET M25, the drain of MOSFET M25, the source of MOSFET M26, the gate of MOSFET M29, the gate of MOSFET M36, the gate of MOSFET M37, and the gate of MOSFET M38. The drain of MOSFET M21 is electrically connected to the source of MOSFET M22. The gate of MOSFET M22 is electrically connected to the gate of MOSFET M26, the drain of MOSFET M26, the drain of MOSFET M27, and the gate of MOSFET M30. The drain of MOSFET M22 is electrically connected to the drain of MOSFET M23, the gate of MOSFET M23, and the gate of MOSFET M27. The source of MOSFET M23 is electrically connected to the drain of MOSFET M24, the gate of MOSFET M24, and the gate of MOSFET M28. The drain of MOSFET M28 is electrically connected to the source of MOSFET M27. The source of MOSFET M24 is electrically connected to the emitter of transistor Q1. The source of MOSFET M28 is electrically connected to the emitter of transistor Q2 through resistor R3. The base and collector of transistor Q1, the base and collector of transistor Q2 are all grounded. The source of MOSFET M30 is electrically connected to the drain of MOSFET M29. The drain of MOSFET M30 is electrically connected to the emitter of transistor Q3 through resistor R4, which is used to output the reference voltage Vref. The base and collector of transistor Q3 are both grounded. The drain of MOSFET M36 is used to output bias current I1, the drain of MOSFET M37 is used to output bias current I2, and the drain of MOSFET M38 is used to output bias current I3.

[0034] exist Figure 4 In this circuit, MOSFETs M31-M35 form a self-starting circuit to prevent all transistors from having no conducting current during power-up, thus freeing the circuit from the degenerate bias point. Furthermore, MOSFETs M21, M25, and M29 are configured with identical width-to-length ratios to obtain the same leakage current, generating a positive temperature coefficient voltage difference across resistor R3. This voltage difference is then transmitted through a current mirror to the branch containing transistor Q3, causing a negative temperature coefficient low voltage at the base-emitter junction of Q3. By adjusting the value of resistor R3, a zero temperature coefficient reference voltage Vref can be obtained, ensuring that the reference voltage Vref is unaffected by temperature. Finally, by replicating the current through MOSFETs M36, M37, and M38, the bias current can be obtained.

[0035] For the bandgap reference circuit in this embodiment, the input-output curves of the bandgap reference circuit at different process angles are as follows: Figure 5 As shown, in Figure 5 Within the range of 3.6 V to 5.4 V, the output voltage difference of the bandgap reference circuit does not exceed 0.01 V. Furthermore, the voltage temperature drift coefficient of the bandgap reference circuit remains stable within 20 ppm / ℃, exhibiting excellent temperature performance.

[0036] Specifically, in this embodiment, the output voltage detection unit 3 includes resistors R1 and R2. One end of resistor R1 is electrically connected to the drain of the power transistor Mp, and the other end of resistor R1 is grounded through resistor R2, and outputs the detection voltage. In addition, the other end of resistor R1 is also grounded through capacitor C2. Capacitor C2 acts as a compensation capacitor to improve the AC stability of the circuit.

[0037] In this embodiment, the frequency response simulation of the LDO voltage regulator circuit is performed, and the loop STB simulation diagram under different load currents is shown below. Figure 6 As shown, from Figure 6 As can be seen, the performance of the LDO regulator fluctuates under different load conditions, but overall it meets the system stability requirements. Specifically, under no-load conditions, the loop phase margin is approximately 60°, but under light load (1 mA), the loop phase margin improves to 70°. One reason for this is that the output resistance of the power transistor is very high under no-load conditions, causing the output pole of the LDO regulator to be very close to the output pole of the buffer, i.e., the secondary pole of the circuit, which affects the phase margin. Under a 2 A current load, the phase margin can still be maintained at 60°, demonstrating the ability to stabilize large load currents.

[0038] Power Supply Rejection Ratio (PSRR) is another important indicator in LDO (Low Voltage Regulator) circuit design. The PSRR measures the circuit's ability to maintain a stable output when the input fluctuates. It can be seen that the higher the PSRR value, the stronger the LDO's power supply rejection capability. In this embodiment, the PSRR curves of the present invention under different loads are shown below. Figure 7 As shown, in Figure 7 The circuit exhibits optimal performance under light load, with a DC PSRR of approximately 71 dB at a 1 mA load and approximately 35 dB at 100 kHz. Under no-load and 2 A load conditions, the performance is relatively similar. The DC PSRR is approximately 57 dB at no load and approximately 33 dB at 100 kHz; under a 2 A load, the DC PSRR is approximately 55 dB and approximately 21 dB at 100 kHz. The overall PSRR decreases significantly between tens and hundreds of kHz, and the simulation results meet the design requirements of the LDO circuit.

[0039] Based on the above, this embodiment designs an LDO regulator circuit with an input voltage of 3.7 V-5.4 V, an output voltage of 3.3 V, and a quiescent operating current of 90 μA, incorporating a bandgap reference circuit. By adding buffer 1 to match the output of error amplifier 4 with the input impedance of power transistor Mp, the load capacity of the LDO regulator circuit is enhanced, enabling it to handle a large current of 2 A. An external capacitor-free design is implemented, and internal compensation through current amplifier 2 and feedback capacitor Cf ensures loop stability while maintaining a high power supply rejection ratio.

[0040] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An LDO voltage regulator circuit, characterized in that, It includes an error amplifier, a buffer, a current amplifier, a power transistor Mp, a feedback capacitor Cf, and an output voltage detection unit; The source of the power transistor Mp is used to input the external signal Vin, and the drain of the power transistor Mp is used to output the regulated voltage. The output voltage detection unit is used to detect the magnitude of the regulated voltage and input the detected voltage to the negative input terminal of the error amplifier. The positive input terminal of the error amplifier is used to input the reference voltage Vref. The output terminal of the error amplifier is electrically connected to the input terminal of the buffer, and the output terminal of the buffer is electrically connected to the gate of the power transistor Mp. One end of the feedback capacitor Cf is electrically connected to the drain of the power transistor Mp, and the other end is electrically connected to the current amplifier; the current amplifier is used to amplify the current input to the feedback capacitor Cf and feed it back to the input of the buffer.

2. The LDO voltage regulator circuit according to claim 1, characterized in that, The error amplifier includes MOS transistors M1-M10; The source of MOSFET M1 and the source of MOSFET M3 are used to input bias current I1; the gate of MOSFET M1 is used to input reference voltage Vref, and the gate of MOSFET M3 is used to input detection voltage; the drain of MOSFET M1 is electrically connected to the drain of MOSFET M2, the gate of MOSFET M2, and the gate of MOSFET M7, respectively, and the source of MOSFET M7 and the source of MOSFET M2 are both grounded; the drain of MOSFET M3 is electrically connected to the drain of MOSFET M4, the gate of MOSFET M4, and the gate of MOSFET M10, respectively, and the source of MOSFET M4 and the source of MOSFET M10 are both grounded; The drain of MOSFET M7 is electrically connected to the source of MOSFET M6. The gate of MOSFET M6 is electrically connected to the drain of MOSFET M6, the drain of MOSFET M5, the gate of MOSFET M5, the gate of MOSFET M8, and the gate of MOSFET M9. The source of MOSFET M9 is electrically connected to the drain of MOSFET M10, and the drain of MOSFET M9 is electrically connected to the drain of MOSFET M8. This is the output terminal of the error amplifier. The sources of MOSFET M8 and MOSFET M5 are used to input the external signal Vin.

3. The LDO voltage regulator circuit according to claim 2, characterized in that, The MOS transistors M1, M3, M5, and M8 are PMOS transistors; The MOS transistors M2, M4, M6, M7, M9, and M10 are NMOS transistors.

4. An LDO voltage regulator circuit according to claim 2 or 3, characterized in that, The buffer includes a MOSFET M11 and a capacitor Cc. The source of the MOSFET M11 is used to input the bias current I3, which is the output terminal of the buffer, and is also electrically connected to one end of the capacitor Cc. The gate of the MOSFET M11 is the input terminal of the buffer and is electrically connected to the other end of the capacitor Cc. The drain of the MOSFET M11 is grounded.

5. The LDO voltage regulator circuit according to claim 4, characterized in that, The MOS transistor M11 is a PMOS transistor.

6. The LDO voltage regulator circuit according to claim 4, characterized in that, The current amplifier includes MOS transistors M12-M15 and a resistor Rf. The gate of MOS transistor M15 is electrically connected to one end of resistor Rf and the other end of feedback capacitor Rf, respectively. The other end of resistor Rf is electrically connected to the drain of MOS transistor M15, the source of MOS transistor M14, and the gate of MOS transistor M13, respectively. The source of MOS transistor M13 and the source of MOS transistor M15 are both grounded. The drain of MOS transistor M14 is electrically connected to the gate of MOS transistor M12 and the gate of MOS transistor M14 respectively, and is used to input bias current I2. The drain of MOS transistor M12 is electrically connected to the drain of MOS transistor M13, and the source of MOS transistor M12 is electrically connected to the input terminal of the buffer.

7. The LDO voltage regulator circuit according to claim 6, characterized in that, The MOS transistor M12 is a PMOS transistor, and the MOS transistors M13, M14 and M15 are NMOS transistors.

8. An LDO voltage regulator circuit according to claim 6, characterized in that, It also includes a bandgap reference circuit, which is used to generate a reference voltage Vref, a bias current I1, a bias current I2 and a bias current I3, and includes MOSFETs M21-M38, transistors Q1-Q3, resistors R3 and R4; The source of MOSFET M31 is electrically connected to the sources of MOSFET M21, MOSFET M25, MOSFET M29, MOSFET M36, MOSFET M37 and MOSFET M38 respectively, for inputting drive power. The gate of MOSFET M31 is electrically connected to the drain of MOSFET M31 and the source of MOSFET M32. The gate of MOSFET M32 is electrically connected to the drain of MOSFET M32 and the drain of MOSFET M33. The gate of MOSFET M33 is electrically connected to the gate of MOSFET M35, the source of MOSFET M33, and the drain of MOSFET M34. The gate of MOSFET M34 is used to input the reference voltage Vref. The sources of MOSFET M34 and MOSFET M35 are both grounded. The drain of MOSFET M35 is electrically connected to the gate of MOSFET M21, the gate of MOSFET M25, the drain of MOSFET M25, the source of MOSFET M26, the gate of MOSFET M29, the gate of MOSFET M36, the gate of MOSFET M37, and the gate of MOSFET M38. The drain of MOSFET M21 is electrically connected to the source of MOSFET M22. The gate of MOSFET M22 is electrically connected to the gate of MOSFET M26, the drain of MOSFET M26, the drain of MOSFET M27, and the gate of MOSFET M30. The drain of MOSFET M22 is electrically connected to the drain of MOSFET M23, the gate of MOSFET M23, and the gate of MOSFET M27. The source of MOSFET M23 is electrically connected to the drain of MOSFET M24, the gate of MOSFET M24, and the gate of MOSFET M28. The drain of MOSFET M28 is electrically connected to the source of MOSFET M27. The source of MOSFET M24 is electrically connected to the emitter of transistor Q1. The source of MOSFET M28 is electrically connected to the emitter of transistor Q2 through resistor R3. The base and collector of transistor Q1, the base and collector of transistor Q2 are all grounded. The source of the MOSFET M30 is electrically connected to the drain of the MOSFET M29. The drain of the MOSFET M30 is electrically connected to the emitter of the transistor Q3 through resistor R4, which is used to output the reference voltage Vref. The base and collector of the transistor Q3 are both grounded. The drain of MOSFET M36 is used to output bias current I1, the drain of MOSFET M37 is used to output bias current I2, and the drain of MOSFET M38 is used to output bias current I3.

9. The LDO voltage regulator circuit according to claim 1, characterized in that, The output voltage detection unit includes resistors R1 and R2. One end of resistor R1 is electrically connected to the drain of the power transistor Mp, and the other end of resistor R1 is grounded through resistor R2, and outputs the detection voltage.

10. An LDO voltage regulator circuit according to claim 9, characterized in that, The other end of the resistor R1 is also grounded through the capacitor C2.

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