Reset circuit, reset method and chip

Abstract

The application provides a reset circuit, a reset method and a chip, and is suitable for the technical field of chip reset. The reset circuit comprises a processing unit and a reset unit. The processing unit is used for cutting off the transmission channel of the host or slave machine that occurs abnormity and taking over the data transmission in the transmission channel when it is determined that the host or slave machine occurs abnormity, and outputting an abnormal interruption signal to the reset control unit. The reset unit is used for outputting a reset confirmation signal to the reset control unit when it is determined that the data transmission in the transmission channel is completed in response to receiving a reset request signal output by the reset control unit based on the abnormal interruption signal, so that the reset control unit resets the to-be-reset domain, and the to-be-reset domain comprises the host or slave machine that occurs abnormity. The embodiment of the application can separately reset the host or slave machine of the to-be-reset domain, and does not need to reset the whole system, thereby improving the reliability and stability of the chip.

Description

Technical Field

[0001] This application relates to the technical field of chip reset, and more particularly to a reset circuit, reset method and chip. Background Technology

[0002] In existing technologies, the following situations generally exist: (1) If the software receives an exception that the downstream slave has crashed due to an error, the crash of the downstream slave will inevitably cause abnormal behavior of the system bus and the upstream master. (2) If the software receives an exception report that the upstream host master has crashed due to an error, it means that the host master can no longer send new requests or collect request replies, and may have already sent some requests.

[0003] However, since the aforementioned host or slave device malfunctions are unrecoverable and cannot be reset individually, the software can only reset the entire system, including the logic that is still operating normally and has not yet been affected, which greatly reduces the reliability and stability of the chip. Summary of the Invention

[0004] In view of this, embodiments of this application provide a reset circuit, a reset method, and a chip to solve the problem in the prior art that when the host or slave device of a chip malfunctions, only the entire system can be reset.

[0005] A first aspect of this application provides a reset circuit applied to a chip. The reset circuit is connected to the host or slave device of the chip. The reset circuit includes: The processing unit is used to disconnect the transmission channel of the malfunctioning host or slave device and take over the data transmission in the transmission channel when it is determined that the host or slave device has malfunctioned, and output an abnormal interruption signal to the reset control unit. The reset unit is used to respond to a reset request signal output by the reset control unit based on an abnormal interrupt signal. When it is determined that data transmission in the transmission channel is completed, the reset unit outputs a reset confirmation signal to the reset control unit so that the reset control unit resets the domain to be reset, which includes the host or slave that has experienced an abnormality.

[0006] In one possible implementation, the processing unit is used to count the requests and responses of the transmission channel using a timer, and when the time for which the number of requests and responses does not match exceeds a preset threshold, it determines that an abnormality has occurred in the host or slave.

[0007] In one possible implementation, the processing unit is used to complete the request output based on the data length information of the request when it is determined that an exception has occurred in the host.

[0008] In one possible implementation, the processing unit is used to generate an error request response when it is determined that an error has occurred in the slave device, in response to the request response that the slave device did not output and / or the new request output by the master device; the error request response carries an error response identifier.

[0009] In one possible implementation, the reset unit is used to control the port of the transmission channel connected to the reset circuit to apply a pull-down signal when it is determined that data transmission in the transmission channel is complete, so as to control the transmission channel not to receive new requests.

[0010] In one possible implementation, the chip includes a top-level bus and at least one subsystem connected to the top-level bus. Each subsystem includes at least one master and at least one slave. The transmission channel between the top-level bus and the subsystem is connected to at least one reset circuit. The domain to be reset includes the subsystem. The processing unit is used to disconnect the transmission channel between the top-level bus and the subsystem and take over the data transmission in the transmission channel when it determines that an abnormality has occurred in the subsystem, and output an abnormal interrupt signal to the reset control unit.

[0011] In one possible implementation, there are at least two transmission channels between the top-level bus and the subsystem, and each transmission channel is connected to at least one reset circuit. For each reset circuit in the subsystem, each reset unit is used to output a reset confirmation signal to the reset control unit, so that the reset control unit performs an AND operation based on the reset confirmation signal of each reset unit, determines that each reset unit outputs a reset confirmation signal, and resets the domain to be reset in the subsystem.

[0012] A second aspect of this application provides a reset method applied to the reset circuit of the first aspect, the method comprising: When a fault is detected in the master or slave device, the transmission channel of the faulty master or slave device is disconnected and the data transmission in the transmission channel is taken over. An abnormal interrupt signal is output to the reset control unit. In response to receiving a reset request signal from the reset control unit based on an abnormal interruption signal, and upon determining that data transmission in the transmission channel is complete, a reset confirmation signal is output to the reset control unit so that the reset control unit resets the domain to be reset; the domain to be reset includes the host or slave that experienced the abnormality.

[0013] In one possible implementation, upon determining that a host or slave device has malfunctioned, the transmission channel of the malfunctioning host or slave device is disconnected and data transmission in the transmission channel is taken over, including: When it is determined that the host has encountered an error, the request is padded and output based on the data length information of the host's request; Alternatively, when an anomaly is determined to have occurred in the slave device, an error response request is generated for any request responses that the slave device did not output and / or new requests from the master device; the error response request carries an error response identifier.

[0014] A third aspect of the present application provides a chip, including: at least one host, at least one slave, and at least one reset circuit according to the first aspect; Each reset circuit is connected to either the master or slave device.

[0015] Compared with the prior art, the embodiments of this application have at least the following technical effects: The reset circuit of the first aspect of this application is applied to a chip. The reset circuit is connected to the master or slave device of the chip. The reset circuit includes a processing unit and a reset unit. The processing unit of this application embodiment is used to, when it is determined that a master or slave device has malfunctioned, disconnect the transmission channel of the malfunctioning master or slave device and take over the data transmission in the transmission channel, and output an abnormal interrupt signal to the reset control unit. Therefore, by disconnecting the transmission channel of the malfunctioning master or slave device and taking over the data transmission in the transmission channel, this application embodiment can avoid problems such as abnormal behavior of the system bus and upstream master caused by slave device malfunctions, as well as the recovery of some requests already sent by the master and request replies.

[0016] Furthermore, in this embodiment, the reset unit, in response to receiving a reset request signal output by the reset control unit based on an abnormal interrupt signal, outputs a reset confirmation signal to the reset control unit when it determines that data transmission in the transmission channel is complete. This enables the reset control unit to reset the domain to be reset, which includes the host or slave device that experienced the abnormality. Therefore, this embodiment can output a reset confirmation signal to the reset control unit when data transmission in the transmission channel is complete, facilitating the reset of the domain to be reset. This allows for individual reset operations on the host or slave device within the domain to be reset, eliminating the need to reset the entire system. Unaffected circuits in normal operation can continue to run, improving the reliability and stability of the chip.

[0017] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1This is a schematic diagram of a chip frame provided in an embodiment of this application; Figure 2 This is a schematic diagram of the framework of another chip provided in an embodiment of this application; Figure 3 This is a schematic diagram of the framework of another chip provided in the embodiments of this application; Figure 4 This is a schematic diagram of the framework of another chip provided in an embodiment of this application; Figure 5 This is a flowchart of a reset method provided in an embodiment of this application.

[0020] Icon labels: 10 - Top-level bus 10; 20-Subsystem; 30 - Reset circuit; 301 - Processing unit; 302 - Reset unit. Detailed Implementation

[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0022] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0023] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] In the description of this application, unless otherwise stated, the " / " used in this specification and appended claims indicates that the related objects are in an "or" relationship. For example, A / B can mean A or B. The "and / or" in this application merely describes the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c. Here, a, b, and c can be single or multiple.

[0025] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0026] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0027] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0028] Research revealed that once the host computer hangs, its related logic remains in a busy state. Because it cannot receive new request responses, downstream host requests will be blocked on the bus. Furthermore, if a request only sends partial content, it will occupy the arbitration channel on some nodes in the system, preventing other channels from obtaining arbitration rights and causing bus path malfunctions. Simultaneously, since the slave devices fail to receive complete requests, they cannot complete the processing of related request responses according to the protocol. Therefore, in this situation, a full system reset and restart are necessary, which greatly reduces the reliability and stability of the chip.

[0029] Once a slave device hangs up, its related logic will definitely not be able to enter an idle state, and requests sent by the upstream host will not receive a response. The system bus's ability to send multiple requests cannot be recovered. If there is a partial response to the request or if a host is still sending new requests to this slave device, it will occupy the arbitration channel on some nodes of the system, causing other channels to be unable to obtain arbitration rights. Therefore, in this case, only a full system reset and restart can be performed, which will greatly reduce the reliability and stability of the chip.

[0030] The reset circuit 30, reset method, and chip provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0031] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0032] This application provides a chip, including: at least one host, at least one slave, and at least one reset circuit 30 according to this application; each reset circuit 30 is connected to the host or the slave.

[0033] See Figure 1 As shown, this application provides a schematic diagram of a chip framework. Figure 1 As shown, the chip includes a top-level bus 10 and at least one subsystem 20 connected to the top-level bus 10. Each subsystem 20 includes at least one master and at least one slave. A transmission channel between the top-level bus 10 and the subsystem 20 is connected to at least one reset circuit 30.

[0034] Alternatively, the chip can be a system-on-a-chip (SoC).

[0035] See Figure 1As shown, I represents the receiving port, T represents the transmitting port, S0, S1, and S2 represent slave devices, M represents the master device, and subsys_bus represents the subsystem bus. A receiving port I and a transmitting port T of the top-level bus 10 can form a transmission channel. A receiving port I and a transmitting port T of the subsystem bus can also form a transmission channel. The reset circuit 30 can be connected to the receiving port I and / or the transmitting port T. Both the receiving port I and the transmitting port T are ports of the transmission channel.

[0036] See Figure 1 As shown, the reset circuit 30 connected to the host is used to monitor whether the host is abnormally hung. The reset circuit 30 connected between the top-level bus 10 and the subsystem 20 is used to monitor whether the subsystem 20 is abnormally hung.

[0037] This application provides a reset circuit 30, which is applied to a chip and is connected to the chip's host or slave device.

[0038] See Figure 2 As shown in the illustration, this application provides a schematic diagram of another chip's framework. Figure 2 As shown, the reset circuit 30 includes a processing unit 301 and a reset unit 302.

[0039] The processing unit 301 is used to disconnect the transmission channel of the malfunctioning host or slave device and take over the data transmission in the transmission channel when it is determined that the host or slave device has malfunctioned, and output an abnormal interrupt signal to the reset control unit.

[0040] The reset unit 302 is used to respond to the reset request signal output by the reset control unit based on the abnormal interrupt signal. When it is determined that the data transmission in the transmission channel is completed, the reset unit outputs a reset confirmation signal to the reset control unit so that the reset control unit resets the domain to be reset, which includes the host or slave that has experienced an abnormality.

[0041] Optionally, the processing unit 301 can take over the data transmission in the transmission channel and perform operations such as replying to requests that have not been completed or have not been received, or reclaiming new requests, so that the data transmission in the transmission channel is completed.

[0042] Optionally, the domain to be reset is the area that needs to be reset, which may include the host, slave and subsystem that has malfunctioned, and may also include the reset circuit 30.

[0043] Optionally, the processing unit 301 is also used to take over the control signals in the transmission channel.

[0044] The reset circuit 30 in this embodiment is applied to a chip and is connected to the chip's master or slave device. The reset circuit 30 includes a processing unit 301 and a reset unit 302. The processing unit 301, when determining that a master or slave device has malfunctioned, disconnects the transmission channel of the malfunctioning master or slave device and takes over data transmission in the transmission channel, outputting an abnormal interrupt signal to the reset control unit. Therefore, by disconnecting the transmission channel of the malfunctioning master or slave device and taking over data transmission in the transmission channel, this embodiment can avoid problems such as abnormal behavior of the system bus and upstream master caused by slave device malfunctions, as well as the recovery of some requests already sent by the master and request replies.

[0045] Furthermore, in this embodiment, the reset unit 302, in response to receiving a reset request signal output by the reset control unit based on an abnormal interrupt signal, outputs a reset confirmation signal to the reset control unit when it determines that data transmission in the transmission channel is complete. This enables the reset control unit to reset the domain to be reset, which includes the host or slave device that experienced the abnormality. Therefore, this embodiment can output a reset confirmation signal to the reset control unit when data transmission in the transmission channel is complete, facilitating the reset of the domain to be reset. This allows for individual reset operations on the host or slave device within the domain to be reset, without requiring a system-wide reset. Unaffected circuits in normal operation can continue to run, improving the reliability and stability of the chip.

[0046] In some embodiments, the processing unit 301 is used to count the requests and responses of the transmission channel using a timer, and when the time for which the number of requests and responses does not match exceeds a preset threshold, it determines that an abnormality has occurred in the host or slave.

[0047] Optionally, a mismatch between the number of requests and request responses can be caused by a non-zero count value. The timer can increment the count by 1 when a request is detected and decrement the count by 1 when a request response is detected. Thus, when the count value is 0, it can be determined that all requests on the transmission channel have been responded to.

[0048] In some embodiments, the processing unit 301 is configured to complete the request and output it based on the data length information of the request when it is determined that the host has encountered an error.

[0049] In practical applications, if the downstream slave device is already in a state where it can receive and respond to requests, but the upstream host is unable to continue sending requests, then the host will experience an error.

[0050] Optionally, a host exception could be an exception such as only being able to send a portion of the requests, being unable to send requests, or being unable to receive request responses.

[0051] See Figure 3As shown, this application provides a schematic diagram of another chip framework. Figure 3 As shown, slave devices S0 and S1 are connected to a reset circuit 30. The reset circuit 30 connected to the slave devices is used to monitor whether any abnormalities occur in the slave devices. Figure 3 The example only shows some slave devices connected to the reset circuit 30. In practical applications, all or all slave devices can be equipped with the reset circuit 30.

[0052] In some embodiments, the processing unit 301 is configured to generate an error request response for requests not output by the slave device and / or new requests output by the master device when it is determined that an error has occurred in the slave device; the error request response carries an error response identifier.

[0053] Optionally, if the upstream host can send requests normally, but the downstream slave cannot respond to the requests, then the slave is considered to be malfunctioning.

[0054] In practical applications, exceptions that occur on the slave device may include the inability to respond to requests, incomplete responses, or inability to receive requests.

[0055] See Figure 4 As shown in the figure, this application provides a schematic diagram of a chip framework. Figure 4 As shown, the reset circuit 30 includes a processing unit 301 and a reset unit 302.

[0056] In some embodiments, the reset unit 302 is used to control the port of the transmission channel connected to the reset circuit 30 to apply a pull-down signal when it is determined that data transmission in the transmission channel is complete, so as to control the transmission channel not to receive new requests.

[0057] Optionally, the processing unit 301 can monitor the requests and responses of the transmission channel, and the reset unit 302 needs to determine that there is no request data being transmitted in the transmission channel, that is, all requests have been responded to.

[0058] In some embodiments, the chip includes a top-level bus 10 and at least one subsystem 20 connected to the top-level bus 10. Each subsystem 20 includes at least one master and at least one slave. The transmission channel between the top-level bus 10 and the subsystem 20 is connected to at least one reset circuit 30. The domain to be reset includes the subsystem 20. The processing unit 301 is used to disconnect the transmission channel between the top-level bus 10 and the subsystem 20 and take over the data transmission in the transmission channel when it is determined that an abnormality has occurred in the subsystem 20, and output an abnormal interrupt signal to the reset control unit.

[0059] See Figure 1As shown, when a transmission channel exists between the top-level bus 10 and the subsystem 20, the reset circuit 30 can be connected between the receive port I of the top-level bus 10 and the transmit port T of the subsystem bus. The reset circuit 30 can control the receive port I of the top-level bus 10 to apply a low signal, thereby preventing the transmission channel from receiving new requests. The reset circuit 30 connected to the top-level bus 10 is used to control the reset of the subsystem 20. The reset circuit 30 connected to the host M can control the receive port I connected to the subsystem bus to apply a low signal, thereby preventing the transmission channel from receiving new requests.

[0060] See Figure 3 As shown, when a transmission channel exists between the top-level bus 10 and the subsystem 20, the reset circuit 30 can be connected between the transmit port T of the top-level bus 10 and the receive port I of the subsystem bus. The reset circuit 30 can control the transmit port T of the top-level bus 10 to apply a low signal, thereby preventing the transmission channel from receiving new requests. The reset circuit 30 connected to the slave device can control the transmit port T connected to the subsystem bus to apply a low signal, thereby preventing the transmission channel from receiving new requests.

[0061] In some embodiments, there are at least two transmission channels between the top-level bus 10 and the subsystem 20, and each transmission channel is connected to at least one reset circuit 30; For each reset circuit 30 in subsystem 20, each reset unit 302 is used to output a reset confirmation signal to the reset control unit, so that the reset control unit performs an AND operation based on the reset confirmation signal of each reset unit 302, determines that each reset unit 302 outputs a reset confirmation signal, and resets the domain to be reset in subsystem 20.

[0062] See Figure 1 As shown, when there are two transmission channels between the top-level bus 10 and the subsystem 20, two reset circuits 30 can be set up and connected between the transmitting port T of the two top-level buses 10 and the receiving port I of the subsystem bus, respectively. Both reset circuits 30 need to send a reset confirmation signal to the reset control unit in order to realize the reset of the corresponding subsystem 20. Figure 3 The illustrated embodiments and Figure 1 The principle is similar.

[0063] In some embodiments, the reset unit 302 is used to reset the reset circuit 30 in response to the reset signal of the reset control unit; when the reset circuit 30 is reset, it sends a reset completion signal to the reset control unit.

[0064] Resetting the domain to be reset in this application embodiment may include resetting the host or slave device of the domain to be reset by sending a reset signal to the host or slave device. Resetting the domain to be reset may also include resetting the reset circuit 30 of the domain to be reset by sending a reset signal to the reset circuit 30.

[0065] Based on the above technical solutions, please refer to [link / reference]. Figure 1 and Figure 2 As shown, when the software wants to reset a certain part of the transmission channel corresponding to the domain to be reset, the reset circuit 30 of this application embodiment can be added. Taking the reset circuit 30 connected to the host as an example, when the reset circuit 30 is used for reset, its working process includes: 1. When the reset circuit 30 is enabled, its internal counter will start working and counting, and at the same time, it will record the relevant information of the request from the processing unit 301 (e.g., data length information) and the recovery status of the request response.

[0066] 2. When the counter exceeds the preset timeout threshold configured by the software, the processing unit 301 will confirm that the upstream host has hanged, cut off and take over the transmission channel of the upstream host, and report a timeout abnormal interrupt signal.

[0067] 3. Upon receiving a timeout exception interrupt signal, the reset control unit initiates a reset request signal for the suspended logic.

[0068] 4. The reset unit 302 receives a reset request signal from the reset control unit.

[0069] 5. Processing unit 301 completes the transmission of partially sent requests and retrieves unretrieved request replies.

[0070] 6. The reset unit 302 on the corresponding transmission channel starts to complete the transmission of the request data that is being transmitted on the channel according to the current state of the transmission channel. When there is no request data being transmitted in the transmission channel, and the transmission data is determined to be completed, back pressure is applied to the upstream and no new request operations are accepted.

[0071] 7. After the transmission channel is cleared, pull the soft reset ready indicator high and output a reset confirmation signal.

[0072] 8. The reset control unit performs an AND operation on all the reset confirmation signals reported by the reset units 302 on the transmission channel of the domain to be reset, and waits for their values ​​to become 1 before issuing the actual reset operation.

[0073] 9. When the actual reset operation is issued and the field to be reset is reset, the reset unit 302 sends a reset completion signal to notify the software that the reset is complete, and the relevant logic can resume normal operation.

[0074] This application embodiment can take over all data transmission channels of a host in a suspended state; it can complete requests that have been partially sent by the suspended host to prevent abnormal behavior of the system arbitrator and downstream slaves.

[0075] Based on the above technical solutions, please refer to [link / reference]. Figure 3 and Figure 4 As shown, when the software wants to reset a certain part of the transmission channel corresponding to the field to be reset, the reset circuit 30 of this application embodiment can be added. Taking the reset circuit 30 connected to the slave device as an example, when the reset circuit 30 is used for reset, its working process includes: 1. When the reset circuit 30 is enabled, its internal counter will start working and counting, and at the same time, it will record the relevant information of the request from the processing unit 301 (e.g., data length information) and the recovery status of the request response.

[0076] 2. When the transmission channel exceeds the preset timeout threshold configured by the software, the processing unit 301 will confirm that the downstream slave has hung up, disconnect and take over the transmission channel of the downstream slave, and report a timeout abnormal interruption.

[0077] 3. The reset control unit receives a timeout exception interrupt and then initiates a reset request signal for the suspended logic.

[0078] 4. The reset unit 302 receives a reset request signal from the reset control unit.

[0079] 5. The reset unit 302 on the corresponding transmission channel starts to complete the transmission of the request data that is being transmitted on the channel according to the current state of the transmission channel. When there is no request data being transmitted in the transmission channel, and the transmission of data in the transmission channel is completed, back pressure is applied to the upstream and no new request operations are accepted.

[0080] 6. The processing unit 301 performs error request replies for all recorded requests for which no reply has been received. After the reply is completed, it raises the soft reset ready indicator and outputs a reset confirmation signal.

[0081] 7. The reset control unit performs an AND operation on the reset confirmation signals reported by all reset units 302 on the transmission channel of the domain to be reset, and waits for the value to become 1 before issuing the actual reset operation.

[0082] 8. When the actual reset is issued and the field to be reset is reset, the reset unit 302 sends a reset completion signal to notify the software that the reset has been completed, and the relevant logic can resume normal operation.

[0083] This application embodiment can take over the transmission channels of all data of the slave device in a suspended state; it can respond to all recorded unreceived request responses in accordance with the protocol; and after the slave device is suspended, it can accept new requests to prevent requests from blocking the upstream bus.

[0084] The technology described in this application can avoid the need for a full chip reset and restart to restore correct function operation when individual host logic or individual slave logic of the system is stuck, while the rest of the system logic is normal. This can greatly increase the robustness and availability of the chip and the system it is in.

[0085] The reset circuit 30 in this embodiment has a start port to control whether the reset circuit 30 works. It can control the transmission channels that are not desired to be taken over by the reset circuit 30 at certain times, and turn on the relevant functions when needed, thereby increasing the flexibility of the reset circuit 30.

[0086] join Figure 5 As shown, this application provides a flowchart of a reset method. Figure 5 As shown, the reset method of this application embodiment is applied to the reset circuit 30, and the method includes steps S501 to S502.

[0087] S501: When it is determined that the host or slave device is abnormal, the transmission channel of the abnormal host or slave device is cut off and the data transmission in the transmission channel is taken over, and an abnormal interruption signal is output to the reset control unit.

[0088] S502. In response to receiving a reset request signal output by the reset control unit based on an abnormal interrupt signal, when it is determined that data transmission in the transmission channel is completed, a reset confirmation signal is output to the reset control unit so that the reset control unit resets the domain to be reset; the domain to be reset includes the host or slave that has experienced an abnormality.

[0089] In some embodiments, when a host or slave device is determined to be malfunctioning, disconnecting the transmission channel of the malfunctioning host or slave device and taking over data transmission in the transmission channel includes: When it is determined that the host has encountered an error, the request is padded and output based on the data length information of the host's request; Alternatively, when an anomaly is determined to have occurred in the slave device, an error response request is generated for any request responses that the slave device did not output and / or new requests from the master device; the error response request carries an error response identifier.

[0090] The implementation principle of the reset method in this application embodiment is the same as that of the reset circuit 30 in this application embodiment. For the specific reset method, please refer to the detailed description of the reset circuit 30 above.

[0091] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0092] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0093] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the above-described method embodiments.

[0094] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0095] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc. The storage medium can also include combinations of the above types of memory.

[0096] This application provides a computer program product that, when run on a processor, enables the processor to execute the steps described in the various method embodiments above.

[0097] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0098] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0099] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0100] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0101] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A reset circuit, characterized in that, The chip is applied to a chip, wherein the reset circuit is connected to the master or slave of the chip, the chip includes a top-level bus and at least one subsystem connected to the top-level bus, each subsystem includes at least one master and at least one slave, and at least one reset circuit is connected to a transmission channel between the top-level bus and the subsystem. The top-level bus and the subsystem have at least two transmission channels, and at least one reset circuit is connected to each transmission channel. The reset circuit includes: The processing unit is used to disconnect the transmission channel of the malfunctioning host or slave and take over the data transmission in the transmission channel when it is determined that the host or slave has malfunctioned, and output an abnormal interruption signal to the reset control unit. A reset unit is configured to respond to receiving a reset request signal output by the reset control unit based on the abnormal interruption signal, and output a reset confirmation signal to the reset control unit when it is determined that data transmission in the transmission channel is completed, so that the reset control unit resets the domain to be reset, the domain to be reset including the host or slave that has experienced an abnormality; The processing unit is used to complete and output the request based on the data length information of the request when it is determined that the host has encountered an anomaly. The processing unit is used to generate an error request response when it is determined that the slave device has malfunctioned, in response to a request response that the slave device has not output and / or a new request output by the master device; the error request response is marked with an error response identifier. The processing unit is used to disconnect the transmission channel between the top-level bus and the subsystem and take over the data transmission in the transmission channel when it is determined that the subsystem has an abnormality, and output an abnormal interruption signal to the reset control unit. For each of the reset circuits in the subsystem, each reset unit is used to output a reset confirmation signal to the reset control unit, so that the reset control unit performs an AND operation based on the reset confirmation signal of each reset unit to determine that each reset unit outputs a reset confirmation signal and resets the domain to be reset in the subsystem.

2. The reset circuit according to claim 1, characterized in that, The processing unit is used to count the requests and responses of the transmission channel using a timer, and when the time for which the number of requests and responses does not match exceeds a preset threshold, it determines that the host or the slave has malfunctioned.

3. The reset circuit according to claim 1, characterized in that, The reset unit is used to control the port of the transmission channel connected to the reset circuit to apply a pull-down signal when it is determined that data transmission in the transmission channel is completed, so as to control the transmission channel not to receive new requests.

4. A reset method, characterized in that, Applied to the reset circuit as described in any one of claims 1-3, the method comprises: When a fault is detected in the master or slave device, the transmission channel of the faulty master or slave device is disconnected and the data transmission in the transmission channel is taken over, and an abnormal interruption signal is output to the reset control unit. In response to receiving a reset request signal output by the reset control unit based on the abnormal interruption signal, when it is determined that data transmission in the transmission channel is completed, a reset confirmation signal is output to the reset control unit so that the reset control unit resets the domain to be reset; the domain to be reset includes the host or slave that experienced the abnormality. The step of disconnecting the transmission channel of the malfunctioning host or slave device and taking over data transmission in the transmission channel when a malfunction is determined to have occurred includes: When it is determined that the host has encountered an anomaly, the request is completed and output based on the data length information of the request from the host. Alternatively, when it is determined that the slave device has malfunctioned, an error request response is generated for the request response that the slave device did not output and / or the new request from the master device; the error request response carries an error response identifier.

5. A chip, characterized in that, include: At least one host, at least one slave, and at least one reset circuit as described in any one of claims 1-3; Each of the reset circuits is connected to either the host or the slave.

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