Power-on control circuit for high voltage chip

Abstract

This invention discloses a power-on control circuit for a high-voltage chip, comprising: an enable control circuit, used to control the enable terminal to switch from a low-level enable signal to a high-level enable signal when the level signal of the supply voltage is detected to rise to a first set threshold, and to input the voltage divider obtained by resistive voltage division of the supply voltage to an undervoltage circuit; and an undervoltage circuit, used to control the comparator circuit to not operate and output a low-level undervoltage signal to prevent erroneous signals caused by power-on misoperation when a low-level enable signal is detected, and to control the comparator circuit to operate and output a low-level undervoltage signal or a high-level non-undervoltage signal when a high-level enable signal is detected. This invention uses the enable signal output from the enable terminal of the enable control circuit as the enable signal of the undervoltage circuit, preventing the undervoltage signal from erroneously flipping under low voltage conditions due to the different voltage margins of the resistive voltage divider and the reference voltage of the comparator in the undervoltage circuit.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design, and more particularly to a power-on control circuit for a high-voltage chip. Background Technology

[0002] In the field of analog integrated circuit design, the battery undervoltage circuit VBAT_UV, which is used for power-on protection of high-voltage chips in high-voltage battery power supply systems, has obvious shortcomings in terms of performance accuracy, scenario adaptability and reliability. It often causes problems such as abnormal analog circuit parameters and power-on failure due to the battery supply voltage being lower than the threshold.

[0003] like Figure 1A As shown, the current VBAT_UV circuit is a fixed-threshold analog comparator scheme that uses voltage divider resistors to sample the battery voltage. The sampled voltage and the reference voltage are input to the analog comparator. When the sampled value is lower than the reference value, an undervoltage protection signal is triggered, cutting off the power-on circuit of the high-voltage chip or locking the power-on enable. R2 and C1 form an RC filter to prevent the circuit from being affected by power supply voltage fluctuations. R4 acts as a hysteresis filter. VBAT represents a high-level power input, and uvloL represents the output level. Figure 1B As shown, during power-up, when the VBAT voltage gradually increases to the voltage margin required for VCC operation, the VCC voltage begins to gradually increase. When VCC increases to the voltage margin required for VBG operation, VBG increases to a stable reference voltage. Because the voltage divider of the VCC resistor gradually increases with the VCC voltage, a non-undervoltage error signal may be generated during power-up (intersection 1 in the figure). Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defects of poor power-on reliability, poor stability and poor power supply safety of high voltage chips due to false triggering in the prior art, and to provide a power-on control circuit for high voltage chips.

[0005] The present invention solves the above-mentioned technical problems through the following technical solution:

[0006] In a first aspect, the present invention provides a power-on control circuit for a high-voltage chip, the power-on control circuit comprising: a step-down circuit, an enable control circuit, and an undervoltage circuit; one end of the enable control circuit is electrically connected to the step-down circuit, and the other end of the enable control circuit is electrically connected to the undervoltage circuit, the undervoltage circuit comprising a comparator circuit;

[0007] The step-down circuit is used to convert the high-voltage power supply into a low-voltage power supply and to input the power supply voltage to the enable control circuit.

[0008] The enable control circuit is used to control the enable terminal to switch from a low-level enable signal to a high-level enable signal when the level signal of the supply voltage is detected to rise to a first set threshold, and to input the voltage divider obtained by resistor voltage divider of the supply voltage to the undervoltage circuit.

[0009] The undervoltage circuit is used to control the comparator circuit to not work and output a low-level undervoltage signal to prevent erroneous signals caused by power-on misoperation when the low-level enable signal is detected, and to control the comparator circuit to work and output the low-level undervoltage signal or the high-level non-undervoltage signal when the high-level enable signal is detected.

[0010] Preferably, the enable control circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first NMOS transistor, a first inverter, a second inverter, a first voltage divider, and a trigger.

[0011] One end of the first resistor is electrically connected to the output terminal of the buck circuit, the other end of the first resistor is electrically connected to one end of the second resistor, the other end of the second resistor is electrically connected to the third resistor, the other end of the third resistor is electrically connected to one end of the fourth resistor, the other end of the fourth resistor is grounded, the source of the first NMOS transistor is grounded, one end of the fifth resistor is electrically connected to the output terminal of the buck circuit, and the other end of the fifth resistor is electrically connected to the drain of the first NMOS transistor.

[0012] One end of the first inverter is electrically connected to the drain of the first NMOS transistor, the other end of the first inverter is electrically connected to one end of the second inverter, the other end of the second inverter is electrically connected to one end of the flip-flop, and the first voltage divider point is electrically connected to the gate of the first NMOS transistor.

[0013] Preferably, the enable control circuit further includes a second voltage divider point and a third voltage divider point, and the undervoltage circuit further includes a third inverter, a delay circuit, a positive feedback circuit, and a fourth inverter.

[0014] One end of the second voltage divider point is electrically connected to the second resistor and the third resistor, one end of the third voltage divider point is electrically connected to the third resistor and the fourth resistor, and the other end of the second voltage divider point and the other end of the third voltage divider point are electrically connected to one end of the comparator circuit.

[0015] The other end of the comparator circuit is electrically connected to one end of the third inverter, the other end of the third inverter is electrically connected to one end of the delay circuit, the other end of the delay circuit is electrically connected to one end of the positive feedback circuit, and the other end of the positive feedback circuit is electrically connected to one end of the fourth inverter.

[0016] The comparator circuit is configured to output a first low-level signal when the voltage divider is higher than the reference voltage when the high-level enable signal is present, and to output a first high-level signal when the voltage divider is lower than the reference voltage.

[0017] The third inverter is used to convert the received first low-level signal into a second high-level signal and to convert the received first high-level signal into a second low-level signal.

[0018] The delay circuit is used to extend the time for converting the received second high-level signal into a third low-level signal and to extend the time for converting the received second low-level signal into a third high-level signal.

[0019] The positive feedback circuit is used to switch the output from a fourth high-level signal to a fourth low-level signal when the received third low-level signal gradually rises to a second set threshold, and to control the PMOS transistor to turn on to quickly pull the third low-level signal to the third high-level signal.

[0020] The fourth inverter is used to convert the received fourth low-level signal into a fifth high-level signal, and to convert the received fourth high-level signal into a fifth low-level signal.

[0021] Preferably, the undervoltage circuit further includes a buffer, and the other end of the fourth inverter is electrically connected to the buffer;

[0022] The buffer is used to enhance the driving capability of the received fifth high-level signal or the fifth low-level signal, and then output the high-level non-undervoltage signal or the low-level undervoltage signal accordingly.

[0023] Preferably, the comparison circuit includes a second NMOS transistor, a third NMOS transistor, and a comparator;

[0024] The gate of the second NMOS transistor is electrically connected to the output terminal of the fourth inverter, the drain of the second NMOS transistor is electrically connected to the second voltage divider point, and the source of the second NMOS transistor is electrically connected to the negative input terminal of the comparator.

[0025] The gate of the third NMOS transistor is electrically connected to the input terminal of the fourth inverter, the drain of the third NMOS transistor is electrically connected to the third voltage divider point, and the source of the third NMOS transistor is electrically connected to the negative input terminal of the comparator.

[0026] Preferably, the delay circuit includes a fourth NMOS transistor, a first capacitor, and a first current source;

[0027] The drain of the fourth NMOS transistor is electrically connected to the first current source, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is electrically connected to the output terminal of the third inverter.

[0028] One end of the first capacitor is electrically connected to the first current source, and the other end of the first capacitor is grounded.

[0029] Preferably, the positive feedback circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fifth NMOS transistor;

[0030] The source of the first PMOS transistor is electrically connected to the output terminal of the buck circuit, the drain of the first PMOS transistor is electrically connected to the source of the second PMOS transistor, and the gate of the first PMOS transistor is electrically connected to the output terminal of the third inverter.

[0031] The drain of the second PMOS transistor is electrically connected to the gate of the fifth NMOS transistor, and the gate of the second PMOS transistor is electrically connected to the drain of the third PMOS transistor.

[0032] The source of the third PMOS transistor is electrically connected to the output terminal of the buck circuit, the drain of the third PMOS transistor is electrically connected to the input terminal of the fourth inverter, and the gate of the third PMOS transistor is electrically connected to the gate of the fifth NMOS transistor.

[0033] The source of the fifth NMOS transistor is grounded, and the drain of the fifth NMOS transistor is electrically connected to the input terminal of the fourth inverter.

[0034] Preferably, the trigger is an SMIT trigger.

[0035] Preferably, the buck circuit includes a low-dropout linear regulator.

[0036] Preferably, the first current source is a current source provided by the low-voltage power supply.

[0037] The positive and progressive effects of this invention are as follows: It provides a power-on control circuit for a high-voltage chip, and sets an enable control circuit before the undervoltage circuit to prevent the undervoltage signal from erroneously flipping under low voltage conditions due to the different voltage margins of the resistor voltage divider and the reference voltage of the comparator in the undervoltage circuit; It completely solves the problems of poor power-on reliability, poor stability and poor power supply safety caused by false triggering of high-voltage chips. Attached Figure Description

[0038] Figure 1A This is a schematic diagram of the power-on control circuit for high-voltage chips in the prior art.

[0039] Figure 1BThis is a schematic diagram of the output waveform of the power-on control circuit of a high-voltage chip in the prior art.

[0040] Figure 2 This is a first circuit diagram of the power-on control circuit of the high-voltage chip in Example 1.

[0041] Figure 3 This is a second circuit diagram of the power-on control circuit of the high-voltage chip in Example 1.

[0042] Figure 4 This is a schematic diagram of the output waveform of the power-on control circuit of the high-voltage chip in Example 1. Detailed Implementation

[0043] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments described herein.

[0044] Example 1

[0045] like Figure 2 As shown, this embodiment provides a power-on control circuit for a high-voltage chip. The power-on control circuit includes: a step-down circuit 11, an enable control circuit 12, and an undervoltage circuit 13. One end of the enable control circuit 12 is electrically connected to the step-down circuit 11, and the other end of the enable control circuit 12 is electrically connected to the undervoltage circuit 13. The undervoltage circuit 13 includes a comparator circuit.

[0046] The step-down circuit 11 is used to convert the high-voltage power supply into a low-voltage power supply and to input the power supply voltage to the enable control circuit 12.

[0047] The enable control circuit 12 is used to control the enable terminal to switch from a low-level enable signal to a high-level enable signal when the level signal of the supply voltage is detected to rise to a first set threshold, and to input the voltage divider obtained after the supply voltage is divided by a resistor to the undervoltage circuit 13.

[0048] The undervoltage circuit 13 is used to control the comparator circuit to not work and output a low-level undervoltage signal when a low-level enable signal is detected, in order to prevent erroneous signals caused by power-on misoperation. When a high-level enable signal is detected, the comparator circuit is controlled to work and output a low-level undervoltage signal or a high-level non-undervoltage signal.

[0049] Specifically, after the step-down circuit 11 converts the high-voltage power supply to a low-voltage power supply, it detects the voltage value of the high-voltage power supply by detecting the voltage value of the low-voltage power supply. Based on the resistor voltage divider, an enable control circuit 12 is set before the normal undervoltage circuit 13 to ensure that the undervoltage circuit 13 does not operate when the original input voltage corresponding to the high-voltage power supply received by the step-down circuit 11 is less than a certain threshold, thus avoiding the output of erroneous signals. Structurally, the innovative design of adding an enable control circuit 12 before the undervoltage circuit 13 prevents the undervoltage signal from erroneously flipping due to the difference in voltage margin between the resistor voltage divider and the reference voltage of the comparator in the undervoltage circuit 13, ensuring the safety and reliability of the power-on control circuit.

[0050] In one embodiment, such as Figure 3 As shown, the enable control circuit 12 includes a first resistor ( Figure 3 R1 and the second resistor are shown in the figure. Figure 3 R2 and the third resistor are shown in the figure. Figure 3 R3 and the fourth resistor are shown in the figure. Figure 3 R4 and the fifth resistor are shown in the diagram. Figure 3 R5 is shown in the diagram, and the first NMOS transistor is shown in the diagram. Figure 3 The diagram shows MN1), the first inverter ( Figure 3 The diagram shows INV1 and the second inverter ( Figure 3 The diagram shows INV2 and the first voltage divider point (INV2). Figure 3 M1 and the trigger are shown in the diagram;

[0051] One end of the first resistor is electrically connected to the output terminal of the step-down circuit 11, the other end of the first resistor is electrically connected to one end of the second resistor, the other end of the second resistor is electrically connected to the third resistor, the other end of the third resistor is electrically connected to the fourth resistor, the other end of the fourth resistor is grounded, the source of the first NMOS transistor is grounded, one end of the fifth resistor is electrically connected to the output terminal of the step-down circuit 11, and the other end of the fifth resistor is electrically connected to the drain of the first NMOS transistor.

[0052] One end of the first inverter is electrically connected to the drain of the first NMOS transistor, the other end of the first inverter is electrically connected to the second inverter, the other end of the second inverter is electrically connected to one end of the flip-flop, and the first voltage divider point is electrically connected to the gate of the first NMOS transistor.

[0053] The step-down circuit 11 includes a low-dropout linear regulator and a Smith flip-flop.

[0054] Specifically, the low-dropout linear regulator in the buck circuit 11 converts the high-voltage power supply to a low-voltage power supply and then inputs the supply voltage to the enable control circuit 12. As the supply voltage level gradually increases, V1 gradually increases, and the MN1 transistor in the enable control circuit 12 gradually turns on, causing the voltage at point V to flip from a high-level signal to a low-level signal, thereby controlling the enable terminal EN to switch from a low-level enable signal to a high-level enable signal.

[0055] In one embodiment, such as Figure 3 As shown, the enable control circuit 12 also includes a second voltage divider point ( Figure 3 The diagram shows M2 and the third pressure dividing point (M2). Figure 3 M3 is shown in the diagram. The undervoltage circuit 13 also includes a third inverter (M3). Figure 3 The diagram shows INV3), delay circuit 132, positive feedback circuit 133, and fourth inverter (…). Figure 3 (INV4 is shown in the image).

[0056] One end of the second voltage divider point is electrically connected to the second resistor and the third resistor, one end of the third voltage divider point is electrically connected to the third resistor and the fourth resistor, and the other ends of the second voltage divider point and the third voltage divider point are electrically connected to one end of the comparator circuit 131.

[0057] The other end of the comparator circuit 131 is electrically connected to one end of the third inverter, the other end of the third inverter is electrically connected to one end of the delay circuit 132, the other end of the delay circuit 132 is electrically connected to one end of the positive feedback circuit 133, and the other end of the positive feedback circuit 133 is electrically connected to one end of the fourth inverter.

[0058] The comparator circuit 131 is used to output a first low-level signal when the voltage divider is higher than the reference voltage and when the voltage divider is lower than the reference voltage when the high-level enable signal is present.

[0059] The third inverter is used to convert the received first low-level signal into a second high-level signal and to convert the received first high-level signal into a second low-level signal.

[0060] The delay circuit 132 is used to extend the time for converting the received second high-level signal into a third low-level signal and to extend the time for converting the received second low-level signal into a third high-level signal.

[0061] The positive feedback circuit 133 is used to switch the output from a fourth high-level signal to a fourth low-level signal when the received third low-level signal gradually rises to a second set threshold, and to control the PMOS transistor to turn on and quickly pull the third low-level signal to a third high-level signal.

[0062] The fourth inverter is used to convert the received fourth low-level signal into a fifth high-level signal, and to convert the received fourth high-level signal into a fifth low-level signal.

[0063] Specifically, the low-level or high-level enable signal output from the enable terminal of the enable control circuit 12 is used as the enable signal for the undervoltage circuit 13. This ensures that when the enable control circuit 12 detects that the supply voltage level signal has not risen to the first set threshold, it controls the comparator of the undervoltage circuit 13 to not operate, outputting a low-level undervoltage signal to prevent power-on jitter from causing the undervoltage circuit 13 to output an incorrect signal. A positive feedback circuit 133 is added after the delay circuit 132 to accelerate the transient response of the circuit. The inverter MOSFET in the positive feedback circuit 133 uses an inverting ratio transistor to reduce dynamic power consumption.

[0064] In one embodiment, such as Figure 3 As shown, the undervoltage circuit 13 also includes a buffer, with the other end of the fourth inverter connected to the buffer ( Figure 3 The electrical connection of BUF1 is shown in the figure;

[0065] The buffer is used to enhance the driving capability of the received fifth high-level signal or fifth low-level signal, and then output a high-level non-undervoltage signal or a low-level undervoltage signal accordingly.

[0066] Specifically, when the fourth inverter receives an input signal with low drive capability, a buffer is added to provide a stronger current drive capability, which can drive a larger external load. The undervoltage circuit 13, which includes a comparator circuit 131, a third inverter, a delay circuit 132, a positive feedback circuit 133, a fourth inverter, and a buffer, overcomes the problems of low detection accuracy, poor scenario adaptability, and high power consumption in high-voltage chip power-on protection scenarios. It provides core technical support, especially for the safe power-on of high-voltage chips in scenarios such as low-power sensitive portable devices and the sleep mode of new energy vehicles.

[0067] In one embodiment, such as Figure 3 As shown, the comparator circuit 131 includes a second NMOS transistor ( Figure 3 The diagram shows MN2 and the third NMOS transistor ( Figure 3 The diagram shows MN3 and the comparator ( Figure 3 COMP is shown in the image.

[0068] The gate of the second NMOS transistor is electrically connected to the output of the fourth inverter, the drain of the second NMOS transistor is electrically connected to the second voltage divider point, and the source of the second NMOS transistor is electrically connected to the negative input of the comparator COMP.

[0069] The gate of the third NMOS transistor is electrically connected to the input of the fourth inverter, the drain of the third NMOS transistor is electrically connected to the third voltage divider point, and the source of the third NMOS transistor is electrically connected to the negative input of the comparator.

[0070] Specifically, the comparator is controlled to work or not work based on the high or low level of the voltage EN output by the enable terminal of the enable control circuit 12. When the voltage EN is low, the comparator COMP is turned off, the comparator output is low, and thus the undervoltage circuit 13 outputs a low level.

[0071] When voltage EN is high, comparator COMP starts normally, comparing the voltage VN at the negative input terminal of the comparator (connected to the second and third NMOS transistors) with the voltage VBG at the positive input terminal. When voltage VN is higher than voltage VBG, the comparator output voltage V5 is low, and the undervoltage circuit 13 output voltage VBAT_UV is low. When voltage VN is lower than voltage VBG, the comparator output voltage V5 is high, and the undervoltage circuit 13 output voltage VBAT_UV is low, indicating that the circuit is in an undervoltage state.

[0072] In one embodiment, such as Figure 3 As shown, the delay circuit 132 includes a fourth NMOS transistor ( Figure 3 The diagram shows MN4 and the first capacitor ( ). Figure 3 The diagram shows C1 and the first current source (C1). Figure 3 I1 is shown in the middle.

[0073] The drain of the fourth NMOS transistor is electrically connected to the first current source, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is electrically connected to the output of the third inverter.

[0074] One end of the first capacitor is electrically connected to the first current source, and the other end of the first capacitor is grounded.

[0075] The first current source is a current source provided by a low-voltage power supply.

[0076] The positive feedback circuit 133 includes a first PMOS transistor ( Figure 3 MP1 and the second PMOS transistor are shown in the figure. Figure 3 MP2 and the third PMOS transistor are shown in the figure. Figure 3 The image shows MP3 and the fifth NMOS transistor (MP3). Figure 3 (MP5 is shown in the image).

[0077] The source of the first PMOS transistor is electrically connected to the output terminal of the buck converter, the drain of the first PMOS transistor is electrically connected to the source of the second PMOS transistor, and the gate of the first PMOS transistor is electrically connected to the output terminal of the third inverter.

[0078] The drain of the second PMOS transistor is electrically connected to the gate of the fifth NMOS transistor, and the gate of the second PMOS transistor is electrically connected to the drain of the third PMOS transistor.

[0079] The source of the third PMOS transistor is electrically connected to the output of the buck converter, the drain of the third PMOS transistor is electrically connected to the input of the fourth inverter, and the gate of the third PMOS transistor is electrically connected to the gate of the fifth NMOS transistor.

[0080] The source of the fifth NMOS transistor is grounded, and the drain of the fifth NMOS transistor is electrically connected to the input of the fourth inverter.

[0081] Specifically, considering the fluctuations during VCC power-up, the undervoltage circuit 13 is delayed. When the comparator output voltage V5 transitions from low to high, the third inverter output voltage V6 transitions from high to low, the fourth NMOS transistor gradually turns off, the first current source charges the first capacitor, and the voltage V7 gradually increases. When it reaches the threshold of the fifth NMOS transistor, Z flips to low. Due to the long delay time, the gradual increase of voltage V7 is prolonged, meaning the duration of the voltage V7 being at the intermediate level between the third and fifth PMOS transistors is longer. Therefore, the current on VCC is larger during this period, hence the addition of a positive feedback circuit 133 composed of the first, second, third, and fifth NMOS transistors.

[0082] When the voltage V7 increases to the threshold of the fifth NMOS transistor switching, the voltage at point Z changes from high level to low level, and the second PMOS transistor turns on. At this time, the voltage V6 is low level, so the first PMOS transistor is also in the conducting state. The voltage V7 is quickly pulled up to high level. In order to reduce the dynamic power consumption when the switching transistors are switching, the third PMOS transistor and the fifth NMOS transistor are designed as inverting ratio transistors.

[0083] like Figure 4 The diagram shows the output waveform of the power-on control circuit. The horizontal axis represents time, and the vertical axis represents voltage. During power-on, the voltage VBAT gradually increases. When VBAT increases to the voltage margin required for VCC to operate, the voltage VCC gradually increases. When VCC increases to the threshold of the enable control circuit 12, the EN output is a high level equal to the VCC value, and the undervoltage circuit 13 starts working. When the VCC voltage is less than the threshold of the enable control circuit 12, the EN output is a low level of 0V, the undervoltage circuit 13 does not work, and an undervoltage signal is output. Figure 1B The comparison shows that the addition of the enable control circuit 12 effectively prevents the intersection point 1 caused by false triggering when the power is first turned on, leaving only one intersection point.

[0084] In this embodiment, a power-on control circuit for a high-voltage chip is provided, wherein the output signal of the enable terminal of the enable control circuit is used as the enable signal of the undervoltage circuit. This prevents the undervoltage signal from erroneously flipping under low voltage conditions due to the different voltage margins of the resistor voltage divider and the reference voltage of the comparator in the undervoltage circuit. This completely solves the problems of poor power-on reliability, poor stability and poor power supply safety caused by false triggering of the high-voltage chip.

[0085] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.

Claims

1. A power-on control circuit for a high-voltage chip, characterized in that, The power-on control circuit includes: a step-down circuit, an enable control circuit, and an undervoltage circuit; one end of the enable control circuit is electrically connected to the step-down circuit, and the other end of the enable control circuit is electrically connected to the undervoltage circuit, the undervoltage circuit including a comparator circuit; The step-down circuit is used to convert the high-voltage power supply into a low-voltage power supply and to input the power supply voltage to the enable control circuit. The enable control circuit is used to control the enable terminal to switch from a low-level enable signal to a high-level enable signal when the level signal of the supply voltage is detected to rise to a first set threshold, and to input the voltage divider obtained by resistor voltage divider of the supply voltage to the undervoltage circuit. The undervoltage circuit is used to control the comparator circuit to not work and output a low-level undervoltage signal to prevent erroneous signals caused by power-on misoperation when the low-level enable signal is detected, and to control the comparator circuit to work and output the low-level undervoltage signal or the high-level non-undervoltage signal when the high-level enable signal is detected.

2. The power-on control circuit for the high-voltage chip as described in claim 1, characterized in that, The enable control circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first NMOS transistor, a first inverter, a second inverter, a first voltage divider point, and a trigger. One end of the first resistor is electrically connected to the output terminal of the buck circuit, the other end of the first resistor is electrically connected to one end of the second resistor, the other end of the second resistor is electrically connected to the third resistor, the other end of the third resistor is electrically connected to one end of the fourth resistor, the other end of the fourth resistor is grounded, the source of the first NMOS transistor is grounded, one end of the fifth resistor is electrically connected to the output terminal of the buck circuit, and the other end of the fifth resistor is electrically connected to the drain of the first NMOS transistor. One end of the first inverter is electrically connected to the drain of the first NMOS transistor, the other end of the first inverter is electrically connected to one end of the second inverter, the other end of the second inverter is electrically connected to one end of the flip-flop, and the first voltage divider point is electrically connected to the gate of the first NMOS transistor.

3. The power-on control circuit for the high-voltage chip as described in claim 2, characterized in that, The enable control circuit further includes a second voltage divider point and a third voltage divider point, and the undervoltage circuit further includes a third inverter, a delay circuit, a positive feedback circuit, and a fourth inverter. One end of the second voltage divider point is electrically connected to the second resistor and the third resistor, one end of the third voltage divider point is electrically connected to the third resistor and the fourth resistor, and the other end of the second voltage divider point and the other end of the third voltage divider point are electrically connected to one end of the comparator circuit. The other end of the comparator circuit is electrically connected to one end of the third inverter, the other end of the third inverter is electrically connected to one end of the delay circuit, the other end of the delay circuit is electrically connected to one end of the positive feedback circuit, and the other end of the positive feedback circuit is electrically connected to one end of the fourth inverter. The comparator circuit is configured to output a first low-level signal when the voltage divider is higher than the reference voltage when the high-level enable signal is present, and to output a first high-level signal when the voltage divider is lower than the reference voltage. The third inverter is used to convert the received first low-level signal into a second high-level signal and to convert the received first high-level signal into a second low-level signal. The delay circuit is used to extend the time for converting the received second high-level signal into a third low-level signal and to extend the time for converting the received second low-level signal into a third high-level signal. The positive feedback circuit is used to switch the output from a fourth high-level signal to a fourth low-level signal when the received third low-level signal gradually rises to a second set threshold, and to control the PMOS transistor to turn on to quickly pull the third low-level signal to the third high-level signal. The fourth inverter is used to convert the received fourth low-level signal into a fifth high-level signal, and to convert the received fourth high-level signal into a fifth low-level signal.

4. The power-on control circuit for the high-voltage chip as described in claim 3, characterized in that, The undervoltage circuit also includes a buffer, and the other end of the fourth inverter is electrically connected to the buffer. The buffer is used to enhance the driving capability of the received fifth high-level signal or the fifth low-level signal, and then output the high-level non-undervoltage signal or the low-level undervoltage signal accordingly.

5. The power-on control circuit for the high-voltage chip as described in claim 3, characterized in that, The comparison circuit includes a second NMOS transistor, a third NMOS transistor, and a comparator; The gate of the second NMOS transistor is electrically connected to the output terminal of the fourth inverter, the drain of the second NMOS transistor is electrically connected to the second voltage divider point, and the source of the second NMOS transistor is electrically connected to the negative input terminal of the comparator. The gate of the third NMOS transistor is electrically connected to the input terminal of the fourth inverter, the drain of the third NMOS transistor is electrically connected to the third voltage divider point, and the source of the third NMOS transistor is electrically connected to the negative input terminal of the comparator.

6. The power-on control circuit for the high-voltage chip as described in claim 3, characterized in that, The delay circuit includes a fourth NMOS transistor, a first capacitor, and a first current source; The drain of the fourth NMOS transistor is electrically connected to the first current source, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is electrically connected to the output terminal of the third inverter. One end of the first capacitor is electrically connected to the first current source, and the other end of the first capacitor is grounded.

7. The power-on control circuit for the high-voltage chip as described in claim 3, characterized in that, The positive feedback circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fifth NMOS transistor; The source of the first PMOS transistor is electrically connected to the output terminal of the buck circuit, the drain of the first PMOS transistor is electrically connected to the source of the second PMOS transistor, and the gate of the first PMOS transistor is electrically connected to the output terminal of the third inverter. The drain of the second PMOS transistor is electrically connected to the gate of the fifth NMOS transistor, and the gate of the second PMOS transistor is electrically connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is electrically connected to the output terminal of the buck circuit, the drain of the third PMOS transistor is electrically connected to the input terminal of the fourth inverter, and the gate of the third PMOS transistor is electrically connected to the gate of the fifth NMOS transistor. The source of the fifth NMOS transistor is grounded, and the drain of the fifth NMOS transistor is electrically connected to the input terminal of the fourth inverter.

8. The power-on control circuit for the high-voltage chip as described in claim 2, characterized in that, The trigger is a Smith trigger.

9. The power-on control circuit for the high-voltage chip as described in claim 2, characterized in that, The step-down circuit includes a low-dropout linear regulator.

10. The power-on control circuit for the high-voltage chip as described in claim 5, characterized in that, The first current source is the current source provided by the low-voltage power supply.

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