Microinstruction generation method for verifying environment, chip verification method and device

Abstract

The embodiment of the present application discloses a microinstruction generation method, a chip verification method and device for verifying an environment, relates to the technical field of integrated circuits, and can effectively improve the microinstruction generation efficiency of the verification environment under the instruction set evolution expansion. The microinstruction generation method comprises the following steps: obtaining a first microinstruction group formed by decomposing a first instruction, wherein the first instruction is an instruction in a first instruction set; in the case that the first microinstruction group meets a preset condition, converting the first microinstruction group into a second microinstruction group, so as to generate a microinstruction meeting a second instruction specification, the second instruction is an instruction in a second instruction set, and the second instruction set is obtained by evolving and expanding the first instruction set. The present application is suitable for microinstruction generation of the verification environment under the instruction set evolution.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a microinstruction generation method, chip verification method, apparatus, electronic device, and storage medium for a verification environment. Background Technology

[0002] Chip verification is a critical process to ensure that chip designs meet specifications. Chip verification often involves verifying whether the instruction pipeline can correctly process instructions. The instruction pipeline is typically divided into multiple components, such as the fetch unit, decode unit, and execute unit. The decode unit breaks down each instruction into a series of corresponding micro-instructions, which the execute unit then executes. If it is necessary to verify the circuit module downstream of the decode unit in the instruction pipeline, a verification component is needed in the verification environment to generate the micro-instruction sequence. This component then provides the micro-instructions as stimuli to the circuit module to be verified.

[0003] In related technologies, verification components typically model each instruction in the instruction set one-to-one to ensure the completeness and accuracy of the verification stimulus. However, this leads to highly coupled verification code and a rigid structure. Whenever the processor instruction set needs to evolve and expand, the verification component used to generate microinstruction sequences also needs to undergo large-scale structural additions and logical updates, which severely reduces the efficiency of microinstruction generation. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a microinstruction generation method, chip verification method, apparatus, electronic device, and storage medium for a verification environment, which can effectively improve the microinstruction generation efficiency of the verification environment under the condition of instruction set evolution and expansion.

[0005] In a first aspect, embodiments of the present invention provide a microinstruction generation method for a verification environment, comprising: obtaining a first microinstruction group formed by decomposing a first instruction, wherein the first instruction is an instruction in a first instruction set; and, when the first microinstruction group meets preset conditions, converting the first microinstruction group into a second microinstruction group to generate microinstructions that meet a second instruction specification, wherein the second instruction is an instruction in a second instruction set, and the second instruction set is evolved and expanded from the first instruction set.

[0006] In one embodiment, the first instruction has M operands; the step of converting the first microinstruction group into a second microinstruction group when the first microinstruction group meets a preset condition includes: detecting whether the first microinstruction group contains a first target opcode; if the first microinstruction group contains the first target opcode, converting the first microinstruction group into the second microinstruction group, wherein the second instruction formed by the second microinstruction group has N operands, where M and N are both positive integers, and M is less than N.

[0007] In one implementation, the first instruction is a two-operand instruction, and the second instruction is a three-operand instruction.

[0008] In one embodiment, the first microinstruction group includes at least one microinstruction; the step of converting the first microinstruction group into the second microinstruction group when the first microinstruction group contains the first target opcode includes: when the first microinstruction group contains the first target opcode, obtaining the microinstruction containing the first target opcode to obtain the microinstruction to be converted, the microinstruction to be converted having M operands, and each microinstruction in the first microinstruction group other than the microinstruction to be converted being a remaining microinstruction; converting the microinstruction to be converted into a target microinstruction according to a preset conversion rule, wherein the target microinstruction has N operands; and generating the second microinstruction group based on the target microinstruction and the remaining microinstructions.

[0009] In one implementation, the first instruction set corresponds to a first register group, which includes a plurality of first architecture registers; the second instruction set corresponds to a second register group, which includes the first register group and at least one newly added architecture register; the step of converting the first microinstruction group into the second microinstruction group when the first microinstruction group meets preset conditions includes: when the first microinstruction group contains the first architecture register, replacing the first architecture register in the first microinstruction group with the newly added architecture register to obtain the second microinstruction group.

[0010] In one implementation, replacing the first architecture register in the first microinstruction group with the newly added architecture register includes: traversing the replacement methods of each of the first architecture registers in the first microinstruction group by the at least one newly added architecture register, wherein each replacement method forms a corresponding second microinstruction group.

[0011] In one implementation, the first instruction has M operands; the first instruction set corresponds to a first register set, which includes multiple first architecture registers; the second instruction set corresponds to a second register set, which includes the first register set and at least one newly added architecture register; the step of converting the first microinstruction set into the second microinstruction set when the first microinstruction set meets preset conditions includes: detecting whether the first microinstruction set contains a first target opcode; if the first microinstruction set contains the first target opcode, converting the first microinstruction set into an intermediate microinstruction set, wherein the intermediate microinstruction set is used to form an intermediate instruction, the intermediate instruction having N operands, where M and N are both positive integers, and M is less than N; detecting whether the intermediate microinstruction set contains the first architecture register; if the intermediate microinstruction set contains the first architecture register, replacing the first architecture register in the intermediate microinstruction set with the newly added architecture register to obtain the second microinstruction set.

[0012] Secondly, embodiments of the present invention also provide a chip verification method, comprising: generating a second microinstruction group, the second microinstruction group being generated based on a microinstruction generation method for a verification environment provided in embodiments of the present invention; and verifying a module to be verified in a chip based on the second microinstruction group.

[0013] In one embodiment, before verifying the module to be verified in the chip based on the second microinstruction set, the method further includes: acquiring a pre-stored third microinstruction set, the third microinstruction set being used to form a third instruction, wherein the third instruction includes a second target opcode, the second target opcode being an opcode included in the second instruction set but not included in the first instruction set; the verification of the module to be verified in the chip based on the second microinstruction set includes: verifying the module to be verified in the chip based on the second microinstruction set and the third microinstruction set.

[0014] In one embodiment, the verification of the module to be verified in the chip based on the second microinstruction group and the third microinstruction group includes: randomly selecting a target microinstruction group from the first microinstruction group, the second microinstruction group and the third microinstruction group; and sending the target microinstruction group to the module to be verified in the chip to verify the module based on the target microinstruction group.

[0015] In one embodiment, the module to be verified includes an execution component of an instruction pipeline or an instruction dispatch component of an instruction pipeline.

[0016] Thirdly, embodiments of the present invention also provide a microinstruction generation apparatus for a verification environment, comprising: a first acquisition unit, configured to acquire a first microinstruction group formed by decomposing a first instruction, wherein the first instruction is an instruction in a first instruction set; and a conversion unit, configured to convert the first microinstruction group into a second microinstruction group when the first microinstruction group meets preset conditions, so as to generate microinstructions that meet a second instruction specification, wherein the second instruction is an instruction in a second instruction set, and the second instruction set is evolved and expanded from the first instruction set.

[0017] In one embodiment, the first instruction has M operands; the conversion unit includes: a first detection module, configured to detect whether the first microinstruction group contains a first target opcode; and a first conversion module, configured to convert the first microinstruction group into a second microinstruction group if the first microinstruction group contains the first target opcode, wherein the second instruction formed by the second microinstruction group has N operands, where M and N are both positive integers, and M is less than N.

[0018] In one implementation, the first instruction is a two-operand instruction, and the second instruction is a three-operand instruction.

[0019] In one embodiment, the first microinstruction group includes at least one microinstruction; the first conversion module is specifically configured to: when the first microinstruction group contains the first target opcode, obtain the microinstruction containing the first target opcode to obtain a microinstruction to be converted, wherein the microinstruction to be converted has M operands, and each microinstruction in the first microinstruction group other than the microinstruction to be converted is a remaining microinstruction; convert the microinstruction to be converted into a target microinstruction according to a preset conversion rule, wherein the target microinstruction has N operands; and generate a second microinstruction group based on the target microinstruction and the remaining microinstructions.

[0020] In one implementation, the first instruction set corresponds to a first register group, which includes a plurality of first architecture registers; the second instruction set corresponds to a second register group, which includes the first register group and at least one newly added architecture register; the conversion unit is specifically used to replace the first architecture register in the first microinstruction group with the newly added architecture register when the first microinstruction group includes the first architecture register, thereby obtaining the second microinstruction group.

[0021] In one implementation, the conversion unit is specifically used to, when the first microinstruction group includes the first architecture register, traverse the replacement methods of the at least one newly added architecture register for each of the first architecture registers in the first microinstruction group, wherein each replacement method forms a corresponding second microinstruction group.

[0022] In one implementation, the first instruction has M operands; the first instruction set corresponds to a first register group, which includes multiple first architecture registers; the second instruction set corresponds to a second register group, which includes the first register group and at least one newly added architecture register; the conversion unit includes: a second detection module, used to detect whether the first microinstruction group contains a first target opcode; a second conversion module, used to convert the first microinstruction group into an intermediate microinstruction group when the first microinstruction group contains the first target opcode, wherein the intermediate microinstruction group is used to form an intermediate instruction, the intermediate instruction has N operands, where M and N are both positive integers, and M is less than N; a third detection module, used to detect whether the intermediate microinstruction group contains the first architecture register; and a replacement module, used to replace the first architecture register in the intermediate microinstruction group with the newly added architecture register when the intermediate microinstruction group contains the first architecture register, to obtain the second microinstruction group.

[0023] Fourthly, embodiments of the present invention also provide a chip verification apparatus, comprising: a generation unit for generating a second microinstruction group based on a microinstruction generation apparatus for a verification environment provided in embodiments of the present invention; and a verification unit for verifying a module to be verified in a chip based on the second microinstruction group.

[0024] In one embodiment, the chip verification device further includes: a second acquisition unit, configured to acquire a pre-stored third microinstruction group before verifying the module to be verified in the chip based on the second microinstruction group, the third microinstruction group being used to form a third instruction, wherein the third instruction includes a second target opcode, the second target opcode being an opcode included in the second instruction set but not included in the first instruction set; and the verification unit, specifically configured to verify the module to be verified in the chip based on the second microinstruction group and the third microinstruction group.

[0025] In one embodiment, the verification unit includes: a selection module, configured to randomly select a target microinstruction group from the first microinstruction group, the second microinstruction group, and the third microinstruction group; and a sending module, configured to send the target microinstruction group to the module to be verified in the chip, so as to verify the module to be verified based on the target microinstruction group.

[0026] In one embodiment, the module to be verified includes an execution component of an instruction pipeline or an instruction dispatch component of an instruction pipeline.

[0027] Fifthly, embodiments of the present invention also provide an electronic device, the electronic device comprising: a processor and a memory, the processor being electrically connected to the memory; the memory being used to store executable program code; the processor running a program corresponding to the executable program code by reading the executable program code stored in the memory, thereby implementing any of the microinstruction generation methods for verification environments or any of the chip verification methods provided by embodiments of the present invention.

[0028] Sixthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement any of the microinstruction generation methods for verification environments or any of the chip verification methods provided in the embodiments of the present invention.

[0029] The embodiments of the present invention provide a microinstruction generation method, chip verification method, apparatus, electronic device, and computer-readable storage medium for a verification environment, which can obtain a first microinstruction group formed by decomposing a first instruction, and convert the first microinstruction group into a second microinstruction group when the first microinstruction group meets preset conditions. Thus, for a first microinstruction group that meets the preset conditions, the first microinstruction group can be converted into a second microinstruction group without needing to generate a corresponding second microinstruction group by modeling the second instruction. Therefore, it can greatly reduce the verification code supplementation or logic update caused by instruction set evolution and expansion, thereby effectively improving the microinstruction generation efficiency of the verification environment under instruction set evolution and expansion. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A flowchart of a microinstruction generation method for a verification environment provided for embodiments of the present invention; Figure 2 A flowchart of a chip verification method provided in an embodiment of the present invention; Figure 3 A schematic diagram of an instruction pipeline structure in the verification environment of the chip verification method provided in an embodiment of the present invention; Figure 4 A detailed flowchart illustrating a chip verification method provided in an embodiment of the present invention; Figure 5 A schematic diagram of a microinstruction generation apparatus for a verification environment provided in an embodiment of the present invention; Figure 6 A schematic diagram of a chip verification device provided for an embodiment of the present invention; Figure 7 A schematic diagram of an electronic device provided as an embodiment of the present invention. Detailed Implementation

[0032] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0034] In a first aspect, embodiments of the present invention provide a microinstruction generation method for a verification environment, which can effectively improve the microinstruction generation efficiency of the verification environment under the condition of instruction set evolution and expansion.

[0035] like Figure 1 As shown, an embodiment of the present invention provides a microinstruction generation method for a verification environment, comprising: S11, Obtain the first micro-instruction group formed by decomposing the first instruction, wherein the first instruction is an instruction in the first instruction set; An instruction set is a collection of instructions used by a processor to compute and control a computer system. Instruction sets are diverse, including, for example, the x86 instruction set and the ARM instruction set. An instruction set defines the instruction formats, operational functions, and operand fetching methods supported by the processor. It acts as a bridge between software and hardware, largely determining the processor's functionality and performance. Each instruction in an instruction set can be further broken down into one or more microinstructions in the instruction pipeline for execution. One or more microinstructions derived from the same instruction can form a microinstruction set. In contrast to microinstructions, instructions in an instruction set can also be called macroinstructions.

[0036] In embodiments of the present invention, the first instruction set can be any instruction set, such as the x86 instruction set, the ARM instruction set, etc. The first instruction can be any instruction in the first instruction set. In embodiments of the present invention, the first instruction can be further decomposed into a first microinstruction group, which may include one or more microinstructions.

[0037] Specifically, an instruction can consist of operands and an opcode. The opcode determines what kind of operation the instruction performs. For example, `add` determines that the instruction performs an addition operation, and `mov` determines that the instruction performs a move operation. The operands specify the objects to be operated on by the opcode. For example, the operands can be a register name.

[0038] Similarly, in the microinstruction group formed by decomposing instructions, each microinstruction can also include its own opcode and operands. The opcode of a microinstruction determines what operation the microinstruction performs, and the operands specify the objects to be operated on by the opcode in the microinstruction. It should be noted that the opcode and operands in a microinstruction are interchangeable with those in an instruction; for example, `mov` is both the opcode in an instruction and the opcode in a microinstruction.

[0039] S12, when the first microinstruction group meets the preset conditions, the first microinstruction group is converted into a second microinstruction group to generate a microinstruction that meets the second instruction specification. The second instruction is an instruction in the second instruction set, which is evolved and expanded from the first instruction set. In this step, it can be checked whether the first microinstruction group meets preset conditions. If the preset conditions are met, the first microinstruction group can be converted into the second microinstruction group. Accordingly, since the first microinstruction group has changed, the resulting second microinstruction group will no longer correspond to the first instruction, but rather to the second instruction. That is, the second microinstruction group can be used to generate microinstructions that meet the specifications of the second instruction. Here, microinstructions that meet the specifications of the second instruction can mean that the microinstructions in the second microinstruction group correspond to the specifications of the second instruction; that is, if the second instruction is decomposed, the microinstructions in the second microinstruction group can be obtained. Here, the first instruction is an instruction in the first instruction set, and the second instruction is an instruction in the second instruction set. In other words, in this step, by converting the first instruction group into the second instruction group, the conversion from the first instruction to the second instruction is achieved.

[0040] It should be noted that, in the embodiments of the present invention, the first instruction set and the second instruction set are not two unrelated instruction sets. In one implementation, the second instruction set can be evolved and expanded from the first instruction set. That is, the second instruction set can be compatible with the first instruction set and extended based on it. The second instruction set can include all the instructions in the first instruction set. In addition, the second instruction set also includes other instructions that do not exist in the first instruction set.

[0041] The microinstruction generation method for a verification environment provided by embodiments of the present invention can obtain a first microinstruction group formed by decomposing a first instruction, and convert the first microinstruction group into a second microinstruction group when the first microinstruction group meets preset conditions. Thus, for a first microinstruction group that meets the preset conditions, the first microinstruction group can be converted into a second microinstruction group without needing to generate a corresponding second microinstruction group by modeling the second instruction. Therefore, it can greatly reduce the verification code additions or logic updates caused by instruction set evolution and expansion, thereby effectively improving the microinstruction generation efficiency of the verification environment under instruction set evolution and expansion.

[0042] In embodiments of the present invention, the second instruction set is evolved and expanded from the first instruction set. The specific expansion method is not limited. For example, in one implementation, all instructions in the first instruction set do not support three operands, while some instructions in the second instruction set can be three-operand instructions; that is, the second instruction set expands the number of operands in the instructions. This reduces or eliminates pseudo-data dependencies between the destination operand and the source operand, helps improve instruction-level parallelism, and makes processor scheduling and execution more efficient.

[0043] In another implementation, the operands of instructions in the first instruction set may involve a certain number (e.g., 32) of architecture registers, while the operands of instructions in the second instruction set can involve more (e.g., 60) of architecture registers. In other words, the second instruction set expands the number of architecture registers. This significantly increases the number of available registers, effectively reducing register pressure and minimizing performance overhead caused by frequent data exchange between registers and memory.

[0044] Depending on the evolution and expansion method, the way to convert the first microinstruction group corresponding to the first instruction into the second microinstruction group corresponding to the second instruction can also be different. The above situations are explained below.

[0045] First, the evolution and expansion of the second instruction set by increasing the number of operands in the instructions will be explained.

[0046] In one embodiment of the present invention, a first instruction in a first instruction set has M operands. Then, in step S11, a first microinstruction group formed by decomposing the first instruction can be obtained. In step S12, if the first microinstruction group meets a preset condition, converting the first microinstruction group into a second microinstruction group may include: detecting whether the first microinstruction group contains a first target opcode; if the first microinstruction group contains the first target opcode, converting the first microinstruction group into the second microinstruction group, wherein the second instruction formed by the second microinstruction group has N operands, where M and N are both positive integers, and M is less than N. For example, in one example, M equals 2, and N equals 3 or 4; in another example, M equals 3, and N equals 4; and in yet another example, M equals 1, and N equals 2 or 3.

[0047] In this embodiment, the first target opcode can refer to an opcode that involves M operands in an instruction or its corresponding microinstruction in the first instruction set and N operands in an instruction or microinstruction in the second instruction set, such as the addition opcode ADD. The specific number of first target opcodes is not limited; it can be one or more. In one implementation, the first target opcodes can be determined by comparing the instructions and microinstructions in the first and second instruction sets. Accordingly, if the first microinstruction group contains the first target opcode, the first microinstruction group can be converted to the second microinstruction group.

[0048] Specifically, in one implementation, the first microinstruction group may include at least one microinstruction. Therefore, when the first microinstruction group contains the first target opcode, converting the first microinstruction group into the second microinstruction group may specifically include: when the first microinstruction group contains the first target opcode, obtaining the microinstruction containing the first target opcode to obtain the microinstruction to be converted, the microinstruction to be converted having M operands, and the remaining microinstructions in the first microinstruction group excluding the microinstruction to be converted; converting the microinstruction to be converted into a target microinstruction according to a preset conversion rule, wherein the target microinstruction has N operands; and generating the second microinstruction group based on the target microinstruction and the remaining microinstructions.

[0049] In this embodiment, a microinstruction containing a first target opcode can be found from the first microinstruction group, and this microinstruction can be used as the microinstruction to be converted. Furthermore, the microinstruction to be converted can be converted into a target microinstruction according to a preset conversion rule, thereby converting a microinstruction containing M operands into a microinstruction containing N operands. For example, if the microinstruction to be converted is ADD R1, R2, the target microinstruction obtained after conversion is ADD R1, R2, R3.

[0050] In one implementation, microinstructions in the first instruction set and the second instruction set that have the same opcode but different numbers of operands can be statistically analyzed to obtain the correspondence between microinstructions containing M operands and microinstructions containing N operands, and the aforementioned preset conversion rule can be formed based on this correspondence.

[0051] Furthermore, after converting the microinstruction to be converted into the target microinstruction, a second microinstruction group can be generated based on the target microinstruction and the remaining microinstructions. Thus, converting the first microinstruction group into the second microinstruction group means converting the microinstruction to be converted in the first microinstruction group into the target microinstruction, while leaving the remaining microinstructions in the first microinstruction group unchanged. The remaining microinstructions, together with the target microinstruction, form the second microinstruction group.

[0052] For example, in one scenario, M equals 2 and N equals 3. The first microinstruction group formed by decomposing the first instruction includes two microinstructions, uinst1 and uinst2. Microinstruction uinst1 contains the first target opcode, so it can be used as the microinstruction to be converted and transformed into the target microinstruction uinst11 (where uinst1 is a two-operand microinstruction and uinst11 is a three-operand microinstruction). Microinstruction uinst2 does not contain the first target opcode; therefore, uinst2 is the remaining microinstruction. A second microinstruction group is generated based on the target microinstruction uinst11 and the remaining microinstruction uinst2. This second microinstruction group can include two microinstructions: the target microinstruction uinst11 and the remaining microinstruction uinst2.

[0053] The following explains the evolution and expansion of the second instruction set by increasing the number of architecture registers.

[0054] In one embodiment of the present invention, a first instruction set corresponds to a first register group, which includes a plurality of first architecture registers; a second instruction set corresponds to a second register group, which includes the first register group and at least one newly added architecture register. Based on this, converting the first microinstruction group into a second microinstruction group when the first microinstruction group meets preset conditions can specifically include: if the first microinstruction group contains the first architecture register, replacing the first architecture register in the first microinstruction group with the newly added architecture register to obtain the second microinstruction group.

[0055] In this embodiment, the first instruction set corresponds to the first register set, meaning that the operands in the first instruction set involve registers in the first register set, i.e., including first architecture registers. The second instruction set corresponds to the second register set, meaning that the operands in the second instruction set involve registers in the second register set. The second register set includes the first register set and also includes newly added architecture registers; that is, the second register set includes all registers in the first register set plus other architecture registers. It should be noted that the number of operands contained in each microinstruction in the first instruction set is unlimited. That is, regardless of how many operands a microinstruction in the first instruction set has, as long as these operands include first architecture registers, then newly added architecture registers can be used to replace the first architecture registers.

[0056] Specifically, when replacing the first architecture register in the first microinstruction group with a newly added architecture register, one newly added architecture register can be used to replace one first architecture register in the first microinstruction group, or multiple newly added architecture registers can be used to replace different first architecture registers in the first microinstruction group respectively. The embodiments of the present invention do not limit this.

[0057] For example, in one implementation, replacing the first architecture register in the first microinstruction group with the newly added architecture register may include: traversing the replacement methods of each of the first architecture registers in the first microinstruction group by the at least one newly added architecture register, wherein each replacement method forms a corresponding second microinstruction group, so that the second microinstruction group can cover a wider range of the second instruction set, thereby effectively improving the completeness of chip verification.

[0058] For example, in one instance, the first instruction set corresponds to the first register set, which includes four first-architecture registers: ax, bx, cx, and dx. The second instruction set corresponds to the second register set, which also includes four first-architecture registers: ax, bx, cx, and dx, and two newly added architecture registers: ex and fx. If the first microinstruction set includes two microinstructions, where one microinstruction u1 includes two first-architecture registers (e.g., mov ax, bx), and the other microinstruction u2 does not include any first-architecture registers, then the newly added architecture registers ex and fx can be used to replace the first-architecture registers ax and bx in the first microinstruction set u1, respectively, to obtain the second microinstruction set. Each replacement method corresponds to one second microinstruction set. For example, in one instance, after the above register replacements, six second microinstruction sets can be obtained. Second microinstruction set 1 can include microinstruction u11 mov ex, bx and microinstruction u2, and second microinstruction set 2 can include u12 mov ax, ex and microinstruction u2. The second microinstruction group 3 may include microinstruction u13 mov fx, bx and microinstruction u2; the second microinstruction group 4 may include microinstruction u14 mov ax, fx and microinstruction u2; the second microinstruction group 5 may include microinstruction u15 mov ex, fx and microinstruction u2; and the second microinstruction group 6 may include microinstruction u16 mov fx, ex and microinstruction u2.

[0059] In the foregoing embodiments, the expansion of the number of operands and the expansion of the number of architecture registers in the second instruction set were described separately, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the two can be combined, that is, the second instruction set can simultaneously expand the number of operands and the number of architecture registers. Based on this, when converting the first microinstruction set to the second microinstruction set, the corresponding conversion methods can also be combined.

[0060] Specifically, in one embodiment of the present invention, a first instruction has M operands; a first instruction set corresponds to a first register group, which includes multiple first architecture registers; a second instruction set corresponds to a second register group, which includes the first register group and at least one newly added architecture register. Based on this, when the first microinstruction group meets preset conditions, converting the first microinstruction group into a second microinstruction group may include: detecting whether the first microinstruction group contains a first target opcode; if the first microinstruction group contains the first target opcode, converting the first microinstruction group into an intermediate microinstruction group, wherein the intermediate microinstruction group is used to form an intermediate instruction, the intermediate instruction having N operands, where M and N are both positive integers, and M is less than N; detecting whether the intermediate microinstruction group contains the first architecture register; if the intermediate microinstruction group contains the first architecture register, replacing the first architecture register in the intermediate microinstruction group with the newly added architecture register to obtain the second microinstruction group.

[0061] In this embodiment, the first microinstruction group containing the first target opcode can be converted into an intermediate microinstruction group, thereby enabling the intermediate microinstruction group to form intermediate instructions and expand the number of operands. Then, the first architecture register in the intermediate microinstruction group is replaced with a new architecture register, thereby expanding the architecture register and obtaining the second microinstruction group.

[0062] Secondly, embodiments of the present invention also provide a chip verification method that can effectively improve chip verification efficiency in the case of instruction set evolution and expansion.

[0063] like Figure 2 As shown, the chip verification method provided by the embodiments of the present invention may include: S21, Generate a second microinstruction group, which is generated based on the microinstruction generation method for verification environment provided in the embodiments of the present invention; The specific implementation method for this step has been explained in detail above, and will not be repeated here.

[0064] S22, the module to be verified in the chip is verified based on the second microinstruction group.

[0065] The chip verification method provided by the embodiments of the present invention can generate a second microinstruction group based on the microinstruction generation method for the verification environment provided by the embodiments of the present invention. Therefore, it can effectively improve the microinstruction generation efficiency of the verification environment under the condition of instruction set evolution and expansion. Furthermore, verifying the module to be verified in the chip based on such a second microinstruction group can also effectively improve the chip verification efficiency under the condition of instruction set evolution and expansion.

[0066] In embodiments of the present invention, after generating the second microinstruction set according to the aforementioned microinstruction generation method for a verification environment, the module to be verified in the chip can be verified based on the second microinstruction set in step S22. For example, in one embodiment, verifying the module to be verified can be performed in a verification environment, using the second microinstruction set as a stimulus to verify the design code of the module to be verified. Here, the module to be verified can be a component downstream of the decoding unit in the instruction pipeline. For example, in one example, the module to be verified can include the execution unit or the instruction dispatch unit of the instruction pipeline.

[0067] The foregoing embodiments detailed how to convert the first microinstruction set corresponding to the first instruction into the second microinstruction set corresponding to the second instruction when the second instruction set expands the number of operands and the number of architecture registers. However, the embodiments of the present invention are not limited to this. In some implementations, the second instruction set may also include instruction types that do not exist in the first instruction set at all, and therefore are inconvenient to convert from the first instruction set. For example, in the x86 apx instruction set, instructions such as PUSH2 and POP2 have been added to support stack operations on 128-bit data at a time, in order to optimize the stack access efficiency of wide data blocks and improve the execution throughput of related instruction sequences. Among them, instructions such as PUSH2 and POP2 are instruction types that do not exist in the original x86 instruction set.

[0068] Based on this, before verifying the module to be verified in the chip based on the second microinstruction group in step S22, the chip verification method provided by the embodiments of the present invention may further include: acquiring a pre-stored third microinstruction group, the third microinstruction group being used to form a third instruction, wherein the third instruction includes a second target opcode, the second target opcode being an opcode included in the second instruction set and not included in the first instruction set; the verification of the module to be verified in the chip based on the second microinstruction group includes: verifying the module to be verified in the chip based on the second microinstruction group and the third microinstruction group.

[0069] In this embodiment, a third microinstruction set is pre-stored, and the third microinstruction set, together with the second microinstruction set, is used to verify the module to be verified in the chip. The third microinstruction set can be used to form a third instruction. The second target opcode in the third instruction exists only in the second instruction set and does not exist in the first instruction set. In this way, the third microinstruction set is used to supplement the instruction types that do not exist in the first instruction set, thereby further improving the verification coverage of the second instruction set in the case of instruction set evolution and expansion.

[0070] It should be noted that, in the embodiments of the present invention, since the second instruction set is an evolution and expansion of the first instruction set, most of the instructions and microinstructions in the second instruction set can be found in the first instruction set. Therefore, they can be obtained by converting the microinstruction groups formed by decomposing the instructions in the first instruction set, greatly reducing the need for verification code additions or logic updates. Thus, the chip verification efficiency under instruction set evolution and expansion scenarios can be significantly improved. Furthermore, a small number of instructions in the second instruction set may not have corresponding prototypes in the first instruction set. Therefore, the corresponding microinstruction groups, i.e., the third microinstruction group, can be pre-stored. During chip verification, the pre-stored third microinstruction group can be used together with the second microinstruction group for verification. In this way, there is no need to implement the conversion between instructions and the third microinstruction group through logic code, thus further improving the chip verification efficiency under instruction set evolution and expansion scenarios.

[0071] In one implementation, verifying the module to be verified in the chip based on the second and third microinstruction sets may specifically include: randomly selecting a target microinstruction set from the first, second, and third microinstruction sets; sending the target microinstruction set to the module to be verified in the chip to verify the module based on the target microinstruction set. In this way, instructions in the second instruction set that are compatible with the first instruction set can be covered by the first microinstruction set; instructions in the second instruction set that can be converted from the first instruction set can be covered by the second microinstruction set; and instructions in the second instruction set that cannot be converted from the first instruction set can be covered by the third microinstruction set. This allows for more thorough and complete verification of the module to be verified in the chip as the instruction set evolves and expands.

[0072] like Figure 3 As shown, in one embodiment of the present invention, the module to be verified is the execution unit of an instruction pipeline. A decoding verification component is built in the verification environment to simulate the decoding component of the instruction pipeline, and a dispatch verification component is built to simulate the instruction dispatch component of the instruction pipeline. The decoding verification component can provide a first microinstruction group, the microinstruction group conversion component can provide a second microinstruction group, and the microinstruction group storage component can provide a third microinstruction group. The first, second, and third microinstruction groups can serve as three sources of instructions for the second instruction set. By random selection, different first, second, and third microinstruction groups are input into the microinstruction queue of the dispatch verification component. Furthermore, the microinstruction queue is sequentially passed through a static constraint detector, a dynamic constraint detector, and a token manager before being sent to the module to be verified—the execution unit. The execution unit can execute each microinstruction in the microinstruction group, thereby achieving verification of the execution unit.

[0073] The main components of an instruction pipeline may include: T0 Instruction Queue: In dual-threaded mode, it is used to store all instructions to be tested from thread 0.

[0074] T1 Instruction Queue: In dual-threaded mode, it is used to store all instructions to be tested from thread 1.

[0075] Instruction-to-microinstruction converter: Used to convert instructions into microinstructions that can be recognized by the execution unit. After conversion, the opcode and operands (including source operands, destination operands, etc.) of the microinstruction are obtained.

[0076] Microinstruction group conversion component: Used to convert the first microinstruction group into the second microinstruction group when the first microinstruction group meets the preset conditions.

[0077] Microinstruction group storage component: used to store the third microinstruction group.

[0078] Microinstruction queue: Used to store microinstructions generated by various threads in a mixed manner.

[0079] Static constraint detector: Microinstructions in the microinstruction queue are constrained to limit and regulate their dispatch behavior. One of these constraints is static constraint. The static constraint detector will detect the microinstructions in the microinstruction queue in sequence, group them in order, and each group of microinstructions will be dispatched to the design module under test in the same clock cycle.

[0080] Dynamic Limit Detector: A set of microinstructions that have passed the static limit detector will be sent to the dynamic limit detector, which will calculate the token consumption of these microinstructions and compare it with the current token reserve of the processor to determine whether these microinstructions will be dispatched in the next clock cycle.

[0081] Token Manager: Establishes a dynamic token management mechanism: tracks token consumption during microinstruction dispatch and token return after execution, and updates the available token balance of the processor in real time.

[0082] Design Module to be Verified: The design code of the module to be verified, which in this case is the design code of the execution component.

[0083] Exception collector: Collects exception events encountered during the execution of the module to be verified and sends them to the exception handler for processing.

[0084] Exception handler: Analyzes exception events received from the exception collector and takes different measures to deal with various exceptions generated by the processor, with the aim of restoring the normal execution process of the processor.

[0085] The information flow in an instruction pipeline can mainly include: (a) The collected instructions are sent to the instruction-microinstruction decoder to be converted into microinstruction sets.

[0086] (b) Send the microinstruction group to the microinstruction queue for dispatch.

[0087] (l) Send the microinstruction group into the microinstruction group conversion component to obtain the second microinstruction group.

[0088] (m) Store the second microinstruction group into the microinstruction queue.

[0089] (n) Randomly retrieve the pre-stored third microinstruction group and store it in the microinstruction queue.

[0090] (c) Take microinstructions out of the microinstruction queue and perform static constraint checks to determine which microinstructions can be dispatched in the same clock cycle.

[0091] (d) Send the statically tested microinstructions to the dynamic limit detector.

[0092] (e) The token manager informs the dynamic limit detector of the current remaining amount of all tokens in the processor.

[0093] (f) If the dynamic limit detection passes, the dynamic limit detector will inform the token manager of the token consumption of the microinstruction to be dispatched.

[0094] (g) Send microinstructions to the module to be verified.

[0095] (h) If an exception occurs during the execution of microinstructions by the module to be verified, the exception information is sent to the exception collector.

[0096] (i) The exception collector collects exceptions, processes them according to thread, and sends them to the exception handler.

[0097] (j) The exception handler takes corresponding actions depending on the exception type, including redeploying new instructions.

[0098] (k) After the design module to be verified has executed the microinstruction, it will return the token of the microinstruction to the token manager.

[0099] The chip verification method provided by the present invention will be described in detail below through a specific embodiment.

[0100] like Figure 4 As shown, the chip verification method provided by the embodiments of the present invention may include: S301. Obtain the first micro-instruction group formed by decomposing the first instruction, wherein the first instruction is an instruction in the first instruction set.

[0101] The first instruction has M operands.

[0102] S302. Detect whether the first microinstruction group contains the first target opcode; S303. If the first microinstruction group contains a first target opcode, convert the first microinstruction group into an intermediate microinstruction group; The intermediate microinstruction group is used to form intermediate instructions. Each intermediate instruction has N operands, where M and N are both positive integers, and M is less than N. S304. Detect whether the intermediate microinstruction group contains the first architecture register; S305. If the intermediate microinstruction group contains the first architecture register, replace the first architecture register in the intermediate microinstruction group with the newly added architecture register to obtain the second microinstruction group.

[0103] S306. Obtain a pre-stored third microinstruction group, which is used to form a third instruction. The third instruction includes a second target opcode, which is an opcode included in the second instruction set but not included in the first instruction set.

[0104] S307. Randomly select a target microinstruction group from the first microinstruction group, the second microinstruction group, and the third microinstruction group; S308. Send the target microinstruction group to the module to be verified in the chip to verify the module to be verified based on the target microinstruction group.

[0105] Thirdly, embodiments of the present invention provide a microinstruction generation apparatus for a verification environment, which can effectively improve the microinstruction generation efficiency of the verification environment under the condition of instruction set evolution and expansion.

[0106] like Figure 5 As shown, the microinstruction generation apparatus for verifying an environment provided by the present invention may include: The first acquisition unit 41 is used to acquire the first micro-instruction group formed by decomposing the first instruction, wherein the first instruction is an instruction in the first instruction set; The conversion unit 42 is used to convert the first microinstruction group into a second microinstruction group when the first microinstruction group meets the preset conditions, so as to generate a microinstruction that meets the second instruction specification. The second instruction is an instruction in the second instruction set, which is evolved and expanded from the first instruction set.

[0107] The microinstruction generation apparatus for a verification environment provided in the embodiments of the present invention can acquire a first microinstruction group formed by decomposing a first instruction, and convert the first microinstruction group into a second microinstruction group when the first microinstruction group meets preset conditions. In this way, for a first microinstruction group that meets the preset conditions, the first microinstruction group can be converted into a second microinstruction group without needing to generate a corresponding second microinstruction group by modeling the second instruction. Therefore, it can greatly reduce the verification code supplementation or logic update caused by instruction set evolution and expansion, thereby effectively improving the microinstruction generation efficiency of the verification environment under instruction set evolution and expansion.

[0108] In one embodiment, the first instruction has M operands; the conversion unit 42 includes: The first detection module is used to detect whether the first microinstruction group contains the first target opcode; The first conversion module is used to convert the first microinstruction group into the second microinstruction group when the first microinstruction group contains the first target opcode, wherein the second instruction formed by the second microinstruction group has N operands, where M and N are both positive integers and M is less than N.

[0109] In one implementation, the first instruction is a two-operand instruction, and the second instruction is a three-operand instruction.

[0110] In one embodiment, the first microinstruction group includes at least one microinstruction; the first conversion module is specifically configured to: when the first microinstruction group contains the first target opcode, obtain the microinstruction containing the first target opcode to obtain a microinstruction to be converted, wherein the microinstruction to be converted has M operands, and each microinstruction in the first microinstruction group other than the microinstruction to be converted is a remaining microinstruction; convert the microinstruction to be converted into a target microinstruction according to a preset conversion rule, wherein the target microinstruction has N operands; and generate a second microinstruction group based on the target microinstruction and the remaining microinstructions.

[0111] In one implementation, the first instruction set corresponds to a first register group, which includes a plurality of first architecture registers; the second instruction set corresponds to a second register group, which includes the first register group and at least one newly added architecture register; the conversion unit 42 is specifically used to replace the first architecture register in the first microinstruction group with the newly added architecture register when the first microinstruction group includes the first architecture register, to obtain the second microinstruction group.

[0112] In one implementation, the conversion unit 42 is specifically configured to, when the first microinstruction group includes the first architecture register, traverse the replacement methods of the at least one newly added architecture register for each of the first architecture registers in the first microinstruction group, wherein each replacement method forms a corresponding second microinstruction group.

[0113] In one implementation, the first instruction has M operands; the first instruction set corresponds to a first register group, which includes multiple first architecture registers; the second instruction set corresponds to a second register group, which includes the first register group and at least one newly added architecture register; the conversion unit 42 includes: a second detection module, used to detect whether the first microinstruction group contains a first target opcode; a second conversion module, used to convert the first microinstruction group into an intermediate microinstruction group when the first microinstruction group contains the first target opcode, wherein the intermediate microinstruction group is used to form an intermediate instruction, the intermediate instruction has N operands, where M and N are both positive integers, and M is less than N; a third detection module, used to detect whether the intermediate microinstruction group contains the first architecture register; and a replacement module, used to replace the first architecture register in the intermediate microinstruction group with the newly added architecture register when the intermediate microinstruction group contains the first architecture register, to obtain the second microinstruction group.

[0114] Fourthly, embodiments of the present invention also provide a chip verification apparatus that can effectively improve chip verification efficiency in the case of instruction set evolution and expansion.

[0115] like Figure 6 As shown, the chip verification apparatus provided in the embodiments of the present invention may include: Generation unit 51 is used to generate a second microinstruction group based on the microinstruction generation device for verification environment provided in the embodiments of the present invention; Verification unit 52 is used to verify the module to be verified in the chip based on the second microinstruction group.

[0116] The chip verification apparatus provided in the embodiments of the present invention can generate a second microinstruction group based on the microinstruction generation apparatus for the verification environment provided in the embodiments of the present invention. Therefore, it can effectively improve the microinstruction generation efficiency of the verification environment in the case of instruction set evolution and expansion. Furthermore, verifying the module to be verified in the chip based on such a second microinstruction group can also effectively improve the chip verification efficiency in the case of instruction set evolution and expansion.

[0117] In one embodiment, the chip verification device further includes: a second acquisition unit, configured to acquire a pre-stored third microinstruction group before verifying the module to be verified in the chip based on the second microinstruction group, the third microinstruction group being used to form a third instruction, wherein the third instruction includes a second target opcode, the second target opcode being an opcode included in the second instruction set but not included in the first instruction set; and a verification unit 52, specifically configured to verify the module to be verified in the chip based on the second microinstruction group and the third microinstruction group.

[0118] In one embodiment, the verification unit 52 includes: a selection module, configured to randomly select a target microinstruction group from the first microinstruction group, the second microinstruction group, and the third microinstruction group; and a sending module, configured to send the target microinstruction group to the module to be verified in the chip, so as to verify the module to be verified based on the target microinstruction group.

[0119] In one embodiment, the module to be verified includes an execution component of an instruction pipeline or an instruction dispatch component of an instruction pipeline.

[0120] Fifthly, embodiments of the present invention also provide an electronic device that can effectively improve the microinstruction generation efficiency or chip verification efficiency of the verification environment under instruction set evolution and expansion.

[0121] like Figure 7 As shown, the electronic device provided in the embodiments of the present invention may include: a processor 71 and a memory 72, wherein the processor 71 and the memory 72 are electrically connected; the memory 72 is used to store executable program code; the processor 71 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 72, so as to implement any of the microinstruction generation methods for verification environments or any of the chip verification methods provided in the foregoing embodiments.

[0122] The specific execution process of the above steps by the processor 71, as well as the steps further executed by the processor 71 by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0123] Sixthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the microinstruction generation methods for verification environments or any of the chip verification methods provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0124] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0125] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0126] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0127] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0128] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0129] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for generating microinstructions for a verification environment, characterized in that, include: Obtain the first micro-instruction group formed by decomposing the first instruction, wherein the first instruction is an instruction in the first instruction set; If the first microinstruction group meets the preset conditions, the first microinstruction group is converted into a second microinstruction group to generate microinstructions that meet the second instruction specification. The second instruction is an instruction in the second instruction set, which is evolved and expanded from the first instruction set.

2. The microinstruction generation method for a verification environment according to claim 1, characterized in that, The first instruction has M operands; The step of converting the first microinstruction group into a second microinstruction group when the first microinstruction group meets preset conditions includes: Detect whether the first microinstruction group contains the first target opcode; If the first microinstruction group contains the first target opcode, the first microinstruction group is converted into the second microinstruction group, wherein the second instruction formed by the second microinstruction group has N operands, where M and N are both positive integers, and M is less than N.

3. The microinstruction generation method for a verification environment according to claim 2, characterized in that, The first instruction is a two-operand instruction, and the second instruction is a three-operand instruction.

4. The microinstruction generation method for a verification environment according to claim 2, characterized in that, The first microinstruction group includes at least one microinstruction; When the first microinstruction group contains the first target opcode, converting the first microinstruction group into the second microinstruction group includes: If the first target opcode is included in the first microinstruction group, the microinstruction containing the first target opcode is obtained to obtain the microinstruction to be converted. The microinstruction to be converted has M operands. Each microinstruction in the first microinstruction group other than the microinstruction to be converted is a remaining microinstruction. According to a preset conversion rule, the microinstruction to be converted is converted into a target microinstruction, wherein the target microinstruction has N operands; The second microinstruction group is generated based on the target microinstruction and the remaining microinstructions.

5. The microinstruction generation method for a verification environment according to claim 1, characterized in that, The first instruction set corresponds to the first register group, and the first register group includes multiple first architecture registers; The second instruction set corresponds to the second register set, which includes the first register set and at least one newly added architecture register. The step of converting the first microinstruction group into a second microinstruction group when the first microinstruction group meets preset conditions includes: If the first architecture register is included in the first microinstruction group, the first architecture register in the first microinstruction group is replaced by the newly added architecture register to obtain the second microinstruction group.

6. The microinstruction generation method for a verification environment according to claim 5, characterized in that, The step of replacing the first architecture register in the first microinstruction set with the newly added architecture register includes: The replacement methods of each of the first architecture registers in the first microinstruction group by the at least one newly added architecture register are traversed, wherein each replacement method forms a corresponding second microinstruction group.

7. The microinstruction generation method for a verification environment according to claim 1, characterized in that, The first instruction has M operands; The first instruction set corresponds to the first register group, and the first register group includes multiple first architecture registers; The second instruction set corresponds to the second register set, which includes the first register set and at least one newly added architecture register. The step of converting the first microinstruction group into a second microinstruction group when the first microinstruction group meets preset conditions includes: Detect whether the first microinstruction group contains the first target opcode; If the first target opcode is contained in the first microinstruction group, the first microinstruction group is converted into an intermediate microinstruction group, wherein the intermediate microinstruction group is used to form an intermediate instruction, and the intermediate instruction has N operands, wherein M and N are both positive integers, and M is less than N; Detect whether the intermediate microinstruction group contains the first architecture register; If the intermediate microinstruction group includes the first architecture register, the first architecture register in the intermediate microinstruction group is replaced by the newly added architecture register to obtain the second microinstruction group.

8. A chip verification method, characterized in that, include: A second microinstruction group is generated, the second microinstruction group being generated based on the microinstruction generation method for a verification environment as described in any one of claims 1 to 7; The module to be verified in the chip is verified based on the second microinstruction group.

9. The chip verification method according to claim 8, characterized in that, Before verifying the module to be verified in the chip based on the second microinstruction group, the method further includes: Obtain a pre-stored third microinstruction group, the third microinstruction group being used to form a third instruction, wherein the third instruction includes a second target opcode, the second target opcode being an opcode included in the second instruction set but not included in the first instruction set; The verification of the module to be verified in the chip based on the second microinstruction group includes: The module to be verified in the chip is verified based on the second microinstruction group and the third microinstruction group.

10. The chip verification method according to claim 9, characterized in that, The verification of the module to be verified in the chip based on the second microinstruction group and the third microinstruction group includes: Randomly select a target microinstruction group from the first microinstruction group, the second microinstruction group, and the third microinstruction group; The target microinstruction set is sent to the module to be verified in the chip to verify the module based on the target microinstruction set.

11. The chip verification method according to claim 8, characterized in that, The module to be verified includes the execution component of the instruction pipeline or the instruction dispatch component of the instruction pipeline.

12. A microinstruction generation device for verifying an environment, characterized in that, include: The first acquisition unit is used to acquire the first micro-instruction group formed by decomposing the first instruction, wherein the first instruction is an instruction in the first instruction set; The conversion unit is used to convert the first microinstruction group into a second microinstruction group when the first microinstruction group meets preset conditions, so as to generate microinstructions that meet the second instruction specification. The second instruction is an instruction in the second instruction set, which is evolved and expanded from the first instruction set.

13. A chip verification device, characterized in that, include: A generation unit is configured to generate a second microinstruction group based on the microinstruction generation apparatus for a verification environment as described in claim 12. The verification unit is used to verify the module to be verified in the chip based on the second microinstruction group.

14. An electronic device, characterized in that, The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the microinstruction generation method for verification environment according to any one of claims 1 to 7 or the chip verification method according to any one of claims 8 to 11.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the microinstruction generation method for a verification environment according to any one of claims 1 to 7 or the chip verification method according to any one of claims 8 to 11.

Images