Fixed-point division calculation method and device, control chip, air conditioner and storage medium

Abstract

The application relates to a fixed-point number division calculation method and device, a control chip, an air conditioner and a storage medium. The method comprises the following steps: obtaining a fixed-point number to be calculated, wherein the fixed-point number to be calculated comprises a first number value as a dividend and a second number value as a divisor; the first number value and the second number value are mapped to a preset fixed-point format respectively to obtain a third number value and a fourth number value represented by the preset fixed-point format, wherein the data convergence efficiency of the preset fixed-point format is higher than that of the original format of the fixed-point number to be calculated; a number value with a preset bit width is extracted from the lowest bit of the fourth number value, and the extracted number value is determined as a fifth number value; the third number value and the fifth number value are iteratively calculated until the first preset condition is met, and the iterative calculation is stopped; and based on the third number value obtained through the final iterative calculation, a division calculation result corresponding to the fixed-point number to be calculated is determined. In this way, the division calculation efficiency of the fixed-point number can be improved.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a method, apparatus, control chip, air conditioner, and storage medium for calculating fixed-point division. Background Technology

[0002] During the operation of an air conditioner, a control chip is usually used to control the motor, compressor, and other components of the air conditioner based on various operating parameters. In the process of control, the control chip inevitably needs to perform division calculations on certain fixed points of the air conditioner.

[0003] In related technologies, fixed-point number division is typically performed by directly iterating the numbers of the dividend and divisor (e.g., using algorithms that recover the remainder or those that do not) or by iterating functions (e.g., using the Newton-Raphson algorithm or the Goldschmidt algorithm). However, this approach suffers from slow data convergence and a large number of iterations, resulting in low overall computational efficiency. Therefore, improving the efficiency of fixed-point number division is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This application provides a method, apparatus, control chip, air conditioner, and storage medium for calculating fixed-point division, in order to solve the problem that the data convergence speed is slow and the number of iterations is large in the related technology, resulting in low efficiency of division calculation.

[0005] In a first aspect, embodiments of this application provide a method for calculating division of fixed-point numbers, the method comprising: Obtain the fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor; The first value and the second value are mapped to a preset point format respectively to obtain a third value and a fourth value represented by the preset point format, wherein the data convergence efficiency of the preset point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated. Extract a value with a preset bit width starting from the least significant bit of the fourth value, and determine the extracted value as the fifth value; The third value and the fifth value are iteratively calculated until the first preset condition is met, and the iterative calculation is stopped. Based on the third value obtained by the final iterative calculation, the division calculation result corresponding to the fixed point number to be calculated is determined. The first preset condition is that the number of iterations reaches the preset number of iterations or the fifth value after iterative calculation is close to the target value. The iterative calculation of the third and fifth values, stopping when the first preset condition is met, and determining the division result corresponding to the fixed-point number to be calculated based on the third value obtained from the final iterative calculation, includes: Based on the fifth numerical value, the iteration factor is calculated; The first multiplier is used to multiply the value of the preset bit width in the lower-order bits of the third value with the iteration factor, and the calculation result is used as the new value of the preset bit width in the lower-order bits of the third value. The second multiplier is used to multiply the value of the third value with the preset bit width in the higher bits by the iteration factor, and the calculation result is used as the new value of the third value with the preset bit width in the higher bits. The new value with a preset bit width in the lower bit of the third value and the new value with a preset bit width in the higher bit of the third value are concatenated to obtain the third value after the current iteration calculation. The fifth value is multiplied by the iteration factor using the third multiplier, and the result is determined as the fifth value after the current iteration. Determine whether the first preset condition is met; If the first preset condition is not met, repeat the above steps until the first preset condition is met, then stop the iterative calculation and determine the division result based on the third value obtained from the final iterative calculation.

[0006] Optionally, mapping the first and second values ​​to a preset point format to obtain a third and fourth value represented using the preset point format includes: The first value and the second value are respectively extended to the first bit width to obtain the extended first value and the extended second value, wherein the first bit width is determined based on the initial bit width of the first value and the second value and the preset point format; The extended first value and the extended second value are shifted left by a second bit width to obtain the left-shifted first value and the left-shifted second value, wherein the second bit width is determined based on the preset point format; The first value after left shift and the second value after left shift are respectively shifted to the right by a third bit width to obtain the third value and the fourth value, wherein the third bit width is determined based on the most significant bit in the second value.

[0007] Optionally, the first multiplier, the second multiplier, and the third multiplier are the same multiplier.

[0008] Optionally, before mapping the first and second values ​​to a preset point format to obtain the third and fourth values ​​represented using the preset point format, the method further includes: Determine whether the first value and the second value satisfy the second preset condition; When the first value and the second value satisfy the second preset condition, the division calculation result is determined based on the first value, the second value and the preset rule, wherein the preset rule is used to characterize the value of the division calculation result when the first value and the second value satisfy the second preset condition; If the first value and the second value do not meet the second preset condition, the step of mapping the first value and the second value to a preset point format to obtain a third value and a fourth value represented by the preset point format is executed.

[0009] Optionally, the preset rules include at least one of the following: When the first value is 0, the result of the division calculation is 0; When the second value is 1, the result of the division calculation is the value corresponding to the first value; When the second value is -1, the result of the division calculation is the opposite of the value corresponding to the first value; When the second value is 0, the result of the division calculation is a first preset value, wherein the first preset value is used to indicate that the result of the division calculation is invalid; When the first value and the second value are equal, and both the first value and the second value are non-zero, the result of the division calculation is 1. When the first value and the second value are opposite, and both the first value and the second value are non-zero, the result of the division calculation is -1. If the absolute value of the first value is less than the absolute value of the second value, the result of the division calculation is 0. If the first value and / or the second value exceed a preset boundary value, the result of the division calculation is taken as a second preset value, wherein the second preset value is used to indicate that the division calculation result is incorrect.

[0010] Optionally, before mapping the first and second values ​​to a preset point format to obtain the third and fourth values ​​represented using the preset point format, the method further includes: When both the first value and the second value are signed fixed-point numbers, the sign bit value of the division result is determined based on the first value and the second value. After iteratively calculating the third and fifth values ​​until the first preset condition is met, and determining the division result corresponding to the fixed-point number to be calculated based on the third value obtained from the final iterative calculation, the method further includes: Based on the sign bit value of the division calculation result, the sign bit of the division calculation result is corrected.

[0011] Secondly, embodiments of this application also provide a fixed-point division calculation device, the device comprising: The acquisition module is used to acquire the fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor; A mapping module is used to map the first value and the second value to a preset point format respectively to obtain a third value and a fourth value represented by the preset point format, wherein the data convergence efficiency of the preset point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated. The first determining module is used to extract a value with a preset bit width starting from the least significant bit of the fourth value, and to determine the extracted value as the fifth value. The second determining module is used to perform iterative calculations on the third value and the fifth value until the first preset condition is met, and then stop the iterative calculation. Based on the third value obtained from the final iterative calculation, the module determines the division calculation result corresponding to the fixed-point number to be calculated. The first preset condition is that the number of iterations reaches a preset number of iterations or the fifth value after iterative calculation is close to the target value.

[0012] Thirdly, embodiments of this application also provide a control chip, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; The processor, when executing a program stored in memory, implements the fixed-point division calculation method described in the first aspect.

[0013] Fourthly, embodiments of this application also provide an air conditioner, which includes the control chip described in the third aspect.

[0014] Fifthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the fixed-point division calculation method described in the first aspect.

[0015] Compared with the prior art, the above-mentioned technical solution provided in this application has the following advantages: The method provided in this application obtains a fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor; maps the first value and the second value to a preset fixed-point format respectively to obtain a third value and a fourth value represented by the preset fixed-point format, wherein the data convergence efficiency of the preset fixed-point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated; extracts a value of a preset bit width from the least significant bit of the fourth value and determines the extracted value as the fifth value; iteratively calculates the third value and the fifth value until the current condition is met, and stops the iterative calculation; and determines the division calculation result corresponding to the fixed-point number to be calculated based on the third value obtained by the final iterative calculation, wherein the first preset condition is that the number of iterations reaches a preset number of iterations or the fifth value after iterative calculation is close to the target value. By using the above method, the first and second values ​​can be mapped to a preset fixed-point format before iterative calculation. Then, iterative calculation is performed based on the mapped third and fourth values. This normalizes the divisor to a smaller range, thereby improving data convergence efficiency and thus improving the efficiency of fixed-point division calculation. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] One embodiment or practice is illustrated by way of example with the corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 A flowchart illustrating a method for calculating division of fixed-point numbers provided in an embodiment of this application; Figure 2 A schematic diagram of a 32-bit fixed-point divider provided in an embodiment of this application; Figure 3 This is one of the simulation waveform diagrams provided in the embodiments of this application; Figure 4 This is the second simulation waveform diagram provided for an embodiment of this application; Figure 5 The third of the simulation waveform diagrams provided in the embodiments of this application; Figure 6 The fourth of the simulation waveform diagrams provided in the embodiments of this application; Figure 7 Fifth of the simulated waveform diagrams provided in the embodiments of this application; Figure 8 The sixth of the simulation waveform diagrams provided for the embodiments of this application; Figure 9 The seventh of the simulated waveform diagrams provided for embodiments of this application; Figure 10 Eighth of the simulated waveform diagrams provided for embodiments of this application; Figure 11 The ninth of the simulated waveform diagrams provided for the embodiments of this application; Figure 12 The tenth example of a simulation waveform diagram provided in the embodiments of this application; Figure 13 This is eleventh of the simulated waveform diagrams provided for embodiments of this application; Figure 14 The twelfth example of a simulation waveform diagram provided for an embodiment of this application; Figure 15 The thirteenth example of the simulation waveform diagram provided in the embodiments of this application; Figure 16 Fourteenth of the simulated waveform diagrams provided for embodiments of this application; Figure 17 A schematic diagram of a fixed-point division calculation device provided in an embodiment of this application; Figure 18 This is a schematic diagram of the structure of a control chip provided in an embodiment of this application; Figure 19 This is a schematic diagram of the structure of an air conditioner provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0022] Because related technologies suffer from slow data convergence speed and a large number of iterations, resulting in low efficiency of division calculations, this application provides a method, apparatus, control chip, air conditioner, and storage medium for calculating fixed-point division, which can improve the efficiency of fixed-point division calculations.

[0023] See Figure 1 , Figure 1 This is a flowchart illustrating a method for calculating fixed-point division, provided in an embodiment of this application. Figure 1 As shown, the method for calculating the division of this fixed-point number may include the following steps: Step S101: Obtain the fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor.

[0024] Specifically, the fixed-point numbers to be calculated can be operating parameters of the air conditioner expressed in any fixed-point form, such as motor operating power and motor current values, set temperature and ambient temperature values, etc. The fixed-point numbers to be calculated can be signed or unsigned fixed-point numbers, and this application embodiment does not specifically limit them.

[0025] Step S102: Map the first and second values ​​to a preset point format to obtain the third and fourth values ​​represented by the preset point format. The data convergence efficiency of the preset point format is higher than that of the original format of the fixed-point number to be calculated.

[0026] Specifically, the aforementioned preset point format can be a Q15 fixed-point format, a Q14 fixed-point format, a Q13 fixed-point format, a Q12 fixed-point format, etc. As an optional implementation, a Q15 fixed-point format can be used as the preset point format. The Q15 fixed-point format can include 1 sign bit (if there is a sign) and 15 decimal places, with the integer part having 0 bits and a value range of [-1, 1].

[0027] When mapping the first and second values ​​to a preset point format, the position of the most significant bit in the second value can be obtained first. Then, based on the position of the most significant bit, the second value is normalized to the interval [0.5, 1). At the same time, the first value is scaled by the same proportion to ensure that the ratio between the dividend and the divisor remains unchanged. This allows both the first and second values ​​to be represented in the preset point format. Normalizing the second value to the interval [0.5, 1) effectively reduces the dynamic range of the operands, improving the convergence efficiency and accuracy of subsequent iterations.

[0028] Step S103: Extract the value of the preset bit width starting from the least significant bit of the fourth value, and determine the extracted value as the fifth value.

[0029] After obtaining the fourth value represented in a preset point format, the value of the least significant bit (within a preset bit width) of the fourth value can be truncated to become the fifth value, which will then be used as the divisor in subsequent iterative calculations. Specifically, the preset bit width depends on the type of preset point format. For example, for a fourth value in Q15 fixed-point format, the preset bit width is 16 bits (15 decimal places plus 1 sign bit), meaning the lower 16 bits of the fourth value need to be truncated to become the fifth value; for a fourth value in Q14 fixed-point format, the preset bit width is 15 bits (14 decimal places plus 1 sign bit), meaning the lower 15 bits of the fourth value need to be truncated to become the fifth value, and so on.

[0030] Step S104: Iterate the calculation of the third and fifth values ​​until the first preset condition is met, and stop the iteration calculation. Based on the third value obtained by the final iteration calculation, determine the division calculation result corresponding to the fixed point number to be calculated. The first preset condition is that the number of iterations reaches the preset number of iterations or the fifth value after iteration calculation is close to the target value.

[0031] Specifically, after obtaining the third and fifth values, iterative calculations can be performed on the third and fifth values ​​to make the fifth value continuously approach the target value. Here, the target value refers to the value 1 under the preset point format, because when the divisor iterates to the value 1, the quotient is very close to the dividend after iteration.

[0032] After each iteration, it is determined whether the first preset condition is met. If the first preset condition is not met, iteration continues until the first preset condition is met, at which point the iteration stops, and the division result corresponding to the fixed-point number to be calculated is determined based on the third value obtained from the final iteration. Here, the first preset condition is that the number of iterations reaches a preset number or the fifth value after iteration is close to the target value. The preset number of iterations can be set according to actual needs, and this embodiment does not impose a specific limitation. As an optional implementation, the preset number of iterations can be 4, which can be determined based on the theoretical calculation error of the divisor approaching 1. When the number of iterations is 1, the error is 10^-2; when the number of iterations is 2, the error is 10^-4; when the number of iterations is 3, the error is 10^-8; and when the number of iterations is 4, the error is 10^-16. For hardware, an error of 10^-16 is sufficiently high in precision. The preset number of iterations is based on a comprehensive consideration of the accuracy and speed of division calculation. When the number of iterations is too high, the calculation time required for division will be longer; when the number of iterations is too low, the error will be relatively large.

[0033] In this way, before performing iterative calculations, the first and second values ​​can be mapped to a preset point format, and then iterative calculations can be performed based on the mapped third and fourth values. This normalizes the divisor to a smaller range, thereby improving data convergence efficiency and thus improving the efficiency of fixed-point division calculations.

[0034] In an optional embodiment, step S102, which maps the first and second values ​​to a preset point format to obtain a third and fourth value represented using the preset point format, includes: The first and second values ​​are respectively extended to the first bit width to obtain the extended first and second values. The first bit width is determined based on the initial bit width of the first and second values ​​and the preset bit format. The extended first value and the extended second value are shifted left by the second bit width respectively to obtain the left-shifted first value and the left-shifted second value. The second bit width is determined based on a preset point format. The first and second values ​​after left shift are shifted to the right by a third bit width to obtain the third and fourth values, respectively. The third bit width is determined based on the most significant bit in the second value.

[0035] Specifically, when mapping the first and second values ​​to a preset point format, the first and second values ​​can be expanded to the first bit width respectively to obtain the expanded first value and the expanded second value. Then, the expanded first value and the expanded second value are shifted left by the second bit width respectively to obtain the left-shifted first value and the left-shifted second value. Next, the left-shifted first value and the left-shifted second value are shifted right by the third bit width respectively to obtain the third value and the fourth value.

[0036] For ease of understanding, we will use a 32-bit signed fixed-point number as the first and second value as examples. First, an efficient divide-and-conquer strategy can be employed to locate the most significant bit (i.e., the position where the first "1" appears) in the second value, reducing latency and improving computation speed. Specifically, the 31 bits of the 32-bit number can be divided into three segments: the high 10 bits, the middle 10 bits, and the low 11 bits (the specific number of segments and the corresponding bit range for each segment can be set according to actual needs; no specific limitation is made here). By performing a bitwise OR operation on the high 10 bits, we can determine if all bits are 0. If the result of the bitwise OR operation is 1, it means that the most significant bit is located in the high 10 bits (bits 30 to 21). At this point, we can further scan this interval bit by bit from high to low to determine the position of the leading 1 (i.e., the position of the most significant bit). If the result of the bitwise OR operation on the high 10 bits is 0, and the result of the bitwise OR operation on the middle 10 bits is 1, then the most significant bit is located in the middle 10 bits (bits 20 to 11). At this point, we can start scanning downwards from bit 20 to locate the position of the leading 1. If the result of the bitwise OR operation on the high 10 bits and the middle 10 bits is 0, then the leading 1 must be located in the low 11 bits (bits 10 to 0). Similarly, we can start scanning downwards from bit 10 to locate the position of the first 1. This method reduces the worst-case 31 judgments to a maximum of 13 (i.e., 2 group judgments + a maximum of 11 intra-bit scans), significantly improving computational efficiency. Furthermore, by quickly determining the most significant bit, it can provide key information for subsequent bit alignment and shift control, effectively reducing redundant calculations and improving the overall performance of the divider.

[0037] Next, based on the detection result of the leading 1 position, the first and second values ​​can be synchronously scaled to ensure that their ratio remains unchanged. First, the 32-bit first and second values ​​can be expanded to 48 bits (here, 48 bits is the initial bit width of the first and second values ​​32 bits + 16 bits corresponding to the Q15 fixed-point format) to preserve precision and prevent shift overflow. Then, both are shifted left by 15 bits to convert to Q15 fixed-point format, so that the decimal point is hidden after the 15th bit. Next, according to the bit index b corresponding to the leading 1 position (i.e., the position of the most significant bit in the second value), the first and second values ​​are uniformly shifted right by b bits. Through this shift operation, the most significant bit of the divisor is aligned to the first decimal place, so that its value falls within the range of [0.5, 1) (i.e., the range of 0x4000 to 0x7FFF under Q15), achieving normalization. This normalization strategy effectively reduces the dynamic range of the operands and improves the convergence efficiency and accuracy of subsequent iterations. The entire process is implemented by combinational logic, with low latency, and is suitable for high-performance fixed-point dividers.

[0038] It should be noted that the first bit width after the expansion of the first and second digits, as well as the second bit width that needs to be shifted left, in the above process are related to the type of preset point format. Different preset point formats require different numbers of bits for expansion and left shift. For example, when the preset point format is Q14 fixed-point format, the 32-bit first and second digits need to be expanded to 47 bits (here, 47 bits is the initial bit width of the first and second digits 32 bits + the 15 bits corresponding to the Q14 fixed-point format) to preserve precision and prevent shift overflow. Subsequently, both are shifted left by 14 bits to convert to Q14 fixed-point format, so that the decimal point is hidden after the 14th bit.

[0039] In this way, the first and second values ​​can be mapped to a preset point format, so that the divisor is normalized to the interval [0.5,1), thereby improving the convergence speed and calculation accuracy of subsequent iterations.

[0040] In one optional embodiment, iterative calculations are performed on the third and fifth values ​​until a first preset condition is met, at which point the iterative calculation stops, and the division result corresponding to the fixed-point number to be calculated is determined based on the third value obtained from the final iterative calculation, including: Based on the fifth value, the iteration factor is calculated; The first multiplier is used to multiply the value of the preset bit width in the lower-order bits of the third value with the iteration factor, and the calculation result is used as the new value of the preset bit width in the lower-order bits of the third value. The second multiplier is used to multiply the value of the preset bit width in the high-order bits of the third value with the iteration factor, and the calculation result is used as the new value of the preset bit width in the high-order bits of the third value. The new value with a preset bit width in the lower bit of the third value and the new value with a preset bit width in the higher bit of the third value are concatenated to obtain the third value after the current iteration calculation. The third multiplier is used to multiply the fifth value with the iteration factor, and the result is determined as the fifth value after the current iteration. Determine whether the first preset condition is met; If the first preset condition is not met at present, repeat the above steps until the first preset condition is met and stop the iterative calculation. Then, determine the division result based on the third value obtained from the final iterative calculation.

[0041] Specifically, the fifth value is the value with a preset bit width in the lower bits of the fourth value. For example, assuming the normalized fourth value is in Q15 fixed-point format, the fifth value is the value in the lower 16 bits of the fourth value. The iteration factor is an intermediate variable in the iterative calculation process, used to multiply with the third or fifth value to achieve iterative changes in the third or fifth value. The first, second, and third multipliers can be the same or different multipliers; this application does not specifically limit this. The bit width requirements of the first, second, and third multipliers are determined based on the bit width of the two input multipliers.

[0042] In each round of iterative calculation, the iteration factor f=2 for the current round is first calculated. d, where f is the iteration factor for the current round, and d is the divisor for the current round (i.e., the fifth value). All values ​​are represented in a preset point format to ensure consistent precision and dynamic range during calculation. Next, the preset bit width value (e.g., the lower 24 bits) of the middle of the dividend (i.e., the third value) is extracted, and this value, along with the iteration factor f, is used as multipliers mul1 and mul2 respectively, and fed into the first multiplier for multiplication. The result is used as the new preset bit width value (e.g., the lower 24 bits of the dividend) of the third value in the next round. Subsequently, the preset bit width value (e.g., the higher 24 bits) of the middle of the dividend (i.e., the third value) is extracted, and this value, along with the iteration factor f, is used as multipliers mul1 and mul2 respectively, and fed into the second multiplier for multiplication. The result is used as the new preset bit width value (e.g., the higher 24 bits of the dividend) of the third value in the next round. Next, the results of the two multiplications are concatenated to form the third value after the current iteration (such as a complete 48-bit dividend), thus updating the dividend. This piecewise multiplication strategy effectively adapts to the bit width limitations of hardware multipliers while preserving high-precision intermediate results. Then, the divisor d and iteration factor f of the current round are used as multipliers mul1 and mul2, respectively, and fed into the third multiplier for multiplication. The output result is used as the divisor for the next round, pushing it closer to 1. Because the Goldschmidt algorithm has square-convergence characteristics, each iteration can approximately double the number of error bits. Therefore, usually only 3 to 4 iterations are needed to achieve the accuracy requirements of the Q15 fixed-point format. After each iteration, it is necessary to determine whether the first preset condition is met: if the number of iterations reaches the preset number of iterations (such as 4 times), or the fifth value after iteration is close to the target value (such as 0x7FFF in Q15 fixed-point format), then the iteration calculation is terminated; otherwise, the iteration calculation continues.

[0043] It's important to note that the number of iterations here can be managed using a 4-bit binary counter, initially set to 1111. After each complete iteration, the counter is shifted right by one bit, for example, from 1111→0111→0011→0000, until it reaches 0000, at which point the iteration process automatically terminates. This mechanism avoids the carry delay and complex logic of traditional addition and subtraction counters, significantly reducing hardware overhead and improving clock frequency and resource utilization. The entire iteration process is controlled by a state machine variable, enabling orderly switching between each step.

[0044] In this way, the divisor can be iterated to a value of 1 under a preset point format with fewer iterations, so that the calculated quotient can be approximated to the dividend, thus quickly obtaining the division result.

[0045] In one alternative embodiment, the first multiplier, the second multiplier, and the third multiplier are the same multiplier.

[0046] Specifically, the first, second, and third multipliers mentioned above can be the same multiplier. This allows for time-sharing multiplexing of the multipliers, reducing the number of multipliers required and enabling the entire divider to use only one multiplier, significantly reducing the overall area of ​​the divider. This design, through shift counting, segmented multiplication, time-sharing multiplexing of multipliers, and state machine control, achieves high parallelism, low latency, and low resource consumption for division operations. It is widely applicable in high-performance computing and real-time signal processing scenarios, possessing good scalability and engineering practicality.

[0047] In an optional embodiment, before step S102, which maps the first and second values ​​to a preset point format to obtain the third and fourth values ​​represented using the preset point format, the method further includes: Determine whether the first and second values ​​satisfy the second preset condition; When the first value and the second value satisfy the second preset condition, the division calculation result is determined based on the first value, the second value and the preset rule, wherein the preset rule is used to characterize the value of the division calculation result when the first value and the second value satisfy the second preset condition. If the first and second values ​​do not meet the second preset condition, the steps are performed to map the first and second values ​​to preset point formats respectively, so as to obtain the third and fourth values ​​represented by the preset point formats.

[0048] Specifically, before entering the main operation process, it can be determined whether the first value and the second value meet the second preset condition. If the first value and the second value meet the second preset condition, the division calculation result can be determined based on the first value, the second value and the preset rule. If the first value and the second value do not meet the second preset condition, the main operation process can be entered and the division calculation result can be obtained through iterative calculation.

[0049] In this way, by performing a preliminary judgment on the first and second values, various preset special cases can be identified and the results can be directly output, avoiding the invocation of complex division logic, thereby significantly reducing latency and hardware overhead.

[0050] In one optional embodiment, the above-mentioned preset rules include at least one of the following: When the first value is 0, the result of the division is 0. When the second value is 1, the result of the division is the value corresponding to the first value. When the second value is -1, the result of the division is the opposite of the value corresponding to the first value; When the second value is 0, the result of the division calculation is a first preset value, which is used to indicate that the result of the division calculation is invalid. When the first and second values ​​are equal, and both the first and second values ​​are non-zero, the result of the division is 1. When the first and second values ​​are opposite, and both the first and second values ​​are non-zero, the result of the division is -1. If the absolute value of the first value is less than the absolute value of the second value, the result of the division is 0. If the first value and / or the second value exceed the preset boundary value, the result of the division calculation is taken as the second preset value, which is used to indicate that the division calculation result is incorrect.

[0051] Specifically, when the dividend (i.e., the first value) is 0, regardless of the value of the divisor (i.e., the second value) (except 0), the quotient is always 0, and 0 is output directly.

[0052] When the divisor (i.e., the second value) is 1, the quotient is equal to the dividend (i.e., the first value) itself, and the dividend is output directly.

[0053] When the divisor (i.e., the second value) is -1, the quotient is the opposite of the dividend (i.e., the first value). The two's complement is quickly obtained and output by "inverting the bits and adding 1".

[0054] When the divisor (i.e. the second value) is 0, although it is not mathematically defined, in order to prevent system abnormalities, 0 can be output as a safe default value to achieve fault tolerance protection.

[0055] When the dividend (i.e., the first value) is equal to the divisor (i.e., the second value) and is not zero, the quotient is 1, and 1 is output directly.

[0056] When the absolute values ​​of the dividend (i.e., the first value) and the divisor (i.e., the second value) are equal, opposite in sign, and both are non-zero, the quotient is -1, and -1 is output directly.

[0057] When the absolute value of the dividend (i.e., the first number) is less than the absolute value of the divisor (i.e., the second number), the result in fixed-point integer division is 0 (rounded down), and 0 can be output directly.

[0058] When the dividend (i.e., the first value) or the divisor (i.e., the second value) exceeds the preset boundary value, the system can quickly identify and output the saturation value (such as the user-defined maximum value) or the error code (such as the user-defined error code 0 or -1).

[0059] In this way, by efficiently identifying one or more of the above special cases, the computational load of the divider can be significantly reduced, and the overall response speed, energy efficiency and system reliability can be improved.

[0060] In an optional embodiment, before step S102, which maps the first and second values ​​to a preset point format to obtain the third and fourth values ​​represented using the preset point format, the method further includes: When both the first and second values ​​are signed fixed-point numbers, the sign bit value of the division result is determined based on the first and second values. After step S104 above, where the third and fifth values ​​are iteratively calculated until the first preset condition is met, and the iterative calculation is stopped, and the division result corresponding to the fixed-point number to be calculated is determined based on the third value obtained from the final iterative calculation, the method further includes: The sign bit of the division result is corrected based on the sign bit value.

[0061] Specifically, when both the first and second values ​​are signed fixed-point numbers, the sign bit of the division result can be determined based on these values. Specifically, the sign bits of the first and second values ​​can be read first, and then the sign of the final quotient can be determined according to their sign relationship: if the two numbers have the same sign (both positive or both negative), the quotient is positive; if the two numbers have different signs, the quotient is negative. This judgment is efficiently achieved through an XOR operation on the sign bits. Simultaneously, the absolute values ​​of the first and second values ​​can be converted to ensure that subsequent division core units only process non-negative numbers, thus simplifying hardware design. If the first and second values ​​are positive, their original values ​​are directly retained; if the first and second values ​​are negative, they are converted to their absolute values ​​through a two's complement operation of "bitwise inversion followed by addition of 1". This process utilizes readily available inversion logic and adders, resulting in low hardware overhead and rapid response. After completing the sign determination and absolute value extraction, the divider performs unsigned number operations based on the two positive numbers, significantly improving computational efficiency and module reusability.

[0062] After determining the division result corresponding to the fixed-point number to be calculated, the sign bit of the division result can be corrected based on its value. Specifically, the unsigned quotient obtained after iterative processing can be signed according to the sign bit value of the division result, thus generating the correct signed operation result. The iterative operation of the Goldschmidt algorithm is usually based on the absolute value of the operands, so the output result is positive. Based on this, the current result can be processed based on the pre-determined sign of the quotient. If the quotient is determined to be positive, the iterative result is directly output; if the quotient is determined to be negative, the current result needs to be converted to its two's complement form. The conversion process is implemented by "bitwise inversion followed by addition of 1" in two's complement operations, ensuring that the negative number representation conforms to the binary signed number standard (Q15 fixed-point format).

[0063] This ensures the accuracy of the sign of the division result when performing division on signed fixed-point numbers. Its design is simple and efficient, requiring only a small number of logic gates and adders to complete the sign assignment, making it suitable for high-speed, low-power fixed-point divider architectures.

[0064] In an optional embodiment, when both the dividend and divisor are 32-bit signed fixed-point numbers, the following can be utilized: Figure 2 The 32-bit fixed-point divider shown performs division operations. This 32-bit fixed-point divider may include a special value fast processing module, a sign module, a leading 1 position detection module, a 0.5-1 mapping module, an iteration module, and a data correction module. Its calculation process includes the following steps: 1) Data input: Both the dividend and divisor are 32-bit signed fixed-point numbers.

[0065] 2) Fast handling of special values: The fast handling of special values ​​module will judge the dividend and divisor for special values. When the divisor and dividend have special values, the result of the divider will be output directly.

[0066] 3) Sign processing: The sign module judges the sign of the dividend and divisor to determine the sign of the output result, and converts both the dividend and divisor to positive numbers for subsequent calculations.

[0067] 4) Leading 1 position detection: The leading 1 position detection module will locate the position of the most significant bit of the divisor.

[0068] 5) 0.5-1 normalization mapping: The 0.5-1 mapping module normalizes the divisor to the interval [0.5, 1) based on the leading 1 position of the divisor, and the dividend is scaled by the same proportion. Both are represented in Q15 fixed-point format.

[0069] 6) Iterative processing: The iterative module is based on the Goldschmidt algorithm and performs iterative processing on the dividend and divisor simultaneously, so that the divisor gradually approaches the value 1 in the Q15 format and outputs a 32-bit unsigned fixed-point number.

[0070] 7) Data Correction: The data correction module assigns a sign to the dividend after iterative processing based on the sign of the result determined by the sign module, and obtains a 32-bit signed fixed-point number, which is used as the result of the divider.

[0071] 8) Data output: Output a 32-bit calculation result.

[0072] It should be noted that the architecture of this 32-bit fixed-point divider can be applied to fixed-point number processing of other bit widths, but the number of bits in the multiplier and the number of bits shifted in the 0.5-1 mapping module need to be changed accordingly. This divider architecture can be applied to unsigned fixed-point number processing, and the intermediate sign module can be omitted, but it cannot be used for floating-point number processing.

[0073] For example, suppose the dividend is 0x7D00 (corresponding to 32000 in decimal) and the divisor is 0x50 (corresponding to 80 in decimal). The leading 1 position detection module detects that the highest bit of the divisor is 7. After a 0.5-1 mapping, the initial value of the iteration count is recorded as 0xF (corresponding to 1111 in binary), the dividend is 0x7D0000, and the divisor is 0x5000. In the first iteration, the iteration count is recorded as 0x7, the iteration factor is 0xB000, and after the iteration, the dividend is 0xABE000 and the divisor is 0x6E00. In the second iteration, the iteration count is recorded as 0x3, the iteration factor is 0x9200, and after the iteration, the dividend is 0xC40B80 and the divisor is 0x7D78. In the third iteration, the iteration count is recorded as 0x1, the iteration factor is 0x8288, and after the iteration, the dividend is 0xC7EBFA and the divisor is 0x7FF3. In the fourth iteration, the iteration number is 0x0, the iteration factor is 0x800D, the dividend after the iteration is 0xC80047, and the divisor is 0x7FFF. After four iterations, the divisor is 0x7FFF, which approximates 1 in the Q15 format. The dividend after the iteration is converted from the Q15 format to the normal format, that is, shifted right by 15 bits, and is denoted as 0x190. Since both the input dividend and divisor are positive numbers, the final result is a positive number, denoted as 0x190 (corresponding to 400 in decimal).

[0074] The following are simulated waveforms of the output results when several different dividends and divisors are input into the above divider for division operations. In the waveforms, clk is the clock signal, divide_i is the input dividend, divisor_i is the input divisor, start_i is the start signal of the divider, count is the counter of the iteration module, state is the state of the iteration module, divisor_r is the iteration value of the divisor during the iteration process, ready_o is the completion signal of the divider, and result_o is the calculation result of the divider. All values ​​in the simulated waveforms are represented in hexadecimal.

[0075] Example 1: The input dividend `dividend_i` is 0, and the input divisor `divisor_i` is 0x78 (decimal 120). After the start signal `start_i` becomes 1, the divider begins operation. Because the conditions of the special value fast processing module are met, after one clock cycle, the completion signal `ready_o` becomes 1, and the output result `result_o` is 0. Figure 3 As shown, the results match the expectations.

[0076] Example 2: The input dividend `dividend_i` is 0x37 (decimal 55), the input divisor `divisor_i` is 0, and the start signal `start_i` becomes 1, the divider begins operation. Because the conditions of the special value fast processing module are met, after one clock cycle, the completion signal `ready_o` becomes 1, and the output result `result_o` becomes 0. Figure 4 As shown, the results match the expectations.

[0077] Example 3: The input dividend `dividend_i` is 0x37 (decimal 55), the input divisor `divisor_i` is 1, and after the start signal `start_i` becomes 1, the divider begins operation. Because the conditions of the special value fast processing module are met, after one clock cycle, the completion signal `ready_o` becomes 1, and the output result `result_o` is 0x37. Figure 5 As shown, the results match the expectations.

[0078] Example 4: The input dividend `dividend_i` is 0x50 (decimal 80), and the input divisor `divisor_i` is 0xFFFFFFFF (decimal -1). After the start signal `start_i` becomes 1, the divider begins operation. Because the conditions of the special value fast processing module are met, after one clock cycle, the completion signal `ready_o` becomes 1, and the output result `result_o` is 0xFFFFFFB0 (decimal -80). Figure 6 As shown, the results match the expectations.

[0079] Example 5: The input dividend `dividend_i` is 0xFFFFF0 (decimal 16777200), and the input divisor `divisor_i` is also 0xFFFFF0 (decimal 16777200). After the start signal `start_i` becomes 1, the divider begins operation. Because the conditions of the special value fast processing module are met, after one clock cycle, the completion signal `ready_o` becomes 1, and the output result `result_o` is 0x1. Figure 7 As shown, the results match the expectations.

[0080] Example 6: The input dividend `dividend_i` is 0x5A (decimal 90), and the input divisor `divisor_i` is 0xFFFFFFA6 (decimal -90). After the start signal `start_i` becomes 1, the divider begins operation. Because the conditions of the special value fast processing module are met, after one clock cycle, the completion signal `ready_o` becomes 1, and the output result `result_o` is 0xFFFFFFFF (decimal -1). Figure 8 As shown, the results match the expectations.

[0081] Example 7: The input dividend `dividend_i` is 0xF0 (decimal 240), and the input divisor `divisor_i` is 0x168 (decimal 360). After the start signal `start_i` becomes 1, the divider begins operation. Because the conditions of the special value fast processing module are met, after one clock cycle, the completion signal `ready_o` becomes 1, and the output result `result_o` is 0. Figure 9 As shown, the results match the expectations.

[0082] Example 8: The input dividend `dividend_i` is 0xA8 (decimal 168), and the input divisor `divisor_i` is 0xFFFFFECA (decimal -310). After the start signal `start_i` becomes 1, the divider begins operation. Because the conditions of the special value fast processing module are met, after one clock cycle, the completion signal `ready_o` becomes 1, and the output result `result_o` is 0. Figure 10 As shown, the results match the expectations.

[0083] Example 9: The input dividend is 0x1E848 (decimal 125000), and the input divisor is 0xFA (decimal 250). After the start_i signal becomes 1, the divider starts operating. After 3 rounds of iteration, the divisor iterates to 0x7FFF. When the ready_o signal becomes 1, the divider completes the operation. The clock cycle used is 12, and the output result_o is 0x1F4 (decimal 500). Figure 11As shown, the results match the expectations.

[0084] Example 10: The input dividend is 0x7D00 (decimal 32000), and the input divisor is 0x50 (decimal 80). After the start_i signal becomes 1, the divider starts its operation. After 4 rounds of iterative calculation, the divisor iterates to 0x7FF3. When the ready_o signal becomes 1, the divider completes its operation. The clock cycle used is 16, and the output result_o is 0x190 (decimal 400). Figure 12 As shown, the results match the expectations.

[0085] Example 11: The input dividend is 0x2321 (decimal 8993), and the input divisor is 0x55 (decimal 85). After the start_i signal becomes 1, the divider starts its operation. After 4 rounds of iterative calculation, the divisor iterates to 0x7FFA. When the ready_o signal becomes 1, the divider completes its operation. The clock cycle used is 16, and the output result_o is 0x69 (decimal 105). Figure 13 As shown, the result matches the expected result (the result retains the integer part).

[0086] Example 12: The input dividend is 0xFFFFCB44 (decimal -13500), and the input divisor is 0xFFFFFDA8 (decimal -600). After the start_i signal becomes 1, the divider starts its operation. After 4 rounds of iterative calculation, the divisor iterates to 0x7FE3. When the ready_o signal becomes 1, the divider completes its operation. The clock cycle used is 16, and the output result_o is 0x16 (decimal 22). Figure 14 As shown, the results match the expectations.

[0087] Example 13: The input dividend is 0x20EA (decimal 8426), and the input divisor is 0xFFFFFDDD (decimal -547). After the start_i signal becomes 1, the divider starts its operation. After 4 rounds of iteration, the divisor becomes 0x7FB7. When the ready_o signal becomes 1, the divider completes its operation. The clock cycle used is 16, and the output result_o is 0xFFFFFFF1 (decimal -15). Figure 15 As shown, the result matches the expected result (the result retains the integer part).

[0088] Example 14: The input dividend is 0xFFFFE2BC (decimal -7492), and the input divisor is 0x170 (decimal 368). After the start_i signal becomes 1, the divider starts its operation. After 4 rounds of iteration, the divisor becomes 0x7FFE. When the ready_o signal becomes 1, the divider completes its operation. The clock cycle used is 16, and the output result_o is 0xFFFFFFEC (decimal -20). Figure 16 As shown, the result matches the expected result (the result retains the integer part).

[0089] The calculation results for each example are shown in the table below:

[0090] Therefore, the fixed-point division calculation method provided in this application significantly simplifies the division process, reduces the execution cycle, and improves the execution efficiency by adding a data preprocessing step to quickly process special divisor and dividend categories, rapidly normalizing the divisor to between 0.5 and 1 in Q15 format and presenting it in a fixed-point form, and using a simple iteration factor to achieve rapid iteration of the dividend and divisor. Furthermore, by employing a time-sharing method for multipliers, the number of multipliers is reduced, meaning the entire division design uses only one multiplier, thus significantly reducing the overall area of ​​the division.

[0091] See Figure 17 , Figure 17 This is a schematic diagram of a fixed-point division calculation device provided in an embodiment of this application. Figure 17 As shown, the fixed-point division calculation device 1700 includes: The acquisition module 1701 is used to acquire the fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor; The mapping module 1702 is used to map the first value and the second value to a preset point format respectively, so as to obtain the third value and the fourth value represented by the preset point format. The data convergence efficiency of the preset point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated. The first determining module 1703 is used to extract a value with a preset bit width from the least significant bit of the fourth value and determine the extracted value as the fifth value. The second determining module 1704 is used to perform iterative calculations on the third and fifth values ​​until the first preset condition is met, and then stop the iterative calculation. Based on the third value obtained from the final iterative calculation, the module determines the division result corresponding to the fixed-point number to be calculated. The first preset condition is that the number of iterations reaches the preset number of iterations or the fifth value after iterative calculation is close to the target value.

[0092] Furthermore, the mapping module 1702 includes: An extension submodule is used to extend the first value and the second value to the first bit width, respectively, to obtain the extended first value and the extended second value. The first bit width is determined based on the initial bit width of the first value and the second value and a preset bit format. The left shift submodule is used to shift the expanded first value and the expanded second value to the left by a second bit width, respectively, to obtain the left-shifted first value and the left-shifted second value. The second bit width is determined based on a preset point format. The right shift submodule is used to right shift the first value after left shift and the second value after left shift by a third bit width to obtain the third value and the fourth value. The third bit width is determined based on the most significant bit in the second value.

[0093] Furthermore, the second determining module 1704 includes: The calculation submodule is used to calculate the iteration factor based on the fifth value; The first multiplication calculation submodule is used to perform multiplication calculation on the preset bit width value of the third value and the iteration factor using the first multiplier, and use the calculation result as the new value of the preset bit width of the third value. The second multiplication calculation submodule is used to perform multiplication calculation on the preset bit width of the higher-order bits of the third value and the iteration factor using the second multiplier, and use the calculation result as the new value of the preset bit width of the higher-order bits of the third value. The splicing submodule is used to splice the new value with a preset bit width in the lower bit of the third value and the new value with a preset bit width in the higher bit of the third value to obtain the third value after the current iteration calculation. The third multiplication calculation submodule is used to perform multiplication calculations on the fifth value and the iteration factor using the third multiplier, and to determine the calculation result as the fifth value after the current iteration calculation. The judgment submodule is used to determine whether the first preset condition is met. The iterative submodule is used to repeat the above steps if the first preset condition is not met, until the iterative calculation stops when the first preset condition is met, and the division calculation result is determined based on the third value obtained from the final iterative calculation.

[0094] Furthermore, the first multiplier, the second multiplier, and the third multiplier are the same multiplier.

[0095] Furthermore, the fixed-point division calculation device 1700 also includes: The judgment module is used to determine whether the first value and the second value satisfy the second preset condition; The third determining module is used to determine the division calculation result based on the first value, the second value and the preset rule when the first value and the second value meet the second preset condition. The preset rule is used to characterize the value of the division calculation result when the first value and the second value meet the second preset condition. The execution module is used to perform the steps of mapping the first and second values ​​to preset point formats respectively, so as to obtain the third and fourth values ​​represented by the preset point formats, when the first value and the second value do not meet the second preset conditions.

[0096] Furthermore, the preset rules include at least one of the following: When the first value is 0, the result of the division is 0. When the second value is 1, the result of the division is the value corresponding to the first value. When the second value is -1, the result of the division is the opposite of the value corresponding to the first value; When the second value is 0, the result of the division calculation is a first preset value, which is used to indicate that the result of the division calculation is invalid. When the first and second values ​​are equal, and both the first and second values ​​are non-zero, the result of the division is 1. When the first and second values ​​are opposite, and both the first and second values ​​are non-zero, the result of the division is -1. If the absolute value of the first value is less than the absolute value of the second value, the result of the division is 0. If the first value and / or the second value exceed the preset boundary value, the result of the division calculation is taken as the second preset value, which is used to indicate that the division calculation result is incorrect.

[0097] Furthermore, the fixed-point division calculation device 1700 also includes: The fourth determination module is used to determine the sign bit value of the division result based on the first and second values ​​when both the first and second values ​​are signed fixed-point numbers. The correction module is used to correct the sign bit of the division result based on the sign bit value.

[0098] It should be noted that the fixed-point division calculation device 1700 can implement the fixed-point division calculation method provided in any of the aforementioned method embodiments, and can achieve the same technical effect, which will not be elaborated here.

[0099] See Figure 18 , Figure 18 A control chip provided in this application embodiment includes a processor 1811, a communication interface 1812, a memory 1813, and a communication bus 1814, wherein the processor 1811, the communication interface 1812, and the memory 1813 communicate with each other through the communication bus 1814. Memory 1813 is used to store computer programs; In one embodiment of this application, the processor 1811, when executing the program stored in the memory 1813, implements the fixed-point number division calculation method provided in any of the foregoing method embodiments.

[0100] See Figure 19 , Figure 19 An air conditioner provided in this application embodiment includes a control chip 1901 provided in any of the foregoing embodiments.

[0101] It should be noted that the control chip 1901 can implement the fixed-point division calculation method provided in any of the aforementioned method embodiments, and can achieve the same technical effect, which will not be elaborated here.

[0102] In addition, embodiments of this application also provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the fixed-point number division calculation method provided in any of the foregoing method embodiments.

[0103] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0104] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0105] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also mean including the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0106] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method of fixed-point division computation, characterized by, The method includes: Obtain the fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor, and the fixed-point number to be calculated is the operating parameter of the air conditioner represented in any fixed-point form; The first value and the second value are mapped to a preset point format respectively to obtain a third value and a fourth value represented by the preset point format, wherein the data convergence efficiency of the preset point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated. Extract a value with a preset bit width starting from the least significant bit of the fourth value, and determine the extracted value as the fifth value; The third value and the fifth value are iteratively calculated until the first preset condition is met, and the iterative calculation is stopped. Based on the third value obtained by the final iterative calculation, the division calculation result corresponding to the fixed point number to be calculated is determined. The first preset condition is that the number of iterations reaches the preset number of iterations or the fifth value after iterative calculation is close to the target value. The iterative calculation of the third and fifth values, stopping when the first preset condition is met, and determining the division result corresponding to the fixed-point number to be calculated based on the third value obtained from the final iterative calculation, includes: S1. Based on the fifth numerical value, the iteration factor is calculated; S2. Using the first multiplier, multiply the value of the preset bit width in the lower-order bits of the third value with the iteration factor, and use the calculation result as the new value of the preset bit width in the lower-order bits of the third value. S3. Use the second multiplier to multiply the value of the preset bit width in the higher bits of the third value with the iteration factor, and use the calculation result as the new value of the preset bit width in the higher bits of the third value. S4. Concatenate the new value with a preset bit width in the lower bit of the third value and the new value with a preset bit width in the higher bit of the third value to obtain the third value after the current iteration calculation. S5. Use the third multiplier to perform multiplication calculation on the fifth value and the iteration factor, and determine the calculation result as the fifth value after the current iteration calculation; S6. Determine whether the first preset condition is met; S7. If the first preset condition is not met, repeat steps S1 to S6 until the first preset condition is met and stop the iterative calculation. Based on the third value obtained from the final iterative calculation, determine the division calculation result. The first multiplier, the second multiplier, and the third multiplier are the same multiplier.

2. The method of claim 1, wherein, The step of mapping the first and second values ​​to a preset point format to obtain a third and fourth value represented by the preset point format includes: The first value and the second value are respectively extended to the first bit width to obtain the extended first value and the extended second value, wherein the first bit width is determined based on the initial bit width of the first value and the second value and the preset point format; The extended first value and the extended second value are shifted left by a second bit width to obtain the left-shifted first value and the left-shifted second value, wherein the second bit width is determined based on the preset point format; The first value after left shift and the second value after left shift are respectively shifted to the right by a third bit width to obtain the third value and the fourth value, wherein the third bit width is determined based on the most significant bit in the second value.

3. The method of claim 1, wherein, Before mapping the first and second values ​​to a preset point format to obtain the third and fourth values ​​represented using the preset point format, the method further includes: Determine whether the first value and the second value satisfy the second preset condition; When the first value and the second value satisfy the second preset condition, the division calculation result is determined based on the first value, the second value and the preset rule, wherein the preset rule is used to characterize the value of the division calculation result when the first value and the second value satisfy the second preset condition; If the first value and the second value do not meet the second preset condition, the step of mapping the first value and the second value to a preset point format to obtain a third value and a fourth value represented by the preset point format is executed.

4. The method of claim 3, wherein, The preset rules include at least one of the following: When the first value is 0, the result of the division calculation is 0; When the second value is 1, the result of the division calculation is the value corresponding to the first value; When the second value is -1, the result of the division calculation is the opposite of the value corresponding to the first value; When the second value is 0, the result of the division calculation is a first preset value, wherein the first preset value is used to indicate that the result of the division calculation is invalid; When the first value and the second value are equal, and both the first value and the second value are non-zero, the result of the division calculation is 1. When the first value and the second value are opposite, and both the first value and the second value are non-zero, the result of the division calculation is -1. If the absolute value of the first value is less than the absolute value of the second value, the result of the division calculation is 0. If the first value and / or the second value exceed a preset boundary value, the result of the division calculation is taken as a second preset value, wherein the second preset value is used to indicate that the division calculation result is incorrect.

5. The method of claim 1, wherein, Before mapping the first and second values ​​to a preset point format to obtain the third and fourth values ​​represented using the preset point format, the method further includes: When both the first value and the second value are signed fixed-point numbers, the sign bit value of the division result is determined based on the first value and the second value. After iteratively calculating the third and fifth values ​​until the first preset condition is met, and determining the division result corresponding to the fixed-point number to be calculated based on the third value obtained from the final iterative calculation, the method further includes: Based on the sign bit value of the division calculation result, the sign bit of the division calculation result is corrected.

6. A fixed-point division computing device, comprising: The device includes: The acquisition module is used to acquire the fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor, and the fixed-point number to be calculated is the operating parameter of the air conditioner represented in any fixed-point form; A mapping module is used to map the first value and the second value to a preset point format respectively to obtain a third value and a fourth value represented by the preset point format, wherein the data convergence efficiency of the preset point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated. The first determining module is used to extract a value with a preset bit width starting from the least significant bit of the fourth value, and to determine the extracted value as the fifth value. The second determining module is used to perform iterative calculations on the third value and the fifth value until the first preset condition is met, and then stop the iterative calculation. Based on the third value obtained by the final iterative calculation, the module determines the division calculation result corresponding to the fixed-point number to be calculated. The first preset condition is that the number of iterations reaches a preset number of iterations or the fifth value after iterative calculation is close to the target value. The second determining module includes: The calculation submodule is used to execute S1 and calculate the iteration factor based on the fifth value; The first multiplication calculation submodule is used to execute S2, use the first multiplier to multiply the value of the preset bit width in the lower bit of the third value with the iteration factor, and use the calculation result as the new value of the preset bit width in the lower bit of the third value. The second multiplication calculation submodule is used to execute S3, use the second multiplier to multiply the value of the preset bit width in the high-order bit of the third value with the iteration factor, and use the calculation result as the new value of the preset bit width in the high-order bit of the third value. The splicing submodule is used to execute S4, splicing the new value with a preset bit width in the lower bit of the third value and the new value with a preset bit width in the higher bit of the third value to obtain the third value after the current iteration calculation. The third multiplication calculation submodule is used to execute S5, use the third multiplier to perform multiplication calculation on the fifth value and the iteration factor, and determine the calculation result as the fifth value after the current iteration calculation; The judgment submodule is used to execute S6 and determine whether the first preset condition is met. The iterative submodule is used to execute S7, repeat steps S1 to S7 if the first preset condition is not met, until the iterative calculation stops when the first preset condition is met, and determine the division calculation result based on the third value obtained from the final iterative calculation. The first multiplier, the second multiplier and the third multiplier are the same multiplier.

7. A control chip, characterized by It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the fixed-point number division calculation method according to any one of claims 1-5.

8. An air conditioner, characterized in that, The air conditioner includes the control chip as described in claim 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the fixed-point number division calculation method according to any one of claims 1-5.

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