A lightweight embedded FPGA virtualization method and system

Abstract

This invention discloses a lightweight embedded FPGA virtualization method and system, belonging to the field of computer technology. The application sublayer generates task instructions based on the application written by the tenant according to the task objective and sends them to the management sublayer. The management sublayer calls the corresponding hardware acceleration bitstream according to the task instructions and uses a dynamic aggregation algorithm to perform resource scheduling on the hardware acceleration bitstream. After resource scheduling, the hardware acceleration bitstream is loaded into the acceleration sublayer through the bridging sublayer. The acceleration sublayer divides the task into multiple isolated acceleration units to accelerate the tenant's task, obtain the calculation results, and send the results back to the application sublayer. The application sublayer stores or displays the results as needed. This invention enables single-tenant single-task, single-tenant multi-task, and multi-tenant multi-task operation on a single FPGA, as well as parallel hardware acceleration, improving FPGA development efficiency, resource utilization, and deployment flexibility.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a lightweight embedded FPGA virtualization method and system. Background Technology

[0002] Currently, edge intelligent terminals are facing a contradiction between "computing power hunger" and "resource constraints." For example, industrial vision inspection requires millisecond-level response, drone swarms need collaborative perception, and robots also need a large number of sensors to perceive the external environment. However, edge devices generally suffer from shortcomings such as limited computing resources, strict power consumption constraints, and limited installation space.

[0003] Field-Programmable Gate Arrays (FPGAs) possess hardware reconfigurability and combine the advantages of general-purpose programmability with dedicated acceleration, making them widely used in edge computing acceleration scenarios. Traditional FPGAs employ a static, dedicated deployment method, where a single task exclusively occupies the entire FPGA chip's hardware resources. This often fails to fully utilize all on-chip resources, resulting in idle hardware resources and low utilization. Furthermore, when switching between multiple tasks frequently, a complete reconfiguration of the entire FPGA is required, incurring significant reconfiguration latency overhead and making it difficult to meet the demands of concurrent multi-task scheduling.

[0004] Existing FPGA virtualization solutions for data centers have high hardware overhead, complex scheduling, and rely on external servers, making them unsuitable for edge devices with scarce resources, onboard autonomy, and highly heterogeneous tasks. At the same time, traditional FPGAs adopt a static exclusive deployment mode, which has the drawbacks of low on-chip resource utilization and large latency in multi-task switching and reconstruction, making it difficult to meet the actual application needs of edge intelligent terminals for multi-tenant multi-task parallel acceleration and efficient resource scheduling in a small space with high computing power, low power consumption, and small space. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a lightweight embedded FPGA virtualization method and system.

[0006] On the one hand, a lightweight embedded FPGA virtualization method is provided, including: Obtain the application and bitstream management files written by the tenant according to the task objectives; The application written by the tenant is input into the application sub-layer to obtain task instructions; The task instruction is sent to the management sub-layer, which then calls the corresponding hardware-accelerated bitstream in the bitstream management file according to the task instruction and uses a dynamic aggregation algorithm to schedule resources for the hardware-accelerated bitstream. The hardware-accelerated bitstream after resource scheduling is loaded into the idle acceleration sublayer through the bridging sublayer, and the acceleration sublayer performs hardware-accelerated calculations to obtain the calculation results. The calculated results are sent back to the application sub-layer, which then stores or displays them as needed.

[0007] Furthermore, the bitstream management file includes the following: Name: The filename of the bitstream; Type: The type of bitstream, whether it is a hardware layer bitstream or a bitstream of a hardware-accelerated task deployed in an IAU; Region: Deployed in a specific IAU; Location: The path to the bitstream file.

[0008] Furthermore, the application sublayer runs multiple applications for multiple tenants, each application including one or more tasks.

[0009] Furthermore, the core components of the bridging sublayer include: AXI Interconnect matrix, MMU, interrupt aggregation and distribution unit, and data communication interface, which realize the connection between the management sublayer and the acceleration sublayer through the bridging sublayer.

[0010] Furthermore, the acceleration sublayer is the part actually used for hardware acceleration. The acceleration sublayer is divided into multiple isolated acceleration units (IAUs). Each IAU has the same clock layout and hardware resources and communicates with the outside world through reserved interfaces.

[0011] Furthermore, the management sublayer calls the corresponding hardware-accelerated bitstream in the bitstream management file according to the task instructions, and uses a dynamic aggregation algorithm to perform resource scheduling on the hardware-accelerated bitstream, including: Task feature extraction stage: The management sublayer parses the management file to distinguish different bit streams by the task instructions submitted by the application sublayer, analyzes and records the characteristics of the task, and extracts the key parameters of the task; During the resource monitoring phase, when resources are running, the working status of the IAU is collected in real time to monitor resource utilization, memory write activity, and task execution speed. Dynamic scheduling phase: Allocate the optimal resource combination to the task based on task characteristics and resource status.

[0012] On the other hand, a lightweight embedded FPGA virtualization system is provided, including: Acquisition module: Acquires the application and bitstream management files written by the tenant according to the task objectives; Application sublayer module: Input the application written by the tenant into the application sublayer to obtain task instructions; Management sub-layer module: Sends task instructions to the management sub-layer, which then calls the corresponding hardware-accelerated bitstream in the bitstream management file according to the task instructions and uses a dynamic aggregation algorithm to schedule resources for the hardware-accelerated bitstream; Hardware acceleration module: Loads the hardware-accelerated bitstream after resource scheduling into the idle acceleration sublayer through the bridging sublayer, and the acceleration sublayer performs hardware-accelerated calculations to obtain the calculation results; Results module: The calculated results are sent back to the application sub-layer, which then stores or displays them as needed.

[0013] Furthermore, an electronic device is also provided, including: Memory, used for non-transitory storage of computer-readable instructions; and Processor, for executing the computer-readable instructions, When the computer-readable instructions are executed by the processor, they perform the method described in the first aspect above.

[0014] In another aspect, a storage medium is also provided for non-transitory storage of computer-readable instructions, wherein when the non-transitory computer-readable instructions are executed by a computer, the method described in the first aspect is performed.

[0015] In another aspect, a computer program product is also provided, including a computer program that, when run on one or more processors, is used to implement the method described in the first aspect above.

[0016] The above technical solution has the following advantages or beneficial effects: This invention discloses a lightweight embedded FPGA virtualization method and system that enables single-FPGA board autonomy and multi-tenant operation without relying on an external server. By finely partitioning PL-side resources to construct isolated acceleration units (IAUs) and achieving hardware physical isolation and standardized interface communication, it effectively improves the utilization rate of on-chip FPGA resources and reduces the reconfiguration time overhead during task switching. At the same time, the layered and decoupled framework design facilitates independent iteration of each module and cross-device portability, significantly reducing development difficulty and significantly improving the development efficiency, task scheduling flexibility, and deployment adaptability of embedded FPGAs in edge intelligence scenarios. It effectively realizes the virtualization of single FPGA devices with limited resources in edge scenarios, enabling multi-tenant multi-task operation and parallel task acceleration. Attached Figure Description

[0017] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0018] Figure 1 This is a flowchart of a lightweight embedded FPGA virtualization method as described in Embodiment 1; Figure 2 This is the hardware-accelerated bitstream generation diagram described in Example 1; Figure 3 This is the bitstream management template diagram described in Example 1; Figure 4 This is a schematic diagram of the overall virtualization model described in Example 1; Figure 5 This is a schematic diagram of the bridging sublayer structure described in Embodiment 1; Figure 6 This is a flowchart of the dynamic aggregation algorithm described in Example 1. Detailed Implementation

[0019] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0020] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments of the invention. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] In this embodiment of the invention, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of this invention, "multiple" refers to two or more.

[0022] Furthermore, to facilitate a clear description of the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0023] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0024] All data acquisition in this embodiment is carried out in accordance with laws and regulations and with user consent, and the data is used legally.

[0025] Example 1 This embodiment provides a lightweight embedded FPGA virtualization method, such as Figure 1 As shown, it includes: Obtain the application and bitstream management files written by the tenant according to the task objectives; The application written by the tenant is input into the application sub-layer to obtain task instructions; The task instruction is sent to the management sub-layer, which then calls the corresponding hardware-accelerated bitstream in the bitstream management file according to the task instruction and uses a dynamic aggregation algorithm to schedule resources for the hardware-accelerated bitstream. The hardware-accelerated bitstream after resource scheduling is loaded into the idle acceleration sublayer through the bridging sublayer, and the acceleration sublayer performs hardware-accelerated calculations to obtain the calculation results. The calculated results are sent back to the application sub-layer, which then stores or displays them as needed.

[0026] This embodiment utilizes the Ultra96-V2 development board, which is equipped with a Xilinx Zynq UltraScale+ MPSoC ZU3EG A484 chip. This chip integrates a quad-core ARM Cortex-A53 processor (Processing System, PS) and programmable logic (PL) resources, 2GB of LPDDR4 memory, and peripheral interfaces such as USB 3.0, DisplayPort, Wi-Fi, and Bluetooth. This device has wide applications in scientific research, industry, and other fields.

[0027] In this embodiment, the application and bitstream management files written by the tenant according to the task objective are obtained and stored on the SD card.

[0028] like Figure 2 As shown, in this embodiment, tenants can use hardware description languages ​​such as Verilog and SystemVerilog to develop hardware acceleration tasks. Alternatively, they can use Vitis HLS to convert programs in high-level programming languages ​​such as C and C++ into hardware description languages, and then use Vivado to complete the synthesis and implementation process, confining the circuit within the boundaries of the IAU and connecting it to the reserved interface of the IAU. Finally, the hardware acceleration task bitstream is generated and placed in the SD card.

[0029] In this embodiment, to manage various hardware bitstreams, a bitstream management file is written in YAML language. The bitstream management file template is as follows: Figure 3As shown, the bitstream management file includes the following: Name: The filename of the bitstream; Type: The type of bitstream, whether it is a hardware layer bitstream or a bitstream of a hardware acceleration task deployed in an IAU; Region: You can specify a specific IAU for deployment, or you can leave it unspecified; Location: Specifies the path of the bitstream file, placing the bitstream management file on the SD card.

[0030] This embodiment uses a lightweight FPGA virtualization model, such as... Figure 4 As shown, considering the need for seamless multi-tenancy and multi-task switching, a tight integration of software and hardware would reduce flexibility. Therefore, a decoupled layered architecture is adopted, consisting of a software layer and a hardware layer. The software layer runs on the PS (Power Supply) and is responsible for resource scheduling, task management, application hosting, data acquisition, and data display. The hardware layer runs on the PL (Power Supply) and is responsible for hardware acceleration and resource isolation. The two layers interact through a predefined communication interface to jointly realize an onboard autonomous multi-tenant virtualization framework, eliminating the need for an external host server.

[0031] The software layer is divided into an application sublayer and a management sublayer. The application sublayer runs the applications written by the tenant, generates task instructions, and sends the task instructions to the management sublayer.

[0032] The application sublayer is a lightweight, isolated container used to host tenant applications. It is developed using programming languages ​​such as C and C++ and can implement functions such as a visual operation interface, data collection, and data preprocessing. It interacts with the management sublayer through reserved data communication interfaces.

[0033] The functionality of an application is determined by the developer and can include interactive interfaces, data acquisition, data preprocessing, and result display. Each tenant can only run one application, but each application can submit multiple hardware-accelerated tasks, and applications are strictly isolated from each other. An application sublayer can run multiple applications from multiple tenants.

[0034] The management sublayer is the control center of the entire lightweight virtualization model. It reads and parses the bitstream management file pre-stored in the SD card according to the task instructions, calls the corresponding hardware-accelerated bitstream, distinguishes different bitstreams by parsing the management file, realizes multi-tenant resource allocation, loads the hardware-accelerated bitstream into the idle IAU, and monitors and records the hardware resource usage in real time.

[0035] The management sublayer can also read the calculated data and send it to the application sublayer, which can then write it to the SD card or output it to the display screen as needed.

[0036] The management sublayer is developed based on the open-source PYNQ system. PYNQ has the support of the open-source community, which greatly reduces the development burden. The management sublayer is the framework's control center, providing functions such as listening interfaces, task scheduling, and data logging. It also provides a unified upward access mechanism to support the operation of tenant applications. It is used to abstract hardware resources, provide data communication interfaces, implement multi-tenant resource allocation, load hardware-accelerated bitstreams into the IAU, monitor and record hardware resource usage in real time, and serve as a communication link to achieve high-speed data communication.

[0037] The hardware layer is divided into a bridging sublayer and an acceleration sublayer. This embodiment, based on the hardware resources of Ultra96-V2 and common applications in edge computing scenarios, finely divides the resources on the PL side into a bridging sublayer and an acceleration sublayer.

[0038] The bridging sublayer acts as a bridge, providing a unified access interface to the management sublayer above and connecting to the acceleration sublayer below, thus enabling communication between the acceleration sublayer and the software layer. The connection between the IAU and the bridging sublayer is as follows: Figure 5 As shown, the core components of the bridging sublayer include: the AXI Interconnect matrix, the MMU, the interrupt aggregation and distribution unit, and the data communication interface. The AXI Interconnect matrix enables intelligent routing between multiple master devices (PS) and multiple IAUs, supporting address decoding, data transmission, and instruction delivery, ensuring orderly scheduling of data flows in high-concurrency scenarios. The MMU is an embedded high-performance memory controller, reducing the CPU's involvement in data handling and improving end-to-end throughput efficiency. The interrupt aggregation and distribution unit cuts off signal transmission during task updates to prevent impact on the overall framework operation. The data communication interface uses the AXI4 and AXI Lite protocols, providing a channel for data and instruction transmission between the lower-layer IAUs and the upper-layer software layer. The bridging sublayer connects the software layer and the acceleration sublayer, enabling data and instruction transmission.

[0039] The acceleration sublayer is the part actually used for hardware acceleration, and it includes multiple IAUs, each of which constitutes the smallest unit for hardware acceleration. In this embodiment, the acceleration sublayer is divided into three isolated acceleration units (IAUs). Each IAU has the same clock layout and hardware resources, and communicates with the outside world through reserved interfaces. Each IAU has reserved AXI4 and AXI Lite interfaces. The AXI4 master interface is used for high-speed, low-latency data transmission, and the AXI Lite slave interface is used for transmitting control commands. There are strict boundary restrictions between IAUs; the circuitry for hardware acceleration tasks must not exceed the boundaries, and circuitry between IAUs must not overlap to prevent signal crosstalk.

[0040] An IAU can host a tenant's hardware acceleration task and interact with other hardware devices through a bridging sublayer. Multiple IAUs can simultaneously accelerate the same task to achieve parallel hardware acceleration. The more IAUs there are, the more tasks can run concurrently, but the fewer resources each IAU has. A balance needs to be struck between the number of IAUs and the available hardware resources. IAUs use the AXI4 master interface as a standardized interface to provide a high-bandwidth, low-latency data channel, and the AXI Lite slave interface to handle control commands, status queries, and interrupt signals.

[0041] In one embodiment, because tenant tasks exhibit high heterogeneity, with both bandwidth-sensitive and computationally intensive tasks coexisting, and bandwidth-sensitive tasks requiring significant data bandwidth while computationally intensive tasks demand high computing power, this embodiment also establishes a task-driven elastic scheduling mechanism and proposes a dynamic aggregation algorithm, such as... Figure 6 As shown, it is divided into three stages: The first stage is task feature extraction: The management sublayer parses the management file to distinguish different bit streams by the task instructions submitted by the application sublayer, analyzes and records the characteristics of the task, and extracts the key parameters of the task, including the specified number of IAUs, the size of the memory buffer, and historical running data.

[0042] Based on the parameters obtained during the task feature extraction phase, the computational communication strength ratio R of the task is calculated using the following formula: (1) in, This is the estimated peak computing power requirement based on a specified number of IAUs and the computing power per IAU. This is the maximum amount of data exchanged per unit time, estimated based on the memory buffer size and historical runtime data.

[0043] when When, it is determined to be computationally intensive; when Furthermore, if the historical memory write bandwidth ratio exceeds a preset threshold, it is determined to be bandwidth-sensitive; otherwise, it is determined to be mixed. , This is a preset threshold.

[0044] The second stage is resource monitoring. When resources are running, the working status of the IAU is collected in real time to monitor resource utilization, memory write activity, and task execution speed.

[0045] Based on the real-time collected IAU working status, the currently idle IAUs are filtered out, and the number of IAUs to be allocated to the task for acceleration is determined according to the task type and the number of idle IAUs.

[0046] Finally, there is the dynamic scheduling phase: based on task characteristics and resource status, the optimal resource combination is allocated to the task. When resources are sufficient, for computationally intensive tasks, multiple IAUs are prioritized for parallel acceleration to achieve a high speedup ratio. For bandwidth-sensitive tasks, the number of IAUs used is limited to avoid memory bandwidth bottlenecks and reduce waste of hardware resources. For mixed tasks, the number of IAUs is dynamically adjusted to achieve a balance between computing power and bandwidth requirements.

[0047] Specifically, for compute-intensive tasks: if only one task is running, all IAUs are used to maximize resource utilization; if multiple tasks of different types are running, compute-intensive tasks are given priority in allocating more IAUs.

[0048] For bandwidth-sensitive tasks: if only one task is running, all IAUs are used to maximize resource utilization; if multiple different types of tasks are running, a small number of IAUs are allocated to the bandwidth-sensitive task to avoid congestion caused by memory bandwidth contention.

[0049] For hybrid tasks: dynamically balance the needs of both.

[0050] Based on the estimated number of IAUs, the hardware-accelerated bitstream of the task is loaded into the corresponding number of IAUs.

[0051] The number of IAUs will be reallocated when any of the following trigger conditions are detected: When continuous Within a monitoring period, if the memory bandwidth utilization exceeds the threshold... At the same time, reduce the number of IAUs allocated to bandwidth-sensitive tasks; When continuous During a monitoring period, when idle IAUs appear, i.e. the average IAU utilization rate decreases, the number of IAUs for compute-intensive and mixed tasks should be increased first. When some tasks have been completed at an accelerated pace, increase the number of IAUs for the remaining tasks.

[0052] After the number of IAUs is redistributed, the system continues to run, continuously monitoring the operational status of IAUs in real time to ensure full utilization of computing resources and guarantee the normal operation of the system.

[0053] This embodiment relies on a declarative resource abstraction model and a task feature-driven elastic scheduling algorithm, namely a dynamic aggregation algorithm, which can dynamically adapt resource allocation for computationally intensive, bandwidth-sensitive, and hybrid tasks, and achieve multi-tenant, multi-task isolation concurrency and hardware parallel acceleration.

[0054] In this embodiment, the specific implementation of the application's functions is determined by the developer. The developer can use programming languages ​​such as C and C++ to develop software that implements functions such as a visual operation interface, data acquisition, and data preprocessing. The application can write source data into memory, submit tasks to the management sublayer, and the management sublayer controls the hardware layer to read data from DDR memory for calculation. The calculation results are then written back to DDR memory, and the application retrieves the calculation results from memory for further processing.

[0055] This embodiment utilizes the gRPC protocol to implement a remote call interface for the application sublayer, defining three core RPC methods: SubmitTask: Submits an accelerated task, including the task ID, target region, and input / output buffer pointers; AllocateBuffer and ReleaseBuffer: Dynamically allocate / release shared memory buffers.

[0056] Example 2 This embodiment provides a lightweight embedded FPGA virtualization system, including: Acquisition module: Acquires the application and bitstream management files written by the tenant according to the task objectives; Application sublayer module: Input the application written by the tenant into the application sublayer to obtain task instructions; Management sub-layer module: Sends task instructions to the management sub-layer, which then calls the corresponding hardware-accelerated bitstream in the bitstream management file according to the task instructions and uses a dynamic aggregation algorithm to schedule resources for the hardware-accelerated bitstream; Hardware acceleration module: Loads the hardware-accelerated bitstream after resource scheduling into the idle acceleration sublayer through the bridging sublayer, and the acceleration sublayer performs hardware-accelerated calculations to obtain the calculation results; Results module: The calculated results are sent back to the application sub-layer, which then stores or displays them as needed.

[0057] The descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0058] The proposed system can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and the division of modules described above is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed.

[0059] Example 3 This embodiment also provides an electronic device, including: one or more processors, one or more memories, and one or more computer programs; wherein, the processor is connected to the memory, and the one or more computer programs are stored in the memory. When the electronic device is running, the processor executes the one or more computer programs stored in the memory to cause the electronic device to perform the method described in Embodiment 1.

[0060] It should be understood that in this embodiment, the processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0061] Memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of memory may also include non-volatile random access memory. For example, memory may also store information about the device type.

[0062] In the implementation process, each step of the above method can be completed by the integrated logic circuits in the processor hardware or by software instructions.

[0063] The method in Embodiment 1 can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor. The software modules can reside in readily available storage media in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, a detailed description is not provided here.

[0064] Those skilled in the art will recognize that the units and algorithm steps described in connection with the various examples of this embodiment can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention.

[0065] Example 4 This embodiment also provides a storage medium for storing computer instructions, which, when executed by a processor, complete the method described in Embodiment 1.

[0066] Example 5 This embodiment also provides a computer program product, including a computer program that, when run on one or more processors, implements the method described in Embodiment 1.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A lightweight embedded FPGA virtualization method, characterized in that, include: Obtain the application and bitstream management files written by the tenant according to the task objectives; The application written by the tenant is input into the application sub-layer to obtain task instructions; The application sublayer runs multiple applications for multiple tenants, and each application includes one or more tasks; The task instruction is sent to the management sub-layer, which then calls the corresponding hardware-accelerated bitstream in the bitstream management file according to the task instruction and uses a dynamic aggregation algorithm to schedule resources for the hardware-accelerated bitstream. The management sublayer calls the corresponding hardware-accelerated bitstream from the bitstream management file according to the task instructions, and uses a dynamic aggregation algorithm to perform resource scheduling on the hardware-accelerated bitstream, including: Task feature extraction stage: The management sublayer parses the management file to distinguish different bit streams by the task instructions submitted by the application sublayer, analyzes and records the characteristics of the task, and extracts the key parameters of the task; During the resource monitoring phase, when resources are running, the working status of the IAU is collected in real time to monitor resource utilization, memory write activity, and task execution speed. Dynamic scheduling phase: Allocate the optimal resource combination to the task based on task characteristics and resource status; The hardware-accelerated bitstream after resource scheduling is loaded into the idle acceleration sublayer through the bridging sublayer, and the acceleration sublayer performs hardware-accelerated calculations to obtain the calculation results. The acceleration sublayer is the part that is actually used for hardware acceleration. The acceleration sublayer is divided into multiple isolated acceleration units (IAUs). Each IAU has the same clock layout and hardware resources and communicates with the outside world through reserved interfaces. The calculated results are sent back to the application sub-layer, which then stores or displays them as needed.

2. The lightweight embedded FPGA virtualization method of claim 1, wherein, The bitstream management file includes the following: Name: The filename of the bitstream; Type: The type of bitstream, whether it is a hardware layer bitstream or a bitstream of a hardware-accelerated task deployed in the IAU; Region: Deployed in a specific IAU; Location: The path to the bitstream file.

3. The lightweight embedded FPGA virtualization method of claim 1, wherein, The core components of the bridging sublayer include: AXI Interconnect matrix, MMU, interrupt aggregation and distribution unit, and data communication interface, which enables the connection between the management sublayer and the acceleration sublayer.

4. A lightweight embedded FPGA virtualization system, comprising: include: Acquisition module: Acquires the application and bitstream management files written by the tenant according to the task objectives; Application sublayer module: Input the application written by the tenant into the application sublayer to obtain task instructions; The application sublayer runs multiple applications for multiple tenants, and each application includes one or more tasks; Management sub-layer module: Sends task instructions to the management sub-layer, which then calls the corresponding hardware-accelerated bitstream in the bitstream management file according to the task instructions and uses a dynamic aggregation algorithm to schedule resources for the hardware-accelerated bitstream; The management sublayer calls the corresponding hardware-accelerated bitstream from the bitstream management file according to the task instructions, and uses a dynamic aggregation algorithm to perform resource scheduling on the hardware-accelerated bitstream, including: Task feature extraction stage: The management sublayer parses the management file to distinguish different bit streams by the task instructions submitted by the application sublayer, analyzes and records the characteristics of the task, and extracts the key parameters of the task; During the resource monitoring phase, when resources are running, the working status of the IAU is collected in real time to monitor resource utilization, memory write activity, and task execution speed. Dynamic scheduling phase: Allocate the optimal resource combination to the task based on task characteristics and resource status; Hardware acceleration module: Loads the hardware-accelerated bitstream after resource scheduling into the idle acceleration sublayer through the bridging sublayer, and the acceleration sublayer performs hardware-accelerated calculations to obtain the calculation results; The acceleration sublayer is the part that is actually used for hardware acceleration. The acceleration sublayer is divided into multiple isolated acceleration units (IAUs). Each IAU has the same clock layout and hardware resources and communicates with the outside world through reserved interfaces. Results module: The calculated results are sent back to the application sub-layer, which then stores or displays them as needed.

5. An electronic device, comprising: include: Memory is used to store computer-readable instructions in a non-transitory manner. as well as Processor, for executing the computer-readable instructions, When the computer-readable instructions are executed by the processor, they perform a lightweight embedded FPGA virtualization method as described in any one of claims 1-3.

6. A storage medium, characterized by Non-transitory storage computer-readable instructions, wherein when the non-transitory computer-readable instructions are executed by a computer, a lightweight embedded FPGA virtualization method according to any one of claims 1-3 is performed.

7. A computer program product, characterised in that, Includes a computer program, which, when run on one or more processors, is used to implement a lightweight embedded FPGA virtualization method as described in any one of claims 1-3.

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