Wafer-level core heterogeneous integration-based security perception task scheduling method and system

Abstract

The present application relates to the technical field of task scheduling, in particular to a security-aware task scheduling method and system based on wafer-level core particle heterogeneous integration, a task scheduling model of a wafer-level core particle heterogeneous integration platform is established, the task scheduling model is a model for simultaneously optimizing the performance and core particle credibility of the wafer-level core particle heterogeneous integration platform under multiple constraint conditions; the task scheduling model is iteratively solved to obtain a final task scheduling scheme and output, wherein in the iterative solving, the tasks are distributed to the corresponding core particles according to the task scheduling scheme obtained by the current solving, the task execution state is monitored to detect task execution abnormalities and count the execution results of each core particle, the core particle credibility and the binary risk matrix in the constraint conditions are updated according to the core particle execution results, and the task scheduling in the next round of model solving is performed. The present application can flexibly balance the performance and safety requirements and improve the trustworthiness of wafer-level chips in safety-critical applications.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design automation (EDA) and task scheduling technology, specifically to task scheduling in wafer-level chip and chiplet heterogeneous integration platforms, and particularly to a security-aware task scheduling method and system based on wafer-level chiplet heterogeneous integration. Background Technology

[0002] System on Wafer (SoW), as an emerging chip integration architecture in recent years, is a key technological direction for addressing the challenges of Moore's Law approaching its physical limits and the increasing difficulty and cost of monolithic chip integration. Chiplet technology breaks down a large chip into several relatively independent small chip units and achieves heterogeneous integration by relying on advanced packaging technologies such as 2.5D / 3D integration, hybrid bonding, and TSV (Through Silicon Via). It has significant technological advantages: the manufacturing yield of its small-sized chips is much higher than that of large-sized monolithic chips; it allows for flexible combination of chips with different process nodes and functions; and it can dynamically adjust the number and type of chips according to actual needs. At the same time, it effectively reduces design and manufacturing costs by reusing mature chip IP.

[0003] In the fields of parallel computing and distributed systems, tasks are typically represented as Directed Acyclic Graphs (DAGs), where nodes represent subtasks with attributes such as execution time and resource requirements, and edges reflect data and control dependencies between tasks. The core objective of task scheduling is to rationally allocate all tasks to computing resources, such as particles, while satisfying dependency and resource constraints, and optimizing specific goals such as total execution time, energy consumption, and load balancing. Existing particle-oriented scheduling techniques mainly fall into two categories: one is linear programming-based scheduling methods, which generate resource lists by acquiring the computational application task graph and particle topology and then perform graph optimization; the other is heuristic scheduling methods, encompassing genetic algorithms, simulated annealing, and particle swarm optimization. These methods are simple to implement and computationally fast, but they have limitations such as not being able to guarantee the optimal solution and being prone to getting trapped in local optima.

[0004] Existing chip scheduling technologies, when applied to wafer-level heterogeneous chip-chip integrated systems, fail to effectively model and quantify the inherent security risks of task-chip combinations. Chips integrated into wafer-level chips typically originate from different vendors, and attackers may insert malicious chips into the supply chain, replacing trusted chips in the original design. This replacement could lead to the implantation of hardware trojans into the entire system, resulting in data theft, functional disruption, or the creation of backdoors. Furthermore, existing research has confirmed that scheduling specific tasks to specific chips can trigger such risks; for example, executing certain tasks on specific chips may activate hardware trojans, trigger security vulnerabilities, or lead to the leakage of sensitive information through side channels. However, existing scheduling decisions only focus on performance indicators such as execution time and resource utilization, ignoring the existence of such security risks. They lack a systematic risk assessment model and fail to incorporate security factors into the scheduling constraint system, resulting in inherent security vulnerabilities in the scheduling scheme from the source, making it impossible to avoid system failure risks caused by inherent security threats. Moreover, existing scheduling methods are generally static, lacking dynamic security adjustment mechanisms based on chip historical behavior, making it difficult to adapt to reliability changes throughout the chip's lifecycle. The operating state of a kernel is not constant; its reliability dynamically changes with factors such as operating time and environmental conditions. For example, performance degradation and increased failure rates are caused by kernel aging, hardware malware activation due to long-term operation, and abnormal kernel behavior caused by temperature and voltage fluctuations. These dynamic changes directly affect the safety and stability of the kernel's task execution. However, current technologies only formulate scheduling strategies based on the initial state of the kernel, failing to adjust the scheduling logic by learning from the kernel's historical execution data, and lacking a closed-loop feedback optimization mechanism. This leads to a continuous accumulation of safety risks caused by the decay of kernel reliability during long-term system operation, gradually reducing the overall operational stability and security of the system. Furthermore, current technologies lack systematic quantitative methods and optimization frameworks, making it impossible to achieve the optimal balance between safety and performance indicators in the scheduling scheme. In practical applications, scheduling strategies must balance both security and performance objectives. Overly conservative scheduling schemes, while mitigating security risks by limiting the scope of chip usage, result in low chip resource utilization and a significant increase in total system execution time, failing to meet high-performance computing demands. Conversely, overly aggressive scheduling schemes, while fully utilizing chip resources to optimize performance, drastically increase the probability of high-risk "task-chip" combinations, leading to a higher probability of security incidents. Current technologies lack a quantifiable security and performance evaluation system and a multi-objective optimization model to balance their weights, focusing solely on either performance or security dimensions, making it difficult to adapt to the diverse security and performance requirements of different scenarios such as finance, defense, and autonomous driving. Summary of the Invention

[0005] To address the issues of unmodeled security risks in task and chip combinations, lack of dynamic security mechanisms based on historical behavior, and difficulty in balancing platform security domain performance in existing wafer-level chip-chip heterogeneous integration platforms, this invention provides a security-aware task scheduling method and system based on wafer-level chip-chip heterogeneous integration. This method utilizes a binary risk matrix to... The inherent security risks of combinations are modeled, combinations with inherent security risks are quantitatively identified, and binary risk constraints are integrated into the scheduling model to prohibit unsafe combinations. The system combines scheduling; at the same time, it establishes a reputation update mechanism based on historical behavior, which dynamically updates the reputation of the core particles by statistically analyzing the historical execution success rate and failure rate of the core particles, so that performance indicators and security risk indicators can be taken into account when optimizing the scheduling scheme.

[0006] According to the design scheme provided by the present invention, on the one hand, a security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration is provided, comprising:

[0007] Obtain the task dependency graph, the wafer-level chip heterogeneous integration platform chip set, and the binary risk matrix between tasks and chips, and set an initial reputation for each chip. The binary risk matrix is ​​used to characterize the inherent security risks under the combination of tasks and chips.

[0008] A task scheduling model for a wafer-level chip-particle heterogeneous integration platform is established. The task scheduling model is a model that simultaneously optimizes the performance of the wafer-level chip-particle heterogeneous integration platform and the chip reputation under multiple constraints. The constraints include task uniqueness constraints, task execution dependency order constraints, chip resource mutual exclusion constraints, binary risk matrix constraints, runtime constraints, and dynamic reputation constraints.

[0009] The task scheduling model is iteratively solved to obtain and output the final task scheduling scheme. In the iterative solution, tasks are distributed to corresponding particles according to the task scheduling scheme obtained by the current solution. Task execution status is monitored to detect task execution anomalies and the execution results of each particle are statistically analyzed. Based on the particle execution results, the particle reputation and binary risk matrix in the constraints are updated and the task scheduling in the next round of model solution is executed.

[0010] As a further step in the security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration of the present invention, the task dependency graph is obtained, including:

[0011] The computational task is divided into several subtasks with task attributes, and the dependencies between the subtasks are extracted. The task attributes include task execution time and task resource requirements.

[0012] Based on subtasks and dependencies, the computation task is transformed into a directed acyclic graph, where nodes represent subtasks and edges represent dependencies between subtasks.

[0013] As a security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration of the present invention, further, a binary risk matrix between tasks and chips is obtained, including:

[0014] The intrinsic security risk analysis method is used to analyze the core particles and obtain the intrinsic security risk analysis results. The intrinsic security risk analysis method includes, but is not limited to: analysis using historical security event data, analysis using core particle security audit results, analysis based on the credibility of third-party core particle suppliers, and analysis based on the formal verification and simulation test results of the core particles.

[0015] A binary risk matrix between the task and the core is constructed based on the results of the intrinsic safety risk analysis.

[0016] As a further step in this invention, a task scheduling model for a wafer-level chip-particle heterogeneous integration platform is established, comprising:

[0017] The system sets a unique constraint based on the premise that a task can only be scheduled to one core; a task dependency order constraint based on the premise that a task can only start execution after all its predecessor tasks are completed; a resource mutual exclusion constraint based on the premise that only one task can be executed in the same core at the same time; a binary risk matrix constraint based on the premise that tasks should not be scheduled to cores with inherent security risks; a runtime constraint based on the premise that the total platform runtime must be greater than or equal to the completion time of all tasks; and a dynamic reputation constraint based on the dynamic update of reputation based on the historical behavior statistics of cores.

[0018] Based on the constraints, a task scheduling model represented by a multi-objective optimization framework is constructed, and the platform performance and core reputation weights are adjusted using the multi-objective optimization framework.

[0019] As a security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration of the present invention, the reputation dynamic constraint is further expressed as: ,in, For core At any moment Reputation; For core In the next moment credibility For core Historical reputation, For core Contribution to current performance A credibility smoothing coefficient set according to the task scenario. , They represent the core particles respectively. Historical execution success rate, historical anomaly rate.

[0020] As a security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration of the present invention, the optimization objective of the task scheduling model is further expressed as: ,in, To optimize the platform's total runtime Performance weights, As a weight for reputation-based revenue, For the task Distributed to core binary variables, Representing the task set and the core set, respectively. This indicates that the updated core is based on the historical behavior statistics of the core particles. Reputation level.

[0021] As a security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration of the present invention, further, the task scheduling in the next round of model solving is performed by updating the chip-particle reputation and binary risk matrix in the constraints according to the chip-particle execution results, including:

[0022] If an abnormal task execution is detected, the corresponding core is obtained, the binary risk matrix is ​​updated, and the reputation of the corresponding core is updated according to the reputation constraint. The updated reputation is then fed back to the next round of task scheduling so that the updated reputation can be used in the task scheduling model to map between task cores.

[0023] Furthermore, this invention also provides a security-aware task scheduling system based on wafer-level chip-particle heterogeneous integration, comprising: a data acquisition module, a model building module, and an optimization output module, wherein...

[0024] The data acquisition module is used to acquire the task dependency graph, the wafer-level chip heterogeneous integration platform chip set, and the binary risk matrix between tasks and chips, and to set an initial reputation for each chip. The binary risk matrix is ​​used to characterize the inherent security risks under the combination of tasks and chips.

[0025] The model building module is used to establish a task scheduling model for the wafer-level chip-particle heterogeneous integration platform. The task scheduling model is a model that simultaneously optimizes the performance of the wafer-level chip-particle heterogeneous integration platform and the chip reputation under multiple constraints. The constraints include task uniqueness constraints, task execution dependency order constraints, chip resource mutual exclusion constraints, binary risk matrix constraints, runtime constraints, and dynamic reputation constraints.

[0026] The optimized output module is used to iteratively solve the task scheduling model, obtain the final task scheduling scheme and output it. In the iterative solution, tasks are distributed to the corresponding cores according to the task scheduling scheme obtained by the current solution. Task execution status is monitored to detect task execution anomalies and the execution result of each core is counted. The core reputation and binary risk matrix in the constraints are updated according to the core execution result and the task scheduling in the next round of model solution is executed.

[0027] The beneficial effects of this invention are:

[0028] This invention achieves quantitative modeling of the security risks of task-chip combination through binary risk matrix constraints, eliminating inherent security risks at the source; establishes a reputation update mechanism based on historical behavior to achieve adaptive learning and closed-loop optimization of chip reliability; and constructs a multi-objective optimization framework to unify security factors and traditional scheduling constraints in one optimization framework, flexibly balancing performance and security requirements, significantly improving the reliability of wafer-level chips in security-critical applications, while reducing security protection costs. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the security awareness task scheduling process based on wafer-level chip-particle heterogeneous integration in the embodiment.

[0030] Figure 2 This is a schematic diagram of the security awareness and task scheduling algorithm in the embodiment. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer and more understandable, the invention will be further described in detail below with reference to the accompanying drawings and technical solutions.

[0032] In task scheduling of wafer-level heterogeneous chip-particle integrated systems, there is a lack of effective modeling and quantification methods for the inherent security risks of task-particle combinations. Existing scheduling methods cannot proactively avoid high-risk scenarios through scheduling decisions while satisfying task dependency constraints, resource constraints, and performance requirements. This invention aims to eliminate inherent security risks at their source. However, the lack of a dynamic reputation update mechanism based on historical behavior prevents the system from learning about core reliability changes and adaptively adjusting scheduling strategies. Furthermore, the absence of a systematic approach to integrating security risk constraints and reputation feedback mechanisms into the existing task scheduling framework makes it difficult to achieve a balanced optimization of security and performance. Therefore, this invention provides embodiments, see [link to embodiments]. Figure 1 As shown, a security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration is provided, comprising:

[0033] S101. Obtain the task dependency graph, the wafer-level chip heterogeneous integration platform chip set, and the binary risk matrix between tasks and chips, and set an initial reputation for each chip. The binary risk matrix is ​​used to characterize the inherent security risks under the combination of tasks and chips.

[0034] In this embodiment, complex computational tasks are transformed into structured dependency graphs that can be efficiently processed by multi-core platforms, providing a foundational model for resource allocation and scheduling decisions. Specifically, the computational task can be divided into several subtasks with task attributes, such as decomposing the computational logic in a deep learning model into operators like matrix multiplication, convolution, and activation functions, with each operator considered as a node in the graph. Dependencies between subtasks are extracted, and these task attributes include task execution time and resource requirements. Based on the subtasks and dependencies, the computational task is transformed into a directed acyclic graph, where nodes represent subtasks, edges represent dependencies between subtasks, and edge weights can represent data transmission volume or communication latency to reflect the cost of cross-core communication.

[0035] The core is analyzed using intrinsic security risk analysis methods to obtain the results. These methods include, but are not limited to: analysis using historical security event data, analysis using core security audit results, analysis based on the credibility of third-party core suppliers, and analysis based on the formal verification and simulation test results of the core. A binary risk matrix between the task and the core is constructed based on the intrinsic security risk analysis results.

[0036] S102. Establish a task scheduling model for the wafer-level chip-particle heterogeneous integration platform. The task scheduling model is a model that simultaneously optimizes the performance of the wafer-level chip-particle heterogeneous integration platform and the chip reputation under multiple constraints. The constraints include task uniqueness constraints, task execution dependency order constraints, chip resource mutual exclusion constraints, binary risk matrix constraints, runtime constraints, and reputation dynamic constraints.

[0037] Specifically, task uniqueness constraints can be set based on the premise that a task can only be scheduled to one core; task dependency order constraints can be set based on the premise that a task can only start execution after all its predecessor tasks are completed; resource mutual exclusion constraints can be set based on the premise that only one task is executed in the same core at the same time; binary risk matrix constraints can be set based on the premise that tasks should not be scheduled to cores with inherent security risks; runtime constraints can be set based on the premise that the total platform runtime must be greater than or equal to the completion time of all tasks; and reputation dynamic constraints can be set based on the dynamic update of reputation based on the historical behavior statistics of cores. Based on these constraints, a task scheduling model represented by a multi-objective optimization framework is constructed, and the platform performance and core reputation weights are adjusted using the multi-objective optimization framework.

[0038] S103. Iteratively solve the task scheduling model to obtain the final task scheduling scheme and output it. In the iterative solution, tasks are distributed to corresponding particles according to the task scheduling scheme obtained by the current solution. Task execution anomalies are detected by monitoring the task execution status and the execution results of each particle are statistically analyzed. Based on the particle execution results, the particle reputation and binary risk matrix in the constraints are updated and the task scheduling in the next round of model solution is executed.

[0039] If an abnormal task execution is detected, the corresponding core is obtained, the binary risk matrix is ​​updated, and the reputation of the corresponding core is updated according to the reputation constraint. The updated reputation is then fed back to the next round of task scheduling so that the updated reputation can be used in the task scheduling model to map between task cores.

[0040] In the specific implementation of the algorithm, the following symbols are defined:

[0041]

[0042] Assign variables, tasks Distributed to core The time is 1.

[0043] (1)

[0044] Task uniqueness constraint: Each task can only be scheduled onto one core.

[0045] (2)

[0046] Dependency order constraint: A task can only begin after all its predecessor tasks have been completed.

[0047] (3)

[0048] in The calculation method is as follows The sum of the start time and the execution time:

[0049]

[0050] Resource mutual exclusion constraint: Only one task can be executed by the same core at the same time.

[0051] (4)

[0052] (5)

[0053] (6)

[0054] (7)

[0055]

[0056] in As an auxiliary binary variable, representing the task Is it in the task? Previously executed. 1 hour indicates exist Then execute. The constant should be large enough to be greater than the total system runtime. This constraint avoids resource contention caused by time overlap.

[0057] Binary risk matrix constraint: It is prohibited to schedule tasks to cores with inherent security risks.

[0058] (8)

[0059] in A value of 1 indicates a security risk, while 0 indicates safety. Risk Matrix The sources include, but are not limited to: historical security incident data, hardware security audit results, credibility assessments of third-party chip suppliers, formal verification and simulation test results.

[0060] System runtime constraint: The total system runtime must be greater than or equal to the completion time of all tasks.

[0061] (9)

[0062] Reputation dynamic constraint: The reputation of the chip is dynamically updated based on historical behavior statistics.

[0063] (10)

[0064] in for At any moment The credibility score ranges from [0,1]. for The credibility at the next moment. (In the formula) For the sake of historical credibility, Contribution to current performance. When A value closer to 1 places greater emphasis on historical reputation. Values ​​close to 0 place greater emphasis on current performance. Using a smooth update that combines historical data with current performance can prevent excessive fluctuations in reputation caused by a single anomaly.

[0065] In formula (10) and The calculation method is as follows, and the number of exceptions includes: number of timeouts, number of output exceptions, and number of security events:

[0066] (11)

[0067] (12)

[0068] Using a multi-objective optimization framework, the weights of performance and reputation can be flexibly adjusted.

[0069] (13)

[0070] in Optimize the total system runtime based on performance weights. . Assign a weight to reputation-based revenue and maximize the use of high-reputation cores.

[0071] The algorithm flow is as follows Figure 2 As shown, it can be summarized as including the following steps:

[0072] Step 1: Risk Assessment and Credit Initialization

[0073] Based on historical security incident data, known high-risk task-particle combinations are labeled. A binary risk matrix is ​​constructed by combining the credibility of third-party particle suppliers with formal verification and simulation test results. An initial credibility level is assigned to each particle. Suggested initial value range:

[0074] Step 2: Scheduling Model Construction

[0075] Based on the definitions of variables, constraints, and objective function in the technical solution, use CPLEX to construct and solve a linear programming model. The inputs and outputs are as follows:

[0076] Input: Task graph Core assembly Risk Matrix Initial credibility .

[0077] Output: Task-core mapping results System uptime and security risk values.

[0078] Step 3: Task Execution and Monitoring

[0079] according to Distribute tasks to the corresponding cores. Monitor task execution status, including running, completed, and timed out. Collect task execution results and detect abnormal behaviors such as output anomalies and security events. After execution, calculate the success rate and failure rate for each core.

[0080] Step 4: Reputation Update and Closed-Loop Optimization

[0081] The success rate and failure rate of the core particle's task execution are calculated using formulas (11) and (12), and the reputation is updated using formula (10). If a new security risk is detected, the risk matrix is ​​dynamically updated, and its reputation is reduced. The updated reputation is then updated. Feedback is relayed to the next round of scheduling. The updated reputation score is used in the objective function to achieve dynamic adaptive scheduling. The reputation score... The value can be adjusted according to the application scenario requirements. For example, a smaller value can be set when the chip is prone to rapid aging and failure in harsh environments. Values ​​that lead to faster response times and decreased chip performance; in stable environments such as data centers, setting larger values... This value helps prevent occasional malfunctions from causing drastic fluctuations in reputation.

[0082] Step 5: Output scheduling scheme

[0083] Output the mapping between tasks and kernels, the total system runtime, and kernel reputation statistics.

[0084] Furthermore, based on the above method, this embodiment of the invention also provides a security-aware task scheduling system based on wafer-level chip-particle heterogeneous integration, comprising: a data acquisition module, a model building module, and an optimization output module, wherein,

[0085] The data acquisition module is used to acquire the task dependency graph, the wafer-level chip heterogeneous integration platform chip set, and the binary risk matrix between tasks and chips, and to set an initial reputation for each chip. The binary risk matrix is ​​used to characterize the inherent security risks under the combination of tasks and chips.

[0086] The model building module is used to establish a task scheduling model for the wafer-level chip-particle heterogeneous integration platform. The task scheduling model is a model that simultaneously optimizes the performance of the wafer-level chip-particle heterogeneous integration platform and the chip reputation under multiple constraints. The constraints include task uniqueness constraints, task execution dependency order constraints, chip resource mutual exclusion constraints, binary risk matrix constraints, runtime constraints, and dynamic reputation constraints.

[0087] The optimized output module is used to iteratively solve the task scheduling model, obtain the final task scheduling scheme and output it. In the iterative solution, tasks are distributed to the corresponding cores according to the task scheduling scheme obtained by the current solution. Task execution status is monitored to detect task execution anomalies and the execution result of each core is counted. The core reputation and binary risk matrix in the constraints are updated according to the core execution result and the task scheduling in the next round of model solution is executed.

[0088] Unless otherwise specifically stated, the relative steps, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of the invention.

[0089] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0090] The units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations are not considered to be beyond the scope of this invention.

[0091] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This invention is not limited to any particular combination of hardware and software.

[0092] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration, characterized in that, Include: Obtain the task dependency graph, the wafer-level chip heterogeneous integration platform chip set, and the binary risk matrix between tasks and chips, and set an initial reputation for each chip. The binary risk matrix is ​​used to characterize the inherent security risks under the combination of tasks and chips. A task scheduling model for a wafer-level chip-particle heterogeneous integration platform is established. The task scheduling model is a model that simultaneously optimizes the performance of the wafer-level chip-particle heterogeneous integration platform and the chip reputation under multiple constraints. The constraints include task uniqueness constraints, task execution dependency order constraints, chip resource mutual exclusion constraints, binary risk matrix constraints, runtime constraints, and dynamic reputation constraints. The task scheduling model is iteratively solved to obtain and output the final task scheduling scheme. In the iterative solution, tasks are distributed to corresponding particles according to the task scheduling scheme obtained by the current solution. Task execution status is monitored to detect task execution anomalies and the execution results of each particle are statistically analyzed. Based on the particle execution results, the particle reputation and binary risk matrix in the constraints are updated and the task scheduling in the next round of model solution is executed.

2. The security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration according to claim 1, characterized in that, Obtain the task dependency graph, including: The computational task is divided into several subtasks with task attributes, and the dependencies between the subtasks are extracted. The task attributes include task execution time and task resource requirements. Based on subtasks and dependencies, the computation task is transformed into a directed acyclic graph, where nodes represent subtasks and edges represent dependencies between subtasks.

3. The security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration according to claim 1, characterized in that, Obtain the binary risk matrix between the task and the core, including: The intrinsic security risk analysis method is used to analyze the core particles and obtain the intrinsic security risk analysis results. The intrinsic security risk analysis method includes, but is not limited to: analysis using historical security event data, analysis using core particle security audit results, analysis based on the credibility of third-party core particle suppliers, and analysis based on the formal verification and simulation test results of the core particles. A binary risk matrix between the task and the core is constructed based on the results of the intrinsic safety risk analysis.

4. The security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration according to claim 1, characterized in that, Establish a task scheduling model for a wafer-level chip-particle heterogeneous integration platform, including: The system sets a unique constraint based on the premise that a task can only be scheduled to one core; a task dependency order constraint based on the premise that a task can only start execution after all its predecessor tasks are completed; a resource mutual exclusion constraint based on the premise that only one task can be executed in the same core at the same time; a binary risk matrix constraint based on the premise that tasks should not be scheduled to cores with inherent security risks; a runtime constraint based on the premise that the total platform runtime must be greater than or equal to the completion time of all tasks; and a dynamic reputation constraint based on the dynamic update of reputation based on the historical behavior statistics of cores. Based on the constraints, a task scheduling model represented by a multi-objective optimization framework is constructed, and the platform performance and core reputation weights are adjusted using the multi-objective optimization framework.

5. The security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration according to claim 1 or 4, characterized in that, The dynamic constraint on creditworthiness is represented as follows: ,in, For core At any moment Reputation; For core In the next moment credibility For core Historical reputation, For core Contribution to current performance A credibility smoothing coefficient set according to the task scenario. , They represent the core particles respectively. Historical execution success rate, historical anomaly rate.

6. The security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration according to claim 1 or 4, characterized in that, The optimization objective of the task scheduling model is expressed as: ,in, To optimize the platform's total runtime Performance weights, As a weight for reputation-based revenue, For the task Distributed to core binary variables, Representing the task set and the core set, respectively. This indicates that the updated core is based on the historical behavior statistics of the core particles. Reputation level.

7. The security-aware task scheduling method based on wafer-level chip-particle heterogeneous integration according to claim 1, characterized in that, Based on the core particle execution results, update the core particle reputation and binary risk matrix in the constraints and execute the task scheduling in the next round of model solving, including: If an abnormal task execution is detected, the corresponding core is obtained, the binary risk matrix is ​​updated, and the reputation of the corresponding core is updated according to the reputation constraint. The updated reputation is then fed back to the next round of task scheduling so that the updated reputation can be used in the task scheduling model to map between task cores.

8. A security-aware task scheduling system based on wafer-level chip-particle heterogeneous integration, characterized in that, It includes: a data acquisition module, a model building module, and an optimization output module, among which, The data acquisition module is used to acquire the task dependency graph, the wafer-level chip heterogeneous integration platform chip set, and the binary risk matrix between tasks and chips, and to set an initial reputation for each chip. The binary risk matrix is ​​used to characterize the inherent security risks under the combination of tasks and chips. The model building module is used to establish a task scheduling model for the wafer-level chip-particle heterogeneous integration platform. The task scheduling model is a model that simultaneously optimizes the performance of the wafer-level chip-particle heterogeneous integration platform and the chip reputation under multiple constraints. The constraints include task uniqueness constraints, task execution dependency order constraints, chip resource mutual exclusion constraints, binary risk matrix constraints, runtime constraints, and dynamic reputation constraints. The optimized output module is used to iteratively solve the task scheduling model, obtain the final task scheduling scheme and output it. In the iterative solution, tasks are distributed to the corresponding cores according to the task scheduling scheme obtained by the current solution. Task execution status is monitored to detect task execution anomalies and the execution result of each core is counted. The core reputation and binary risk matrix in the constraints are updated according to the core execution result and the task scheduling in the next round of model solution is executed.

9. An electronic device, characterized in that, include: At least one processor, and a memory coupled to said at least one processor; The memory stores a computer program that can be executed by the at least one processor to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, enables the implementation of the method as described in any one of claims 1 to 7.

Images