Control device, control method, and electronic device for multiplex communication

Abstract

This application provides a control device, control method, and electronic device for multi-channel communication, relating to the field of communication technology. The device includes a CPLD and multiple slave device interfaces. The CPLD includes a master device SGPIO interface module, a multiplexing module, and a counting module. The master device SGPIO interface module is used to receive or transmit multiple frames of communication data. The counting module, connected between the master device SGPIO interface module and the multiplexing module, is used to determine an incrementing count value based on the multiple frames of communication data and output the count value to the multiplexing module. The multiplexing module is connected to the multiple slave device interfaces and is used to determine the target slave device interface from among the multiple slave device interfaces based on the count value and transmit the multiple frames of communication data to the target slave device interface. This application effectively avoids increased hardware design costs, bill of materials adjustments, and extended testing cycles while ensuring real-time communication without requiring changes to the hardware design.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a control device, control method and electronic device for multi-channel communication. Background Technology

[0002] In modern high-performance server design, to achieve fine-grained monitoring, configuration management, and fault diagnosis of various subsystems, master devices (such as board management controllers or complex programmable logic devices (CPLDs)) need to communicate efficiently and reliably with multiple slave devices. The Serial General Purpose Input / Output (SGPIO) communication protocol, due to its inherent stability, excellent anti-interference capabilities, and low power consumption, has become a key technology in server hardware design for implementing such master-slave communication. This protocol enables dynamic resource allocation, energy optimization, and real-time management of system health status in complex data center environments.

[0003] Currently, a common technical solution for meeting the SGPIO communication needs between a server master device and multiple slave devices is to adopt a direct many-to-many connection architecture. In this solution, the master device (usually a CPLD or BMC) allocates an independent SGPIO interface to each slave device that needs to communicate and establishes a direct point-to-point connection. This design allows the master device to communicate with multiple slave devices in parallel, thereby ensuring the real-time performance of the communication to a certain extent.

[0004] However, the aforementioned direct many-to-many connection scheme can lead to increased hardware design costs in some scenarios. Summary of the Invention

[0005] The control device, control method, and electronic equipment for multi-channel communication provided in this application are used to effectively avoid increasing hardware design costs, adjusting bill of materials, and extending the testing cycle while ensuring real-time communication.

[0006] In a first aspect, this application provides a control device for multiplexed communication, including: a CPLD and multiple slave device interfaces, wherein the CPLD includes: a master device SGPIO interface module, a multiplexing module and a counting module;

[0007] The main device's SGPIO interface module is used to receive or send multiple frames of communication data.

[0008] The counting module is connected between the main device's SGPIO interface module and the multiplexing module. It is used to determine the incrementing count value of the flag based on multiple frames of communication data and output the count value to the multiplexing module.

[0009] The multiplexing module connects to multiple slave device interfaces and is used to determine the target slave device interface from among the multiple slave device interfaces based on the count value, and transmit multiple frames of communication data to the target slave device interface.

[0010] In one possible embodiment, the counting module includes a data frame detection submodule and a counter submodule; wherein,

[0011] The data frame detection submodule is used to detect the transmission status of any frame of communication data in a multi-frame communication data, and generate the corresponding transmission flag signal when it is determined that the transmission of a single frame of communication data has been completed.

[0012] The counter submodule, connected to the data frame detection submodule, is used to accumulate and count the number of frames of multi-frame communication data that have been sent in response to the transmission flag signal, so as to obtain the count value.

[0013] In one possible embodiment, the counter submodule includes an overflow unit for automatically resetting the count value to zero and restarting the increment when the count value reaches a preset maximum value, wherein the preset maximum value is equal to the number of device interfaces.

[0014] In one possible embodiment, a data buffer unit is provided between the multiplexing module and multiple slave device interfaces. The data buffer unit is used to temporarily store multiple frames of communication data, and after all multiple frames of communication data have been stored, the multiple frames of communication data are written to the corresponding target slave device interface.

[0015] In one possible embodiment, a redundant path mapping module is provided between the multiplexing module and multiple slave device interfaces, which is used to switch the interface connected to the transmission path of multiple frames of communication data to the corresponding backup slave device interface when an abnormality is detected in the target slave device interface.

[0016] In one possible embodiment, a fault recovery module is provided between the redundant path mapping module and the multiplexing module, which is used to switch the interface connected to the transmission path back to the target slave device interface when the target slave device interface is detected to be restored.

[0017] In one possible embodiment, the bit width of the counting module is determined based on the number of multiple slave device interfaces.

[0018] In one possible embodiment, the counting module integrates a load detection module for adjusting the increment frequency of the counting module based on the queue length of multi-frame communication data.

[0019] Secondly, this application provides a control method for multiplexing, applied to a control device including the multiplexing provided above, the control method comprising:

[0020] Detect the transmission flag signal of multiple frames of communication data received or sent by the SGPIO interface module of the main device;

[0021] The counting value of the counting module is incremented according to the transmitted flag signal;

[0022] Based on the count value, the target slave device interface is selected through the multiplexing module, and multiple frames of communication data are transmitted to the target slave device interface.

[0023] Thirdly, this application provides an electronic device, including: a memory and a processor;

[0024] The memory stores the instructions that the computer executes;

[0025] The processor executes computer execution instructions stored in memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0026] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the first aspect and / or various possible embodiments of the first aspect.

[0027] Fifthly, this application provides a computer program product, including a computer program that, when executed, implements the first aspect and / or various possible implementations of the first aspect.

[0028] This application provides a control device, control method, and electronic device for multi-channel communication, relating to the field of communication technology. The device includes a CPLD and multiple slave device interfaces. The CPLD includes a master device SGPIO interface module, a multiplexing module, and a counting module. The master device SGPIO interface module is used to receive or transmit multiple frames of communication data. The counting module, connected between the master device SGPIO interface module and the multiplexing module, is used to determine an incrementing count value based on the multiple frames of communication data and output the count value to the multiplexing module. The multiplexing module is connected to the multiple slave device interfaces and is used to determine the target slave device interface from among the multiple slave device interfaces based on the count value and transmit the multiple frames of communication data to the target slave device interface. This application achieves ordered multi-channel communication control of multiple slave device interfaces from a master device within a single control unit by setting a master device SGPIO interface module, a counting module, and a multiplexing module in a programmable logic device. The master device SGPIO interface module receives or sends multiple frames of communication data, the counting module determines an incrementing count value based on the multiple frames of communication data, and the multiplexing module identifies the target slave device interface from multiple slave device interfaces based on the count value and transmits the multiple frames of communication data. This reduces the logic resource consumption caused by direct connection of independent interfaces and avoids the increased latency and control complexity caused by introducing external switching devices, thereby improving the real-time performance, stability, and system scalability in multi-channel SGPIO communication scenarios. Furthermore, compared to existing technologies that require replacing the CPLD with a higher-performance model when the number of slave device interfaces exceeds the CPLD logic resource limit, this application eliminates the need for hardware design changes, effectively avoiding increased hardware design costs, bill of materials adjustments, and extended testing cycles while ensuring real-time communication. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0030] Figure 1 A schematic diagram of the control scheme structure used in existing technologies for multi-channel communication. Figure 1 ;

[0031] Figure 2 A schematic diagram of the control scheme structure used in existing technologies for multi-channel communication. Figure 2 ;

[0032] Figure 3 A schematic diagram of the control scheme structure used in existing technologies for multi-channel communication. Figure 3 ;

[0033] Figure 4 This is a schematic diagram of the structure of the control device for multi-channel communication provided in the embodiments of this application;

[0034] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0035] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0037] Multi-channel SGPIO communication control technology is widely used in board-level interconnect scenarios in servers, storage devices, and industrial control platforms, especially in system architectures where the master device needs to manage multiple functional slave devices simultaneously. In such hardware systems, the master device is typically a Baseboard Management Controller (BMC), CPLD, or other management control unit, while the slave devices can be power modules, fan modules, backplane units, sensor boards, or storage expansion components. The master device needs to send status synchronization information, configuration data, or control commands to each slave device via SGPIO links, while also needing to perform periodic polling and status acquisition in accordance with the overall system operation rhythm.

[0038] As server node integration continues to increase, the number of slave devices faced by a single master controller continues to grow, gradually forming a multi-channel communication architecture within the hardware system, consisting of a master device interface, multiple slave device interfaces, and corresponding signal distribution paths. Under this architecture, how to effectively manage multiple slave device interfaces within limited logical resources and maintain the stability and real-time performance of the communication process has become a typical requirement in server hardware design.

[0039] In the existing technology, three types of solutions are usually adopted to realize SGPIO communication between master device and multiple slave devices. Figure 1 A schematic diagram of the control scheme structure used in existing technologies for multi-channel communication. Figure 1 .like Figure 1As shown, this control scheme configures an independent communication interface for each slave device, and the master device (such as BMC or CPLD) directly establishes a one-to-one connection with each slave device. This method is relatively straightforward in structure and the control logic is relatively clear. The master device can complete the data transmission and reception of each slave device according to the predetermined timing sequence.

[0040] However, this existing technology faces significant limitations when dealing with a large number of slave devices. As the number of slave devices increases, the number of independent SGPIO interfaces also grows. This leads to a continuous increase in the I / O and internal logic resources consumed by the master device (whether it's a BMC device due to insufficient pin count or a CPLD device due to insufficient internal logic resource capacity). Once the required number of interfaces exceeds the capacity limit of the currently selected device, designers are forced to upgrade to higher-specification, more expensive devices. Such device upgrades not only trigger a series of chain reactions, including schematic adjustments, PCB layout modifications, bill of materials replacements, and an expansion of the testing and verification scope, but also significantly increase overall development costs and time-to-market. Therefore, this existing technology suffers from technical bottlenecks such as limited hardware resources, high costs, and long development cycles when handling large-scale SGPIO communication needs.

[0041] Figure 2 A schematic diagram of the control scheme structure used in existing technologies for multi-channel communication. Figure 2 .like Figure 2 As shown, the existing technical solution requires the use of an external switching device, a switching chip, to establish a multiplexing relationship between the master device and multiple slave devices. By controlling the EN signal at different times, the master device interface is redirected to different slave device interfaces, thereby reducing the number of interfaces directly occupied by the master control side. Although this existing technical solution alleviates the problem of interface resource shortage to some extent, the external switching device itself introduces additional switching paths and control links, making the communication process susceptible to the device response time, path stability, and signal integrity.

[0042] In scenarios involving high-frequency polling, rapid status updates, or continuous multi-frame transmission, improper coordination between switching timing and data transmission rhythm can easily lead to problems such as delayed channel switching, interrupted data frame transmission, and blurred timing boundaries, thereby affecting communication reliability. Furthermore, adding switching devices introduces additional wiring complexity, power consumption burden, and potential failure points, further increasing system maintenance difficulty and overall reliability risks.

[0043] Figure 3 A schematic diagram of the control scheme structure used in existing technologies for multi-channel communication. Figure 3 .like Figure 3As shown, in this prior art solution, the BMC device 11 is configured as the master SGPIO device 111. In contrast, the CPLD device acts as the slave SGPIO device, and the CPLD device integrates a data bus controller (DBC) and a multiplexer (MUX).

[0044] exist Figure 3 The image specifically showcases two CPLD devices: CPLD-12 and CPLD-13. CPLD-12 integrates: a slave SGPIO device 121 for communication with the master SGPIO device 111; two MUXs: MUX-122 and MUX-124; register 123; and a DBC-125. CPLD-13 integrates: a slave SGPIO device 131; two MUXs: MUX-3132 and MUX-4134; register 133; and a DBC-135. These components work together to manage and control the flow of SGPIO communication data.

[0045] In this configuration, the BMC is primarily responsible for sending communication data, while CPLD1 and CPLD2, as slave devices, are responsible for receiving data sent by the BMC and performing data switching and parsing. Specifically, the control logic for data switching and parsing is mainly implemented in CPLD1 and CPLD2. The switching control modules in CPLD1 and CPLD2 are designed to filter the communication data stream sent by the BMC, processing only the target data that needs to be parsed, and temporarily storing this target data in the register module, while ignoring other non-target data.

[0046] The existing technical solution uses a switching condition based on the number of bytes of received communication data. When the number of received bytes reaches a preset threshold, a data switching or processing mechanism is triggered. Therefore, the focus of this existing technical solution is on how the slave device can effectively process the communication data sent by the master device, especially how to filter and store data based on specific byte count conditions. Although this existing technical solution clearly defines the roles of the master and slave devices and defines the data processing flow, its switching mechanism relies on a fixed byte count, which may have limitations when dealing with dynamically changing or variable-length data transmissions. Furthermore, its design focuses on the internal data processing logic of the slave device, rather than optimizing overall communication efficiency or resource utilization.

[0047] In summary, existing solutions struggle to simultaneously balance logical resource consumption, real-time communication performance, and system implementation complexity.

[0048] In view of this, how to complete the orderly control of multiple slave device interfaces with less hardware resources in a multi-channel SGPIO communication scenario, and ensure that multiple frames of communication data can be transmitted stably according to a determined target path, has become an urgent technical problem to be solved.

[0049] To address the aforementioned technical problems, this application proposes a control device for multi-channel communication. This device is based on a CPLD (Content Management Logic Controller) to construct a communication control architecture. Within the CPLD, a master device SGPIO interface module, a counting module, and a multiplexing module are configured, and these modules work in conjunction with multiple slave device interfaces. Specifically, the master device SGPIO interface module receives or transmits multiple frames of communication data. The counting module determines an incrementing count value based on the multiple frames of communication data. Then, the multiplexing module uses this count value to determine the target slave device interface from among the multiple slave device interfaces and transmits the multiple frames of communication data to the target slave device interface.

[0050] This application combines counting control and interface selection within the same programmable logic device, enabling the orderly allocation of multiple communication paths without relying on external switching devices. This balances resource utilization, communication efficiency, and system complexity in multi-device management scenarios such as servers.

[0051] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0052] Figure 4 This is a schematic diagram of the structure of the control device for multiplexing provided in the embodiments of this application, as shown below. Figure 4 As shown, the control device for multi-channel communication includes: a CPLD and multiple slave device interfaces, wherein the CPLD includes: a master device SGPIO interface module, a multiplexing module and a counting module;

[0053] The main device's SGPIO interface module is used to receive or send multiple frames of communication data.

[0054] The counting module is connected between the main device's SGPIO interface module and the multiplexing module. It is used to determine the incrementing count value of the flag based on multiple frames of communication data and output the count value to the multiplexing module.

[0055] The multiplexing module connects to multiple slave device interfaces and is used to determine the target slave device interface from among the multiple slave device interfaces based on the count value, and transmit multiple frames of communication data to the target slave device interface.

[0056] In this embodiment, CPLD refers to a chip-type logic device used to implement configurable logic control and interface allocation in board-level circuits. It is used to carry the master device SGPIO interface module (SGPIO_Master), multiplexing module (MUX) and counting module (Count), and complete the generation, selection and forwarding of multiple communication paths within the same logic carrier, thereby reducing the dependence on external switching devices.

[0057] This CPLD can be installed in the logic control area of ​​a server motherboard, storage backplane, or industrial control board, and connected to multiple slave device interfaces via onboard traces. Its inputs receive communication control signals from the master control chip, while its outputs correspond to the selection and data channels of multiple slave device interfaces, thus forming a continuous data processing link within the same device. It should be noted that this is merely an example.

[0058] Furthermore, multiple slave device interfaces refer to external communication ports or board-level interfaces that are connected to the output of the CPLD's multiplexing module. They are used to receive multiple frames of communication data forwarded by the multiplexing module and send the communication data to the corresponding slave devices to achieve independent management of multiple communication objects.

[0059] Multiple slave device interfaces can be physically distributed in different areas of the same board and connected to the CPLD through independent wiring, connector contacts or flexible interconnection structures. Each interface corresponds electrically to a controlled transmission path so that it can be selected as the target channel under the indication of the count value.

[0060] The device interface can be a pin header interface, a board-to-board connector interface, or a high-speed serial transceiver interface. It can also be a differential signal interface conducted through the backplane, or a fixed pad interface that is directly soldered to the under-mount module. It should be noted that this is only an example.

[0061] Furthermore, the main device SGPIO interface module refers to the interface control unit located inside the CPLD, used to output communication frames to the subsequent logic. It is used to receive or send multiple frames of communication data, including clock signals (SGPIO-CLOCK), load signals (SGPIO-LOAD), output data (SGPIO-DOUT), and input data (SGPIO-DIN). According to a preset protocol, it sends continuous communication data frames to the counting module and the multiplexing module, thereby providing a unified data source for subsequent channel selection and data distribution.

[0062] The aforementioned communication data is processed by the SGPIO main control module, which mainly includes: an SGPIO clock generation module, an SGPIO clock edge detection module, a data receiving module, and a data transmitting module. The SGPIO clock generation module is responsible for generating the clock signal required for SGPIO signals; the SGPIO clock edge detection module uses this clock signal to detect its rising or falling edge, providing a precise time reference for subsequent data synchronization and frame identification; the data receiving module converts the received serial data stream into parallel data for subsequent logic processing. Furthermore, the data transmitting module is also responsible for converting parallel data back into serial data for output. The data receiving and data transmitting modules work together to complete the conversion between serial and parallel data, laying the foundation for the effective detection and processing of data frames.

[0063] The main device SGPIO interface module is located at the front end of the entire data processing link. One side can be connected to the SGPIO transmitter, level conversion unit or protocol control source on the main control side, while the other side is connected to the counting module and multiplexing module through internal logic connections to form a synchronous trigger signal when the frame starts, the frame ends or the inter-frame interval arrives.

[0064] The SGPIO interface module of the master device can be in the form of serial interface control logic, bus interface control logic, or custom protocol control logic, or it can be a composite logic consisting of shift registers, frame synchronization detection units, and status output units. It should be noted that this is only an example.

[0065] The counting module is a timing logic unit connected between the master device's SGPIO interface module and the multiplexing module. It is used to generate an incrementing count value based on multiple frames of communication data. Its function is to mark each of the communication frames that have been sent or are about to be sent, thereby providing the multiplexing module with a basis for selecting the target slave device interface.

[0066] The counting module is positioned after the main device's SGPIO interface module and before the multiplexing module. It is typically connected to the main device's SGPIO interface module via frame completion indication, sending enable signals, or synchronization pulses. It also transmits the current counting status to the multiplexing module through the counting output terminal, so that each frame of data can correspond to a predetermined interface selection state.

[0067] The counting module can be a synchronous counter, an asynchronous counter, or a state machine counting structure, or it can be a register counting unit with a reset terminal, an enable terminal, and a carry control terminal. It should be noted that this is only an example.

[0068] A multiplexing module is a logical switching unit that connects to multiple slave device interfaces and selects between multiple interfaces based on a count value to complete data forwarding. Its function is to route multiple frames of communication data output by the master device's SGPIO interface module to the currently selected target slave device interface in order to achieve sequential allocation of multiple communication paths.

[0069] The multiplexing module is located in the middle to rear section of the data path inside the CPLD. Its input is coupled to the output of the master device SGPIO interface module and the counting output of the counting module. Its output is connected to multiple slave device interfaces, and it determines the target channel corresponding to the current frame through selection logic, decoding logic or lookup table logic.

[0070] The multiplexing module can take the form of a combination of encoder and decoder, a cascaded switch tree structure, or a selection array structure based on a lookup table. It should be noted that this is only an example.

[0071] As can be seen from the above analysis, in the operation of the multi-communication control device provided in this application embodiment, the master device SGPIO interface module first receives multiple frames of communication data from the master control side, and sends the continuous communication data into the internal logic link in units of frames; the counting module determines the incrementing count value of the flag through the multiple frames of communication data; the multiplexing module then selects multiple slave device interfaces according to the count value, and forwards the current frame to the predetermined target slave device interface.

[0072] Meanwhile, the main device's SGPIO interface module, counting module, and multiplexing module are all integrated within the same programmable logic device, which shortens the coupling path between the data source, counting basis, and target selection logic, makes communication timing easier to unify, and enables the deterministic switching of paths and the stability of data forwarding in multi-frame continuous transmission scenarios.

[0073] Furthermore, since multiple slave device interfaces are allocated in an orderly manner through an internal counting and selection mechanism, when increasing the number of slave devices, there is no need to expand the independent control interfaces in a one-to-one correspondence manner, nor is there a need to add an external switching chip. This helps to reduce board-level wiring complexity, reduce logic resource waste, and improve the overall integration.

[0074] In summary, this embodiment of the application, by setting a master device SGPIO interface module, a counting module, and a multiplexing module in a programmable logic device, and receiving or sending multiple frames of communication data through the master device SGPIO interface module, the counting module determines the incrementing count value of the flag based on the multiple frames of communication data, and the multiplexing module determines the target slave device interface from multiple slave device interfaces based on the count value and transmits multiple frames of communication data, can realize ordered multi-channel communication control of the master device to multiple slave device interfaces within a single control device. This reduces the logic resource occupation caused by direct connection of independent interfaces, avoids the increase in latency and control complexity caused by the introduction of external switching devices, and thus improves the real-time performance, stability, and system scalability in multi-channel SGPIO communication scenarios. In addition, compared with the existing technology that requires replacing with a higher-performance CPLD model when the number of slave device interfaces exceeds the CPLD logic resource limit, this embodiment of the application does not require changes to the hardware design, and can effectively avoid increasing hardware design costs, adjusting the bill of materials, and extending the testing cycle while ensuring communication real-time performance.

[0075] In one possible implementation, the counting module includes a data frame detection submodule and a counter submodule; wherein, the data frame detection submodule is used to detect the transmission status of any frame of communication data in the multi-frame communication data, and generate a corresponding transmission flag signal when it is determined that the transmission of a single frame of communication data is completed; the counter submodule is connected to the data frame detection submodule and is used to accumulate and count the number of frames of multi-frame communication data that have been transmitted in response to the transmission flag signal, so as to obtain a count value.

[0076] In this implementation, the data frame detection submodule is a logic detection unit used to identify the status of the data transmission process output by the SGPIO interface module of the master device. Its core function is to identify the single frame boundary from the continuously transmitted multi-frame communication data and confirm whether the current frame has been completed, thereby providing accurate triggering conditions for subsequent counting.

[0077] Optionally, the data frame detection submodule can be arranged on the transmit control path of the SGPIO interface module of the master device, and connected to the transmit enable signal, byte count signal, frame synchronization signal or end indication signal to monitor the transmission status of any frame of communication data in real time, and output the transmission flag signal when the last valid bit, the last valid byte or the frame end handshake signal is detected.

[0078] The counter submodule is a counting unit electrically connected to the data frame detection submodule. Its function is to receive the transmission flag signal, increment the number of communication data frames that have been sent, and output the accumulation result as a count value, which is used by the subsequent multiplexing module as the basis for selecting the target slave device interface.

[0079] Furthermore, the counting module is usually integrated inside the CPLD and located between the master device SGPIO interface module and the multiplexing module. Its input is connected to the master device SGPIO interface module to obtain the transmission status information, and its output is connected to the multiplexing module to output the count value.

[0080] Based on the above structure, the data frame detection submodule continuously monitors the transmission status of any frame in the multi-frame communication data during operation. When it is confirmed that a single frame of communication data has been sent, a transmission flag signal is generated in a timely manner. The counter submodule then accumulates the frame completion event according to the flag signal, thereby forming a continuously increasing count value, and passes the count value to the multiplexing module for interface selection.

[0081] Therefore, the embodiments of this application can accurately identify and count multi-frame communication processes with less hardware resources, avoid additional delays and path instability caused by relying on external switching devices, maintain determinism and continuity of multi-channel SGPIO communication at the frame-level control granularity, and reduce the complexity of CPLD external circuits and improve overall communication reliability.

[0082] Based on the foregoing embodiments, the counter submodule further includes an overflow unit, which is used to automatically reset the count value to zero and restart the increment when the count value reaches a preset maximum value, wherein the preset maximum value is equal to the number of device interfaces.

[0083] In this embodiment, the overflow unit is a loop control unit for realizing the periodic looping of the count value. It is used to make a threshold judgment on the current counting state output by the counter submodule, and generate a zero control signal when the count value reaches the preset maximum value, so that the counter submodule automatically returns to the initial state after completing the current round of counting and enters the next round of incrementing, thereby enabling the multi-channel communication process to loop according to the number of slave device interfaces.

[0084] The overflow unit can be structurally integrated into the terminal counting detection logic inside the counter submodule. One end receives the current count value, and the other end outputs a clear enable, rollback enable, or synchronous reset signal to the input of the counter submodule so that it can switch to the initial counting state when the count value reaches the threshold.

[0085] For example, the overflow unit can be composed of a numerical comparator, a threshold detection circuit, a reset gating circuit, and a synchronous clear trigger circuit. The numerical comparator is used to compare the current count value with the preset maximum value bit by bit. The threshold detection circuit is used to output an overflow judgment signal when the comparison result meets the equality condition. The reset gating circuit is used to determine whether to apply zeroing control to the counting submodule register according to the overflow judgment signal. The synchronous clear trigger circuit is used to update the count value to the initial value when the clock edge arrives.

[0086] The preset maximum value is consistent with the number of slave device interfaces. When the control device of multi-channel communication is configured with multiple slave device interfaces, the overflow unit sets the maximum value to the number of slave device interfaces, so that the count value corresponds to different slave device interfaces in each round of increment, and automatically returns to the initial interface number to continue the loop after traversing all interfaces.

[0087] When the control device is started, the counter submodule sets the count value to zero or the corresponding initial value under the action of the initial control signal, and increments it successively as each frame of communication data is sent. As the count value changes continuously, the multiplexing module selects the slave device interface corresponding to the current count value in sequence, so that multiple frames of communication data are distributed to each slave device interface in a predetermined order. When the count value grows to the preset maximum value that is the same as the number of slave device interfaces, the overflow unit immediately detects the threshold state and outputs a zeroing control signal to return the count value to the initial value. Then the counter starts incrementing again, thus forming a continuous cyclic counting process.

[0088] Since the preset maximum value corresponds to the number of slave device interfaces, and the wraparound period of the count value is consistent with the traversal period of the slave device interfaces, all slave device interfaces can be covered in a stable order in each round of the loop, avoiding count overruns or interface omissions, and enabling multi-channel communication data to achieve repeated, stable and orderly path switching within a limited count range.

[0089] Based on the above analysis, it can be seen that the embodiments of this application do not require additional complex address decoding logic to complete the multi-interface cyclic selection, which can reduce the implementation complexity of count management and help improve the continuity and consistency of multi-channel communication control.

[0090] Based on the above embodiments, the multi-channel communication control device provided in this application automatically switches to the first SGPIO channel when the first valid flag bit is counted; and switches to the second SGPIO channel when the second valid flag bit is counted. This means that the multi-channel communication control device provided in this application has a valid flag bit generation module. When the valid flag bit generation module detects the falling edge of the SGPIO clock signal and the high level of the SGPIO LOAD signal, it can be considered that a valid flag bit of a frame of data has been successfully received. At this time, the counting module is responsible for counting the number of valid flag bits.

[0091] Furthermore, the aforementioned counting module can dynamically adjust the triggering conditions of the SGPIO LOAD and SGPIO DOUT signals. For example, an SGPIO LOAD synchronization mechanism can be defined, through which the counting module can determine when to trigger the SGPIO LOAD signal to load data, or when to trigger the SGPIO DOUT signal to output data; a valid flag latching mechanism can be defined, under which the counting module can latch the valid flag, and the condition for clearing the latched valid flag is the detection of a falling edge of the SGPIO LOAD signal; a valid flag synchronization mechanism can be defined, under which the counting module synchronizes the status of all valid flags; a mechanism for counting the number of falling edges of the valid flag can be defined, under which the counting module checks the falling edge of the SGPIO LOAD signal and counts the number of falling edges of the SGPIO LOAD signal.

[0092] Based on the aforementioned embodiments, a data buffer unit is further provided between the multiplexing module and the multiple slave device interfaces. The data buffer unit is used to temporarily store multiple frames of communication data, and after all multiple frames of communication data have been stored, the multiple frames of communication data are written to the corresponding target slave device interface.

[0093] In this embodiment, the data buffer unit is a buffer control unit used to temporarily store multiple frames of communication data between the multiplexing module and multiple slave device interfaces, and outputs the data to the corresponding target slave device interface only after confirming that all communication data to be transmitted has entered the buffer. Therefore, the function of the data buffer unit is to provide a stable data transition area for interface selection and channel switching, avoiding frame loss, frame errors, or write timing deviations caused by direct cross-interface transmission of multiple frames of communication data when the routing selection changes.

[0094] The data buffer unit is typically located on the output side of the multiplexing module and on the input side of multiple slave device interfaces. The input of the data buffer unit is connected to the data output of the multiplexing module, and the output of the data buffer unit is connected to the write port or chip select port of the corresponding slave device interface. This allows the data buffer unit to forward data according to the address mapping relationship of the target slave device interface after the multiplexing module determines the target slave device interface based on the count value.

[0095] When the control device starts, the master device's SGPIO interface module first outputs multiple frames of communication data to the CPLD according to a predetermined communication sequence. The multiplexing module, controlled by the counter value provided by the counting module, determines the corresponding target slave device interface and sends the communication data to be transmitted to the data buffer unit located on its output side. The data buffer unit sequentially buffers the received multiple frames of communication data. While the buffer is not full and multiple frames of communication data have not been fully stored, the data is only temporarily held in the buffer medium and not directly written to the external slave device interface, thus creating a buffer isolation between channel selection changes, interface switching, and data arrival. Once it is determined that all multiple frames of communication data have been stored, the data buffer unit, based on the target slave device interface address determined by the multiplexing module, writes the buffered data to the corresponding slave device interface in one go or at predetermined intervals, ensuring that each frame of communication data can be stably output along the determined target path.

[0096] Because the data buffer unit absorbs the transient impact of interface switching during transmission, a smoother coordination relationship can be formed between the continuous frame sending rhythm of the master device's SGPIO interface module, the frame order update of the counting module, and the target selection process of the multiplexing module. This reduces the risk of transmission interruption caused by switching delay and improves the integrity and write consistency of multi-frame communication data in multi-slave device scenarios.

[0097] Based on the above analysis, it can be seen that the embodiments of this application can enhance the stability of multi-channel SGPIO communication without adding external switching devices, and enable multiple frames of data to fall into the corresponding buffer path in an orderly manner from the device interface according to the target, thereby improving the reliability of the control device under high-frequency polling and continuous transmission conditions.

[0098] In one possible implementation, a redundant path mapping module is set between the multiplexing module and multiple slave device interfaces. This module is used to switch the interface connected to the transmission path of multiple frames of communication data to the corresponding backup slave device interface when an anomaly is detected in the target slave device interface.

[0099] In this implementation, the redundant path mapping module is a control unit used to remap multiple communication paths. It is mainly used to switch the transmission path that originally pointed to the target slave device interface to the corresponding backup slave device interface according to the pre-established backup mapping relationship when the target slave device interface is abnormal, so that multiple frames of communication data can continue to be transmitted when the main path fails.

[0100] The redundant path mapping module is typically positioned between the multiplexing module and multiple slave device interfaces, and is connected to the selection output of the multiplexing module and the input of each slave device interface. The input side of the redundant path mapping module receives the slave device interface selection result, the target slave device interface number, and the communication enable signal output by the multiplexing module. The output side of the redundant path mapping module sends the switched slave device interface routing information to the subsequent interface connection path to control the communication data to finally reach the backup slave device interface.

[0101] When the control device starts, the redundant path mapping module first reads the preset interface mapping configuration and divides the multiple slave device interfaces into two categories: primary slave device interfaces and backup slave device interfaces. Simultaneously, it establishes an association between each primary slave device interface and its corresponding backup slave device interface. During normal communication, the multiplexing module determines the primary slave device interface to be used based on the count value output by the counting module, and designates the determined primary slave device interface as the target slave device interface. The redundant path mapping module continuously monitors the link status of this target slave device interface. The link status may include one or more abnormal conditions such as response timeout, abnormal return status, abnormal electrical connectivity, lost link heartbeat, or communication verification failure.

[0102] When the detection result indicates that the target slave device interface is malfunctioning, the redundant path mapping module generates a switching control signal and redirects the transmission path originally connected to the target slave device interface to the corresponding backup slave device interface according to the preset mapping relationship. This allows multiple frames of communication data to continue to be output along the backup path without interruption. At this time, the multiplexing module maintains its original counting and selection rhythm, while the redundant path mapping module replaces the interface connection relationship in the subsequent stage, thereby avoiding data frame transmission blockage, polling interruption, or communication link suspension due to the failure of a single interface.

[0103] Since the switching process is completed directly by internal logic without relying on external switching devices, it can reduce additional wiring and device response delay, reduce the impact of path jitter on timing boundaries, and maintain good communication continuity, link stability and fault tolerance in multi-frame continuous transmission scenarios.

[0104] In one possible implementation, a fault recovery module is provided between the redundant path mapping module and the multiplexing module, which is used to switch the interface connected to the transmission path back to the target slave device interface when the target slave device interface is detected to be restored.

[0105] In this implementation, the fault recovery module is a recovery control unit used to switch the interface connected to the transmission path back to the target slave device interface when the target slave device interface is detected to be restored. Its function is to enable the control device to automatically switch back to the master slave device interface after the fault is eliminated, thereby restoring the original communication topology and avoiding long-term occupation of backup resources.

[0106] Furthermore, the fault recovery module is located in the collaborative control link between the redundant path mapping module and the multiplexing module. Its input is connected to the status feedback signal used to characterize the working status of the target slave device interface, and its output is connected to the path selection control signal so that the interface selection result can be updated again according to the recovery status when the redundant path has completed the transmission.

[0107] Optionally, the fault recovery module can be implemented using logic circuitry with a recovery confirmation window, which avoids false switching caused by transient jitter by continuously receiving a recovery signal within a preset time window.

[0108] When the control device starts, the fault recovery module first works with the redundant path mapping module to establish an initial path state and writes the target slave device interface as the default transmission path into the status holding register. During normal communication, the multiplexing module selects the corresponding target slave device interface according to the count value output by the counting module. The redundant path mapping module only switches to the backup slave device interface to take over the transmission when it detects an abnormality in the target slave device interface. If the target slave device interface experiences an abnormality and then recovers, the fault recovery module will continuously confirm the recovery status. Only after the conditions of link validity, normal response, or error elimination are continuously met within the confirmation window will the module send a switchback control signal to the multiplexing module, causing the transmission path to switch back from the backup slave device interface to the original target slave device interface.

[0109] Since the back-off process is based on recovery confirmation and state preservation, it can avoid the transient jitter that triggers erroneous switching when the interface is just restored, and also prevent the backup path from being occupied for a long time and reducing the system resource utilization. This allows multiple SGPIO communications to return to the predetermined main path topology after the fault self-recovery, maintaining the determinism and continuity of the communication link.

[0110] In one possible implementation, the bit width of the counting module is determined based on the number of slave device interfaces.

[0111] When the control device is started, the master device SGPIO interface module receives or sends multiple frames of communication data. The counting module predetermines the counting bit width based on the number of multiple slave device interfaces, and updates the counting value when it detects that a single frame of communication data has been sent or the next frame of transmission has begun. The counting value increases sequentially according to the number of slave device interfaces and automatically wraps around after reaching the preset upper limit.

[0112] For example, assuming the number of slave device interfaces is 2, the counter's bit width is 2 bits. With a bit width of 2, the counting value is a power of 2. For instance, after the count reaches 2'b11, adding 1 results in a count of 2'b00. Assuming the number of slave device interfaces is 6, the counter's bit width is 3 bits, supporting 8 SGPIO channels. Assuming the number of slave device interfaces is 10, the counter's bit width is 4 bits, supporting up to 16 SGPIO channels. Furthermore, if the count reaches 3'b111, or 7, adding more will cause the count to overflow, becoming 3'b000. This allows for automatic switching of SGPIO channels without relying on peripheral devices. The reason for this automatic switching is that the counters defined in this embodiment are 3'b000 – SGPIO0; 3'b001 – SGPIO1; 3'b010 – SGPIO2; 3'b011 – SGPIO3.

[0113] This example demonstrates that the bit width of the counting module can be dynamically adjusted via logic circuitry to accommodate different numbers of slave device interfaces. For instance, when the control device supports 6 SGPIO communication channels, the counter bit width is 3 bits; when the control device supports 16 communication channels, the bit width is extended to 4 bits.

[0114] As can be seen from the above analysis, the embodiments of this application realize bit width adjustment through logic control, which significantly reduces the complexity of hardware design and improves the scalability of the control device.

[0115] In one possible implementation, the counting module integrates a load detection module to adjust the increment frequency of the counting module based on the queue length of multiple frames of communication data.

[0116] In this implementation, the load detection module is a control unit used to detect the occupancy status of multi-frame communication data queues and adjust the counting progress rhythm of the counting module according to the occupancy status.

[0117] The load detection module is usually located inside the counting module, or configured in the same logical area of ​​the CPLD as the counting module. Its input is connected to the buffer queue of multi-frame communication data, the register to be sent, or the read / write pointer status signal. Its output is connected to the enable terminal, increment control terminal, frequency division control terminal, or gated clock terminal of the counting module, so as to adaptively adjust the incrementing time of the count value without changing the basic connection relationship between the main device SGPIO interface module and the multiplexing module.

[0118] When the control device starts, multi-frame communication data first enters the transmission queue on the SGPIO interface module side of the master device. The load detection module simultaneously samples the length of the transmission queue and outputs a corresponding frequency adjustment signal based on the backlog of frames to be transmitted in the transmission queue. When the transmission queue is short and the communication load is light, the load detection module allows the counting module to increment at a higher frequency, enabling the multiplexing module to complete the switching of the target slave device interface more quickly, thereby improving polling efficiency. When the transmission queue is long and the data backlog is significant, the load detection module reduces the increment frequency of the counting module or temporarily keeps the count value unchanged, preventing the multiplexing module from switching channels too quickly before the data is fully prepared, thus avoiding frame transmission jitter, interface idleness, or buffer overflow caused by excessively fast channel switching. Through the above linkage method, the advancement speed of the counting module can adaptively adjust with the actual load changes of multi-frame communication data, keeping the target slave device interface selection rhythm consistent with the data supply rhythm, thereby ensuring the stability of the communication path while reducing unnecessary switching overhead and improving overall transmission efficiency.

[0119] Based on the above analysis, it can be seen that the embodiments of this application can dynamically control the counting cycle of the counting module according to the queue length of the communication data without relying on external switching devices. This can improve the real-time performance and resource utilization in multi-channel SGPIO communication scenarios and reduce the risk of channel scheduling mismatch caused by load fluctuations.

[0120] Furthermore, this application embodiment also provides a control method for multiplexing communication, applied to a control device including the multiplexing communication provided above. The control method includes: detecting a transmission flag signal of multiple frames of communication data received or sent by the master device SGPIO interface module; incrementing the count value of the counting module according to the transmission flag signal; selecting a target slave device interface through a multiplexing module according to the count value, and transmitting the multiple frames of communication data to the target slave device interface.

[0121] In this embodiment, by detecting the transmission flag signals of multiple frames of communication data received or sent by the SGPIO interface module of the master device, the transmission rhythm and switching timing corresponding to each frame of communication data can be accurately identified, thereby enabling the counting module to increment the count value in an orderly manner during the transmission process. Based on the count value, the multiplexing module completes the target slave device interface selection, allowing multiple frames of communication data to be allocated to different slave device interfaces in a predetermined order, thus avoiding path switching delays and timing instability problems caused by external switching devices.

[0122] Therefore, this method can achieve unified control of multiple slave device interfaces with less hardware resources, making the multi-frame data transmission process more stable and real-time, and helping to reduce the design complexity of the control device and the overall implementation cost.

[0123] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, a processing module can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as program code in the device's memory, and its functions can be called and executed by a processing element. The implementation of other modules is similar. Moreover, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. During implementation, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0124] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a System-On-a-Chip (SOC).

[0125] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5 As shown, the electronic device 500 provided in this application embodiment may include: a processor 501, and a memory 502 communicatively connected to the processor, wherein:

[0126] The memory stores the instructions that the computer executes;

[0127] The processor executes computer execution instructions stored in memory to implement the method described in the foregoing method embodiments.

[0128] It should be understood that processor 501 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor. Memory 502 may include high-speed random access memory (RAM), and may also include non-volatile memory (NVM), such as at least one disk storage device, or a USB flash drive, external hard drive, read-only memory, disk, or optical disc, etc.

[0129] Optionally, the electronic device 500 may also include a communication interface 503. In specific implementations, if the communication interface 503, memory 502, and processor 501 are implemented independently, they can be interconnected via a bus to complete communication. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.

[0130] Optionally, in a specific implementation, if the communication interface 503, memory 502, and processor 501 are integrated on a single chip, then the communication interface 503, memory 502, and processor 501 can communicate through an internal interface.

[0131] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the methods described in any of the foregoing embodiments.

[0132] It is understood that the computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0133] An exemplary computer-readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the computer-readable storage medium. Of course, the computer-readable storage medium can also be a component of the processor. The processor and the computer-readable storage medium can reside in an ASIC. Alternatively, the processor and the computer-readable storage medium can exist as discrete components in an electronic device.

[0134] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a computer-readable storage medium, include several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application.

[0135] This application also provides a computer program product, including a computer program that, when executed, implements the method described in any of the foregoing embodiments.

[0136] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0137] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0138] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0139] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0140] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A control device for multi-channel communication, characterized in that, include: The programmable logic device includes a master serial universal input / output interface module, a multiplexing module, and a counting module. The main device serial universal input / output interface module is used to receive or send multiple frames of communication data. The counting module is connected between the serial universal input / output interface module of the main device and the multiplexing module, and is used to determine the incrementing count value of the flag according to the multi-frame communication data, and output the count value to the multiplexing module; The multiplexing module is connected to the plurality of slave device interfaces and is used to determine the target slave device interface from the plurality of slave device interfaces according to the count value, and transmit the multi-frame communication data to the target slave device interface.

2. The apparatus according to claim 1, characterized in that, The counting module includes a data frame detection submodule and a counter submodule; wherein... The data frame detection submodule is used to detect the transmission status of any frame of communication data in the multi-frame communication data, and generate a corresponding transmission flag signal when it is determined that the transmission of a single frame of communication data is completed. The counter submodule, connected to the data frame detection submodule, is used to accumulate and count the number of frames of the multi-frame communication data that have been sent in response to the transmission flag signal, so as to obtain the count value.

3. The apparatus according to claim 2, characterized in that, The counter submodule includes an overflow unit, which is used to automatically reset the count value to zero and restart the increment when the count value reaches a preset maximum value, wherein the preset maximum value is equal to the number of slave device interfaces.

4. The apparatus according to any one of claims 1 to 3, characterized in that, A data buffer unit is provided between the multiplexing module and the multiple slave device interfaces. The data buffer unit is used to temporarily store the multiple frames of communication data, and after all the multiple frames of communication data have been stored, the multiple frames of communication data are written to the corresponding target slave device interface.

5. The apparatus according to any one of claims 1 to 3, characterized in that, A redundant path mapping module is provided between the multiplexing module and the multiple slave device interfaces. When an abnormality is detected in the target slave device interface, the interface connected to the transmission path of the multi-frame communication data is switched to the corresponding backup slave device interface.

6. The apparatus according to claim 5, characterized in that, A fault recovery module is provided between the redundant path mapping module and the multiplexing module, which is used to switch the interface connected to the transmission path back to the target slave device interface when the target slave device interface is detected to be restored.

7. The apparatus according to any one of claims 1 to 3, characterized in that, The bit width of the counting module is determined based on the number of the plurality of slave device interfaces.

8. The apparatus according to any one of claims 1 to 3, characterized in that, The counting module integrates a load detection module, which is used to adjust the increment frequency of the counting module according to the queue length of the multi-frame communication data.

9. A control method for multiplexed communication, characterized in that, The control method, applied to a control apparatus for multiplexing as described in any one of claims 1 to 8, comprises: Detect the transmission flag signal of multiple frames of communication data received or sent by the serial universal input / output interface module of the main device; The counting value of the counting module is incremented according to the transmission flag signal; Based on the count value, the target slave device interface is selected by the multiplexing module, and the multi-frame communication data is transmitted to the target slave device interface.

10. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in claim 9.

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