Axiprotocol translation bridge, method and apparatus supporting transport parameter set resolution

Abstract

The application relates to the data carrying technical field, and provides an AXI protocol conversion bridge, method and device supporting transmission parameter set analysis, wherein parameter collection is completed when a channel enabling signal is valid, parameter output is completed when the channel is idle, a subsystem self-owned protocol analysis unit automatically analyzes the transmission parameter set into an AXI transaction descriptor required by AXI transmission, an AXI protocol conversion unit converts the AXI transaction descriptor into AXI bus read-write control signals to initiate read-write transactions to a DDR storage control interface, a FIFO cache unit caches read-write data between a target access module and the AXI bus, and generates a target access module response signal according to the full or empty state of the FIFO, the transmission parameters are automatically converted into control parameters required by AXI read-write transactions, the design complexity of the subsystem self-owned protocol adapting to AXI is reduced, and transmission waiting delay is reduced.

Description

Technical Field

[0001] This invention belongs to the field of data transfer technology, and relates to an AXI protocol conversion bridge, method and device that supports the parsing of transmission parameter sets. Background Technology

[0002] In hardware-accelerated systems, Direct Memory Access (DMA) modules or Enhanced Direct Memory Access (EDMA) modules are typically used to move data between external DDR memory and internal processing modules. The initiating end needs to provide not only read and write addresses but also generate burst length, transfer size, write byte strobe, and handshake control signals for each channel, based on the data width and address alignment. AXI (Advanced eXtensible Interface) read and write accesses are completed through separate read address, read data, write address, write data, and write response channels. Therefore, when DMA / EDMA uses its own internal protocol to describe data movement tasks, it needs to be parsed and converted into AXI-executable read and write transactions.

[0003] In existing designs, a common approach is to directly integrate the AXI access control logic into the DMA / EDMA module, allowing the DMA / EDMA to handle address alignment, burst splitting, write byte strobe generation, and AXI channel handshake control. While this approach is straightforward, it tightly couples the DMA / EDMA module to the AXI protocol. If the bus interface is changed, the data bit width is adjusted, or the burst transmission rules are modified, the relevant control logic also needs to be modified accordingly, resulting in poor module reusability.

[0004] Another approach is for the DMA / EDMA module to directly send read / write requests and read / write data signals to the backend interface. The backend interface generates corresponding AXI read / write accesses based on the current read / write requests, performing operations such as address updates, transmission length control, burst splitting, and handling of unaligned accesses. In this case, the DMA / EDMA module needs to continuously generate read / write requests, but the backend interface cannot automatically generate a continuous AXI burst access flow based on a single transmission task, resulting in complex control logic for the DMA / EDMA module.

[0005] Within the subsystem, the internal proprietary protocol output by the DMA / EDMA module needs to be converted into AXI bus read / write transactions, a process that is quite complex. Furthermore, the inconsistent transmission rhythms between the DMA / EDMA module and the AXI side can easily lead to mutual congestion. Therefore, a protocol conversion scheme is urgently needed that can directly receive and parse the transmission parameter set, reduce the complexity of the subsystem's proprietary protocol design, and minimize transmission latency. Summary of the Invention

[0006] To address the problems existing in the above-mentioned traditional methods, this invention proposes an AXI protocol conversion bridge that supports transmission parameter set parsing, an AXI protocol conversion method that supports transmission parameter set parsing, and a computer device. This can reduce the design complexity of directly adapting the subsystem's own protocol to the AXI protocol and reduce the impact of AXI-side handshake waiting on the data flow of the target access module.

[0007] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, an AXI protocol conversion bridge that supports the parsing of transmission parameter sets is provided, including: The parameter set buffer unit is used to receive and latch the transmission parameter set output by the target access module. When the channel enable signal is valid, the current parameters are latched. When the channel is idle, the latched parameters are output as the current valid task. The target access module includes a direct memory access module or an enhanced direct memory access module. The transmission parameter set includes the source address, destination address, number of bytes to be transmitted per block, number of blocks to be transmitted, inter-block address offset, and write byte mask signal. The subsystem has its own protocol parsing unit, which is used to parse the valid transmission parameter set output by the parameter set caching unit and generate the AXI transaction descriptor required for AXI transmission; among them, for read access, the source address is used as the current transmission base address, and for write access, the destination address is used as the current transmission base address. The AXI protocol conversion unit is used to convert AXI transaction descriptors into AXI bus read and write control signals. Specifically, the read transaction outputs the AXI read address, read burst length, and read transfer size and receives the read data returned by the DDR storage control interface, while the write transaction outputs the AXI write address, write burst length, write transfer size, write data, and write byte strobe signal and receives the AXI write response. The FIFO buffer unit is used to buffer read and write data between the target access module and the AXI bus, and to generate a target access module response signal based on the FIFO status.

[0008] In one embodiment, for a write request, the data written by the target access module first enters the FIFO cache unit write FIFO, and then is retrieved from the write FIFO by the AXI protocol conversion unit and sent to the DDR storage control interface. For read requests, the data returned by the DDR storage control interface first enters the FIFO cache unit to read the FIFO, and then the target access module reads it from the read FIFO. The FIFO cache unit generates a read response based on the empty state of the read FIFO and a write response based on the full state of the write FIFO.

[0009] In one embodiment, the subsystem's own protocol parsing unit updates the current address, remaining bytes to be transmitted, and remaining blocks after an AXI burst transmission is completed; Once all blocks have been transmitted, the subsystem's own protocol parsing unit outputs a task completion signal.

[0010] In one embodiment, the parameter set caching unit latches the current transmission parameter set input by the target access module when the channel enable signal is valid, and outputs the latched parameters as the current valid task to the subsystem's own protocol parsing unit when the channel is idle.

[0011] In one embodiment, the AXI protocol conversion unit is connected between the subsystem's own protocol parsing unit and the DDR storage control interface. In read transactions, it outputs the AXI read address, read burst length, and read transfer size, and receives read data returned by the DDR storage control interface. In write transactions, it outputs the AXI write address, write burst length, write transfer size, write data, and write byte strobe signal, and receives the AXI write response.

[0012] In one embodiment, the subsystem’s own protocol parsing unit uses the source address as the current transmission base address and calculates the AXI read access address, read burst length and read transmission size by combining the number of bytes transmitted in a single block. The AXI protocol conversion unit initiates an AXI read transaction based on the read access AXI transaction descriptor output by the subsystem's own protocol parsing unit. The read data returned by the DDR storage control interface is cached in the read FIFO and then read by the target access module.

[0013] In one embodiment, the subsystem's own protocol parsing unit uses the destination address as the current transmission base address, and calculates the AXI write access address, write burst length, write transmission size, first-shot write byte gating, and last-shot write byte gating by combining the number of bytes transmitted in a single block and the write byte mask; The write data output by the target access module is buffered by the write FIFO, then retrieved by the AXI protocol conversion unit and sent to the DDR storage control interface. The AXI protocol conversion unit receives the AXI write response returned by the DDR storage control interface.

[0014] On the other hand, an AXI protocol conversion method that supports transmission parameter set parsing is also provided, including the following steps: The parameter set buffer unit receives and latches the transmission parameter set output by the target access module; wherein, when the channel enable signal is valid, the current parameter is latched, and when the channel is idle, the latched parameter is output as the current valid task. The target access module includes a direct memory access module or an enhanced direct memory access module. The transmission parameter set includes source address, destination address, number of bytes to be transmitted per block, number of blocks to be transmitted, inter-block address offset, and write byte mask signal. The subsystem's own protocol parsing unit parses the latched valid transmission parameter set to generate the AXI transaction descriptor required for AXI transmission; for read access, the source address is used as the current transmission base address, and for write access, the destination address is used as the current transmission base address. The AXI protocol conversion unit converts the AXI transaction descriptor into AXI bus read / write control signals. Specifically, the read transaction outputs the AXI read address, read burst length, and read transfer size, and receives the read data returned by the DDR storage control interface. The write transaction outputs the AXI write address, write burst length, write transfer size, write data, and write byte strobe signal, and receives the AXI write response. The FIFO buffer unit is used to cache the read and write data between the target access module and the AXI bus, and a target access module response signal is generated according to the FIFO status.

[0015] In one embodiment, the steps of using a FIFO buffer unit to buffer read and write data between the target access module and the AXI bus, and generating a target access module response signal based on the FIFO state, include: For write requests, the data written by the target access module first enters the write FIFO, and then the AXI protocol conversion unit retrieves it from the write FIFO and sends it to the DDR storage control interface. For read requests, the data returned by the DDR storage control interface first enters the read FIFO, and then the target access module reads it from the read FIFO; the FIFO cache unit generates a read response based on the empty state of the read FIFO and a write response based on the full state of the write FIFO.

[0016] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned AXI protocol conversion bridge, method, and device supporting transmission parameter set parsing receive and latch the transmission parameter set issued by the target access module through a parameter set buffer unit. Parameter acquisition is completed when the channel enable signal is valid, and parameter output is completed when the channel is idle, preventing parameters from being overwritten during task execution. Then, the subsystem's proprietary protocol parsing unit automatically parses the transmission parameter set into the AXI transaction descriptor required for AXI transmission. The AXI protocol conversion unit then converts the AXI transaction descriptor into AXI bus read / write control signals to initiate read / write transactions to the DDR memory control interface. Simultaneously, the FIFO buffer unit buffers read / write data between the target access module and the AXI bus, and generates a target access module response signal based on the FIFO's empty / full status. This scheme can automatically convert transmission parameters such as source address, destination address, number of bytes transferred per block, number of blocks transferred, and inter-block address offset into the access address, burst length, transmission size, and write byte strobe signals required for AXI read / write transactions, greatly reducing the design complexity of directly adapting the subsystem's internal proprietary protocol to the AXI protocol. Meanwhile, the target access module read / write response is generated by the FIFO buffer unit according to the FIFO empty / full status, so that the target access module continues to transmit data only when the FIFO is operable, reducing the blockage of the target access module's data stream by the AXI side handshake waiting, thereby reducing transmission waiting latency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the module architecture of an AXI protocol conversion bridge that supports transmission parameter set parsing in one embodiment; Figure 2 This is a schematic diagram of the overall workflow of an AXI protocol conversion bridge that supports transmission parameter set parsing in one embodiment. Figure 3 This is a flowchart of an AXI protocol conversion method that supports transmission parameter set parsing in one embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0020] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0021] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0022] This paper presents an AXI protocol conversion bridge that supports transmission parameter set parsing, applicable to protocol conversion scenarios between target access modules and DDR memory control interfaces in hardware acceleration systems. In this subsystem, the internal protocol output by the target access module needs to be converted into AXI bus read / write transactions to access DDR memory. Target access modules include Direct Memory Access (DMA) or Enhanced Direct Memory Access (EDMA). The AXI protocol conversion bridge connects the target access module and the DDR memory control interface, receiving the transmission parameter set from the target access module, automatically parsing and generating the control parameters required for AXI read / write transactions, and buffering read / write data using a FIFO to achieve protocol conversion between the target access module's transmission interface and the AXI bus interface. The internal structure of the AXI protocol conversion bridge is as follows: Figure 1 As shown, it includes a parameter set caching unit, a subsystem-specific protocol parsing unit, an AXI protocol conversion unit, and a FIFO caching unit.

[0023] It is understood that in this invention, the transmission parameter set is a data transfer task description information issued by the target access module in its internal proprietary protocol format. It contains all the control parameters required to complete a full data transfer operation, specifically including the source address, destination address, number of bytes transferred per block, number of transfer blocks, inter-block address offset, and write byte mask signal. Specifically, the source address indicates the starting storage location from which the data originates during read access, the destination address indicates the target storage location where the data is written during write access, the number of bytes transferred per block represents the total number of data bytes contained in each transfer block, the number of transfer blocks represents the total number of data blocks to be transferred in this task, the inter-block address offset represents the distance between the starting addresses of two adjacent data blocks in the storage space, and the write byte mask is used to indicate the position of valid bytes in the write operation.

[0024] In one embodiment, such as Figure 1 As shown, an AXI protocol conversion bridge supporting transmission parameter set parsing is provided, including a parameter set buffer unit, a subsystem-specific protocol parsing unit, an AXI protocol conversion unit, and a FIFO (First-In-First-Out) buffer unit. The parameter set buffer unit receives and latches the transmission parameter set output by the target access module. Specifically, when the channel enable signal is valid, the current parameters are latched; when the channel is idle, the latched parameters are output as the currently valid task. The target access module includes a direct memory access module or an enhanced direct memory access module, i.e., a DMA / EDMA module. The transmission parameter set includes the source address, destination address, number of bytes transferred per block, number of blocks transferred, inter-block address offset, and write byte mask signal.

[0025] The subsystem's proprietary protocol parsing unit parses the valid transmission parameter set output by the parameter set caching unit to generate the AXI transaction descriptor required for AXI transmission. For read access, the source address is used as the current transmission base address; for write access, the destination address is used. The AXI protocol conversion unit converts the AXI transaction descriptor into AXI bus read / write control signals. For read transactions, it outputs the AXI read address, read burst length, and read transfer size, and receives read data returned from the DDR memory control interface. For write transactions, it outputs the AXI write address, write burst length, write transfer size, write data, and write byte strobe signal, and receives the AXI write response. The FIFO caching unit caches read / write data between the target access module and the AXI bus, and generates a target access module response signal based on the FIFO state.

[0026] It is understood that this embodiment proposes an AXI protocol conversion bridge that supports transmission parameter set parsing and FIFO low-latency caching. It can directly receive the transmission parameter set sent by the DMA / EDMA module, automatically parse and generate the control parameters required for AXI read and write transactions, and realize the protocol conversion between the DMA / EDMA module transmission interface and the AXI bus interface by caching the read and write data through FIFO.

[0027] Specifically, when the channel enable signal is valid, the parameter set buffer unit latches the transmission parameter set currently input to the interface by the target access module, saving the complete source address, destination address, number of bytes transmitted per block, number of transmission blocks, inter-block address offset, and write byte mask value into an internal register. When the channel idle signal indicates that there is no task currently being executed, the parameter set buffer unit outputs the latched parameters as the currently valid task to the subsequent subsystem's proprietary protocol parsing unit.

[0028] This two-stage processing method, which latches first and then outputs, resolves the timing conflict between the target access module continuously sending new parameters and the conversion bridge processing the previous task. If the parameter set caching unit directly transmits interface signals to the subsystem's own protocol parsing unit, when the subsystem's own protocol parsing unit has not yet completed the generation of the current task's AXI burst transaction, the newly arrived parameter set from the target access module may overwrite the parameter values ​​currently in use, causing address errors or length deviations in the data transfer of the current task. Through the latching and idle output mechanism, the parameter set caching unit physically isolates the input-side parameter updates from the processing-side parameter usage, ensuring that the parameter set used by each transmission task remains stable throughout its entire execution cycle, fundamentally avoiding the risk of parameters being overwritten during task execution.

[0029] The subsystem's proprietary protocol parsing unit parses the transmission parameter set and generates the AXI transaction descriptor required for AXI transmission. The AXI transaction descriptor is structured data connecting the subsystem's proprietary protocol parsing unit and the AXI protocol conversion, containing all the parameterized descriptions needed to generate a complete AXI bus read / write transaction. For read access, the subsystem's proprietary protocol parsing unit uses the source address as the current transmission base address. For write access, the subsystem's proprietary protocol parsing unit uses the destination address as the current transmission base address. Through the above parsing operations, the subsystem's proprietary protocol parsing unit transforms the transmission task described by the target access module using its internal proprietary protocol into an AXI transaction descriptor decoupled from the specific bus protocol details, providing a unified and standardized input interface for subsequent AXI protocol conversion. This method of converting proprietary protocols to intermediate descriptions eliminates the need for the target access module to be aware of the specific timing and signal format of the AXI protocol; it only needs to issue the transmission parameter set according to the internal proprietary protocol format, significantly reducing the design complexity of the target access module and its coupling with the AXI protocol.

[0030] The AXI protocol conversion unit converts the AXI transaction descriptors output by the subsystem's proprietary protocol parsing unit into AXI bus read / write control signals. In read transactions, the AXI protocol conversion unit outputs the AXI read address, read burst length, and read transfer size to the DDR memory control interface and receives the read data returned by the DDR memory control interface. In write transactions, the AXI protocol conversion unit outputs the AXI write address, write burst length, write transfer size, write data, and write byte strobe signals to the DDR memory control interface and receives the AXI write response to confirm the completion of the write transaction. The design of the AXI protocol conversion unit ensures that the front-end parameter set parsing and AXI transaction descriptor generation logic are completely independent of the subsequent AXI bus physical layer timing control. When it is necessary to change the bus interface type, adjust the data bit width, or modify the burst transfer rules, only the timing generation logic within the AXI protocol conversion unit needs adaptive modification, while the parameter set caching unit and the subsystem's proprietary protocol parsing unit require no changes, thus achieving excellent module reusability and portability.

[0031] The FIFO buffer unit is used to buffer read and write data between the DMA / EDMA module and the AXI bus, and generates DMA / EDMA module response signals based on the FIFO state. In actual system operation, the data output or consumption rate of the target access module often differs from the transmission rate on the AXI bus side. If this rate mismatch is not handled, it will cause both sides to wait for each other, resulting in transmission blockage. The FIFO buffer unit, by inserting a data buffer between the two sides, decouples the read and write operations on the target access module side from those on the AXI bus side in terms of time, allowing the target access module and the AXI bus to transmit data at their own pace, avoiding mutual blockage due to rate mismatch.

[0032] The aforementioned AXI protocol conversion bridge, which supports transmission parameter set parsing, provides stable and complete parameter input to the subsystem's proprietary protocol parsing unit through the latched output control of the parameter set buffer unit. The AXI transaction descriptor output of the subsystem's proprietary protocol parsing unit provides a unified and standardized control input to the AXI protocol conversion unit. The bus signal generation of the AXI protocol conversion unit provides data consumption or data production drive for the FIFO buffer unit. The empty / full status of the FIFO buffer unit is then fed back to the target access module through an acknowledgment signal, forming a closed-loop flow control.

[0033] The data flow, control flow, and status feedback flow among the four main units intertwine to form an organic protocol conversion system. This system automatically converts transmission parameters such as source address, destination address, number of bytes transmitted, number of blocks transmitted, and inter-block address offset into the access address, burst length, transmission size, and write byte strobe signal required for AXI read / write transactions. This significantly reduces the design complexity of directly adapting the subsystem's proprietary protocols to the AXI protocol. Simultaneously, the FIFO buffer unit generates read / write responses for the target access module based on the FIFO's empty / full status, reducing the impact of AXI-side handshake waiting on the target access module's data flow and thus lowering transmission latency.

[0034] In some implementations... Figure 2 A schematic diagram of the overall workflow of the AXI protocol conversion bridge that supports transmission parameter set parsing is shown below: (1) The DMA / EDMA module outputs the transmission parameter set, which is first latched into the parameter set buffer unit.

[0035] (2) The parameter set buffer unit sends the latched valid transmission parameters to the subsystem's own protocol parsing unit, which then generates AXI transmission description information.

[0036] (3) The AXI protocol conversion unit receives the AXI transmission description information and initiates an AXI read transaction or write transaction to the DDR storage control interface based on the information.

[0037] (4) Read and write data are buffered and transferred between the DMA / EDMA module and the AXI side through the FIFO buffer unit. The FIFO buffer unit generates a read / write response for the DMA / EDMA module based on its empty / full status. Through the above circuit connection design, the present invention realizes an integrated structure of transmission parameter set parsing, AXI protocol conversion and low-latency data buffering.

[0038] In one embodiment, for a write request, the data written by the target access module first enters the FIFO cache unit (write FIFO), and then the AXI protocol conversion unit retrieves it from the write FIFO and sends it to the DDR storage control interface. For a read request, the data returned by the DDR storage control interface first enters the FIFO cache unit (read FIFO), and then the target access module reads it from the read FIFO. The FIFO cache unit generates a read response based on the empty state of the read FIFO and a write response based on the full state of the write FIFO.

[0039] Specifically, the write FIFO is located between the target access module's write data path and the AXI protocol conversion unit. Write data output by the target access module is not directly sent to the AXI side; instead, it is first buffered in the write FIFO. When the AXI protocol conversion unit detects that the AXI write data channel is ready and the write FIFO is not empty, it retrieves the write data from the write FIFO and sends it to the DDR memory control interface in batches according to the AXI write burst timing. This FIFO pre-buffering method frees the target access module's write data output rate from the real-time constraint of the AXI write channel handshake delay. The target access module can continuously write data to the write FIFO at its own pace, as long as there is still free space in the write FIFO. When the write FIFO is nearly full, the FIFO buffer unit invalidates the write acknowledgment, and the target access module pauses writing and waits for the FIFO space to be released.

[0040] The read FIFO is located between the AXI protocol conversion unit's read data path and the target access module. Read data returned from the DDR storage control interface is not sent directly to the target access module; instead, it is first buffered in the read FIFO. When the target access module detects that its read channel is ready and the read FIFO is not empty, it retrieves the read data from the read FIFO. This FIFO-based buffering method means that the rate of AXI read data return no longer constrains the target access module's read rhythm in real time; read data can be temporarily stored in the read FIFO, waiting for the target access module to read it during idle periods. When the read FIFO is empty, the FIFO buffer unit invalidates the read response, and the target access module pauses reading and waits for data to arrive.

[0041] It is understandable that by generating read and write responses based on the empty and full states of the read and write FIFO respectively, low-latency adaptation to the transmission rhythm differences between the target access module and the AXI bus is achieved. The target access module only continues to transmit data when the FIFO is operational, without having to wait directly for the handshake to complete on the AXI bus side. This effectively reduces mutual waiting and transmission blocking caused by rate mismatch between the two sides, and lowers the overall transmission latency.

[0042] In one embodiment, after a single AXI burst transmission is completed, the subsystem's proprietary protocol parsing unit updates the current address, remaining bytes to be transmitted, and remaining blocks. Once all blocks have been transmitted, the subsystem's proprietary protocol parsing unit outputs a task completion signal. Specifically, in multi-block transmission scenarios, the number of transmission blocks in the transmission parameter set indicates the total number of data blocks to be moved in this task. After each AXI burst transmission, the subsystem's proprietary protocol parsing unit updates the current address based on the number of bytes moved in this transmission. That is, it adds the number of bytes moved in this transmission to the current address, making the updated address point to the starting position of the next data block. At the same time, it decrements the remaining number of bytes to be moved, and decrements the remaining number of blocks after all data in a transmission block has been moved. The updated current address will be used as the starting address of the next AXI burst transmission, ensuring correct address connection between consecutive AXI burst transmissions. When the remaining number of blocks decreases to zero, it indicates that all transmission blocks have completed data movement, and the subsystem's proprietary protocol parsing unit outputs a task completion signal, informing the target access module that the current transmission task has been fully executed and the next set of transmission parameter sets can be sent.

[0043] Understandably, this update mechanism solves the problem of automatic address advancement and transmission progress tracking for continuous AXI burst transactions in multi-block transmission tasks. It enables the target access module to issue a parameter set containing multi-block transmission information only once, without having to issue new parameters or continuously generate read / write requests after each block transmission is completed, which significantly simplifies the control logic on the target access module side.

[0044] In one embodiment, the parameter set buffer unit latches the current transmission parameter set input by the target access module when the channel enable signal is valid, and outputs the latched parameters as the current valid task to the subsystem's own protocol parsing unit when the channel is idle.

[0045] Specifically, the parameter set buffer unit internally maintains two control signals: a channel enable signal and a channel idle signal. The channel enable signal is synchronously set by the target access module when it outputs a valid transmission parameter set, indicating that the transmission parameter set data on the current interface is valid and can be latched. When the parameter set buffer unit detects a valid edge of the channel enable signal, it latches the source address, destination address, number of bytes transmitted per block, number of transmission blocks, inter-block address offset, and write byte mask of the current interface into its internal register set. The channel idle signal is generated by feedback from the subsequent processing status. It is valid when the subsystem's proprietary protocol parsing unit, AXI protocol conversion unit, and FIFO buffer unit are all in an idle state and there are no tasks being executed. When the parameter set buffer unit detects a valid channel idle signal, it outputs the transmission parameters latched in its internal register set as the currently valid task to the subsystem's proprietary protocol parsing unit.

[0046] Understandably, this latching output timing constraint mechanism based on dual control signals fundamentally resolves the contradiction between the continuous transmission of parameters by the target access module and the sequential processing of tasks within the conversion bridge. Latching ensures the accuracy of parameter acquisition timing, while idle output ensures the safety of parameter usage timing. The two complement each other in the time dimension, preventing newly input transmission parameters from overwriting the currently processed parameters during task execution.

[0047] In one embodiment, the AXI protocol conversion unit is connected between the subsystem's proprietary protocol parsing unit and the DDR memory control interface. In read transactions, it outputs the AXI read address, read burst length, and read transfer size, and receives read data returned by the DDR memory control interface. In write transactions, it outputs the AXI write address, write burst length, write transfer size, write data, and write byte strobe signal, and receives the AXI write response.

[0048] Specifically, the AXI protocol conversion unit is physically located between the subsystem's proprietary protocol parsing unit and the DDR memory control interface. Its input port receives the AXI transaction descriptor output by the subsystem's proprietary protocol parsing unit, and its output port, according to the AXI bus protocol standard, can be divided into multiple independent channels, each connected to the DDR memory control interface. In read transactions, the AXI protocol conversion unit sends three signals—AXI read address, read burst length, and read transfer size—to the DDR memory control interface via the read address channel, and receives the read data returned by the DDR memory control interface via the read data channel after the read address handshake is complete. In write transactions, the AXI protocol conversion unit sends three signals—AXI write address, write burst length, and write transfer size—via the write address channel, sends write data and write byte strobe signals sequentially via the write data channel, and receives the AXI write response returned by the DDR memory control interface via the write response channel after all write data transmissions are completed.

[0049] It is understandable that the AXI protocol conversion unit, as the final link in the conversion from AXI transaction descriptors to physical bus signals, uses a parameterized intermediate description format at its input side to interface with the subsystem's own protocol parsing unit, decoupling it from specific AXI protocol versions and signal bit widths. Its output side strictly follows the AXI bus protocol standard timing to generate physical signals. This layered design ensures that when adapting to different versions of the AXI protocol or DDR memory control interfaces with different data bit widths, only the output timing logic of the AXI protocol conversion unit needs adaptive adjustment, while the preceding parameter parsing logic remains unaffected.

[0050] In one embodiment, the subsystem's proprietary protocol parsing unit uses the source address as the current transmission base address and calculates the AXI read access address, read burst length, and read transmission size based on the number of bytes transmitted per block. The AXI protocol conversion unit initiates an AXI read transaction based on the read access AXI transaction descriptor output by the subsystem's proprietary protocol parsing unit. The read data returned by the DDR storage control interface is buffered in the read FIFO and then read by the target access module.

[0051] Specifically, in read access scenarios, the subsystem's proprietary protocol parsing unit extracts the source address from the transmission parameter set as the current transmission base address, and calculates the access start address, read burst length, and read transmission size of this AXI read transaction based on the number of bytes transmitted per block. The read burst length is obtained by dividing the number of bytes transmitted per block by the AXI data bus width and rounding up, while the read transmission size is determined by the width of a single AXI data pulse. The calculation results are sent to the AXI protocol conversion unit as a read access AXI transaction descriptor. The AXI protocol conversion unit generates an AXI read address channel signal and a read burst control signal based on the read access AXI transaction descriptor, and initiates an AXI read transaction to the DDR storage control interface. The DDR storage control interface returns read data according to the AXI read timing sequence. After the read data enters the AXI protocol conversion unit through the AXI read data channel, it is written into the read FIFO for buffering. After detecting a valid read acknowledgment signal, the target access module retrieves the read data sequentially from the read FIFO, completing a complete read access process from the target access module's read request to the actual data acquisition.

[0052] It is understandable that in this read access path, the source address serves as the address base for the entire read transaction. A complete causal chain and address consistency guarantee mechanism are formed between the base address determination and address calculation of the subsystem's own protocol parsing unit, the read address output of the AXI protocol conversion unit, and the read data return of the DDR storage control interface.

[0053] In one embodiment, the subsystem's proprietary protocol parsing unit uses the destination address as the current transmission base address and calculates the AXI write access address, write burst length, write transmission size, first-slot write byte strobe, and last-slot write byte strobe by combining the number of bytes transmitted per block and the write byte mask. The write data output by the target access module is buffered in the write FIFO, then retrieved by the AXI protocol conversion unit and sent to the DDR storage control interface. The AXI protocol conversion unit receives the AXI write response returned by the DDR storage control interface.

[0054] Specifically, in write access scenarios, the subsystem's proprietary protocol parsing unit extracts the destination address from the transmission parameter set as the current transmission base address. Combining this with the number of bytes transmitted per block and the write byte mask, it calculates the access start address, write burst length, write transmission size, first-slot write byte strobe, and last-slot write byte strobe for this AXI write transaction. The first-slot write byte strobe indicates the valid byte position of the first data in an AXI write burst transmission, used to handle cases where the write start address is not aligned. The last-slot write byte strobe indicates the valid byte position of the last data, used to handle cases where the total write transmission amount is not an integer multiple of the bus width. The calculation result is sent to the AXI protocol conversion unit as a write access AXI transaction descriptor. On the data side, the write data output by the target access module is first written into the write FIFO for buffering. The AXI protocol conversion unit generates AXI write address channel signals and write burst control signals based on the write access AXI transaction descriptor. Simultaneously, it retrieves write data from the write FIFO and sends the write data and write byte strobe signals to the DDR storage control interface sequentially through the write data channel according to the AXI write timing. After all write data transmission is complete, the AXI protocol conversion unit receives the AXI write response returned by the DDR storage control interface through the write response channel, and confirms whether the write transaction has been successfully completed based on the response value.

[0055] It is understandable that in this write access path, the destination address serves as the address base for the entire write transaction, the write byte mask guides the calculation of the effective byte positions of the first and last frames, the data retrieval from the write FIFO buffer and the AXI protocol conversion unit constitutes asynchronous pipeline coordination, and the AXI write response provides hardware-level confirmation of the correctness of the write transaction. The four elements work closely together in the write path.

[0056] Compared to existing technologies, the aforementioned AXI protocol conversion bridge, which supports DMA / EDMA transmission parameter set parsing, can automatically convert transmission parameters such as source address, destination address, number of bytes transmitted, number of blocks transmitted, and inter-block address offset into the access address, burst length, transmission size, and write byte strobe signal required for AXI read / write transactions. This significantly reduces the design complexity of directly adapting the subsystem's proprietary protocol to the AXI protocol. By using a FIFO buffer unit to cache read / write data between the DMA / EDMA module and the AXI side, and generating DMA / EDMA read / write responses based on the FIFO's empty / full status, the impact of AXI-side handshake waiting on DMA / EDMA module data transmission is reduced, thereby lowering transmission latency.

[0057] Each module in the aforementioned AXI protocol conversion bridge that supports transmission parameter set parsing can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of a device with data processing capabilities, or stored in software within the memory of the aforementioned device, so that the processor can call and execute the operations corresponding to each module. The aforementioned device can be, but is not limited to, various types of computer devices already existing in the art.

[0058] In one embodiment, such as Figure 3 As shown, an AXI protocol conversion method supporting transmission parameter set parsing is also provided, which may include the following steps S12 to S18: S12, the parameter set buffer unit receives and latches the transmission parameter set output by the target access module; wherein, when the channel enable signal is valid, the current parameters are latched, and when the channel is idle, the latched parameters are output as the current valid task. The target access module includes a direct memory access module or an enhanced direct memory access module. The transmission parameter set includes source address, destination address, number of bytes transmitted per block, number of transmission blocks, inter-block address offset, and write byte mask signal. S14, the subsystem's own protocol parsing unit parses the latched valid transmission parameter set to generate the AXI transaction descriptor required for AXI transmission; among which, for read access, the source address is used as the current transmission base address, and for write access, the destination address is used as the current transmission base address. S16, using the AXI protocol conversion unit to convert the AXI transaction descriptor into AXI bus read / write control signals; wherein, the read transaction outputs the AXI read address, read burst length and read transfer size and receives the read data returned by the DDR storage control interface, and the write transaction outputs the AXI write address, write burst length, write transfer size, write data and write byte strobe signal and receives the AXI write response. S18 uses the FIFO buffer unit to buffer the read and write data between the target access module and the AXI bus, and generates a target access module response signal according to the FIFO status.

[0059] The aforementioned AXI protocol conversion method, which supports transmission parameter set parsing, provides stable and complete parameter input to the subsystem's proprietary protocol parsing unit through the latched output control of the parameter set buffer unit. The AXI transaction descriptor output of the subsystem's proprietary protocol parsing unit provides a unified and standardized control input to the AXI protocol conversion unit. The bus signal generation of the AXI protocol conversion unit provides data consumption or data production drive for the FIFO buffer unit. The empty / full status of the FIFO buffer unit is then fed back to the target access module via an acknowledgment signal, forming a closed-loop flow control.

[0060] The data flow, control flow, and status feedback flow among the four main units intertwine to form an organic protocol conversion system. This system automatically converts transmission parameters such as source address, destination address, number of bytes transmitted, number of blocks transmitted, and inter-block address offset into the access address, burst length, transmission size, and write byte strobe signal required for AXI read / write transactions. This significantly reduces the design complexity of directly adapting the subsystem's proprietary protocols to the AXI protocol. Simultaneously, the FIFO buffer unit generates read / write responses for the target access module based on the FIFO's empty / full status, reducing the impact of AXI-side handshake waiting on the target access module's data flow and thus lowering transmission latency.

[0061] In one embodiment, step S18 described above may further include the following processing: For write requests, the data written by the target access module first enters the write FIFO, and then the AXI protocol conversion unit retrieves it from the write FIFO and sends it to the DDR storage control interface. For read requests, the data returned by the DDR storage control interface first enters the read FIFO, and then the target access module reads it from the read FIFO. The FIFO buffer unit generates a read response based on the empty state of the read FIFO and a write response based on the full state of the write FIFO.

[0062] It is understood that the specific limitations of the features in the various embodiments of the AXI protocol conversion method that supports transmission parameter set parsing can be found in the explanation of the corresponding features in the various embodiments of the AXI protocol conversion bridge that supports transmission parameter set parsing, which will not be repeated here.

[0063] It should be understood that, although Figure 3 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 3 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0064] In one embodiment, a computer device is also provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the AXI protocol conversion method supporting transmission parameter set parsing in the above embodiment.

[0065] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. An AXI protocol conversion bridge that supports transmission parameter set parsing, characterized in that, include: The parameter set buffer unit is used to receive and latch the transmission parameter set output by the target access module. When the channel enable signal is valid, the current parameters are latched. When the channel is idle, the latched parameters are output as the current valid task. The channel enable signal is set synchronously by the target access module when outputting a valid transmission parameter set. The channel idle signal is generated by the feedback of the subsequent processing status. The channel idle signal is valid when the subsystem's own protocol parsing unit, AXI protocol conversion unit, and FIFO buffer unit are all in an idle state. The target access module includes a direct memory access module or an enhanced direct memory access module. The transmission parameter set includes source address, destination address, number of bytes transmitted per block, number of transmission blocks, inter-block address offset, and write byte mask signal. The subsystem's proprietary protocol parsing unit parses the valid transmission parameter set output by the parameter set caching unit to generate the AXI transaction descriptor required for AXI transmission. After an AXI burst transmission is completed, the subsystem's proprietary protocol parsing unit updates the current address, the number of remaining transmission bytes, and the number of remaining blocks. When all blocks have been transmitted, the subsystem's proprietary protocol parsing unit outputs a task completion signal. Specifically, for read access, the source address is used as the current transmission base address, and for write access, the destination address is used as the current transmission base address. The AXI protocol conversion unit is used to convert AXI transaction descriptors into AXI bus read / write control signals. The interface between the input side and the subsystem's own protocol parsing unit adopts a parameterized intermediate description format, which is decoupled from the specific AXI protocol version and signal bit width. Specifically, the read transaction outputs the AXI read address, read burst length, and read transfer size and receives the read data returned by the DDR storage control interface, while the write transaction outputs the AXI write address, write burst length, write transfer size, write data, and write byte strobe signal and receives the AXI write response. The FIFO buffer unit is used to buffer read and write data between the target access module and the AXI bus, and to generate a target access module response signal based on the FIFO status.

2. The AXI protocol conversion bridge supporting transmission parameter set parsing according to claim 1, characterized in that, For write requests, the data written by the target access module first enters the FIFO cache unit to write the FIFO, and then the AXI protocol conversion unit retrieves it from the write FIFO and sends it to the DDR storage control interface. For read requests, the data returned by the DDR storage control interface first enters the FIFO cache unit to read the FIFO, and then the target access module reads it from the read FIFO. The FIFO cache unit generates a read response based on the empty state of the read FIFO and a write response based on the full state of the write FIFO.

3. The AXI protocol conversion bridge supporting transmission parameter set parsing according to claim 1, characterized in that, When the channel enable signal is valid, the parameter set buffer unit latches the current transmission parameter set input by the target access module. When the channel is idle, it outputs the latched parameters as the current valid task to the subsystem's own protocol parsing unit.

4. The AXI protocol conversion bridge supporting transmission parameter set parsing according to claim 1, characterized in that, The AXI protocol conversion unit is connected between the subsystem's proprietary protocol parsing unit and the DDR memory control interface. In read transactions, it outputs the AXI read address, read burst length, and read transfer size, and receives read data returned by the DDR memory control interface. In write transactions, it outputs the AXI write address, write burst length, write transfer size, write data, and write byte strobe signal, and receives the AXI write response.

5. The AXI protocol conversion bridge supporting transmission parameter set parsing according to claim 1, characterized in that, The subsystem's proprietary protocol parsing unit uses the source address as the current transmission base address and combines it with the number of bytes transmitted per block to calculate the AXI read access address, read burst length, and read transmission size. The AXI protocol conversion unit initiates an AXI read transaction based on the read access AXI transaction descriptor output by the subsystem's own protocol parsing unit. The read data returned by the DDR storage control interface is cached in the read FIFO and then read by the target access module.

6. The AXI protocol conversion bridge supporting transmission parameter set parsing according to claim 1, characterized in that, The subsystem's proprietary protocol parsing unit uses the destination address as the current transmission base address, and combines the number of bytes transmitted in a single block and the write byte mask to calculate the AXI write access address, write burst length, write transmission size, first-slot write byte gating, and last-slot write byte gating; The write data output by the target access module is buffered by the write FIFO, then retrieved by the AXI protocol conversion unit and sent to the DDR storage control interface. The AXI protocol conversion unit receives the AXI write response returned by the DDR storage control interface.

7. An AXI protocol conversion method supporting transmission parameter set parsing, characterized in that, Including the following steps: The parameter set buffer unit receives and latches the transmission parameter set output by the target access module. When the channel enable signal is valid, the current parameters are latched. When the channel is idle, the latched parameters are output as the current valid task. The channel enable signal is set synchronously by the target access module when outputting a valid transmission parameter set. The channel idle signal is generated by the status feedback of the subsequent processing stage. The channel idle signal is valid when the subsystem's own protocol parsing unit, AXI protocol conversion unit, and FIFO buffer unit are all in an idle state. The target access module includes a direct memory access module or an enhanced direct memory access module. The transmission parameter set includes the source address, destination address, number of bytes transmitted per block, number of transmission blocks, inter-block address offset, and write byte mask signal. The subsystem's proprietary protocol parsing unit parses the latched valid transmission parameter set to generate the AXI transaction descriptor required for AXI transmission. After an AXI burst transmission is completed, the subsystem's proprietary protocol parsing unit updates the current address, the number of remaining transmission bytes, and the number of remaining blocks. When all blocks have been transmitted, the subsystem's proprietary protocol parsing unit outputs a task completion signal. Specifically, for read access, the source address is used as the current transmission base address, and for write access, the destination address is used as the current transmission base address. The AXI protocol conversion unit converts AXI transaction descriptors into AXI bus read / write control signals. The interface between the input side and the subsystem's own protocol parsing unit adopts a parameterized intermediate description format, which is decoupled from the specific AXI protocol version and signal bit width. Specifically, the read transaction outputs the AXI read address, read burst length, and read transfer size and receives the read data returned by the DDR storage control interface. The write transaction outputs the AXI write address, write burst length, write transfer size, write data, and write byte strobe signal and receives the AXI write response. The FIFO buffer unit is used to cache the read and write data between the target access module and the AXI bus, and a target access module response signal is generated according to the FIFO status.

8. The AXI protocol conversion method supporting transmission parameter set parsing according to claim 7, characterized in that, The steps of using a FIFO buffer unit to cache read and write data between the target access module and the AXI bus, and generating a target access module response signal based on the FIFO state, include: For write requests, the data written by the target access module first enters the write FIFO, and then the AXI protocol conversion unit retrieves it from the write FIFO and sends it to the DDR storage control interface. For read requests, the data returned by the DDR storage control interface first enters the read FIFO, and then the target access module reads it from the read FIFO; the FIFO cache unit generates a read response based on the empty state of the read FIFO and a write response based on the full state of the write FIFO.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the AXI protocol conversion method supporting transmission parameter set parsing as described in claim 7 or 8.

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