A request parallel merging apparatus and method

Abstract

The application provides a request parallel merging device and method, and relates to the technical field of request merging. The request parallel merging device comprises a reorganization buffer configured to store a plurality of to-be-processed transaction layer requests and to output address information and read-write attribute information of the plurality of to-be-processed transaction layer requests in parallel; an address comparison unit coupled with the reorganization buffer and configured to generate a matching vector; a conflict detection unit coupled with the reorganization buffer and configured to generate a safe release signal; a non-sequential extraction logic unit coupled with the address comparison unit and the conflict detection unit respectively and configured to extract corresponding data blocks; and a multi-slot mapping engine coupled with the non-sequential extraction logic unit and configured to dynamically map and compact the extracted data blocks into data slots of a data packet. The request parallel merging device and method provided by the application have the advantages of low delay, high throughput, better consistency and energy efficiency ratio.

Description

Technical Field

[0001] This application relates to the field of request merging technology, and more specifically, to a request parallel merging apparatus and method. Background Technology

[0002] In the field of high-speed interconnects, with the commercial deployment of protocols such as CXL (Compute Express Link) 3.1 and PCIe 6.0, link speeds have increased to 64 GT / s (gigabits per second) or even higher. To match such high physical link bandwidth and reduce interface power consumption, modern controllers generally adopt transaction layer packetization mechanisms based on fixed-size transmission units (such as the 256B Flit in CXL 3.1). However, how to efficiently and with low latency compact transaction layer requests from multiple sources of varying sizes into a limited number of transmission unit data slots remains a core challenge for the industry.

[0003] In existing technologies, a common approach is to use transaction merging based on a static timeout mechanism and request merging and packaging strategy that fills in IDLE (idle tokens). This strategy has the following characteristics: Serial Address Retrieval: When determining whether a newly arrived request can be merged with an existing request in the buffer, the hardware comparator within the controller employs a serial polling mechanism. In each clock cycle, it can only compare the new request address with one existing request address in the buffer. If the buffer depth is N, in the worst case, it will take N clock cycles to complete a single merge search decision.

[0004] Sequential data extraction: The data extraction logic is tightly coupled with the read pointer of the buffer and strictly adheres to the first-in, first-out (FIFO) reading rule. This means that even if address comparison reveals that the entries at the tail of the buffer are consecutive to the entries at the head and meet the merging conditions, the existing logic cannot skip the intermediate entries and directly extract the data of the tail entries because other unrelated entries are interspersed in between.

[0005] Lack of conflict checking mechanism: In the above-mentioned serial scanning and merging decision-making process, existing technical solutions generally lack the ability to check for address conflicts of intermediate entries in real time. For example, when attempting to merge a subsequent write request with the current request, if there is a read operation on the same address in between, the system cannot effectively identify and avoid the potential risk of reading and writing data after the read operation.

[0006] Fixed slot mapping: For unaligned or empty requests, existing solutions often simply abandon merging or use the protocol-defined IDLE to fill the remaining slots, lacking flexible dynamic mapping capabilities.

[0007] The aforementioned existing technical solutions are still usable in low-bandwidth or latency-insensitive application scenarios, but their inherent defects become unacceptable when faced with ultra-high-speed links of 64 GT / s provided by protocols such as CXL 3.1. Specifically, the serial address retrieval mechanism leads to excessive processing latency, the sequential data extraction mechanism leads to low effective throughput, the lack of a conflict checking mechanism leads to risks in data consistency, and the fixed slot mapping mechanism leads to poor energy efficiency.

[0008] In summary, existing request merging and packaging strategies suffer from high latency, low bandwidth, poor consistency, and poor energy efficiency. Summary of the Invention

[0009] The purpose of this application is to provide a request parallel merging apparatus and method to solve the problems of high latency, low bandwidth, poor consistency and poor energy efficiency in the request merging and packing strategies of the prior art.

[0010] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: On one hand, embodiments of this application provide a request parallel merging apparatus, the request parallel merging apparatus comprising: The reorganization buffer is configured to store multiple pending transaction layer requests and output the address information and read / write attribute information of the multiple pending transaction layer requests in parallel. The address comparison unit, coupled to the reassembly buffer, is configured to synchronously compare the target address with the address information of all pending transaction layer requests in the reassembly buffer within one clock cycle, and generate a matching vector; wherein the target address is the address of the currently selected target request, and the target request is the request selected as the starting point for the merge search in this packaging operation; The conflict detection unit, coupled to the reassembly buffer, is configured to determine, within one clock cycle, whether there is a consistency conflict between each pending transaction layer request and the target request based on address information and read / write attribute information, and generate a safe release signal. The non-sequential extraction logic unit, coupled to the address comparison unit and the conflict detection unit respectively, is configured to extract, in a non-sequential manner, the data blocks corresponding to the pending transaction layer requests that simultaneously satisfy address matching and are conflict-free from the reassembly buffer according to the matching vector and the secure release signal; wherein, the data block is the actual data payload or request control information carried in the pending transaction layer request; A multi-slot mapping engine, coupled to the non-sequential extraction logic unit, is configured to dynamically map and compact the extracted data blocks into data slots of the data packets.

[0011] Optionally, the address comparison unit includes N sets of hardware XOR logic gates, where N is the depth of the reassembly buffer. The N sets of hardware XOR logic gates are used to perform bit-to-bit comparison between the target address and the address information of N pending transaction layer requests within one clock cycle.

[0012] Optionally, the address comparison unit includes a content-addressable memory or a hash mapping unit, which is used to locate the request index that matches the target address within one clock cycle.

[0013] Optionally, the collision detection unit includes a Hazard check circuit composed of a comparator array and a priority encoding logic module; The comparator array is used to detect in parallel within one clock cycle whether the target address overlaps with the addresses of all pending transaction layer requests in the reassembly buffer. The priority encoding logic is used to determine whether there is a read-after-write, write-after-read, or write-after-write conflict based on the combination of read and write attributes, and outputs a high-level active safety release signal when there is no conflict.

[0014] Optionally, the conflict detection unit is further configured to output a prohibition signal to the non-sequential extraction logic unit when any write operation request is detected among multiple pending transaction layer requests, so as to trigger the non-sequential extraction logic unit to disable the non-sequential extraction function.

[0015] Optionally, the non-sequential extraction logic unit includes a multiplexer control array, which is used to extract the data block corresponding to the selected pending transaction layer request from the reassembly buffer based on the logical AND operation result of the matching vector and the secure release signal.

[0016] Optionally, the multi-slot mapping engine includes a hardware barrel shifter, which is used to calculate and execute the offset of the data block in the data slot of the data packet within one clock cycle, based on the amount of data in the extracted data block.

[0017] Optionally, the non-sequential extraction logic is further configured to send a feedback signal to the reassembly buffer after extracting the data block, so as to clear the valid bit of the corresponding entry.

[0018] Optionally, the request parallel merging device further includes an encapsulator coupled to the multi-slot mapping engine, the encapsulator being configured to encapsulate the compacted data packets into protocol frames and send them to the physical layer.

[0019] On the other hand, embodiments of this application also provide a method for requesting parallel merging, the method comprising: When the reorganization buffer stores multiple pending transaction layer requests, the address information and read / write attribute information of the multiple pending transaction layer requests are output in parallel. Within one clock cycle, the target address is synchronously compared with the address information of all pending transaction layer requests in the reassembly buffer, and a matching vector is generated; wherein, the target address is the address of the currently selected target request, and the target request is the request selected as the starting point for the merge search in this packaging operation; Within the clock cycle, based on the address information and read / write attribute information, it is determined whether there is a consistency conflict between each pending transaction layer request and the target request, and a safe release signal is generated. Based on the matching vector and the secure release signal, data blocks corresponding to pending transaction layer requests that simultaneously satisfy address matching and are conflict-free are extracted from the reassembly buffer in a non-sequential manner; wherein, the data block is the actual data payload or request control information carried in the pending transaction layer request; The extracted data blocks are dynamically mapped and compacted into the data slots of the data packets.

[0020] Compared with the prior art, this application has the following advantages: In the parallel request merging apparatus provided in this application, because the reassembly buffer outputs the address information and read / write attribute information of multiple pending transaction layer requests in parallel, the address comparison unit can synchronously scan all entries in the queue within a single clock cycle, significantly reducing search complexity and effectively minimizing latency. The conflict detection unit simultaneously determines whether there is a consistency conflict between each pending transaction layer request and the target request, ensuring storage consistency security under extreme performance. The non-sequential extraction logic unit allows the circuit to skip irrelevant intermediate entries and directly retrieve matching data from the middle of the reassembly buffer for reassembly based on the address matching result, improving effective throughput. Furthermore, by dynamically mapping and compacting the extracted data blocks to the data slots of the data packets through a multi-slot mapping engine, bit-level compaction can be achieved, improving energy efficiency.

[0021] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is an exemplary block diagram of a merging strategy in the prior art.

[0024] Figure 2 An exemplary block diagram of a request parallel merging apparatus provided for embodiments of this application.

[0025] Figure 3 Another exemplary block diagram of the request parallel merging apparatus provided for embodiments of this application.

[0026] Figure 4 An exemplary flowchart of the request parallel merging method provided in the embodiments of this application.

[0027] In the picture: 110 - Reassembly buffer; 120 - Address comparison unit; 130 - Conflict detection unit; 140 - Non-sequential extraction logic unit; 150 - Multi-slot mapping engine; 160 - Encapsulation packer. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0030] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Some embodiments of this application are described in detail below with reference to the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] As described in the background section, existing CXL or PCIe controller designs typically employ a timer-based merging strategy to improve link utilization. When the first transaction enters the buffer, the controller starts a fixed-duration timer. Before the timer reaches zero, the controller continuously waits for subsequent transactions to arrive in order to attempt to fill a complete transmission unit (such as a CXL 256B Flit). This mechanism is uninterruptible; that is, regardless of whether a subsequent request is a high-priority read request or a low-priority write request, it must wait for the timer to expire. Furthermore, if the collected data is insufficient to fill all the slots of a 256B Flit when the timer expires, the controller will use the protocol-defined IDLE (idle symbol) to force-fill the remaining space.

[0033] like Figure 1 The diagram illustrates an exemplary block diagram of a merging strategy in the prior art. In the diagram, Entry0, Entry1, and Entry2 represent the depth values ​​of the buffer. Each Entry can be used to store one transaction layer request; for example, Entry0 stores transaction layer request A, Entry1 stores transaction layer request B, and Entry2 stores transaction layer request C. As shown, the prior art uses a serial search mechanism when performing address merging retrieval, meaning the hardware comparator can only complete the verification of one set of addresses per clock cycle. This means that if the buffer depth is N, in the worst case (i.e., the match is at the end of the queue), it will take N clock cycles to complete a search decision.

[0034] Furthermore, the data extraction logic in traditional solutions is tightly coupled with the read pointer. Even if a search reveals that Entry2 and Entry0 have contiguous addresses, the existing logic cannot skip Entry1 and directly extract Entry2. This strong first-in-first-out constraint leads to a significant number of merging opportunities being wasted due to irrelevant requests being inserted in between.

[0035] Meanwhile, during serial scanning, existing technologies often lack address conflict (hazard) checks for intermediate Entries (such as Entry 1). If Entry 1 is a write operation targeting the same address, directly merging subsequent packets may lead to serious data consistency issues.

[0036] Furthermore, in the 64GT / s environment of CXL3.1, the link layer has extremely high requirements for transaction processing speed (nanosecond level). This time-complex search scheme will directly cause the sender to generate a large number of bubbles due to insufficient processing, thus offsetting the advantages brought by the high bandwidth of CXL.

[0037] Understandably, existing request merging mechanisms have the following drawbacks: 1. Processing latency increases linearly with queue depth, which cannot meet the real-time requirement of 64GT / s: In existing technologies, due to the use of serial comparison logic, the hardware can only verify one set of addresses per clock cycle. If the transaction buffer depth is N, the worst-case latency for searching a mergeable entry is N clock cycles. On the 64GT / s link of CXL3.1, the arrival and transmission frequency of Flits (data packets) is extremely high. This search latency causes severe bubbles to form inside the controller, preventing the transmitter from filling the physical bandwidth in time and resulting in the idle of expensive 64GT / s link resources.

[0038] 2. The sequential extraction mechanism leads to a significant waste of merging opportunities: Existing technologies typically adhere strictly to the FIFO (First-In, First-Out) sequential extraction rule. If Entry0 at the head of the queue and EntryN at the tail have contiguous addresses, but an unrelated Entry1 is interspersed in between, existing logic usually abandons merging Entry0 and EntryN due to Entry1 blocking the flow. This lack of flexibility results in a large number of 64B requests not being compacted within the Flit, causing the Flit load utilization to remain low for an extended period and significantly reducing the system's effective throughput.

[0039] 3. Lack of real-time conflict detection poses a risk of data consistency failure: Existing technologies often lack the ability to check for address conflicts in intermediate entries when attempting to merge subsequent entries. For example, if a write request is waiting to be merged, and a read / write request for the same address appears in the middle of the queue, skipping and merging the subsequent packet directly would reverse the data read / write order. This is unacceptable in the ARM coherent architecture and could lead to system crashes or incorrect calculation results. Therefore, for safety reasons, existing technologies often avoid deep out-of-order merging.

[0040] 4. Unable to handle precise compaction of non-aligned requests within Flit: Existing technologies can typically only handle perfectly aligned address merging. For requests that are not 64B boundary aligned or contain holes, merging is often abandoned due to a lack of fine-grained slot mapping logic. This results in a large number of redundant IDLE slots within the 256B Flit, wasting link power and bandwidth.

[0041] Therefore, there is an urgent need for a new transaction layer request merging strategy that can achieve single-cycle parallel address retrieval, support non-sequential data extraction, have real-time conflict detection capabilities, and perform dynamic slot mapping, in order to overcome the above-mentioned defects of existing technologies and meet the requirements of next-generation high-speed interconnect protocols for extreme latency, bandwidth, and energy efficiency.

[0042] In view of this, this application provides a request parallel merging apparatus. As one implementation, please refer to [link to relevant documentation]. Figure 2 The request for parallel merging device includes: The reassembly buffer 110 is configured to store multiple pending transaction layer requests and output their address information and read / write attribute information in parallel. The address comparison unit 120, coupled to the reassembly buffer 110, is configured to synchronously compare the target address with the address information of all pending transaction layer requests in the reassembly buffer 110 within one clock cycle, and generate a matching vector. The target address is the address of the currently selected target request, and the target request is the request selected as the starting point for the merge search in this packaging operation. The conflict detection unit 130, coupled to the reassembly buffer 110, is configured to, within one clock cycle, compare the address information with the read / write attribute information... The system determines whether there is a consistency conflict between each pending transaction layer request and the target request, and generates a safe release signal. The non-sequential extraction logic unit 140, coupled to the address comparison unit 120 and the conflict detection unit 130, is configured to extract, in a non-sequential manner, the data blocks corresponding to the pending transaction layer requests that simultaneously satisfy address matching and have no conflicts from the reassembly buffer 110 according to the matching vector and the safe release signal. The data blocks are the actual data payload or request control information carried in the pending transaction layer requests. The multi-slot mapping engine 150, coupled to the non-sequential extraction logic unit 140, is configured to dynamically map and compact the extracted data blocks into the data slots of the data packets.

[0043] Understandably, this application achieves efficient merging of transaction layer requests by constructing a parallel processing pipeline that completes request filtering, conflict determination, and data integration within a single clock cycle. This pipeline uses a reorganization buffer 110 as the data temporary storage and distribution hub, an address comparison unit 120 and a conflict detection unit 130 as the parallel decision-making core, a non-sequential extraction logic unit 140 as the dynamic scheduling hub, and a multi-slot mapping engine 150 as the final compaction execution module. Together, they constitute a request parallel merging device for a Compute Express Link (CXL) 3.1 protocol controller.

[0044] Specifically, the reassembly buffer 110 is a temporary storage structure with multi-port parallel output capability. It can simultaneously expose the base address and read / write attribute signals of all valid entries in the queue to the backend logic, and supports the release of non-sequential entries based on the valid bit (indicating whether the entry is currently valid). For example, if the reassembly buffer 110 stores 10 pending transaction layer requests, then during request merging, the reassembly buffer 110 will expose the address information and read / write attribute signals of the 10 pending transaction layer requests to the backend, so that the backend units can perform parallel processing.

[0045] Address comparison unit 120 can be a parallel address comparison array, used to perform bit-to-bit comparison of the target address with all entries in the reconstruction buffer 110 within a single clock cycle, and output an N-bit matching vector representing address affinity.

[0046] The collision detection unit 130 is a Hazard check circuit, which includes a comparator array and priority encoding logic. It is used to identify whether there are consistency collisions such as read-after-write (RAW) against the same address in the reassembly buffer 110, and outputs a high-level active safety release signal.

[0047] The non-sequential extraction logic unit 140 acts as a scheduling center. Based on the matching vector output by the address comparison unit 120 and the safe release signal output by the conflict detection unit 130, it extracts a 64-byte data block from the reassembly buffer 110 in a non-sequential manner. The data block is the actual data load or request control information carried in the pending transaction layer request.

[0048] The multi-slot mapping engine 150 is responsible for dynamically mapping and compacting the extracted data blocks into the data slots of the data packet (FlowControl Unit, Flit). Specifically, it automatically calculates the offset within one clock cycle based on the data volume of the data block, and accurately fills the 64-byte data block into the 14 data slots inside the 256-byte flow control unit to achieve data compaction.

[0049] As can be seen, the request parallel merging device provided in this application gets rid of the timing bottleneck of traditional serial scanning and line-by-line judgment, and enables address matching, conflict detection and data extraction of multiple transaction layer requests to be completed in parallel within the same clock cycle, which significantly improves the throughput efficiency and resource utilization of the CXL bus controller in high-concurrency request scenarios.

[0050] The working principle of each unit is explained in detail below: The reassembly buffer 110 is a storage array with multi-port parallel output capability, and its core hardware implementation is a register file or a multi-port static random access memory. This buffer consists of multiple independent storage entries, each storing a pending transaction layer request. The buffer depth N can be flexibly configured according to the application scenario; for example, N can take values ​​from 32 to 128. It should be noted that the depth described in this application represents the maximum number of pending transaction layer requests that the reassembly buffer 110 can store simultaneously.

[0051] Each storage entry contains three independent storage fields: an address field, which stores the target base address of the request; an attribute field, which stores the read / write attribute information and operation type information of the request; and a data field, which stores the data block carried by the request. In addition, each entry is equipped with a validity bit trigger to indicate whether the entry currently contains a valid pending request.

[0052] Unlike conventional first-in-first-out (FIFO) queues, the reassembly buffer 110 provided in this application employs a multi-channel parallel output architecture on its read port. The address field, attribute field, and valid bit of each storage entry are fanned out directly to the back-end logic via an independent bus, enabling the back-end module to acquire the status information of all entries within the same clock cycle. The data field is connected to the back-end data path via a multiplexer array, supporting direct selection of data output for any entry based on an external index signal, without adhering to the FIFO order.

[0053] Specifically, all storage entries in the buffer simultaneously drive their address information, read / write attribute information, and valid bit signal to independent output buses. These buses are fan-out connected to the inputs of both the address comparison unit 120 and the conflict detection unit 130, allowing the back-end circuitry to perceive the entire queue status within a single clock cycle. For example, when it is necessary to determine whether a target address matches the addresses of all pending requests in the reassembly buffer 110, the parallel address comparison array can simultaneously receive the address information of all entries without waiting for polling one by one. Similarly, the conflict detection unit 130 can also synchronously acquire the read / write attributes of all entries to complete global conflict determination within the same cycle, thereby greatly reducing latency.

[0054] Furthermore, the reassembly buffer 110 also supports non-sequential fetching. Traditional first-in-first-out buffers can only read data from the head of the queue, and after reading, all subsequent entries need to be shifted forward. This not only limits the flexibility of merging but also introduces additional data movement overhead. The reassembly buffer 110 of this application, through index addressing and a multiplexer array, allows non-sequential fetching logic to directly specify the index of any entry and read the data of that entry from the data field and drive it to the output in the same cycle.

[0055] Regarding memory space release, the reorganization buffer 110 employs a logic deletion mechanism based on valid bits. When an entry is successfully retrieved, the non-sequential retrieval logic feeds back the index of the retrieved entry to the buffer. Based on this index, the reorganization buffer 110 only clears the valid bit trigger corresponding to that entry, while the address, attributes, and data information within the entry remain unchanged, and the valid bits and storage content of other entries are unaffected. This release method does not involve physical data movement, therefore it can be completed within a single clock cycle without interfering with the queuing status of other entries. When a new transaction layer request arrives, the reorganization buffer 110 prioritizes writing the request to a free entry with a valid bit of zero, thereby achieving the recycling of memory space.

[0056] In summary, for the reorganization buffer 110, when a new transaction layer request arrives, the reorganization buffer 110 scans free entries with a valid bit of zero, writes the requested address, attributes, and data into the corresponding fields, and sets the valid bit of the entry to one. Secondly, when the parallel address comparison unit 120 and the conflict detection unit 130 make decisions, the buffer outputs the addresses and attributes of all valid entries in parallel to these two modules. Then, when the non-sequential extraction logic determines that an entry needs to be extracted, the buffer outputs the data of that entry to the multi-slot mapping engine 150 through a multiplexer based on the received index signal. Simultaneously, the buffer clears the valid bit of the entry to zero based on the same feedback signal. Finally, the cleared entry becomes free and can be used by subsequent new requests. Therefore, the core function of the reorganization buffer 110 provided in this application is to provide underlying storage support for parallel search, conflict detection, and non-sequential merging.

[0057] As one implementation, the address comparison unit 120 includes N sets of hardware XOR logic gates, where N is the depth of the reassembly buffer 110. The N sets of hardware XOR logic gates are used to perform bit-to-bit comparison between the target address and the address information of N pending transaction layer requests within one clock cycle.

[0058] This application utilizes N sets of hardware XOR logic gates to synchronously complete the bit-to-bit comparison between the target address and all N pending transaction layer request addresses within the same clock cycle, and outputs an N-bit matching vector. Each bit of this matching vector corresponds to a request entry. When a bit is at a logic high level, it indicates that the address of the corresponding entry meets the affinity condition with the target address, such as address contiguousness, address alignment, or belonging to the same cache line, or other preset merging rules.

[0059] It should be noted that the target address mentioned in this application refers to the address of the currently selected target request, which is the request selected as the starting point for merging in this packaging operation. In an exemplary scenario, the target request can be the first request in the reassembly buffer 110. In this case, the address comparison unit 120 can synchronously compare the address of the target request with the addresses of all other pending transaction layer requests in the reassembly buffer 110 to determine whether there are identical or adjacent addresses. If they match, it means that they can be merged; if they do not match, they cannot be merged. For example, if the reassembly buffer 110 includes pending transaction layer requests A, B, C, D, E, F, and G, then A can be used as the target request, and then A can be compared with the remaining pending transaction layer requests to generate a matching vector.

[0060] In another exemplary scenario, when a new request is stored in the reorganization buffer 110, since the request has a higher priority, it needs to be executed first. In this case, the new request can be used as the target request and compared with the address of the pending transaction layer request in the reorganization buffer 110 to determine whether they are the same or adjacent addresses.

[0061] Furthermore, the address port of the reassembly buffer 110 is fan-out connected to the address comparison unit 120 via a parallel bus, allowing the address information of all valid entries to be simultaneously sent to the inputs of each set of XOR logic gates. When the head of the queue requests to trigger a search action, the address comparison unit 120 responds immediately and outputs the address matching status of the entire queue within the same cycle.

[0062] As an alternative implementation, the address comparison unit 120 can also employ a content-addressable memory or a hash mapping unit. The content-addressable memory or hash mapping unit is used to locate the request index that matches the target address within one clock cycle. Specifically, the content-addressable memory structure takes the target address as input and directly returns the indices of all matching entries within a single cycle; the hash mapping unit, on the other hand, distributes requests to multiple sub-queues by performing hash operations on the addresses, requiring only small-scale parallel comparisons within the corresponding hash slots during the search.

[0063] Through the above design, the address comparison unit 120 completely abandons the sequential waiting logic and adopts a full-queue parallel sensing architecture, fundamentally reducing the time complexity of address retrieval. This enables the controller to complete a full scan of the entire buffer within a single clock cycle, ensuring line-speed decision-making even in a 64 GT / s high-speed signal environment. It also completely eliminates pipeline bubbles caused by search lag, thereby maximizing the effective utilization of the CXL physical link.

[0064] When the system uses a non-sequential extraction method to match and merge addresses of multiple pending transaction layer requests, if read and write operations for the same address overlap in the buffer (e.g., a read request followed by a write request, or in reverse order), and the system executes out-of-order merging and transmission without identification, the data access order will violate the storage consistency protocol. Specifically, this may violate consistency constraints defined in the ARM CHI protocol, such as read-after-write, write-after-read, and write-after-write, leading to serious consequences such as data corruption, incorrect calculation results, or even system crashes.

[0065] Traditional address merging logic in CXL or PCIe controllers typically only focuses on address contiguousness or alignment, lacking the ability to synchronously verify the overlap between read / write attributes and address spaces of various requests. Especially when the system allows skipping intermediate entries to directly retrieve matching items from the middle of the queue for performance improvements, if an incomplete write operation request is interspersed in the middle, this write operation may overwrite data about to be read, or its own data may be prematurely exposed by subsequent incorrectly merged read operations, thus violating the strong consistency memory model upon which the entire on-chip system relies.

[0066] To address the aforementioned issues, this embodiment employs a conflict detection unit 130, comprised of a comparator array and a priority encoding logic module. Specifically, the conflict detection unit 130 can perform two parallel tasks within the same clock cycle: firstly, it uses the comparator array to detect in parallel whether the target address overlaps with the addresses of all pending transaction layer requests in the reassembly buffer 110; secondly, through the priority encoding logic module, it determines whether there are read-after-write, write-after-read, or write-after-write conflicts based on the combination of read and write attributes of each request, and outputs a high-level active safety release signal when it confirms that there are no consistency conflicts of any of the above types.

[0067] Specifically, the conflict detection unit 130 includes a Hazard check circuit composed of a comparator array and a priority encoding logic module. The comparator array is used to detect in parallel within one clock cycle whether the target address overlaps with the addresses of all pending transaction layer requests in the reassembly buffer 110. The priority encoding logic module is used to determine whether there is a read-after-write, write-after-read, or write-after-write conflict based on the read / write attribute combination of each pending transaction layer request, and outputs a high-level active safety release signal when there is no conflict. The target address here is also the address of the currently selected target request, which is the request selected as the starting point for the merge search in this packing operation. The address port and read / write attribute port of the reassembly buffer 110 are fan-out connected to the conflict detection unit 130 via a parallel bus, allowing the address information and read / write attribute information of all valid entries to be simultaneously sent to the inputs of the comparator array and the priority encoding logic module.

[0068] As an alternative, the conflict detection unit 130 can also be configured to output a prohibition signal to the non-sequential extraction logic unit 140 when any write operation request is detected among multiple pending transaction layer requests, thereby triggering the non-sequential extraction logic unit 140 to disable the non-sequential extraction function. This solution is a conservative interception alternative, that is, in scenarios where fine-grained conflict determination cannot be performed, consistency security is ensured by globally disabling the out-of-order mechanism.

[0069] Therefore, the conflict detection unit 130 in this embodiment does not perform post-transmission verification, but rather performs hardware-level consistency risk screening synchronously during the address matching decision stage, effectively constructing a storage barrier embedded at the front end of the data path. This design ensures that non-sequential retrieval logic is allowed to initiate data retrieval only when the address matches and there are no potential consistency conflicts. This maintains high performance in single-cycle parallel search and out-of-order compaction while strictly meeting the rigid requirements of mainstream consistency architectures such as ARM for memory access order, avoiding system-level reliability failures due to over-optimization.

[0070] In a traditional first-in, first-out (FIFO) buffer structure, transaction layer requests must be extracted and packaged strictly in the order they enter. If a request with an irrelevant or non-mergeable address exists at the head of the queue—such as a write-back operation accessing a completely unrelated memory region—subsequent requests, even those with consecutive addresses and capable of efficient merging, will be blocked by this head-of-queue blocking event and unable to participate in the packaging process. This head-of-queue blocking phenomenon forces a large number of data blocks that could otherwise be compressed into a single 256-byte data packet to be sent in a dispersed manner, severely reducing the link's payload capacity.

[0071] Analysis of the cause of this problem reveals that the data extraction logic in the existing controller is tightly coupled with the read pointer. Its hardware design only supports sequential traversal and release, lacking the ability to jump across entries. Even if the address comparison unit 120 has identified an entry in the middle of the queue that matches the target request address, the system cannot bypass the invalid entries in the middle and directly retrieve the data, thus missing the opportunity to densely fill the 14 data slots inside Flit.

[0072] To address the aforementioned issues, this embodiment solves them by providing a non-sequential extraction logic unit 140, which includes a multiplexer control array. This non-sequential extraction logic unit 140 generates a set of gating signals within a single clock cycle based on the logical AND operation result of the matching vector and the secure release signal. This drives the corresponding multiplexer array in the reassembly buffer 110, thereby skipping intermediate entries with address mismatches or consistency conflicts and directly extracting the data block corresponding to the selected pending transaction layer request.

[0073] Specifically, the non-sequential extraction logic unit 140 includes a multiplexer control array. This control array is used to extract the data block corresponding to the selected pending transaction layer request from the reassembly buffer 110 based on the result of a logical AND operation between the matching vector and the secure release signal. The matching vector is generated by the address comparison unit 120 within one clock cycle, with each bit corresponding to the address matching status of a pending transaction layer request in the reassembly buffer 110. The secure release signal is generated by the conflict detection unit 130 within the same clock cycle, indicating whether the corresponding entry satisfies the storage consistency constraint. The result of the logical AND operation is the set of candidate entries that simultaneously satisfy address matching and have no consistency conflicts. The reassembly buffer 110 has a parallel output port, which can simultaneously send the data blocks of all valid entries to the input of the multiplexer array. The multiplexer control array uses this selection signal to only open the data path corresponding to the selected entry, achieving physical-level skip-type data retrieval.

[0074] As an alternative implementation, the non-sequential extraction logic unit 140 can also employ a virtual linking scheme, that is, without actually moving the data, it logically concatenates multiple scattered data blocks into a continuous data packet by modifying the pointer linked list. Alternatively, a tag-based tracking alternative can be used, where each request is assigned a unique identifier, and the extraction logic reassembles the data based on the logical order of the identifiers rather than their physical location. All of the above alternatives are equivalent solutions to the technical concept of this invention.

[0075] Therefore, the non-sequential extraction logic unit 140 in this embodiment breaks through the rigid limitation of the FIFO mechanism on the data extraction path, enabling the system to dynamically select the optimal merging combination without changing the physical layout of the buffer. As long as there is any entry in the queue that matches the target request address and has no consistency risk, regardless of whether it is at the head, middle, or tail of the queue, it can be located and extracted immediately, thereby significantly improving the filling density of the 14 data slots within the 256-byte Flit. In typical random memory access scenarios, the effective payload utilization of a single frame Flit can be increased from about 50% in traditional solutions to over 90%, greatly enhancing the actual data throughput of the CXL 3.1 link and truly releasing the engineering value of the 64GT / s high bandwidth.

[0076] In the 256-byte data packet specified in the CXL 3.1 protocol, it is internally divided into 14 slots that can be used to carry actual data. However, these slots are not arranged linearly but are subject to the combined constraints of the protocol frame structure, checksum field, control header, and alignment constraints. When the non-sequential fetch logic unit 140 feeds one, two, or three 64-byte data blocks, if they are simply placed according to a fixed starting position, it is easy for some slots to be ineffective due to address boundary misalignment, data volume mismatch, or incomplete byte enable. In this case, the system has to fill a large number of free symbols to meet the Flit format requirements, resulting in wasted link bandwidth and unnecessary signal switching power consumption at the physical layer.

[0077] Analysis of the causes of this problem reveals that traditional packetization logic typically employs a static slot allocation strategy. For example, the first 64-byte data block is fixed in slots 0 to 3, and the second is fixed in slots 4 to 7. However, actual requests often have arbitrary byte offsets. For instance, they may only require the transmission of 32 bytes with a starting address that is not an integer multiple of 64 bytes, or they may need to be split across 64-byte boundaries, or the number of blocks to be merged may dynamically change, containing different combinations of one, two, or three 64-byte data blocks. The lack of real-time and flexible physical location relocation capabilities prevents data blocks from being perfectly embedded into available slots, forcing the sacrifice of space for format compliance.

[0078] To address the aforementioned issues, this embodiment solves them by implementing a multi-slot mapping engine 150 that includes a hardware barrel shifter. This multi-slot mapping engine 150 can calculate and execute the offset of the extracted data block in the data slot of the data packet within one clock cycle, based on the amount of data in the extracted data block, thereby achieving dynamic slot alignment and compaction with byte-level precision.

[0079] Specifically, the multi-slot mapping engine 150 includes a hardware barrel shifter. This hardware barrel shifter calculates and executes the offset of a data block within the data slots of a data packet within one clock cycle, based on the amount of data in the extracted data block. This data amount includes different combinations of one, two, or three 64-byte data blocks. The hardware barrel shifter is a programmable digital shift circuit that supports left or right shifts of any integer byte in the range of 0 to 255 bytes on the input data within a single clock cycle. The offset calculation is performed automatically based on the current merging quantity and the original byte offset information of each data block, without external instruction intervention. The result is that the entire input 64-byte data block is moved to a contiguous, unoccupied available area within the 14 pre-defined data slots of the 256-byte Flit, ensuring that its starting position meets the technical requirements of the CXL 3.1 protocol regarding slot boundaries, byte enable masks, and CRC and FEC insertion positions. The output of the multi-slot mapping engine 150 is directly delivered to the encapsulation packer 160 for subsequent protocol frame encapsulation.

[0080] As an alternative implementation, the multi-slot mapping engine 150 can also employ a lookup table mapping scheme, where all possible merge combinations and their corresponding optimal slot offset parameters are pre-stored in read-only memory, and the shift parameters are obtained by looking up the table at runtime based on the actual number of merges. Alternatively, a multi-level crossbar switch scheme can be used, which flexibly routes the byte paths of each 64B data block to the target slot location through a reconfigurable hardware interconnect matrix. Although this method incurs a larger area overhead, it supports more fine-grained arbitrary mapping.

[0081] Therefore, the multi-slot mapping engine 150 in this embodiment achieves true bit-level compaction through a hardware barrel shifter, no longer relying on natural alignment or artificially reserved redundant space. Its single-cycle dynamic offset calculation and execution ensures that regardless of changes in the number of input data blocks, whether the starting address is aligned, or whether byte enable is sparse, the optimal filling path can be found among the 14 data slots within the 256B Flit, maximizing the compression of the proportion of idle symbols. This not only significantly improves the effective payload density of a single Flit but also reduces the number of switching of high-frequency signals at the physical layer by reducing the transmission of invalid symbols, thereby effectively reducing dynamic power consumption and improving the energy efficiency ratio of the entire chip's unit data transmission. This is particularly suitable for high-throughput, low-power-sensitive CXL 3.1 interconnect scenarios in data centers.

[0082] After performing non-sequential extraction and multi-slot compaction of data blocks, the result is merely the raw data packet body conforming to the logical structure of the CXL3.1 protocol. It does not yet possess the complete protocol frame format required for physical link recognition and reliable transmission. Without standardized encapsulation, this data cannot be correctly parsed, verified, and driven by the downstream physical layer, nor can it meet the mandatory requirements of the CXL protocol for end-to-end data integrity, error detection, and recovery capabilities.

[0083] Specifically, the CXL 3.1 link layer protocol stipulates that each outgoing Flit must contain a strictly defined frame header, payload, and additional protection fields. In particular, Cyclic Redundancy Check (CRC) codes are used to detect bit-flipping errors during transmission, and forward error correction codes are used to automatically repair partial errors. The position, length, calculation range, and generation algorithm of these fields are all explicitly defined by the standard; any missing or misaligned fields will cause the receiver to discard the Flit, resulting in transaction retransmission or even link slowdown. The aforementioned address comparison unit 120, collision detection unit 130, non-sequential extraction logic unit 140, and multi-slot mapping engine 150 are only responsible for constructing the correct data content and spatial layout; they do not undertake the task of protocol compliance encapsulation.

[0084] To address the aforementioned issues, this embodiment solves them by setting up a packer 160 coupled to the multi-slot mapping engine 150. This packer 160 is configured to encapsulate the compacted data packets into protocol frames and send them to the physical layer, thereby completing the crucial transformation from internally compressible data to a link-transmittable frame.

[0085] Specifically, please refer to Figure 3 The parallel merging device in this embodiment also includes an encapsulator 160 coupled to the multi-slot mapping engine 150. The encapsulator 160 is configured to encapsulate the compacted data packets into protocol frames and send them to the physical layer. The compacted data packets refer to a 256-byte data structure output by the multi-slot mapping engine 150, which has been byte-level aligned and padded according to the 14 data slots specified in the CXL 3.1 protocol. The specific operations of protocol frame encapsulation include: adding a frame header field conforming to the CXL 3.1 specification to the front of the data packet, appending a CRC checksum calculated according to the protocol algorithm, and embedding an FEC encoding field dynamically configured or fixedly embedded according to link quality. The entire encapsulation process is completed within a single clock cycle, and the insertion position, byte order, and checksum range of all fields strictly comply with the technical requirements of Chapters 4 and 12 of the CXL specification. After encapsulation, the encapsulator 160 delivers the complete protocol frame to the physical layer through a standard interface, where the physical layer performs the final level conversion, serialization, and differential signal driving.

[0086] As an alternative implementation, the functionality of the packaging packer 160 can also be partially implemented by the embedded microprocessor or firmware. For example, the microprocessor can dynamically load CRC polynomial parameters or FEC configuration tables for different link rates and then send them to the hardware packaging logic for execution.

[0087] Therefore, the encapsulator 160 in this embodiment is not a simple data forwarding module, but a key compliance interface that ensures the solution of this application can be truly implemented in a real CXL 3.1 link. It transforms the high-performance data results generated by the aforementioned front-end optimization modules into standard protocol frames that can be unambiguously identified, error-detected, and error-corrected at the physical layer. This ensures that the entire request parallel merging mechanism is not only logically efficient, but also fully compatible with existing standards in engineering implementation, possessing the technical feasibility and industrial adaptability to be directly integrated into mass-produced CXL controller chips.

[0088] As one implementation method, please refer to Figure 4 This application also provides a method for requesting parallel merging, the method comprising: S102, when the reassembly buffer 110 stores multiple pending transaction layer requests, the address information and read / write attribute information of the multiple pending transaction layer requests are output in parallel.

[0089] S104, within one clock cycle, the target address is synchronously compared with the address information of all pending transaction layer requests in the reassembly buffer 110, and a matching vector is generated; wherein, the target address is the address of the currently selected target request, and the target request is the request selected as the starting point for the merge search in this packaging operation.

[0090] S106, within one clock cycle, determines whether there is a consistency conflict between each pending transaction layer request and the target request based on the address information and read / write attribute information, and generates a safe release signal.

[0091] S108, based on the matching vector and the safe release signal, extract the data blocks corresponding to the pending transaction layer requests that simultaneously satisfy address matching and have no conflicts from the reassembly buffer 110 in a non-sequential manner; wherein, the data block is the actual data payload or request control information carried in the pending transaction layer request.

[0092] S110 dynamically maps and compacts the extracted data blocks into the data slots of the data packets.

[0093] Based on the method provided in this application, the method mainly includes a full queue exposure step, a parallel comparison and conflict detection step, a decision filtering step, an extraction and compaction step, and a packaging and pointer release step.

[0094] In the full queue exposure step, the reassembly buffer 110 first receives pending transaction layer requests from the system bus. When a new request arrives, the reassembly buffer 110 scans the valid bit status of each internal storage entry, searches for a free entry with a valid bit of zero, writes the address information, read / write attribute information, and data block of the new request into the corresponding storage domain, and sets the valid bit of the entry to a logic high level, indicating that the entry currently contains a valid pending request.

[0095] After completing the aforementioned write operation, the reassembly buffer 110 initiates a parallel output mechanism. Specifically, the reassembly buffer 110 simultaneously drives the address information and read / write attribute information of all storage entries with valid bits set to one to the outside via their respective independent output buses. These buses are fan-out connected to the input terminals of the address comparison unit 120 and the conflict detection unit 130, respectively. Through this design, the address comparison unit 120 and the conflict detection unit 130 can obtain the complete status information of all valid entries in the reassembly buffer 110 within the same clock cycle, without waiting for polling one by one. This full queue exposure mechanism is the physical basis for all subsequent parallel operations.

[0096] In the parallel comparison and collision detection steps, the address comparison unit 120 and the collision detection unit 130 work simultaneously, and both complete their respective calculation tasks within the same clock cycle.

[0097] Address comparison unit 120 receives the address information of all valid entries output in parallel by reassembly buffer 110, and simultaneously receives the target address for this round of packing operation. The target address here refers to the address of the currently selected target request, which is the request chosen as the starting point for the merge search in this packing operation. Address comparison unit 120 internally contains N sets of hardware XOR logic gates, where N is the depth of reassembly buffer 110. These XOR logic gates perform bit-to-bit comparisons between the target address and the address information of each valid entry within the same clock cycle. After the comparison is complete, address comparison unit 120 outputs an N-bit matching vector, where each bit of the matching vector corresponds to a storage entry in reassembly buffer 110. When a bit is logic high, it indicates that the address of the corresponding entry and the target address meet affinity conditions, such as address contiguousness, address alignment, or belonging to the same cache line, or other preset merging rules.

[0098] Meanwhile, the conflict detection unit 130 receives the address information and read / write attribute information of all valid entries output in parallel by the reassembly buffer 110. The conflict detection unit 130 internally includes a Hazard check circuit composed of a comparator array and a priority encoding logic module. The comparator array checks in parallel within the same clock cycle whether the target address overlaps with the address of each valid entry. The priority encoding logic module determines whether there are consistency conflicts such as read-after-write, write-after-read, or write-after-write based on the combination of read / write attributes of each entry. After completing the above determination, the conflict detection unit 130 outputs an N-bit safety release signal, which is active high. That is, when a certain bit is logic high, it indicates that there is no conflict that would violate memory consistency between the corresponding entry and the target request, and merging can be safely performed.

[0099] Through the parallel design described above, the address comparison unit 120 and the conflict detection unit 130 simultaneously complete the address matching judgment and consistency security check within the same clock cycle, providing complete input information for subsequent decision filtering.

[0100] In the decision filtering step, the out-of-sequence extraction logic unit 140 receives a match vector from the address comparison unit 120 and a safety release signal from the collision detection unit 130. The out-of-sequence extraction logic unit 140 internally includes a multiplexer control array, which first performs a bitwise logical AND operation on the match vector and the safety release signal.

[0101] Specifically, the rule for the logical AND operation is as follows: for each entry in the reassembly buffer 110, the result is high only if the corresponding bit in the matching vector is high (indicating address matching) and the corresponding bit in the secure release signal is also high (indicating no conflict). The entries corresponding to all high bits in the result are the set of candidate entries that simultaneously satisfy the address matching condition and have no consistency conflicts.

[0102] Based on this calculation result, the non-sequential fetch logic unit 140 determines the index of the entry that is currently eligible for fetching. This decision-making process is completed within a single clock cycle, without waiting for additional arbitration or sorting operations.

[0103] In the extraction and compaction steps, the multiplexer control array of the non-sequential extraction logic unit 140 generates a set of gating signals based on the candidate entry index determined in the decision filtering step. These gating signals are sent to the multiplexer array of the reassembly buffer 110, driving the multiplexers to directly skip intermediate entries with address mismatches or consistency conflicts, and only enabling the data path corresponding to the selected entry. Based on these gating signals, the reassembly buffer 110 simultaneously reads out the data blocks stored in the selected entries and drives them to the output. Because the reassembly buffer 110 adopts a parallel output architecture, multiple data blocks can be extracted simultaneously within the same clock cycle without following a first-in-first-out order.

[0104] The extracted data blocks are then fed into the multi-slot mapping engine 150. The multi-slot mapping engine 150 contains a hardware barrel shifter that automatically calculates the optimal placement of each data block within a 256-byte data packet's slot within a single clock cycle, based on the number of data blocks extracted and their original byte offsets. After calculation, the barrel shifter performs a shift operation, precisely moving each data block to its target slot. This process achieves dynamic alignment and compaction at the byte level and even bit level, ensuring that data blocks are tightly packed and minimizing the filling of idle symbols.

[0105] After being compacted by the multi-slot mapping engine 150, multiple data blocks that were originally scattered in different locations in the reassembly buffer 110 are integrated into a 256-byte data packet with extremely high fill density. The data slots within this data packet are fully utilized, and the number of free slots is compressed to a minimum.

[0106] In the encapsulation and pointer release steps, the compacted data packet is delivered to the encapsulator 160. The encapsulator 160 performs protocol frame encapsulation on the data packet, specifically including: adding a frame header field conforming to the CXL 3.1 specification to the front of the data packet, appending a cyclic redundancy check (CRC) code calculated according to the protocol algorithm, and embedding a forward error correction (FEC) code field according to link quality configuration or fixed embedding. The entire encapsulation process is completed within a single clock cycle, and the insertion position, byte order, and check range of all fields strictly adhere to the corresponding requirements of the CXL specification. After encapsulation, the encapsulator 160 sends the complete protocol frame to the physical layer through a standard interface, where the physical layer performs the final level conversion, serialization, and differential signaling.

[0107] Simultaneously with data transmission, the storage space release operation of the reassembly buffer 110 is also performed. Specifically, the storage space release is triggered by the non-sequential fetch logic unit 140 while fetching data. When the non-sequential fetch logic unit 140 sends a strobe signal to the multiplexer array of the reassembly buffer 110 to fetch data, the unit simultaneously sends a feedback signal to the valid bit control logic of the reassembly buffer 110. This feedback signal carries the index information of the fetched entry. Based on the received feedback signal, the reassembly buffer 110 only clears the valid bit trigger of the corresponding entry, while the address information, attribute information, and data block inside the entry remain unchanged. The valid bits and storage contents of other entries are also unaffected.

[0108] This release method based on clearing the valid bit is a logical deletion mechanism that does not involve the physical movement of data. Therefore, it can be completed within a single clock cycle without interfering with the queuing status of other entries. When a new transaction layer request arrives, the reorganization buffer 110 prioritizes writing the request to the free entry with the valid bit set to zero, thereby achieving the recycling of storage space. Since the release operation only relies on feedback from the non-sequential fetch logic unit 140 and does not require waiting for confirmation of completion from the encapsulator 160, the storage space can be released immediately after data is fetched without incurring additional waiting cycles. This ensures the efficient and continuous operation of the entire pipeline.

[0109] In summary, the parallel request merging apparatus provided in this application, by outputting the address information and read / write attribute information of multiple pending transaction layer requests in parallel through the reassembly buffer, allows the address comparison unit to synchronously scan all entries in the queue within a single clock cycle, significantly reducing search complexity and effectively minimizing latency. The conflict detection unit simultaneously determines whether there is a consistency conflict between each pending transaction layer request and the target request, ensuring storage consistency security under extreme performance. The non-sequential extraction logic unit allows the circuit to skip irrelevant intermediate entries and directly retrieve matching data from the middle of the reassembly buffer for reassembly based on the address matching result, improving effective throughput. Furthermore, by dynamically mapping and compacting the extracted data blocks to the data slots of the data packets through a multi-slot mapping engine, bit-level compaction can be achieved, improving energy efficiency.

[0110] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0111] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A request parallel merging device, characterized in that, The request parallel merging device includes: The reorganization buffer is configured to store multiple pending transaction layer requests and output the address information and read / write attribute information of the multiple pending transaction layer requests in parallel. The address comparison unit, coupled to the reassembly buffer, is configured to synchronously compare the target address with the address information of all pending transaction layer requests in the reassembly buffer within one clock cycle, and generate a matching vector; wherein the target address is the address of the currently selected target request, and the target request is the request selected as the starting point for the merge search in this packaging operation; The conflict detection unit, coupled to the reassembly buffer, is configured to determine, within one clock cycle, whether there is a consistency conflict between each pending transaction layer request and the target request based on address information and read / write attribute information, and generate a safe release signal. The non-sequential extraction logic unit, coupled to the address comparison unit and the conflict detection unit respectively, is configured to extract, in a non-sequential manner, the data blocks corresponding to the pending transaction layer requests that simultaneously satisfy address matching and are conflict-free from the reassembly buffer according to the matching vector and the secure release signal; wherein, the data block is the actual data payload or request control information carried in the pending transaction layer request; A multi-slot mapping engine, coupled to the non-sequential extraction logic unit, is configured to dynamically map and compact the extracted data blocks into data slots of the data packets.

2. The request parallel merging apparatus according to claim 1, characterized in that, The address comparison unit includes N sets of hardware XOR logic gates, where N is the depth of the reassembly buffer. The N sets of hardware XOR logic gates are used to perform bit-to-bit comparison between the target address and the address information of N pending transaction layer requests within one clock cycle.

3. The request parallel merging apparatus according to claim 1, characterized in that, The address comparison unit includes a content-addressable memory or a hash mapping unit, which is used to locate the request index that matches the target address within one clock cycle.

4. The request parallel merging apparatus according to claim 1, characterized in that, The collision detection unit includes a Hazard check circuit composed of a comparator array and a priority encoding logic module. The comparator array is used to detect in parallel within one clock cycle whether the target address overlaps with the addresses of all pending transaction layer requests in the reassembly buffer. The priority encoding logic is used to determine whether there is a read-after-write, write-after-read, or write-after-write conflict based on the combination of read and write attributes, and outputs a high-level active safety release signal when there is no conflict.

5. The request parallel merging apparatus according to claim 1, characterized in that, The conflict detection unit is also configured to output a prohibition signal to the non-sequential extraction logic unit when any write operation request is detected among multiple pending transaction layer requests, so as to trigger the non-sequential extraction logic unit to disable the non-sequential extraction function.

6. The request parallel merging apparatus according to claim 1, characterized in that, The non-sequential extraction logic unit includes a multiplexer control array, which is used to extract the data block corresponding to the selected pending transaction layer request from the reassembly buffer based on the logical AND operation result of the matching vector and the secure release signal.

7. The request parallel merging apparatus according to claim 1, characterized in that, The multi-slot mapping engine includes a hardware barrel shifter, which is used to calculate and execute the offset of the data block in the data slot of the data packet within one clock cycle, based on the amount of data in the extracted data block.

8. The request parallel merging apparatus according to claim 1, characterized in that, The non-sequential extraction logic is further configured to send a feedback signal to the reassembly buffer after extracting the data block, so as to clear the valid bit of the corresponding entry to zero.

9. The request parallel merging apparatus according to claim 1, characterized in that, The request parallel merging device also includes an encapsulator coupled to the multi-slot mapping engine, which is configured to encapsulate the compacted data packets into protocol frames and send them to the physical layer.

10. A method for requesting parallel merging, characterized in that, The request parallel merging method includes: When the reorganization buffer stores multiple pending transaction layer requests, the address information and read / write attribute information of the multiple pending transaction layer requests are output in parallel. Within one clock cycle, the target address is synchronously compared with the address information of all pending transaction layer requests in the reassembly buffer, and a matching vector is generated; wherein, the target address is the address of the currently selected target request, and the target request is the request selected as the starting point for the merge search in this packaging operation; Within the clock cycle, based on the address information and read / write attribute information, it is determined whether there is a consistency conflict between each pending transaction layer request and the target request, and a safe release signal is generated. Based on the matching vector and the secure release signal, data blocks corresponding to pending transaction layer requests that simultaneously satisfy address matching and are conflict-free are extracted from the reassembly buffer in a non-sequential manner; wherein, the data block is the actual data payload or request control information carried in the pending transaction layer request; The extracted data blocks are dynamically mapped and compacted into the data slots of the data packets.

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