Method, device and equipment for selecting on-chip aging monitoring points and storage medium

Abstract

The application relates to the chip testing technical field, in particular to a selection method and device of on-chip aging monitoring points, equipment and a storage medium. The method comprises the following steps: dimension reduction and path weight evaluation are performed on the multi-dimensional gate level features of each path; a plurality of representative paths are selected to construct a representative path set; based on a delay boundary constraint and a logic shielding strategy of trigger node observability forward shift, reverse topological tracking is performed from the end of the representative path to the fan-in direction, a plurality of candidate observation points are calibrated from each representative path, and a candidate observation point set is constructed; a mapping relationship is constructed based on the representative path set and the candidate observation point set; under the coverage or observation point number constraint, the target observation node is dynamically selected through a global optimal planning model in combination with the path weight. The application can reduce the material cost, improve the signal capture efficiency, and realize the global optimal target observation node monitoring selection.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to methods, apparatus, equipment and storage media for selecting on-chip aging monitoring points. Background Technology

[0002] As integrated circuit (IC) manufacturing processes advance to deep submicron and nanometer nodes, the reliability of chips in complex physical environments is becoming increasingly prominent. In order to ensure the reliable operation of the system throughout the entire chip lifecycle management (SLM) process, it is urgent to insert in-situ timing monitoring logic inside the chip to observe the aging state of the circuit in real time.

[0003] Existing technologies propose in-situ sensor placement methods based on the ends of timing paths. These methods identify critical paths with minimal timing margins at worst-case process corners and place triggers with aging functions at their ends for monitoring. However, in modern VLSI (System-on-a-Chip) designs, the number of critical paths is significant. Placing aging sensors on all potentially timing-sensitive paths to cover all potential critical paths would lead to increased silicon area, wiring congestion, and extremely high static and dynamic power consumption. Furthermore, placing timing monitoring points at the physical ends of timing paths means that minor delay anomalies caused by aging are easily masked by the control states of other bypass signals during signal propagation in multi-level logic gates, resulting in a very low probability of effective level transitions at the path's end nodes. To overcome the problems of excessive end-monitoring load and low coverage, existing technologies also propose monitoring methods using timing margin probes. These methods perform node timing margin analysis on the timing diagram to identify shared intermediate nodes across multiple paths and insert node pins based on the transition frequencies of these intermediate nodes to achieve one-to-many monitoring. However, this approach relies solely on simple graph theory-based shared node analysis, failing to mathematically isolate redundant paths arising from similar PVT sensitivities. When faced with complex process variations and layout distributions in real chips, it struggles to guarantee that the selected intermediate nodes truly represent the diverse aging states of the entire chip. Furthermore, given physical area constraints, it can only select local nodes, unable to achieve globally optimal node selection for the entire chip.

[0004] It is evident that existing methods for selecting on-chip aging monitoring points suffer from high material costs, low signal acquisition efficiency, and the inability to achieve global planning for monitoring point selection. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for selecting on-chip aging monitoring points, in order to solve the technical problems of high material cost, low signal acquisition efficiency, and inability to achieve global planning of monitoring point selection in the above-mentioned prior art on-chip aging monitoring point selection methods.

[0006] According to one aspect of the embodiments of this application, this application provides a method for selecting on-chip aging monitoring points. The method includes: performing dimensionality reduction and path weight evaluation on the multi-dimensional gate features of each path, selecting multiple representative paths to construct a representative path set; based on the logical masking strategy of delay boundary constraints and forward shifting of trigger node observability, performing reverse topology tracing from the end of the representative path towards the fan-in direction, identifying multiple candidate observation points from each of the representative paths and constructing a candidate observation point set; constructing a mapping relationship based on the representative path set and the candidate observation point set, and dynamically selecting target observation nodes through a global optimal planning model under the constraints of coverage or the number of observation points, combined with path weights.

[0007] Optionally, the step of performing dimensionality reduction and path weight evaluation on the multi-dimensional gate-level features of each path, and selecting multiple representative paths to construct a representative path set, includes: scanning the chip netlist using a timing margin analysis algorithm to screen critical paths with timing margins less than a preset safety threshold; extracting multi-dimensional gate-level features for each critical path, including extracting at least one of topological features, timing and parameter features, temperature sensitivity features, dynamic behavior features, and physical space features; constructing a feature vector corresponding to each critical path based on the extracted multi-dimensional gate-level features, and concatenating the feature vectors of all critical paths to construct a path feature matrix; performing mathematical dimensionality reduction on the path feature matrix, and evaluating the weights of the processed paths to screen multiple representative paths and construct the representative path set.

[0008] Optionally, the step of performing mathematical dimensionality reduction on the path feature matrix, evaluating the weights of the processed paths, selecting multiple representative paths, and constructing the representative path set includes: extracting the dominant mutation direction of the path feature matrix in the feature space using a first feature decomposition algorithm; performing principal component decomposition in the feature space based on the dominant mutation direction using a second feature decomposition algorithm to remove redundant paths; projecting the feature vectors of the remaining paths onto the dominant mutation subspace extracted by the singular value decomposition algorithm, and selecting the path corresponding to the feature combination containing the largest independent information content as the representative path; evaluating the weights of each representative path, selecting the representative paths according to the weights, and constructing the representative path set based on the remaining representative paths.

[0009] Optionally, the step of weighting each representative path, filtering the representative paths according to their weights, and constructing the representative path set based on the remaining representative paths includes: calculating the weight score of each representative path in the representative path set using a preset weighting evaluation model based on the establishment time leeway of the representative paths, where the weight score represents the temporal risk level of the path; prioritizing each representative path based on its weight score; filtering the representative paths in the representative path set based on their priority; and constructing the representative path set based on the remaining representative paths according to their weight priority.

[0010] Optionally, the logic masking strategy based on delay boundary constraints and forward shifting of trigger node observability involves reverse topology tracing from the end of the representative path towards the fan-in direction, identifying multiple candidate observation points from each representative path, and constructing a candidate observation point set. This includes: performing reverse topology tracing from the end of the representative path towards the fan-in direction, calculating the total absolute delay time traversed by the reverse topology tracing; determining the delay boundary constraints based on the total absolute delay time, the delay boundary constraints including a lower bound and an upper bound for candidate observation points on the path; constructing the candidate observation point set by constructing path nodes falling within the range of the lower bound and the upper bound of candidate observation points, wherein the candidate observation point set includes path nodes selected within the range of the lower bound and the upper bound of candidate observation points when the logic masking strategy is triggered, and the logic masking strategy is triggered when the logic gate transition probability is lower than a preset transition probability threshold.

[0011] Optionally, the step of constructing a mapping relationship based on the representative path set and the candidate observation point set, and dynamically selecting target observation nodes by combining path weights under coverage or observation point number constraints, includes: constructing a mapping relationship based on the representative path set and the candidate observation point set, wherein the mapping channel between the representative path and the candidate observation point in the mapping relationship represents a cross-coverage relationship; and dynamically selecting target observation nodes by using a global optimal planning model based on the cross-coverage relationship and the weight score of the representative path under coverage or observation point number constraints.

[0012] Optionally, the step of dynamically selecting the target observation node based on the cross-coverage relationship and the weight scores of the representative paths under the constraints of coverage or number of observation points, using a global optimal programming model, includes: obtaining the sum of the weight scores of each representative path mapped to the candidate observation point based on the cross-coverage relationship; selecting the candidate node corresponding to the largest sum of weights as the target observation node using the global optimal programming model, under the constraint of the number of observation points, based on the sum of weight scores of each representative path mapped to the candidate observation point; or selecting the candidate node with the largest and smallest sum of weight scores of each representative path mapped to the candidate observation point as the target observation node, under the constraint of coverage, using the global optimal programming model.

[0013] According to another aspect of the embodiments of this application, this application provides an on-chip aging monitoring point selection device, the device comprising: a path filtering module, used to perform dimensionality reduction and path weight evaluation on the multi-dimensional gate features of each path, and select multiple representative paths to construct a representative path set; a node tracking module, used to perform reverse topology tracing from the end of the representative path to the fan-in direction based on a logical masking strategy of delay boundary constraints and forward shifting of trigger node observability, and to identify multiple candidate observation points from each of the representative paths and construct a candidate observation point set; and a target node selection module, used to construct a mapping relationship based on the representative path set and the candidate observation point set, and dynamically select target observation nodes by combining path weights under the constraints of coverage or the number of observation points through a global optimal planning model.

[0014] According to another aspect of the embodiments of this application, this application provides a computer device, including: a processor, a memory, and a network interface. The memory stores machine-readable instructions executable by the processor. When the computer device is running, the processor communicates with the memory through the network interface, and the processor executes the machine-readable instructions to perform the steps of the on-chip aging monitoring point selection method as described above.

[0015] According to another aspect of the embodiments of this application, this application provides a computer-readable medium having processor-executable non-volatile program code that causes the processor to perform the steps of the on-chip aging monitoring point selection method.

[0016] Compared with related technologies, the technical solutions provided in this application have the following advantages: This application provides a method for selecting on-chip aging monitoring points. By introducing multi-dimensional gate-level features for mathematical dimensionality reduction, redundant paths with similar temperature sensitivity can be eliminated at the source. A very small number of representative paths can replace a massive set of data, thereby significantly reducing the number of sensors required and the cost of hardware area. By setting delay boundary constraints and a logic masking strategy that moves the observability of trigger nodes forward, reverse topology tracing is performed from the end of the representative path towards the fan-in direction. This allows for interception and monitoring before the signal is masked by logic gates, fundamentally eliminating blind spots and greatly improving the effective capture rate of aging transitions. Under the constraints of coverage or the number of observation points, the problem is transformed into a coverage problem. The set of representative paths is mapped to the set of candidate observation points, and cross-search is performed based on a global optimal planning model. This ensures coverage of the entire chip's aging paths under strict hardware constraints. Furthermore, by combining weighted search, paths that could lead to catastrophic system failures with slight aging are likely to be covered first, thus achieving efficient and accurate selection of global target monitoring points. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating an optional on-chip aging monitoring point selection method according to an embodiment of this application; Figure 2 This is a schematic flowchart of another optional on-chip aging monitoring point selection method provided according to an embodiment of this application; Figure 3 This is an optional on-chip circuit topology provided according to an embodiment of this application; Figure 4 This is another optional on-chip circuit topology provided according to an embodiment of this application; Figure 5 This is a schematic diagram of an optional bipartite graph-based mathematical mapping model provided according to an embodiment of this application; Figure 6 This is a block diagram of an optional on-chip aging monitoring point selection device according to an embodiment of this application; Figure 7 This is a schematic diagram of an optional computer device structure provided for an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] To address the problems mentioned in the background art, according to one aspect of the embodiments of this application, an embodiment of a method for selecting on-chip aging monitoring points is provided.

[0022] It should be noted that the method for selecting on-chip aging monitoring points provided in this application embodiment is generally executed by a server and / or terminal device, and correspondingly, the device for selecting on-chip aging monitoring points is generally set in the server / terminal device.

[0023] like Figure 1 As shown, Figure 1 A flowchart illustrating a method for selecting on-chip aging monitoring points according to an embodiment of the present invention. Taking the method of selecting on-chip aging monitoring points being executed by a server as an example, the method includes the following steps: Step S101: Perform dimensionality reduction and path weight evaluation on the multi-dimensional gate features of each path, and select multiple representative paths to construct a representative path set.

[0024] In this embodiment, the connections between the on-chip components form multiple branches, each serving as a timing path. In the aging monitoring scenario of large-scale integrated circuits, there will be a massive number of timing paths that need to be monitored. To quickly and efficiently select monitoring points, this embodiment first performs feature extraction and dimensionality reduction processing, and then evaluates path weights to select representative paths. By replacing the massive complete set with a very small number of representative paths, the number of sensors required and the hardware area cost can be significantly reduced.

[0025] Specifically, at advanced process nodes (referring to 16nm / 14nm and below nanometer-level advanced processes), there are a massive number of timing paths within the chip. A large number of physically adjacent or structurally similar paths exhibit a high correlation with aging and voltage drop sensitivities; for example, NBTI leads to an increase in the PMOS threshold voltage. Therefore, to avoid redundant waste of sensor resources, this embodiment distinguishes paths by extracting gate-level features from each path, aggregating similar paths, and extracting the most representative orthogonal path subset (representative path set). Here, gate features refer to the physical parameters, electrical parameters, and structural topology parameters extracted using the standard chip unit logic gates (inverters, NAND gates, NOR gates, buffers, flip-flops, etc.) as the smallest analytical granularity.

[0026] In some embodiments, the paths after feature downgrading can be weighted and evaluated, and then representative paths can be selected based on the weights to construct a representative path set. Alternatively, the paths selected after feature downgrading can be used as representative paths to construct a representative path set, and then the representative paths can be weighted and evaluated to quantify their priority. The core benchmark for this evaluation is the temporal hazard level of the path.

[0027] In this embodiment, by introducing multi-dimensional gate-level feature extraction and mathematical dimensionality reduction, redundant paths with similar PVT (temperature) sensitivity can be eliminated at the source, and a very small number of representative paths can be used to replace the massive full set, thereby significantly reducing the number of sensors required and the cost of hardware area.

[0028] Step S102: Based on the logical masking strategy of delay boundary constraints and forward shift of the observability of trigger nodes, reverse topology tracing is performed from the end of the representative path to the fan-in direction, and multiple candidate observation points are identified from each of the representative paths and a candidate observation point set is constructed.

[0029] In this embodiment, after determining the set of representative paths with high weights, it is necessary to determine the specific logical nodes in which the aging sensors are physically inserted, i.e., aging monitoring points OP or observation points OP. In order to delineate an optimal monitoring point distribution range, a hybrid tracking algorithm combining static timing analysis, circuit diagram structural features, and dynamic probability statistics is used to delineate the upper and lower boundaries of candidate observation points, and delay boundary constraints are formed based on the upper and lower boundaries.

[0030] Specifically, the algorithm starts from the endpoint of a selected representative path and performs reverse node tracing along the fan-in direction of the combinational logic network. When calculating the total path length, it not only counts the number of logic gates along the path but also uses the STA tool to extract the precise timing of each logic gate unit, calculating the total absolute delay time traversed during reverse tracing. For the lower boundary of the delay boundary constraint, the algorithm pre-sets a forward depth limit to prevent the delay from being too small, for example, it cannot be less than 90% of the total delay. For the upper boundary of the delay boundary constraint, the algorithm pre-sets a limit closer to the endpoint direction to prevent masking, for example, it cannot be greater than 99% of the total delay.

[0031] Specifically, the aforementioned logic masking strategy for advancing observability of trigger nodes can refer to the observability advancement mechanism triggered when encountering logic gate masking aging transitions, making the probability of originally observable level transitions extremely low and unable to capture any effective signals. Here, observability advancement refers to actively moving the observation point OP, which was originally in a position of extremely low observability, forward along the data flow direction within the range defined by the lower boundary, forcibly crossing over such logic gates that trigger high-probability masking, finding a position that meets the observability requirements, and dynamically adjusting the upper boundary.

[0032] Furthermore, after performing reverse topology tracing based on the above constraints and strategies, corresponding candidate observation points will be identified from each representative path, and a set of candidate observation points can be constructed based on these candidate observation points.

[0033] In this embodiment, a logic masking strategy that triggers the forward movement of observability of nodes is proposed, breaking through the traditional end-point monitoring method. This strategy actively moves the observation points that were originally in a position with extremely low observability forward along the data flow direction within the range defined by the lower boundary, forcibly bypassing logic gates that trigger high-probability masking. This intercepts and monitors the signal before it is masked, thereby fundamentally eliminating the blind spot of missed reports, greatly improving the effective capture rate of aging transitions, and reducing the impact on the original timing.

[0034] Step S103: Based on the representative path set and the candidate observation point set, a mapping relationship is constructed. Under the constraints of coverage or the number of observation points, the target observation node is dynamically selected by combining the path weight through a global optimal planning model.

[0035] Among these, a representative set of paths with high weights is obtained. and a high-quality set of candidate observation points that have been screened and filtered to avoid detection. Subsequently, in the physical implementation of integrated circuits, considering the limitations of chip area, wiring resources, and power consumption budget, SLM systems typically specify a threshold for the absolute number of aging sensors that can be inserted, denoted as a constraint constant. (Number of observation points constraint); or conversely, the system specifies a required safe coverage rate, requiring the sensor area overhead to be minimized (coverage rate constraint).

[0036] In this embodiment, in order to achieve based on The goal is to maximize the monitoring of all representative paths using aging sensors, or to cover all specified paths with the fewest possible aging sensors. This is achieved by transforming the engineering chip resource allocation problem into a global optimization problem. A global optimal planning model is used to optimize the selection set, supporting bidirectional conversion between maximum and minimum coverage. Ultimately, multiple target observation nodes are selected, and aging sensors are deployed at each node. This ensures full coverage of the chip's aging paths under strict hardware constraints.

[0037] In this embodiment of the invention, by introducing multi-dimensional gate-level features for mathematical dimensionality reduction, redundant paths with similar PVT sensitivity can be eliminated at the source, replacing the massive full set with a very small number of representative paths, thereby significantly reducing the required number of sensors and hardware area costs. By setting delay boundary constraints and a logic masking strategy that moves the observability of trigger nodes forward, reverse topology tracing is performed from the end of the representative path towards the fan-in direction, enabling interception and monitoring before the signal is masked by logic gates, thus fundamentally eliminating blind spots and accurately locking candidate observation points, greatly improving the effective capture rate of aging transitions. Under the constraints of coverage or the number of observation points, by transforming the problem into a coverage problem, the set of representative paths is mapped to the set of candidate observation points, and cross-search is performed based on a global optimal planning model, ensuring coverage of the entire chip's aging paths under strict hardware constraints. Furthermore, by combining weighted search, paths that would lead to catastrophic system failures with slight aging are likely to be covered first, thereby efficiently and accurately selecting global target monitoring points. Finally, a complete three-part systematic framework logic method is used to achieve global selection of aging monitoring points by clustering of correlation paths and extracting representative paths based on multi-dimensional features, moving the observation point range forward and delineating the safety boundary based on reverse tracing of the fan-in direction based on temporal topology, and calculating the global optimization of the maximum set of target observation points under the constraints of coverage or the number of observation points.

[0038] In some alternative embodiments, step S101 includes: S1011 uses a timing margin analysis algorithm to scan the chip netlist and filter critical paths with timing margins less than a preset safety threshold. S1012, perform multi-dimensional gate-level feature extraction on each of the key paths, including extracting at least one of topological features, temporal and parameter features, temperature sensitivity features, dynamic behavior features, and physical space features; S1013, construct a feature vector corresponding to each key path based on the extracted multi-dimensional gate-level features, and concatenate the feature vectors of all key paths to construct a path feature matrix; S1014, the path feature matrix is ​​subjected to mathematical dimensionality reduction, and the processed paths are weighted and evaluated to select multiple representative paths and construct the representative path set.

[0039] The timing margin analysis algorithms include, but are not limited to, Aging-aware STAR (Static Timing Analysis) and RC (Remote Control Parameter Extraction) tools. These tools can perform a full scan of the chip netlist to identify potential critical paths with timing margins less than a preset safety threshold, such as 5% of clock cycles. For each extracted critical path, multi-dimensional gate-level features reflecting its physical and electrical nature are automatically extracted, generating a feature vector for each critical path.

[0040] The extracted gate-level features include, but are not limited to: Topology features: the number of logic gates traversed by the path, and the usage ratio of various standard cells in the path, including but not limited to NAND, NOR, INV, XOR, etc. Different cell structures exhibit significantly different resistance to aging. Timing and parameter features: STA simulations are performed under different process corners to extract the cumulative absolute delay. Process corners include SS, TT, FF, etc. PVT sensitivity features: by injecting small environmental variable disturbances into STA or SPICE (Simulation Program with Integrated Circuit Emphasis) simulations, the change in supply voltage along the corresponding path is calculated. ), Ambient temperature change ( ) and the natural fluctuation of transistor threshold voltage ( The partial derivative sensitivity coefficient of the signal. Dynamic behavioral characteristics: slew time, toggle rate, and signal probability (i.e., the percentage of time a path node is in logic "0" or logic "1" under typical workloads), serving as data for analyzing logic masking. Physical spatial characteristics: the two-dimensional coordinates of the layout where the path is located. Due to the spatial process variability in wafer manufacturing, the aging speed of transistors in adjacent areas tends to be similar, while areas that are far apart may have significant differences. Therefore, physical region identifiers must be included in the feature vector to ensure that the finally selected target observation nodes can cover all quadrants of the layout.

[0041] Among them, deviations in advanced chip manufacturing processes are reflected in the version. Figure 2 The silicon wafer aging rate may differ greatly between the upper left and lower right regions of the layout due to uneven distribution on the 2D plane. When constructing the path feature matrix, the 2D region coordinates of the layout and electrical indicators such as drift sensitivity under different extreme process angles are introduced. The final selected target observation points are not only high-risk nodes in terms of timing, but also evenly and reasonably distributed in various quadrants of the layout in terms of physical spatial layout, so as to form a three-dimensional defense network that can truly reflect the overall macroscopic and microscopic health status of the entire chip.

[0042] Furthermore, the features extracted from each path undergo uniform mean removal and normalization preprocessing to eliminate dimensional differences and numerical biases. Feature vectors are then constructed, and the feature vectors of the massive number of extracted key paths are concatenated into a path feature matrix. , scale ,in, The total number of candidate paths. This represents the total number of extracted feature dimensions. Due to the significant physical and logical similarities between paths, the matrix... Typically, these paths exhibit extremely high rank-deficient characteristics or multicollinearity. To eliminate highly correlated redundant paths, mathematical dimensionality reduction and extraction theories can be used at an abstract level to remove redundancy caused by PVT sensitivity or structural similarity. This allows for the precise selection of a set of mathematically highly independent representative paths (orthogonal path subsets) from tens of thousands of initial paths, for example, through dimensionality reduction using singular value decomposition combined with QR principal component decomposition. Each representative path represents a unique subset of circuits in terms of PVT sensitivity, process corner response, and topology type, preserving the timing degradation characteristics of the entire chip to the maximum extent while exponentially reducing the scale of subsequent computations. The selected representative paths are then weighted, with a higher weight indicating a higher degree of timing risk and requiring more urgent attention.

[0043] In this embodiment, by screening critical paths, the deployment of sensors on every path is avoided, reducing redundant waste of resources. By abstracting multi-dimensional physical and electrical attributes such as multi-process corner timing, PVT sensitivity, flip-flop probability and spatial distribution into high-dimensional mathematical feature structures for differentiation, similar paths are aggregated and dimensionality reduced to extract the most representative path. This can eliminate highly correlated redundant paths, preserve the timing decay characteristics of the entire chip to the maximum extent, and exponentially reduce the scale of subsequent calculations.

[0044] In some optional embodiments, step S1014 specifically includes: The dominant mutation direction of the path feature matrix is ​​extracted in the feature space using the first eigenvalue decomposition algorithm. Based on the dominant mutation direction, principal component decomposition is performed in the feature space using the second feature decomposition algorithm to filter out redundant paths. The feature vectors of the remaining paths are projected into the dominant mutation subspace extracted by the singular value decomposition algorithm, and the path corresponding to the feature combination containing the largest amount of independent information is selected as the representative path. Each representative path is weighted and evaluated, and the representative paths are then filtered based on their weights. The remaining representative paths are then used to construct the representative path set.

[0045] The first eigenvalue decomposition algorithm is Singular Value Decomposition (SVD), and the corresponding second eigenvalue decomposition algorithm is QR principal component decomposition. Of course, the first eigenvalue decomposition algorithm can also be Principal Component Analysis (PCA), Factor Analysis (FA), Independent Component Analysis (ICA), etc. The second eigenvalue decomposition algorithm can also be Column Principal Component Decomposition (LUPP), Rank Revealed Singular Value Decomposition (RR-SVD), Gram-Schmidt Orthogonalization (GS) with selected principal components, etc. Combinations of the first and second eigenvalue decomposition algorithms include, but are not limited to, PCA with Column Principal Component Decomposition (LU) and FA with GS orthogonalization.

[0046] In some examples, singular value decomposition (SVD) and QR principal component decomposition (QR PDT) are combined for mathematical dimensionality reduction. First, SVD is used to extract the most important principal directions of variation from the high-dimensional path feature space, suppressing noise and weak redundancy. Then, QR PDT is used to identify and remove linearly related and structurally / PVT-similar redundant paths in the feature space. Finally, the remaining paths are projected onto the principal variation subspace, and the mathematically non-redundant and most representative paths are selected according to the independent information maximization criterion.

[0047] Specifically, the constructed path feature matrix contains massive amounts of path coupling information, exhibiting linear redundancy and feature overlap due to numerous PVT linkages and structural similarities. Therefore, singular value decomposition (SVD) can be used to decompose the original high-dimensional space into several mutually orthogonal variation components. Based on the magnitude of the singular values, strong information-dominated variation directions are distinguished from weak noise and weak redundancy variation directions. The orthogonal basis corresponding to large singular values ​​is retained to form the dominant variation subspace, while the weak perturbation components corresponding to small singular values ​​are discarded. This completes the first layer of global dimensionality reduction, mapping the original high-dimensional path features to a low-dimensional orthogonal subspace and separating effective variation from ineffective redundant noise.

[0048] Furthermore, based on the dominant mutation direction, redundant paths are eliminated through QR principal component decomposition. Within the feature space of the dominant mutation determined by SVD, a QR decomposition with principal component selection is performed on the mapped path feature matrix. Through principal component permutation and sorting, the linear correlation of row vectors in the matrix is ​​identified. Paths that can be linearly represented by other path feature vectors are determined to be redundant, while those with independent principal component contributions are determined to be non-redundant and effective paths. In this way, redundant paths with convergent PVT sensitivity, highly similar structural features, and substitutable information can be directly eliminated, retaining only paths with linear independence.

[0049] Furthermore, the feature vectors of the remaining paths after filtering out redundant paths are projected onto the dominant mutation subspace. This projects the feature vectors of all valid paths remaining after QR filtering onto the dominant mutation subspace pre-extracted by SVD. After projection, the paths are decoupled from the original high-dimensional space, and the mutation contribution, information overlap, and independence of each path can be quantified. This decouples paths that were originally entangled and had overlapping features in the orthogonal subspace, highlighting their independent information. Finally, representative paths are selected according to the criterion of maximum independent information content. In the projected low-dimensional subspace, the independent information content, mutation coverage, and vector orthogonality of each path feature combination are quantified and evaluated. The combination with the maximum information content, the highest mutual independence, and complementary mutation dimensions can be used as the selection principle to select the optimal feature combination. The physical path corresponding to the optimal feature combination is determined as the final representative path. The selected representative paths are further weighted and evaluated, and a second round of selection is performed to finally construct a representative path set from the remaining representative paths.

[0050] In this embodiment, by combining SVD decomposition and QR principal component decomposition, high-dimensional reduction and orthogonal dominant mutation direction mining can be achieved, filtering weak noise and global weak redundancy. Linear correlation verification and redundant path removal are performed in the feature space, eliminating redundancy caused by PVT sensitivity or structural similarity. Through subspace projection and information content optimization, feature decoupling and maximizing independent information content filtering can be achieved, resulting in a mathematically independent and globally representative set of core paths. The final result is a representative set of paths that is far fewer in number than the initial path set, but is mathematically highly independent and can completely cover global PVT mutations and structural features.

[0051] In some optional embodiments, the above steps—evaluating the weights of each representative path, filtering the representative paths according to their weights, and constructing the representative path set based on the remaining representative paths—specifically include: Based on the establishment time leeway of the representative paths, the weight score of each representative path in the representative path set is calculated through a preset weight evaluation model. The weight score represents the temporal risk level of the path. The representative paths are prioritized based on the weight scores, and the representative paths in the representative path set are filtered based on the priority. The remaining representative paths are then used to construct the representative path set according to the priority of their weights.

[0052] Specifically, after extracting representative paths, each representative path undergoes a priority quantification assessment, with the core benchmark being the timing hazard level of the path. The path establishment time timing margin can be obtained by extracting the total delay of the path data path, clock tree arrival delay, and register establishment time constraints, combined with PVT and clock skew correction, and then performing a path-by-path timing deduction. It can also be incorporated into the path feature matrix as a gate-level feature dimension to support subsequent mathematical dimensionality reduction and representative path selection.

[0053] In some examples, the pre-defined weight evaluation model may include non-linear exponential penalty functions, hyperbolic tangent penalty functions (Tanh penalty), arctangent penalty functions (Arctan penalty), logarithmic penalty functions (Log logarithmic penalty), etc. As shown in equation (1), evaluation is performed using a non-linear exponential penalty function. For each representative path... Calculate weighted scores : (1) in, The setup slack represents the setup time margin of a representative path. The smaller the slack value, the closer the signal arrival time is to the clock capture edge, the more tight the timing of the path is at this time, and the higher the risk of failure. This represents a system-defined aging sensitivity coefficient constant. ).

[0054] Using the above formula (1), when establishing time series margin The path's weight score as it approaches a critical value or becomes negative. This will result in a dramatic exponential amplification. This mechanism ensures that in the subsequent competition for observation point resources, paths that are prone to catastrophic system failure even with slight aging will have absolute priority for being covered by sensors.

[0055] Furthermore, after calculating the weight score of each path, they can be sorted in descending order to quickly obtain a representative set of paths arranged according to their priority. The higher the priority, the higher the temporal risk.

[0056] In this embodiment, a weighted evaluation model is used to evaluate the weights of representative paths based on their time-series margins. The weight score is then used to represent the temporal risk level of the path. Priority evaluation is performed based on the weight score. This approach not only accurately reflects the critical state of the path's temporal margin using the time-series margin, but also amplifies the weight differences by imposing a stronger penalty on paths with small time-series margins and high temporal risks through a nonlinear exponential penalty function. This achieves automatic highlighting of high-risk paths and reasonable weakening of low-risk redundant paths. Ultimately, representative paths are stratified and graded according to their temporal risk levels, and high-risk key monitoring paths are accurately selected, improving the accuracy of path selection and temporal risk identification.

[0057] In some optional embodiments, step S102 above includes: S1021, Perform reverse topology tracing from the end of the representative path toward the fan-in direction, and calculate the total absolute delay time traversed by the reverse topology tracing; S1022, Determine the delay boundary constraint based on the total absolute delay time, wherein the delay boundary constraint includes the lower bound of the candidate observation points and the upper bound of the candidate observation points of the path; S1023, construct the candidate observation point set by constructing the path nodes that fall within the range of the lower bound and the upper bound of the candidate observation point, wherein the candidate observation point set includes the path nodes selected within the range of the lower bound and the upper bound of the candidate observation point when the logic masking strategy is triggered, and the logic masking strategy is triggered when the logic gate transition probability is lower than a preset transition probability threshold.

[0058] In this embodiment, combined with Figure 2 As shown, after determining the set of representative paths with high weights, it is necessary to determine the insertion nodes for the aging sensors. First, the upper boundary (upper bound of candidate observation points) and lower boundary (lower bound of candidate observation points) of the candidate observation points are defined, that is, the range of candidate observation points is defined within the representative paths. Starting from the end point of the selected representative path, reverse node tracing is performed along the fan-in direction of the combinational logic network. During the reverse tracing process, the total path length is calculated, the number of logic gates along the path is counted, and the precise timing of each unit is extracted using the STA tool to calculate the total absolute delay time traversed during reverse tracing.

[0059] Specifically, for defining the range of candidate observation points along a representative path, its lower boundary can be determined by setting a forward depth limit to prevent the delay from being too small, for example, it should not be less than 90% of the total absolute delay time. If the forward depth is too close to the starting point, the number of logic gates accumulated at that node will be too small, and the amount of aging absolute delay it can reflect will be extremely weak, easily drowned out by environmental noise, such as voltage ripple and crosstalk. Furthermore, it will be difficult to coordinate with timing margin monitoring circuits, exceeding the timing margin monitoring range.

[0060] like Figure 3 As shown, based on the circuit topology, during reverse tracing, a core candidate boundary line is defined as 90% of the total absolute delay time. Assuming the cumulative delay at node OP0 is 100%, and the delay at node OP1 relative to node OP0 is 92%, and path 2 largely overlaps with path 1, the delay at the fork point already accounts for 90% of node OP0's delay. This sufficiently accumulates the degradation characteristics of most transistors on path 1, and node OP1 can completely cover the worst-case scenario of node OP0. Furthermore, nodes backtracking towards the 90% boundary region in the Fan-in direction are often logical intersection points of multiple critical paths, such as path 1 and path 2. Defining the lower bound of candidate observation points at these nodes allows for the selection of a wider set of common candidate points (candidate observation points), thereby significantly reducing the number of observation points required.

[0061] Furthermore, for the upper boundary of the candidate observation point range defined on the representative path, a waiting depth limit can be set near the endpoint direction to prevent shielding and overloading, for example, it cannot exceed 99% of the total delay. This leaves sufficient parasitic delay buffer space to ensure that the delay introduced by the sensor can be absorbed by the remaining path tolerance, while avoiding the most severe logic shielding area at the very end.

[0062] Combination Figure 4 As shown, in some examples, if a representative path passes through a certain level of logical node, and the bypass control terminal of that node is clamped with a very high probability during system operation, such as... Figure 4 In this scenario, the bypass is in a 95% logic 1 state, which severely shields the aging transitions on the representative path from the logic gates. The minor delay variations caused by aging in the preceding circuit cannot be propagated to the end. This phenomenon makes the probability of observable level transitions at the target observation node extremely low. If an aging sensor is placed here or downstream, it may be unable to capture any valid signal for an extended period. To address this, in this embodiment, a transition probability threshold can be preset, for example, 5%. When the logic gate transition probability is lower than the preset threshold, a logic shielding strategy that triggers observability forward shifting of the node is used. This actively moves the observation point, which was originally in a very low observability position, forward along the data flow direction within the range defined by the lower boundary, forcibly bypassing logic gates that cause high-probability shielding, finding a path node that meets the observability requirements, and defining the upper boundary of the candidate observation point. In other words, the predetermined upper boundary of the candidate observation point for this path is dynamically adjusted. Finally, the path nodes that fall within the range between the lower bound of the candidate observation point and the adjusted upper bound of the candidate observation point are selected as the high-quality candidate observation point set.

[0063] In this embodiment, a detection mechanism that performs reverse topology tracing from the end point to the fan-in direction on representative paths actively avoids temporal convergence dead zones. Combined with the statistical data of the logical dynamic jump probability of path nodes, the observation points are moved forward based on the logic shielding strategy, actively bypassing clamping logic gates that are prone to logic shielding effects. This dynamically calculates, defines, and corrects the lower and upper bounds of candidate observation points for each representative path to select more representative candidate observation points. This allows the aging sensor to be placed on highly active preceding path nodes to observe the aging situation, which greatly improves the effective capture hit rate and detection sensitivity of aging anomalies, eliminates monitoring dead zones in the SLM system, achieves comprehensive monitoring, and avoids omissions.

[0064] In some alternative embodiments, step S103 includes: S1031, a mapping relationship is constructed based on the representative path set and the candidate observation point set, wherein the mapping channel between the representative path and the candidate observation point in the mapping relationship represents the cross-coverage relationship; S1032, under the constraints of coverage rate or number of observation points, the target observation node is dynamically selected through a global optimal planning model based on the cross-coverage relationship and the weight score of the representative path.

[0065] In the physical implementation of integrated circuits, due to limitations in chip area, wiring resources, and power consumption budget, SLM systems typically specify a threshold for the absolute number of aging sensors that can be inserted, denoted as a constraint constant. (Observation point number constraint); or conversely, the system specifies a required safe coverage rate, requiring the aging sensor area overhead to be minimized (coverage constraint). In this embodiment, a representative path set with high weights is obtained... and a set of high-quality candidate observation points that have been screened and filtered to avoid detection. Subsequently, the problem of allocating engineering chip resources is abstracted and mapped to the classic global optimization problem in operations research and graph theory. Based on the global optimization theory, the selection set is optimized, and bidirectional conversion between maximum coverage and minimum set coverage is supported.

[0066] Combination Figure 5 As shown, a mathematical mapping model based on a bipartite graph is constructed. In the physical netlist of integrated circuits, an upstream physical node often fans out and converges into multiple downstream timing paths. Figure 5 In the bipartite graph model, the left-hand nodes represent the representative set of paths after dimensionality reduction. Each representative path carries a risk weight. (Weighted scores), the right-hand nodes represent the set of candidate physical observation points after screening. The connection between the left and right nodes represents the cross-over relationship of the physical circuit, i.e., a candidate point on the right. It can radiate and emit connecting lines, covering a subset on the left that contains multiple downstream paths. .

[0067] The system supports bidirectional transformation between maximum coverage and minimum set coverage. When physical resources are limited, i.e., under the constraint of the number of observation points, the system uses the MCP (Maximum Coverage Problem) model to maximize the sum of the covered weights on the left side of the bipartite graph. When a specific safe coverage rate must be guaranteed, i.e., under the coverage rate constraint, the system seamlessly switches to the SCP (Set Cover Problem) model to find the minimum number of nodes on the right side. Both models share the same underlying data structure; only the objective function and constraints need to be interchanged.

[0068] In this embodiment, by establishing a mapping relationship between a representative path set and a candidate observation point set, and using the mapping channel to represent the cross-coverage association between the two, while incorporating the weight score of the representative path, accurate matching and coverage between observation nodes and key time-series paths can be achieved. By abstracting the problem into a maximum coverage or minimum set coverage model, the system systematically seeks to obtain the maximum coverage under a given constraint of the number of observation points, or to obtain the minimum set coverage under a given coverage constraint. Whether it is to maximize monitoring by strictly adhering to the minimum silicon wafer area budget, or to achieve a safety coverage baseline with the lowest cost, it can provide higher cost performance, and the two can be seamlessly switched. Finally, based on the global optimal planning model, the target observation node is dynamically and accurately selected with only sensor pins, ensuring coverage of the entire chip aging path under strict hardware constraints, and improving the rationality, globality, and optimal adaptability of the target observation node.

[0069] In some optional embodiments, step S1032 specifically includes: Based on the cross-coverage relationship, the sum of the weight scores of each representative path mapped by the candidate observation point is obtained; Based on the sum of the weight scores of each representative path mapped by the candidate observation point, and under the constraint of the number of observation points, the candidate node corresponding to the largest sum of weights is selected as the target observation node through the global optimal planning model; or Based on the sum of the weight scores of each representative path mapped to the candidate observation point, and under the constraint of coverage, the candidate node with the largest and smallest sum of weight scores of each representative path mapped to the candidate observation point is selected as the target observation node by the global optimal planning model.

[0070] In this embodiment, before finding the optimal solution using the global optimal planning model, the problem is described and transformed as follows: Known representative path set Among them, each representative path The weighted score representing the time-series risk is: .

[0071] Known set of candidate observation points From a graph theory perspective, a candidate observation point It can cover a subset containing multiple downstream paths. .

[0072] Mode A (Resource-Constrained: MCP Model): Strictly satisfying the maximum selection requirement Under the constraint of the number of observation points, intelligent combination The goal is to find points that maximize the total weight of the covered path.

[0073] Mode B (Goal-Oriented: SCP Model): This mode seeks to minimize the number of observation points required (minimizing set size) while ensuring coverage of all or a specific proportion of high-risk paths (coverage constraint). Since both models originate from the same source, the same algorithm engine can be seamlessly switched between them.

[0074] In some examples, based on the absolute optimization solution of exact mathematical programming, taking the integer linear programming (ILP) solution as an example, the theoretically absolute optimal solution can be obtained by constructing an optimization space through rigorous linear algebraic equations. Two key sets of Boolean (0 or 1) decision variables are introduced: For all candidate points .like The representative decided on the Sensors are inserted at each physical node. For all representative paths .like Representing the Each path is monitored and covered by at least one selected sensor. For Maximum Coverage Pattern (MCP), the following globally optimal planning model is constructed: The objective function is to maximize the sum of the weights of all successfully covered representative paths. (2) The constraints include: First constraint (area / quantity hard constraint): (3) Second constraint (overriding logic mapping constraint): (4) It should be noted that if converted to the Minimum Set Coverage (SCP) mode, the objective function only needs to be modified to minimize the total number of selected points. And change the constraint to a covering variable for all paths. The required security coverage threshold must be met.

[0075] Furthermore, the above equations (2) to (4) are solved precisely by the solver, and finally a set of selected points representing the globally optimal placement scheme is output, that is, the set of target observation nodes.

[0076] In other examples, when dealing with extremely large SoCs with tens of millions of equivalent gate logic, the time complexity of accurate solution can explode exponentially. In such cases, heuristic algorithms can be used for optimization. This embodiment uses a greedy algorithm to execute the MCP objective as an example, and the execution flow is as follows: Create a set of selected observation points and a set of covered paths. Traverse each candidate observation point. Check the set of paths it can cover. Remove paths that already exist in the covered path set, and assign weight scores to the remaining new paths. The scores are accumulated to obtain the current real-time contribution score for that point. The candidate observation point with the highest current real-time contribution score is selected and added to the set of selected observation points. All new paths covered by that point are merged into the set of covered paths. These new paths will not have any weight in future scoring, thus preventing the redundant stacking of aging sensors. A check is then performed to determine if the number of points has reached the upper limit. (Or determine if the path is fully covered in SCP mode). If not, clear the previous round's score cache and jump back to step two to traverse each candidate observation point i, performing iterative loops. The algorithm will eventually obtain a set of optimal observation points through layers of filtering, which is the set of target observation nodes.

[0077] In this embodiment, by summing the weight scores of the representative paths corresponding to each candidate observation point, two constraint optimization logics are constructed based on the importance weight of the path. One logic selects the candidate node with the largest total path weight as the target observation node, given a limited number of observation points, using a globally optimal planning model. The other logic, under the constraint of meeting full path coverage requirements, optimizes the combination of candidate nodes that maximizes the total weight and minimizes the number of observation points. This quantifies the contribution of each candidate observation point to the coverage of key representative paths, prioritizes the coverage of high-importance paths based on weight scores, and achieves globally optimal node deployment under both observation point number and coverage constraints. This avoids redundant observation node deployment, saves hardware monitoring resources, and ensures complete and effective coverage of high-weight time-series paths and aging-sensitive paths, improving the quantification, rationality, and resource utilization efficiency of on-chip observation node selection.

[0078] According to another aspect of the embodiments of this application, this application provides an on-chip aging monitoring point selection device, such as... Figure 6 As shown, the device includes: The path filtering module M601 is used to perform dimensionality reduction and path weight evaluation on the multi-dimensional gate features of each path, and select multiple representative paths to construct a representative path set. The node tracking module M602 is used to perform reverse topology tracking from the end of the representative path to the fan-in direction based on the logic masking strategy of delay boundary constraints and trigger node observability forward movement, and to identify multiple candidate observation points from each of the representative paths and construct a candidate observation point set. The target node selection module M603 is used to construct a mapping relationship based on the representative path set and the candidate observation point set, and dynamically select target observation nodes by combining path weights under the constraints of coverage or the number of observation points and through a global optimal planning model.

[0079] It should be noted that in this embodiment, the path filtering module M601 can be used to execute step S201 in this application embodiment, the node tracking module M602 in this embodiment can be used to execute step S202 in this application embodiment, and the target node selection module M603 in this embodiment can be used to execute step S203 in this application embodiment.

[0080] Optionally, the path filtering module M601 described above is specifically used for: scanning the chip netlist using a timing margin analysis algorithm to filter critical paths with timing margins less than a preset safety threshold; extracting multi-dimensional gate-level features for each critical path, including extracting at least one of topological features, timing and parameter features, temperature sensitivity features, dynamic behavior features, and physical space features; constructing feature vectors corresponding to each critical path based on the extracted multi-dimensional gate-level features, and concatenating the feature vectors of all critical paths to construct a path feature matrix; performing mathematical dimensionality reduction on the path feature matrix, and weighting the processed paths to evaluate the weights, filtering multiple representative paths, and constructing the representative path set.

[0081] Optionally, the steps performed by the path filtering module M601, namely: performing mathematical dimensionality reduction on the path feature matrix, evaluating the weights of the processed paths, filtering multiple representative paths, and constructing the representative path set, include: extracting the dominant mutation direction of the path feature matrix in the feature space using a first feature decomposition algorithm; performing principal component decomposition in the feature space based on the dominant mutation direction using a second feature decomposition algorithm to remove redundant paths; projecting the feature vectors of the remaining paths onto the dominant mutation subspace extracted by the singular value decomposition algorithm, and filtering the path corresponding to the feature combination containing the largest independent information content as the representative path; evaluating the weights of each representative path, filtering the representative paths according to the weights, and constructing the representative path set based on the remaining representative paths.

[0082] Optionally, the steps performed by the path filtering module M601, namely: weighting each representative path, filtering the representative paths according to their weights, and constructing the representative path set based on the remaining representative paths, include: calculating the weight score of each representative path in the representative path set using a preset weighting evaluation model based on the establishment time leeway of the representative paths, wherein the weight score represents the temporal risk level of the path; prioritizing each representative path based on its weight score; filtering the representative paths in the representative path set based on their priority; and constructing the representative path set based on the remaining representative paths according to their weight priority.

[0083] Optionally, the node tracking module M602 described above is specifically used for: performing reverse topology tracing from the end of the representative path towards the fan-in direction, calculating the total absolute delay time traversed by the reverse topology tracing; determining the delay boundary constraint based on the total absolute delay time, the delay boundary constraint including the lower bound and upper bound of the candidate observation points of the path; constructing the candidate observation point set by constructing the path nodes falling within the range of the lower bound and the upper bound of the candidate observation points, wherein the candidate observation point set includes the path nodes selected within the range of the lower bound and the upper bound of the candidate observation points when the logic masking strategy is triggered, the logic masking strategy being triggered when the logic gate transition probability is lower than a preset transition probability threshold.

[0084] Optionally, the target node selection module M603 is specifically used to: construct a mapping relationship based on the representative path set and the candidate observation point set, wherein the mapping channel between the representative path and the candidate observation point in the mapping relationship represents a cross-coverage relationship; and dynamically select target observation nodes through a global optimal planning model based on the cross-coverage relationship and the weight score of the representative path under the constraint of coverage rate or number of observation points.

[0085] Optionally, the steps performed by the target node selection module M603 above: under the constraints of coverage or the number of observation points, dynamically selecting the target observation node based on the cross-coverage relationship and the weight scores of the representative paths through a global optimal planning model includes: obtaining the sum of the weight scores of each representative path mapped by the candidate observation point based on the cross-coverage relationship; selecting the candidate node corresponding to the largest sum of weights as the target observation node through the global optimal planning model based on the sum of weight scores of each representative path mapped by the candidate observation point, while satisfying the constraints of the number of observation points; or selecting the candidate node with the largest and smallest sum of weight scores of each representative path mapped by the candidate observation point as the target observation node based on the sum of weight scores of each representative path mapped by the candidate observation point, while satisfying the coverage constraints through the global optimal planning model.

[0086] It should be noted that the examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the content disclosed in the above embodiments. It should also be noted that the above modules, as part of the system, can run in the hardware environment of the on-chip aging monitoring point selection device, and can be implemented in software or hardware.

[0087] According to another aspect of the embodiments of this application, this application provides a computer device, such as... Figure 7As shown, it includes a memory 701, a processor 703, a communication interface 705, and a communication bus 707. The memory 701 stores a computer program that can run on the processor 703. The memory 701 and the processor 703 communicate through the communication interface 705 and the communication bus 707. When the processor 703 executes the computer program, it implements the steps of the above-mentioned on-chip aging monitoring point selection method.

[0088] The memory and processor in the aforementioned computer equipment communicate with each other via a communication bus and a communication interface. The communication bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0089] The aforementioned memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0090] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0091] According to another aspect of the embodiments of this application, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps of the on-chip aging monitoring point selection method in any of the above embodiments.

[0092] Optionally, in embodiments of this application, the computer-readable medium is configured to store program code for the processor to perform the steps of the on-chip aging monitoring point selection method described in the above embodiments.

[0093] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof. For software implementation, the techniques described herein can be implemented by units that perform the functions described herein. Software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0094] It should be noted that, in this document, relational terms such as "first," "second," etc., are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprises a…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0095] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for selecting on-chip aging monitoring points, characterized in that, The method includes: Dimensionality reduction and path weight evaluation are performed on the multi-dimensional gate features of each path, and multiple representative paths are selected to construct a representative path set; Based on the logical masking strategy of delay boundary constraints and forward shift of trigger node observability, reverse topology tracing is performed from the end of the representative path in the inward direction, and multiple candidate observation points are identified from each of the representative paths and a candidate observation point set is constructed. A mapping relationship is constructed based on the representative path set and the candidate observation point set. Under the constraints of coverage or the number of observation points, the target observation node is dynamically selected by combining the path weight through a global optimal planning model. The process of dimensionality reduction and path weight evaluation of multi-dimensional gate-level features for each path, and selection of multiple representative paths to construct a representative path set, includes: scanning the chip netlist using a timing margin analysis algorithm to screen critical paths with timing margins less than a preset safety threshold; extracting multi-dimensional gate-level features for each critical path, including extracting at least one of topological features, timing and parameter features, temperature sensitivity features, dynamic behavior features, and physical space features; constructing feature vectors corresponding to each critical path based on the extracted multi-dimensional gate-level features, and concatenating the feature vectors of all critical paths to construct a path feature matrix; performing mathematical dimensionality reduction on the path feature matrix, and evaluating the weights of the processed paths to select multiple representative paths and construct the representative path set. The step of performing mathematical dimensionality reduction on the path feature matrix, evaluating the weights of the processed paths, selecting multiple representative paths, and constructing the representative path set includes: extracting the dominant mutation direction of the path feature matrix in the feature space using a first feature decomposition algorithm; performing principal component decomposition in the feature space based on the dominant mutation direction using a second feature decomposition algorithm to remove redundant paths; projecting the feature vectors of the remaining paths onto the dominant mutation subspace extracted by the singular value decomposition algorithm, and selecting the path corresponding to the feature combination containing the largest independent information content as the representative path; evaluating the weights of each representative path, selecting the representative paths according to the weights, and constructing the representative path set based on the remaining representative paths. The step of weighting and evaluating each representative path, filtering the representative paths according to their weights, and constructing the representative path set based on the remaining representative paths includes: calculating the weight score of each representative path in the representative path set using a preset weighting evaluation model based on the establishment time leeway of the representative paths, where the weight score represents the temporal risk level of the path; prioritizing each representative path based on its weight score; filtering the representative paths in the representative path set based on their priority; and constructing the representative path set based on the remaining representative paths according to their weight priority.

2. The method for selecting on-chip aging monitoring points according to claim 1, characterized in that, The logical masking strategy based on delay boundary constraints and forward shifting of trigger node observability performs reverse topology tracing from the end of the representative path towards the fan-in direction, identifies multiple candidate observation points from each representative path, and constructs a candidate observation point set, including: Perform reverse topology tracing from the end of the representative path toward the fan-in direction, and calculate the total absolute delay time traversed by the reverse topology tracing. The delay boundary constraint is determined based on the total absolute delay time, and the delay boundary constraint includes a lower bound and an upper bound for candidate observation points of the path; The candidate observation point set is constructed by constructing path nodes that fall within the range of the lower bound and the upper bound of the candidate observation point. The candidate observation point set includes path nodes selected within the range of the lower bound and the upper bound of the candidate observation point when the logic masking strategy is triggered. The logic masking strategy is triggered when the logic gate transition probability is lower than a preset transition probability threshold.

3. The method for selecting on-chip aging monitoring points according to claim 1, characterized in that, The process of constructing a mapping relationship based on the representative path set and the candidate observation point set, and dynamically selecting target observation nodes by combining path weights and a globally optimal planning model under constraints of coverage or the number of observation points, includes: A mapping relationship is constructed based on the representative path set and the candidate observation point set, wherein the mapping channel between the representative path and the candidate observation point in the mapping relationship represents the cross-coverage relationship; Under the constraints of coverage rate or number of observation points, the target observation node is dynamically selected through a global optimal planning model based on the cross-coverage relationship and the weight score of the representative path.

4. The method for selecting on-chip aging monitoring points according to claim 3, characterized in that, Under the constraints of coverage rate or number of observation points, the dynamic selection of target observation nodes based on the cross-coverage relationship and the weight score of the representative path using a global optimal planning model includes: Based on the cross-coverage relationship, the sum of the weight scores of each representative path mapped by the candidate observation point is obtained; Based on the sum of the weight scores of each representative path mapped by the candidate observation point, and under the constraint of the number of observation points, the candidate observation point corresponding to the largest sum of weights is selected as the target observation node through the global optimal planning model; or Based on the sum of the weight scores of each representative path mapped to the candidate observation point, and under the constraint of coverage, the candidate observation point with the largest and smallest sum of weight scores of each representative path mapped to the candidate observation point is selected as the target observation node by the global optimal planning model.

5. A device for selecting on-chip aging monitoring points, used to implement the method for selecting on-chip aging monitoring points as described in any one of claims 1 to 4, characterized in that, The device includes: The path selection module is used to perform dimensionality reduction and path weight evaluation on the multi-dimensional gate features of each path, and select multiple representative paths to construct a representative path set. The node tracking module is used to perform reverse topology tracking from the end of the representative path to the fan-in direction based on the logical masking strategy of delay boundary constraints and trigger node observability forward movement, and to identify multiple candidate observation points from each of the representative paths and construct a candidate observation point set. The target node selection module is used to construct a mapping relationship based on the representative path set and the candidate observation point set, and dynamically select target observation nodes by combining path weights under the constraints of coverage or the number of observation points and through a global optimal planning model.

6. A computer device, comprising: A processor, a memory, and a network interface, wherein the memory stores machine-readable instructions executable by the processor, characterized in that: when the computer device is running, the processor communicates with the memory via the network interface, and the processor executes the machine-readable instructions to perform the steps of the on-chip aging monitoring point selection method as described in any one of claims 1 to 4.

7. A computer-readable medium having processor-executable non-volatile program code, characterized in that, The program code causes the processor to execute the steps of the on-chip aging monitoring point selection method according to any one of claims 1 to 4.

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