A method for cooperative control of a distributed digital quantum computing system

Abstract

The application relates to the technical field of quantum computing, and provides a cooperative control method of a distributed digital quantum computing system. A classical bit signal is obtained by each computing node, is coupled after dual mapping, and is used to generate a one-dimensional vector as a quantum state vector based on an Ising spin model to obtain a digital quantum bit; the digital quantum bit is encoded into a logical quantum bit based on a surface code, and a quantum bit measurement stabilizer is used to detect errors; a lattice merging or splitting operation is performed to realize elastic stretching; the computing node carrying the logical quantum bit and a central controller star are interconnected based on a time-sensitive network and a software-defined network architecture; the central controller is cooperatively scheduled, computing tasks are distributed to target computing nodes, and three-dimensional lattice merging or splitting across computing nodes is used to realize expansion or contraction of cross-node logical quantum bits. High-fidelity simulation of a digital quantum bit, fault-tolerant encoding and elastic stretching of a logical quantum bit, and cross-node deterministic cooperative scheduling are realized.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, and more specifically, to a cooperative control method for a distributed digital quantum computing system. Background Technology

[0002] With the rapid development of quantum computing technology, the industry is currently at a critical juncture, transitioning from "Noisy Medium-Scale Quantum Computing (NISQ)" to "Fault-Tolerant Quantum Computing." Despite continuous record-breaking physical quantum hardware, its scalability faces severe challenges due to underlying physical laws. Physical quantum computing directly utilizes microscopic particles such as photons, superconducting circuits, or ions as physical qubits. While leveraging quantum superposition and entanglement to achieve exponential computing power unmatched by classical computers for specific problems, the extreme fragility of quantum states makes them highly susceptible to environmental noise (such as temperature fluctuations and electromagnetic interference), leading to decoherence and computational errors. Furthermore, theoretical limitations such as the Eastin-Knill infeasibility theorem make the construction of multiple logic quantum gates difficult, and quantum error correction requires a large number of physical bits to encode a single logic bit (redundancy ratios have reached as high as 1000:1). This makes the expansion, connection, and entanglement of large-scale physical qubits extremely challenging and presents significant fault-tolerant bottlenecks. In addition, in distributed quantum computing scenarios, issues such as collaborative scheduling among multiple nodes, deterministic guarantees of network transmission, and elastic expansion of logic qubits across nodes also urgently need to be addressed.

[0003] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0004] The purpose of this application is to provide a cooperative control method for a distributed digital quantum computing system, which has the advantages of enabling high-fidelity simulation of digital qubits, fault-tolerant coding and elastic scaling of logical qubits, and deterministic cooperative scheduling across computing nodes.

[0005] In a first aspect, this application provides a cooperative control method for a distributed digital quantum computing system, the system comprising multiple computing nodes and a central controller, including: Each computing node acquires two classical bit signals, couples the two classical bit signals through dual mapping, and generates a one-dimensional vector based on the projection length of the magnetic moment of the spin operator in the principal direction in the Ising spin model. The one-dimensional vector is used as the quantum state vector to obtain the digital quantum bit. Each computing node encodes multiple digital qubits into logical qubits based on a surface code, wherein the surface code consists of a two-dimensional lattice of data qubits and characterization qubits, and the characterization qubits measure the stabilizers between themselves and their neighboring data qubits to detect errors; In response to the computational task requirements, lattice merging or lattice splitting operations are performed on the logical qubits to achieve the elastic contraction or expansion of the logical qubits. Based on an architecture combining time-sensitive networking and software-defined networking, multiple computing nodes carrying the logical qubits are interconnected with the central controller in a star topology. The central controller coordinates the scheduling of each computing node, distributes computing tasks to the target computing node, and expands or shrinks the logical qubits across nodes based on three-dimensional lattice merging or splitting operations.

[0006] Furthermore, the generation of a one-dimensional vector based on the projection length of the magnetic moment of the spin operator in the Ising spin model along the principal direction includes: The longest operator magnetic moment length is defined as 1, and the one-dimensional vector is generated by representing the continuous value from 0 to 1 based on the projection length of the magnetic moment of the spin operator in the principal direction.

[0007] Furthermore, each computing node encodes the multiple digital qubits into logical qubits based on surface codes, including: The data qubits and the characterization qubits are arranged into a two-dimensional lattice, such that the data qubits are in simultaneous eigenstates around each crystal face, and the characterization qubits measure the tetragonal stabilizers of the crystal face at the center of the patch surrounded by the data qubits. All data qubits are prepared as ground state or equal-amplitude superposition state and multiple rounds of characterization measurements are performed to obtain the logical initial state. At the end of the calculation, the logical measurement results are read after error correction. Logical operators based on the boundary definition of a two-dimensional lattice are used to obtain logical qubits with a preset code distance.

[0008] Furthermore, the lattice merging operation includes: An intermediate data qubit is introduced between the encoding crystal planes corresponding to the two logical qubits to be merged. The eigenvalues ​​of the logical operator product of the two logical qubits are inferred by measuring the stabilizer that crosses the boundary. The two encoding crystal planes are merged into a single surface, and the merged logical state is conditionally mapped according to the measurement results.

[0009] Furthermore, the lattice splitting operation includes: In the plane of logic qubits to be split, a row of intermediate data qubits is measured to remove the intermediate data qubits from the lattice, splitting the single code plane into two independent code planes, so that the logic state of the original logic qubits is distributed to the two newly generated logic qubits.

[0010] Furthermore, the method also includes: Using lattice surgery to construct a fault-tolerant logic control gate, the control logic qubit is merged and split with the intermediate logic qubit initialized to an equal amplitude superposition state, and then the intermediate logic qubit is merged and split with the target logic qubit. Multiple rounds of error correction are performed during the merging process to maintain the code distance. Furthermore, a logic single-qubit rotation gate is implemented through state injection. The data qubit corresponding to the quantum state to be injected is subjected to a controlled NOT gate operation with the adjacent characterization qubit. The injected logic qubit is obtained through stabilizer measurement, and the code distance of the logic qubit is extended to the target code distance through a merging operation.

[0011] Furthermore, the architecture based on the combination of time-sensitive networking and software-defined networking interconnects multiple computing nodes carrying the logical qubits with the central controller in a star topology, including: The central controller calculates the explicit path and establishes a mapping relationship between service flow and forwarding cycle; The business flows entering the architecture are identified and filtered, multiple copies are made and sent through multiple paths, and periodic scheduling and forwarding are performed based on the message periodic attributes. Redundancy is eliminated at the exit point to restore the original data packets. The architecture distinguishes bandwidth resources between deterministic and non-deterministic service flows, and schedules idle resources to non-deterministic flows during their idle periods.

[0012] Furthermore, the coordinated scheduling of each computing node through the central controller includes: Receive the registration information of computing nodes and establish a global quantum state mapping table; Dynamically add computing nodes or disable nodes that do not participate in computing based on the computing task requirements; Deregister the faulty node and migrate its digital qubits to other nodes; The computational task is broken down and the results are summarized.

[0013] Furthermore, the expansion or contraction of cross-node logical qubits based on cross-computing node 3D lattice merging or splitting operations includes: The two-dimensional lattice corresponding to the logical qubit is stacked, and interlayer digital qubits are arranged between adjacent stacked layers, with the interlayer digital qubits surrounding the entire edge of the logical qubit. Cross-layer lattice merging is achieved by turning off the stabilizers at the edge of the surface to be merged and turning on the interlayer stabilizers using the interlayer digital qubits; or cross-layer lattice splitting is achieved by measuring the interlayer data qubits to complete the expansion or contraction of logical qubits across computing nodes.

[0014] Furthermore, the computing node uses carry-and-join representation to store quantum states, performs local quantum state preparation and local quantum gate operations, receives instructions from the central controller and reports local status and calculation results, and executes lattice merging and lattice splitting operation instructions issued by the central controller.

[0015] As can be seen from the above, the cooperative control method for a distributed digital quantum computing system provided in this application solves the problems of difficult manipulation of physical quantum bits, limited expansion, and lack of deterministic guarantees in multi-node cooperative computing by generating digital qubits based on the Ising spin model, surface code fault-tolerant encoding, lattice operation elastic scaling, deterministic network interconnection, and unified cooperative scheduling by a central controller. It has the advantages of being able to realize high-fidelity simulation of digital qubits, fault-tolerant encoding and elastic scaling of logical qubits, and deterministic cooperative scheduling across computing nodes. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the steps of the collaborative control method for a distributed digital quantum computing system disclosed in an embodiment of the present invention. Figure 2 This is a schematic diagram of qubits arranged in a lattice as disclosed in an embodiment of the present invention; Figure 3 This is a schematic diagram of the quantum bit representation of the surface code disclosed in an embodiment of the present invention; Figure 4 This is a schematic diagram of the physical quantum bit arrangement of lattice merging disclosed in an embodiment of the present invention; Figure 5 This is a schematic diagram of the lattice-splitting quantum bit arrangement disclosed in an embodiment of the present invention; Figure 6 This is a schematic diagram of the CNOT-operated quantum bit layout with lattice surgery disclosed in an embodiment of the present invention; Figure 7 This is a schematic diagram of injecting an arbitrary state |Ψ〉 = α|0〉 + β|1〉 into a curved surface, as disclosed in an embodiment of the present invention; wherein, Figure 7 (a) in the figure is a schematic diagram of the initial state of injecting arbitrary state into the surface in this embodiment; Figure 7 (b) in the figure is a schematic diagram of the state after performing a controlled NOT gate operation on the pink qubit in this embodiment; Figure 7In this embodiment, (c) represents the logical |Ψ| with a distance of 3 obtained after measuring the stabilizer. A schematic diagram of a dynamic surface; Figure 7 In this embodiment, (d) represents the additional blue qubit prepared as |0. A schematic diagram of the state; Figure 7 In this embodiment, (e) represents the merging of the blue qubit into the original logical qubit, resulting in a logical |Ψ with a distance of 4. A schematic diagram of a dynamic surface; Figure 8 This is a schematic diagram of the deterministic network architecture disclosed in the embodiments of the present invention; Figure 9 This is a schematic diagram of the deterministic forwarding process disclosed in an embodiment of the present invention; Figure 10 This is a schematic diagram of the star topology of the central controller disclosed in an embodiment of the present invention; Figure 11 This is a schematic diagram of the three-dimensional layout of qubits disclosed in an embodiment of the present invention; Figure 12 This is a configuration diagram of digital qubits disclosed in an embodiment of the present invention; Figure 12 (a) is a schematic diagram of the two-dimensional quantum bit lattice stacked layer in this embodiment; Figure 12 (b) in the figure is a schematic diagram of the interlayer quantum bit configuration in this embodiment; Figure 12 (c) in the figure is an enlarged schematic diagram of the interlayer data quantum bit connectivity in this embodiment; Figure 12 (d) in this embodiment is a schematic diagram of merging logic qubits from different layers; Figure 13 This is a schematic diagram of the three-dimensional placement structure of the logic qubits disclosed in an embodiment of the present invention; Figure 14 This is based on the embodiments of the present invention. Figure 13 A schematic diagram of performing general logic controlled NOT gate operations on a three-dimensional placement structure; Figure 14 (a) is a schematic diagram of the spatial layout of the two general logic NOT gates in the three-dimensional lattice in this embodiment; Figure 14 (b) is a schematic diagram of CNOT operation implemented by lattice surgery in this embodiment. Detailed Implementation

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these embodiments belong; the terminology used herein and in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit these embodiments; the terms "comprising" and "having," and any variations thereof, in the specification of these embodiments and the foregoing drawings, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification of these embodiments and the foregoing drawings are used to distinguish different objects, not to describe a particular order.

[0019] The implementation details of the technical solution in this embodiment are described in detail below: This application proposes a cooperative control method for a distributed digital quantum computing system, the system comprising multiple computing nodes and a central controller, such as... Figure 1 As shown, the method includes: S101, each computing node acquires two classical bit signals, couples the two classical bit signals through dual mapping, and generates a one-dimensional vector based on the projection length of the magnetic moment of the spin operator in the principal direction in the Ising spin model. The one-dimensional vector is used as the quantum state vector to obtain the digital quantum bit.

[0020] In this embodiment, each computing node acts as an independent classical computing unit, responsible for simulating a certain number of digital qubits. Specifically, addressing the difficulties of physical quantum computing and the fault tolerance challenges of multi-logic qubit expansion, logical qubits are prepared in a digital qubit manner to facilitate qubit manipulation. Each computing node acquires the classical bit signals output from two classical computing circuits, and prepares a classical bit based on each circuit as the fundamental signal for single-qubit simulation. The two classical bits are coupled through dual mapping to form a commutation relationship, simulating a random 1-bit physical qubit signal. Furthermore, the Ising spin model is introduced, where a spin operator represents a simulated physical bit signal. A 1-dimensional vector in 0-1 space is generated based on the projection length of the magnetic moment of the spin operator in the principal direction. Using the generated 1-dimensional vector as a simulated quantum state vector, the simulation of one physical qubit, i.e., one digital qubit, can be realized. Therefore, digital qubits generated based on classical computer simulations completely avoid physical environment noise and decoherence problems, can execute complex quantum algorithms with an extremely low error rate, do not require harsh physical environments such as extremely low temperatures or ultra-high vacuum, and have good programmability and reproducibility.

[0021] Furthermore, in S101, the generation of a one-dimensional vector based on the projection length of the magnetic moment of the spin operator in the principal direction in the Ising spin model includes: defining the longest operator magnetic moment length as 1, and generating the one-dimensional vector by representing a continuous value from 0 to 1 according to the projection length of the magnetic moment of the spin operator in the principal direction.

[0022] Specifically, when generating a one-dimensional vector based on the projected length of the magnetic moment of the spin operator in the principal direction in the Ising spin model, the longest operator magnetic moment length is defined as 1. Since operators with different spin directions have different angles with the principal direction, their projected lengths in the principal direction are different. The length of the projected length of the magnetic moment of the spin operator in the principal direction can represent a continuous value from 0 to 1, generating a one-dimensional vector in 0-1 space. This one-dimensional vector serves as the simulated quantum state vector, with its components taking values ​​in the continuous interval from 0 to 1. This allows for accurate characterization of the superposition state of digital qubits, achieving high-fidelity simulation of physical qubits based on classical computing resources.

[0023] S102, each computing node encodes multiple digital qubits into logical qubits based on a surface code, wherein the surface code consists of a two-dimensional lattice composed of data qubits and characterization qubits, and the characterization qubits measure the stabilizers between themselves and their neighboring data qubits to detect errors.

[0024] In this embodiment, each computing node encodes multiple digital qubits into logical qubits based on surface codes.

[0025] Surface codes use a two-dimensional canonical lattice composed of entangled qubits to provide the basis for defining logical qubits. This lattice consists of two types of qubits: data qubits and characterization qubits. Characterization qubits interact repeatedly and frequently with neighboring data qubits and are measured to detect errors. Data qubits are measured at a lower frequency and are used only for computation. Figure 2 The diagram shown illustrates the arrangement of qubits into a lattice according to this embodiment. Large dots represent data qubits, while small dots represent characterizing qubits; the lines in the diagram are for visual aids and do not represent any physical interactions or structures. Figure 2 This represents a portion of the basic lattice structure of the surface code. Data qubits are shown as larger, and characterization qubits are shown as smaller. The label "A" indicates a crystal plane, and "B" indicates a lattice plane.

[0026] The physical X or Z operations of the data qubits along the Z or X boundaries define each logical X or Z operator, respectively. One bit of logical information is encoded in the logical qubit at code distance d. The data qubits are simultaneously in eigenstates around each facet, i.e., around the Pauli-Z operator around each crystal facet (e.g., A in the figure) and the Pauli-X operator around each lattice point (e.g., B in the figure). That is, for all crystal faces F and lattice points V, the stabilizer of the system is represented as... (1) Where {i∈F} and {j∈V} are the data qubits of each crystal plane and lattice plane, respectively.

[0027] Characterizing qubits involves maintaining the lattice in the simultaneous eigenstates of these operators to accommodate potential qubit and measurement errors. To this end, a characterization qubit is placed at the center of each patch surrounded by data qubits, and the tetragonal stabilizer of that patch is measured in each round of error correction. Thus, by utilizing the topological encoding properties of surface codes, the characterization qubit provides continuous fault-tolerant protection for the data qubits, ensuring the reliability of the logic qubits in subsequent operations.

[0028] Further, in S102, each computing node encodes multiple digital qubits into logical qubits based on surface codes, including: arranging the data qubits and the characterization qubits into a two-dimensional lattice, such that the data qubits are in simultaneous eigenstates around each crystal face, and the characterization qubits measure the tetragonal stabilizers of the crystal face at the center of the patch surrounded by the data qubits; preparing all data qubits into ground state or equal-amplitude superposition state and performing multiple rounds of characterization measurements to obtain the logical initial state; reading the logical measurement results after error correction at the end of the computation; defining logical operation operators based on the boundaries of the two-dimensional lattice to obtain logical qubits with a preset code distance.

[0029] Specifically, each computing node arranges data qubits and characterization qubits into a two-dimensional lattice. The data qubits are in simultaneous eigenstates around each crystal plane, i.e., around each crystal plane (e.g., ...). Figure 2 Pauli-Z operator in A) and each lattice point (e.g. Figure 2 The Pauli-X operator surrounding B) refers to the plane for all crystal planes F and lattice points V. It represents the tetragonal stabilizer of the measurement plane at the center of a patch surrounded by data qubits. Through repeated and frequent interactions with neighboring data qubits, it continuously detects and corrects possible qubit and measurement errors, thereby maintaining the lattice in a stable eigenstate while simultaneously operating as a stabilizer operator, providing a fault-tolerant basis for the encoding of logic qubits.

[0030] like Figure 3 The diagram shown is a schematic representation of the quantum bit representation of the surface code in this embodiment. Figure 3As shown by the red boundary (X) L This indicates that the Pauli-X gate is in an eigenstate, Z L (This indicates that the Pauli-Z gate is in an eigenstate), introducing one degree of freedom, so the entire lattice can be used to encode one logical qubit.

[0031] Using surface codes, in order to prepare an initial ground state Prepare all data qubits as the ground state, i.e., |0 The state is then characterized through multiple rounds of measurements to ensure fault tolerance. Similarly, a superposition of equal amplitude states... This is achieved by preparing all qubits into a superposition state of equal amplitude, i.e. The initial state of the logical qubit is prepared by performing multiple rounds of characterization measurements. At the end of the computation, the value of the logical qubit is read by measuring all qubits in the measurement substrate. These measurements are then error-corrected, and the logical measurement results are read from the parity check of the measured logical operator. Thus, fault-tolerant preparation of the initial state of the logical qubit is achieved through the preparation of the ground state or equal-amplitude superposition state and multiple rounds of characterization measurements; at the end of the computation, the operation result of the logical qubit is accurately read through the error-corrected logical measurements.

[0032] Furthermore, in this embodiment, the physical X or Z operations of the data qubits along the Z or X boundaries define each logical X or Z operator. One bit of logical information is encoded in a logical qubit with a preset code distance. The surface code employs a method of introducing one degree of freedom, allowing the entire lattice to encode one logical qubit. By defining logical operation operators based on the boundaries of a two-dimensional lattice, logical qubits with preset code distances are obtained, enabling the logical qubits to possess error correction capabilities matching the preset code distance. This ensures that the logical qubits maintain sufficient fault tolerance performance during subsequent lattice merging, lattice splitting, and general logic gate operations.

[0033] S103, in response to the computing task requirements, perform lattice merging or lattice splitting operations on the logical qubits to achieve elastic shrinkage or expansion of the logical qubits; In this embodiment, similar to surface surgery in geometric topology, the lattice points of the surface code are "merged" and "split" by introducing discontinuous deformation of the lattice, thereby achieving the shrinking and expansion of logical qubits. Responding to computational task demands, when the computational task scale decreases or computational resources need to be consolidated, a lattice merging operation is performed on the logical qubits, merging two logical qubits into one, achieving the shrinking of the logical qubits; when the computational task scale increases or computational resources need to be expanded, a lattice splitting operation is performed on the logical qubits, splitting one logical qubit into two, achieving the expansion of the logical qubits. Thus, through the flexible combination of lattice merging and lattice splitting, the digital quantum computing system can dynamically adjust the number of logical qubits according to the actual computational task requirements, achieving elastic scaling of qubits.

[0034] Furthermore, in this embodiment, similar to surface surgery in geometric topology, the contraction and expansion of logical qubits are achieved by introducing discontinuous deformation of the lattice to "merge" and "split" the lattice points of the surface code. Lattice Merging: The encoding of a logical qubit is represented by a plane, called the code surface of that logical qubit. Merging two code surfaces into a single surface is achieved by measuring the stabilizers at the surface boundaries during the error correction cycle. Lattice Splitting: Splitting the code surface is the opposite of lattice merging. By cutting the joint stabilizers, additional code surface boundaries are formed, turning one code surface into two.

[0035] Furthermore, the lattice merging operation includes: introducing an intermediate data qubit between the encoded crystal planes corresponding to the two logical qubits to be merged; inferring the eigenvalue of the logical operator product of the two logical qubits by measuring the stabilizer that crosses the boundary; merging the two encoded crystal planes into a single surface; and performing conditional mapping on the merged logical state based on the measurement results.

[0036] Specifically, in this embodiment, the encoding of a logical qubit is represented by a plane, called the code surface of that logical qubit. Two code surfaces are merged into a single surface, achieved by measuring the stabilizers at the surface boundaries during the error correction cycle. Specifically, as... Figure 4 The diagram shows the physical qubit arrangement for lattice merging in this embodiment. The left and right continuous surfaces encode independent logic qubits. The pink qubits constitute the intermediate qubit line for the merging operation. There are two logic surface code planes, each of which is stable and encodes one logic qubit, and a row of uninitialized digital qubits in the "middle". This is achieved through a pre-prepared state... The intermediate data qubits are then processed through multiple rounds of error correction, merging the two systems by treating the entire system as a single data plane. Using reliable X-stabilizer measurements across the boundary, the eigenvalues ​​of these X-stabilizer products can be reliably inferred, which is equivalent to the two logical qubit operators X. L X L Therefore, the above merging process is equivalent to measuring X. L X L This embodiment calls this merging operation lattice merging: the boundaries of two surfaces are merged together. The merged lattice may have a series of incorrect characterization measurements at the junction, which can be corrected by parity checking to keep the logic qubits in the correct state. X is measured on the two original qubits. L X L This action produces two results. First, the post-measurement state is nondeterministic and dependent on the measurement result. Second, the curved surface now has only one qubit degree of freedom, therefore the original logical qubit state needs to be mapped to the merged new logical qubit state. Consider... and The result of the merge is for X L X L The measurement; if performed on two different qubits, the state after the measurement will be as shown in equation (2), where M is the result of the logical measurement, i.e., 0 or 1. To understand which corrections need to be applied, equation (2) is expanded and rewritten as follows: (2) in , M It is the result of a logical measurement, i.e., 0 or 1.

[0037] To understand which corrections need to be applied, formula (2) is expanded and rewritten as follows: (3) Further consideration is needed regarding mapping to the merged individual qubits. (Logic) L The state of the new surface will be the merged even-parity state Z. L Operators are the primitive simple product Z. L Operators. Logic L It will be the odd parity state Z of the original product L Operators. The combination of parity states will differ depending on the merged measurement results; therefore, an X-based... L X L The conditional mapping of the measurement results is as follows: (4) If this embodiment now uses symbols Describing the merging operation, using equation (3) and this mapping, this embodiment obtains... (5) Similar to the truth table in classical computation, the truth table for qubit merging operations has the following states: L or state L It is an XOR: (6) Based on the truth table of the above merging operation, the lattice merging operation is completed. With two surface code logic qubits as input, the merged result is a single surface code logic qubit, and the logic qubit is shrunk.

[0038] Furthermore, the lattice splitting operation includes: measuring a row of intermediate data qubits in the plane of logic qubits to be split to remove the intermediate data qubits from the lattice, dividing a single code plane into two independent code planes, so that the logic state of the original logic qubits is distributed to the two newly generated logic qubits.

[0039] Specifically, lattice splitting is the reverse operation of merging. A single logic qubit plane is divided in half by a row of measurements that remove data qubits from the lattice. This leaves two separately stable planes at the end of the operation.

[0040] like Figure 5 The diagram shows a schematic of the lattice-split qubit arrangement in this embodiment. The pink qubit is measured in the X substrate, leaving two independent and stable logic qubit surfaces. The middle qubit row is measured in the Pauli-X substrate. This is the same as the merged configuration, in which case the marked qubit is the middle qubit (the pink marked dot), initialized to... State. Similar to merging, the effect of the splitting operation can be seen through its influence on the logic operators. After the splitting operation, i.e., after measuring the intermediate qubit, the original surface splits into two surfaces; after d rounds of error correction (d being the code distance), the two surfaces stabilize. Unlike merging, splitting can change the code distance: symmetrically splitting a square surface halves the code distance. To obtain two surfaces with a distance of d, this embodiment needs to start with a surface of size d×2d (this surface also has a code distance d). After the splitting is complete, this embodiment can examine the new lattice plane operator at the connection point. The splitting operation splits a surface into two independent surfaces, and the logic states are distributed on these two surfaces: they are defined by referencing a single lattice logic operator, rather than their own independent operators, meaning the logic X operators of these two surfaces will be in an entangled state.

[0041] The splitting process preserves the logic Z operator but divides the logic X into two qubits, provided that the necessary modifications or logic operator definitions are arranged, as follows: (7) By swapping X and Z in the above parameters, this embodiment can obtain a coarse split result. This method retains the logical X operator but splits the logical Z, as shown below: (8) Similar to the merging operation, the splitting operation is not a unitary transformation because the number of digital qubits is not preserved. However, unlike the merging case, no information at the logical level is lost: the original state of a single qubit can be logically recovered by performing a reverse merging operation after the split. The splitting process distributes the state to two logical qubits, splitting one logical qubit into two logical qubits, thus expanding the logical qubit size.

[0042] Furthermore, the method further includes constructing a fault-tolerant logic-controlled NOT gate using lattice manipulation. Further, the method further includes: constructing a fault-tolerant logic-controlled NOT gate using lattice manipulation, merging and then splitting the control logic qubit with an intermediate logic qubit initialized to an equal-amplitude superposition state, then merging and then splitting the intermediate logic qubit with the target logic qubit, performing multiple rounds of error correction during the merging process to maintain code distance; Furthermore, a logic single-qubit rotation gate is implemented through state injection. The data qubit corresponding to the quantum state to be injected is subjected to a controlled NOT gate operation with the adjacent characterization qubit. The injected logic qubit is obtained through stabilizer measurement, and the code distance of the logic qubit is extended to the target code distance through a merging operation.

[0043] Specifically, in this embodiment, based on the splitting and merging of surface codes, a universal logic quantum gate operation can be realized by constructing a set containing a logic CNOT gate and arbitrary logic single-qubit rotations (through state injection). For example... Figure 6 The diagram shows a schematic of the CNOT-operated qubit layout with lattice manipulation in this embodiment, where the control state (C) and target state (T) surfaces interact through merging and splitting with the intermediate state surface (INT). This embodiment begins with two logical qubits at a distance d, which are: Control state: (9) Target state: (10) There is also an intermediate logical qubit surface with a distance of d, initialized to logical . The state (i.e., the equal-amplitude superposition state) and the two physical qubit stripes, the former being both The second one is in the state. State. First, merge surfaces C and INT. After merging, define the logical state, in which a single surface is generated: (11) Where M is Z L Z L The measurement result operator performs the operation during the merging process. If M is even, the basis of the qubit is redefined by phase flipping, resulting in... (12) To achieve full fault tolerance, d rounds of error correction are performed to achieve the merging operation; the code distance after merging remains d. Then, the new surface is smoothly split back into the original two surfaces, and the qubits split in the X basis are measured. Logical operator X L The redefinition or surface modification yields two new surface states. (13) The code distance between the two qubits is also d, and this step also requires d rounds of error correction.

[0044] Then merge the INT and T surfaces: (14) Here, M′ again represents the merged measurement result, and we have redefined the logic state that depends on the merged measurement result. This operation also requires d rounds of error correction, ultimately leaving two logic qubits with a distance of d. The result of this operation is a fully reversible CNOT operation. Through multiple error corrections, fault tolerance can be maintained at all times, and during this process, the code distance of any logic surface does not fall below d. Thus, a fault-tolerant unitary NOT gate CNOT operation has been constructed.

[0045] Furthermore, this embodiment implements a single-qubit logic gate through state injection. State injection allows both state preparation and arbitrary single-qubit rotation. Arbitrary rotation of the surface code requires the use of an auxiliary state. A CNOT operation is performed between the auxiliary qubit and the logic qubit to realize a rotation gate on the logic qubit.

[0046] like Figure 7 As shown, this embodiment will use arbitrary states. A schematic diagram of the injected surface. First, prepare a logic qubit surface with a distance of 3. Except for one data qubit, all qubits are in the same position. The remaining qubits are the arbitrary states to be injected. A controlled-NOT (CNOT) operation is performed between this qubit and the representation qubits above and below it. These representation qubits are then swapped with the data qubit immediately above or below them, forming a three-qubit state. ,like Figure 7 (b) is then used to stabilize the surface and obtain the logical state. Logical qubits with a distance of 3 on the surface, such as Figure 7 (c) Additional physical qubits are prepared as... state, such as Figure 7 The (d) in the original logical qubit is then merged into the logical state to obtain the logical state. Logical qubits with a distance of 4 on the surface, such as Figure 7 (e) In this context, through further merging, the surface can be increased to any desired code distance. Similarly, arbitrary state injections can be obtained. Combining the above CNOT gate operations, arbitrary universal logic quantum gate operations can be implemented.

[0047] S104, based on an architecture combining time-sensitive networking and software-defined networking, interconnects multiple computing nodes carrying the logical qubits with the central controller in a star topology.

[0048] In this embodiment, the system adopts a star topology, a distributed digital quantum network with a central controller at its core. Individual digital quantum computing nodes execute computational tasks, and all computing nodes are only interconnected with the central controller; direct communication between nodes is not possible. Based on an architecture combining Time-Sensitive Networking (TSN) and Software-Defined Networking (SDN), multiple computing nodes carrying the logical qubits are interconnected with the central controller in a star topology. Network communication employs deterministic networking technology, distributively connecting scalable computing nodes to achieve reliable transmission with low latency and bounded jitter. In this embodiment, network communication uses deterministic networking technology (a combination of TSN and SDN), distributively connecting n scalable computing nodes to achieve reliable transmission with low latency and bounded jitter. TSN is a series of standards developed by the TSN working group within the IEEE 802.1 working group. SDN is a network architecture proposed by the Clean-Slate research group at Stanford University, and is an implementation of network virtualization.

[0049] like Figure 8The diagram illustrates the deterministic network architecture of this embodiment. This architecture primarily comprises computing node terminal systems (senders and receivers), an SDN controller, and network routing and switching nodes. Based on different network locations, at the forwarding layer, the routing and switching nodes can be categorized into ingress edge nodes (first nodes), transmission nodes (intermediate nodes), and egress edge nodes (tail nodes). This architecture offers the advantage of centralized control. The central controller performs unified collaborative scheduling and management of all computing nodes and resources. Network communication paths are all point-to-point links between nodes and the central controller, allowing for precise measurement and assurance of communication latency and bandwidth.

[0050] Furthermore, in S104, the architecture based on the combination of time-sensitive networking and software-defined networking interconnects multiple computing nodes carrying the logical qubits with the central controller in a star topology, including: the central controller calculating explicit paths and establishing a mapping relationship between service flows and forwarding cycles; identifying and filtering service flows entering the architecture, replicating multiple copies and sending them along multiple paths, periodically scheduling forwarding according to message cycle attributes, and performing redundancy elimination at the exit to restore the original data packets; the architecture distinguishes bandwidth resources between deterministic and non-deterministic service flows, and schedules idle resources for non-deterministic flows during the idle periods of deterministic flows.

[0051] Specifically, in this embodiment, the central controller acts as the brain of the entire network system, collecting network topology and latency information, calculating paths that meet end-to-end latency requirements of services, and establishing a mapping relationship between deterministic service flows and forwarding cycles. Specifically, to eliminate the impact of protocol convergence time and maintain the stability of forwarding paths, the central controller calculates the optimal explicit path for deterministic service flows using specific protocols or a centralized control unit, and can rely on redundant paths to ensure uninterrupted service when individual links fail. For networks that do not yet support SDN controllers, network service flows and path information can be manually configured at the ingress edge nodes. Thus, by establishing the mapping relationship between explicit paths and forwarding cycles, end-to-end deterministic transmission guarantees are ensured for service flows carrying quantum state information between distributed nodes.

[0052] Furthermore, the incoming service flows are identified and filtered. Specifically, the ingress edge node determines whether the end-to-end service flows of the terminal system are allowed to enter the network for deterministic forwarding based on packet characteristics, and divides packets with irregular arrival times into different forwarding cycles according to time. Service flows entering the network are called deterministic service flows, which can be defined by the five-tuple of an IP packet (source IP address, destination IP address, source port, destination port, protocol type, etc.). The ingress edge node identifies and filters packets entering the designated interface based on flow characteristics, and then encapsulates packets allowed to enter the deterministic forwarding path, attaching the periodic attributes of each forwarding node. When a deterministic service flow exceeds the reserved bandwidth of the interface, the ingress edge node will discard packets exceeding the bandwidth, and will not provide deterministic transmission guarantees for them.

[0053] Furthermore, through a reliable delivery mechanism, multiple copies of deterministic business flows are sent out along multiple paths at the ingress edge nodes using packet replication and encoding techniques. Each replicated packet is forwarded to or near its destination. Therefore, a single random event or device failure will not result in the loss of any packet, thus providing high reliability for quantum state transmission across computing nodes and ensuring the reliable delivery of collaborative control information between computing nodes and the central controller in a distributed digital quantum computing system.

[0054] Furthermore, periodic scheduling and forwarding are performed based on the message periodicity attribute. Specifically, the encapsulated data packets are shaped at the ingress edge node, queued according to the period, and forwarded within the specified period. For example... Figure 9 The diagram illustrates the deterministic forwarding process in this embodiment. When a data packet arrives at a downstream transmission node or egress edge node, the forwarding node places the packet into the corresponding queue based on the periodic attribute carried in the packet header, and then waits for periodic scheduling and forwarding. The transmission node and egress edge node queue and send out packets sent by the upstream node within a certain period from a designated interface of their own node within a specified period. Thus, through end-to-end periodic scheduling and forwarding, low-latency, bounded jitter-free deterministic transmission of service flows carrying quantum state information is ensured between distributed computing nodes.

[0055] In this embodiment, redundancy elimination is performed at the egress point to restore the original data packets. Specifically, network edge nodes eliminate redundant copies and restore the original data packets through redundancy elimination, packet sorting, and data decoding techniques. The egress edge nodes eliminate redundant copies from multiple paths and restore the original data packets, thereby ensuring the reliable delivery of deterministic service flows and guaranteeing the continuity and data integrity of cross-node collaborative computing in the distributed digital quantum computing system.

[0056] To maintain high bandwidth utilization, idle resources from deterministic flows are allocated to non-deterministic flows within each scheduling cycle. This elastic scheduling mechanism enables seamless and smooth adjustment between deterministic and non-deterministic resources. Furthermore, congestion protection mechanisms, including forwarding slot allocation, resource reservation (such as link bandwidth reservation and node buffer reservation), and packet preemption, achieve ultra-low latency and zero congestion loss. These mechanisms can be applied independently or in combination; when used in combination, they provide maximum QoS guarantees for the reliability of low-latency services.

[0057] S105, the central controller coordinates the scheduling of each computing node, distributes computing tasks to the target computing node, and expands or shrinks the logical qubits across nodes based on the three-dimensional lattice merging operation or the three-dimensional lattice splitting operation across computing nodes.

[0058] In this embodiment, the system adopts a star topology, a distributed digital quantum network with a central controller at its core. Individual digital quantum computing nodes execute computational tasks, and all computing nodes are only interconnected with the central controller; nodes do not communicate directly with each other. Figure 10 The diagram shows the star topology of the central controller in this embodiment. Based on the collaborative scheduling method for digital quantum computing node resources, a unified user interface and computing task management template, along with a customized digital quantum network operating system, are used to manage the digital quantum computing nodes and network, distribute computing tasks, and aggregate and output computing results, enabling collaborative computing among multiple digital quantum computing nodes. The central controller coordinates the collaborative scheduling of each computing node, uniformly scheduling all digital quantum computing resources, coordinating collaborative computing tasks among nodes, and distributing computing tasks to target computing nodes. Simultaneously, the expansion or contraction of cross-node logical qubits is achieved based on three-dimensional lattice merging or splitting operations across computing nodes; the two-dimensional curved lattice operation process of the surface code is extended to a three-dimensional structure. Based on the logical data qubits of the surface code and the three-dimensional architecture representing the qubits, two-dimensional digital qubit layers can be superimposed, and multiple additional digital qubits can be added between adjacent layers. Through the "merging" and "splitting" process of the three-dimensional lattice operation, general logical quantum control NOT gate operations are performed on the proposed architecture, which has lateral operation capability, ensuring that errors affecting one qubit will not propagate throughout the system, thereby maintaining the integrity of quantum information, realizing three-dimensional nearest neighbor connectivity between digital qubits, and elastic expansion and contraction of logical qubits across computing nodes.

[0059] Furthermore, in S105, the coordinated scheduling of each computing node through the central controller includes: receiving the registration information of the computing nodes and establishing a global quantum state mapping table; dynamically adding computing nodes or blocking nodes that do not participate in the computation according to the computation task requirements; deregistering faulty nodes and migrating their digital qubits to other nodes; and splitting the computation task and summarizing the results.

[0060] In this embodiment, when the central controller coordinates the scheduling of each computing node, it uses a unified scheduling algorithm to manage all computing nodes uniformly, maintain a consistent view of the global quantum state, and accurately schedule the computing tasks of each node, avoiding the complex overhead of distributed consensus. Before participating in computation, a new computing node needs to register with the central controller, including its computing resources, digital quantum computing capabilities, and configuration information. The central controller allocates initial qubits (empty states) to it and updates the global quantum state mapping table to establish a consistent view of the global quantum state. Based on the computational task requirements, as the scale of the computational task increases, the central controller dynamically adds computing nodes. The specific number of nodes required to participate in the computation is set according to the needs of the computational task distribution. The central controller allocates the newly added qubits to the new nodes through consistent hashing or dynamic partitioning algorithms, achieving horizontal scaling. For nodes that do not participate in parallel iterative computation according to the computational task requirements, the central controller dynamically blocks them and excludes them from the coordinated scheduling and management of computation. For computing nodes that fail or cease participating in computational tasks, the central controller performs deregistration by removing them from the capability table, thus enabling the node's exit. Before exiting, the central controller migrates the digital qubits it is responsible for to other nodes through merging and splitting operations, ensuring computational continuity before allowing the node to safely go offline. Furthermore, based on a unified task template, the central controller splits computational tasks to accommodate the parallel computing needs of distributed computing nodes; it then aggregates the results from each computing node according to a specific strategy and outputs them to the user. A unified user interface is used to receive user computational task requests and provide feedback on results. The central controller can be deployed as a multi-active cluster to avoid single points of failure; when the primary controller fails, the backup controller seamlessly takes over, ensuring service continuity.

[0061] Furthermore, in S105, the expansion or contraction of cross-node logical qubits based on the three-dimensional lattice merging or splitting operation across computing nodes includes: stacking the two-dimensional lattices corresponding to the logical qubits, arranging interlayer digital qubits between adjacent stacked layers, the interlayer digital qubits surrounding the entire edge of the logical qubits; closing the stabilizers at the edge of the surface to be merged and opening the interlayer stabilizers through the interlayer digital qubits to achieve cross-layer lattice merging; or achieving cross-layer lattice splitting by measuring the interlayer data qubits to complete the expansion or contraction of logical qubits across computing nodes.

[0062] Specifically, data qubits and characterization qubits using surface-coded lattice surfaces are arranged in a two-dimensional lattice manner to form stacked layers of two-dimensional qubit lattices, and interlayer digital qubits are arranged between adjacent stacked layers; such as Figure 11 The diagram shows a three-dimensional layout of the qubits in this embodiment. White circles represent upper-layer digital qubits, gray circles represent lower-layer digital qubits. For visualization purposes, only a portion of the lower-layer qubits is shown. Black dashed lines represent intra-layer connections, and blue dashed lines represent inter-layer connections. The inter-layer physical qubits are located at the center of the red grid and are connected to the eight data qubits at the vertices of the grid. Figure 12 This is a configuration diagram of the digital qubits in this embodiment. (As shown...) Figure 12 As shown in (a), two-dimensional layers are stacked, with interlayer digital qubits (red dots) placed along the edges of logical qubits (black, gray, and light gray parallelograms) connecting the layers; as Figure 12 As shown in (b), the top view of the first layer and the interlayer, in order to enable lattice manipulation from all directions, the red dot layer digital qubits surround the entire edge of the logic qubits; as Figure 12 As shown in (c) of the diagram, the enlarged view of the circle shows that the dashed lines connecting the data qubits between layers indicate connectivity between the two data qubits. Logical CNOTs can be implemented by utilizing the interlayer cross-layer CNOT connectivity; as shown in the diagram. Figure 12 As shown in (d), logical qubits from different layers are merged. The merging operation can be achieved by turning off the stabilizers at the edge of the surface to be merged and turning on the stabilizers using interlayer digital qubits.

[0063] like Figure 13The diagram shows a three-dimensional placement structure of the logic qubits in this embodiment. By placing the logic auxiliary qubit layer at the bottom and superimposing a checkerboard lattice structure on top, the red and blue boxes represent logic representation and logic data qubits. Operations between different positions utilize lateral swaps and lattice operations with logic representation qubits. Lattice operations are primarily performed on this structure; the interlayer digital qubits involved in the lattice operation must always exist between the representation qubit layers. Since the logic representation qubits exist next to any logic data qubit, two logic data qubits can always be connected via lattice operations. Even with a large lattice layer, CNOT operations can be performed at any position via lattice operations, thus any CNOT can be completed within a 3d period. Furthermore, since the logic data qubits are surrounded by logic representation qubits, the reachability between qubits is improved, thereby increasing the number of operations that can be performed simultaneously.

[0064] like Figure 14 The above is shown as the basis of this embodiment. Figure 13 A schematic diagram illustrating the execution of general logic controlled NOT gate operations on a three-dimensional placement structure. (See diagram for example.) Figure 14 As shown, in (a) dark blue represents CNOT 1 and orange represents CNOT 2; in (b) in CNOT 1 and CNOT 2, the target qubit and control qubit are merged with adjacent lattices of the logical representation qubit, thus enabling CNOT through lattice manipulation. Since these processes can be performed simultaneously, it can be confirmed that CNOT 1 and CNOT 2 can be performed concurrently.

[0065] Furthermore, the computing node uses carry-and-join representation to store quantum states, performs local quantum state preparation and local quantum gate operations, receives instructions from the central controller and reports local status and calculation results, and executes lattice merging and lattice splitting operation instructions issued by the central controller.

[0066] Specifically, in this embodiment, each computing node is an independent set of von Neumann computers or computing units responsible for simulating a certain number of digital qubits. The nodes internally use carry-and-join representation to store quantum states, and each node can carry multiple logical qubits. Nodes do not communicate directly; all cross-node collaborative operations (such as quantum state transmission and carry coordination in merging operations) are relayed through the central controller. The computing nodes perform local quantum state preparation and evolution, as well as local quantum gate operations, completing the state initialization and basic logical operations of the digital qubits locally. Simultaneously, the computing nodes receive instructions from the central controller, report their local state and computation results, and execute lattice merging and splitting operation instructions issued by the central controller. Specifically, in the star topology architecture, all computing nodes only establish connections with the central controller; computing nodes do not need to maintain connection states with other nodes, reducing the implementation complexity of the nodes. The central controller audits and controls all communication content to meet security and compliance requirements. When the central controller issues instructions for lattice merging or lattice splitting, the computing nodes execute the corresponding operations locally and complete the cross-node quantum state transmission and carry coordination through the central controller, ensuring the consistency and continuity of collaborative computing among nodes in the distributed digital quantum computing system.

[0067] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A cooperative control method for a distributed digital quantum computing system, the system comprising multiple computing nodes and a central controller, characterized in that, The cooperative control method for the distributed digital quantum computing system includes: Each computing node acquires two classical bit signals, couples the two classical bit signals through dual mapping, and generates a one-dimensional vector based on the projection length of the magnetic moment of the spin operator in the principal direction in the Ising spin model. The one-dimensional vector is used as the quantum state vector to obtain the digital quantum bit. Each computing node encodes multiple digital qubits into logical qubits based on a surface code, wherein the surface code consists of a two-dimensional lattice of data qubits and characterization qubits, and the characterization qubits measure the stabilizers between themselves and their neighboring data qubits to detect errors; In response to the computational task requirements, lattice merging or lattice splitting operations are performed on the logical qubits to achieve elastic contraction or expansion of the logical qubits. Based on an architecture combining time-sensitive networking and software-defined networking, multiple computing nodes carrying the logical qubits are interconnected with the central controller in a star topology. The central controller coordinates the scheduling of each computing node, distributes computing tasks to the target computing node, and expands or shrinks the logical qubits across nodes based on three-dimensional lattice merging or splitting operations.

2. The cooperative control method for a distributed digital quantum computing system according to claim 1, characterized in that, The method for generating a one-dimensional vector based on the projection length of the magnetic moment of the spin operator in the Ising spin model along the principal direction includes: The longest operator magnetic moment length is defined as 1, and the one-dimensional vector is generated by representing the continuous value from 0 to 1 based on the projection length of the magnetic moment of the spin operator in the principal direction.

3. The cooperative control method for a distributed digital quantum computing system according to claim 1, characterized in that, Each computing node encodes multiple digital qubits into logical qubits based on surface codes, including: The data qubits and the characterization qubits are arranged into a two-dimensional lattice, such that the data qubits are in simultaneous eigenstates around each crystal face, and the characterization qubits measure the tetragonal stabilizers of the crystal face at the center of the patch surrounded by the data qubits. All data qubits are prepared as ground state or equal-amplitude superposition state and multiple rounds of characterization measurements are performed to obtain the logical initial state. At the end of the calculation, the logical measurement results are read after error correction. Logical operators are defined based on the boundary of a two-dimensional lattice to obtain logical qubits with a preset code distance.

4. The cooperative control method for a distributed digital quantum computing system according to claim 1, characterized in that, The lattice merging operation includes: An intermediate data qubit is introduced between the encoding crystal planes corresponding to the two logical qubits to be merged. The eigenvalues ​​of the logical operator product of the two logical qubits are inferred by measuring the stabilizer that crosses the boundary. The two encoding crystal planes are merged into a single surface, and the merged logical state is conditionally mapped according to the measurement results.

5. The cooperative control method for a distributed digital quantum computing system according to claim 1, characterized in that, The lattice splitting operation includes: In the plane of logic qubits to be split, a row of intermediate data qubits is measured to remove the intermediate data qubits from the lattice, splitting the single code plane into two independent code planes, so that the logic state of the original logic qubits is distributed to the two newly generated logic qubits.

6. The cooperative control method for a distributed digital quantum computing system according to claim 5, characterized in that, The method further includes: Using lattice surgery to construct a fault-tolerant logic control gate, the control logic qubit is merged and split with the intermediate logic qubit initialized to an equal amplitude superposition state, and then the intermediate logic qubit is merged and split with the target logic qubit. Multiple rounds of error correction are performed during the merging process to maintain the code distance. Furthermore, a logic single-qubit rotation gate is implemented through state injection. The data qubit corresponding to the quantum state to be injected is subjected to a controlled NOT gate operation with the adjacent characterization qubit. The injected logic qubit is obtained through stabilizer measurement, and the code distance of the logic qubit is extended to the target code distance through a merging operation.

7. The cooperative control method for a distributed digital quantum computing system according to claim 1, characterized in that, The architecture, which combines time-sensitive networking and software-defined networking, interconnects multiple computing nodes carrying the logical qubits with the central controller in a star topology, including: The central controller calculates the explicit path and establishes a mapping relationship between service flow and forwarding cycle; The business flows entering the architecture are identified and filtered, multiple copies are made and sent through multiple paths, and periodic scheduling and forwarding are performed based on the message periodic attributes. Redundancy is eliminated at the exit point to restore the original data packets. The architecture distinguishes bandwidth resources between deterministic and non-deterministic service flows, and schedules idle resources to non-deterministic flows during their idle periods.

8. The cooperative control method for a distributed digital quantum computing system according to claim 1, characterized in that, The coordinated scheduling of each computing node through the central controller includes: Receive the registration information of computing nodes and establish a global quantum state mapping table; Dynamically add computing nodes or disable nodes that do not participate in computing based on the computing task requirements; Deregister the faulty node and migrate its digital qubits to other nodes; The computational task is broken down and the results are summarized.

9. The cooperative control method for a distributed digital quantum computing system according to claim 1, characterized in that, The expansion or contraction of cross-node logical qubits based on cross-computing node merging or splitting operations includes: The two-dimensional lattice corresponding to the logical qubit is stacked, and interlayer digital qubits are arranged between adjacent stacked layers, with the interlayer digital qubits surrounding the entire edge of the logical qubit. Cross-layer lattice merging is achieved by turning off the stabilizers at the edge of the surface to be merged and turning on the interlayer stabilizers using the interlayer digital qubits; or cross-layer lattice splitting is achieved by measuring the interlayer data qubits to complete the expansion or contraction of logical qubits across computing nodes.

10. The cooperative control method for a distributed digital quantum computing system according to claim 1, characterized in that, The computing node uses carry-and-join representation to store quantum states, performs local quantum state preparation and local quantum gate operations, receives instructions from the central controller and reports local status and calculation results, and executes lattice merging and lattice splitting operation instructions issued by the central controller.

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