Display panel and gate driving circuit thereof

Abstract

The application provides a display panel and a gate drive circuit thereof. By setting the first drive unit and the second drive unit to share a clock control signal, the same gate drive module can output a second display drive signal and a fourth display drive signal with a phase difference, realizing the alternation of a display picture and a black insertion picture, and reducing the space occupancy of the gate drive circuit on the display panel. By respectively receiving a first control signal and a second control signal which are complementary, the first drive unit and the second drive unit can make the effective level of the second display drive signal and the fourth display drive signal in different time periods, thereby realizing seamless switching between normal picture display and black insertion display and improving dynamic display quality. The effective level of the current target level transmission signal in a frame period does not have a blanking period, and the effective level between the clock control signals does not have a blanking period, which can make the transmission of the second display drive signal and the fourth display drive signal continuous.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to display panels and their gate driving circuits. Background Technology

[0002] To solve the ghosting phenomenon that occurs when the display panel switches between dynamic images, black bars are usually inserted between the display intervals of one frame to complete the initialization before the next frame is displayed. This reduces or eliminates the visual persistence of the human eye on the previous frame, thereby achieving the goals of eliminating ghosting, improving dynamic clarity, and improving dynamic response, thus improving the dynamic display quality of the display panel.

[0003] When alternating between normal and black screen displays, two display drive signals are needed to switch the screen. However, the related technologies require two sets of gate drive circuits to output two different display drive signals, which causes the gate drive circuits to occupy more bezel space on the display panel. Summary of the Invention

[0004] The display panel and its gate driving circuit provided in this application can reduce the space occupied by the gate driving circuit on the display panel.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted in this application is: to provide a gate driving circuit for a display panel, specifically including: multiple cascaded gate driving modules; each gate driving module includes: The first driving unit has a first input terminal that receives a first target stage transmission signal output by the front-end gate driving module or a first control signal corresponding to the first target stage transmission signal; a second input terminal that receives a first display driving signal output by the front-end gate driving module; and a third input terminal that receives a clock control signal. The output terminal of the first driving unit is connected to the corresponding display gate line on the display panel, and is used to output a second display driving signal to the display gate line to drive the pixel unit corresponding to the display gate line to display a normal image. The first display driving signal and the second display driving signal have the same function. The second driving unit has a first input terminal that receives a first target stage transmission signal output by the front-stage gate driving module or a first control signal corresponding to the first target stage transmission signal; a second input terminal that receives a third display driving signal output by the front-stage gate driving module; and a third input terminal that receives a clock control signal. The output terminal of the second driving unit is connected to the corresponding black gate line on the display panel, and is used to output a fourth display driving signal to the black gate line to drive the pixel unit corresponding to the black gate line to display a black image. The third and fourth display driving signals have the same function; however, the effective levels of the second and fourth display driving signals are in different time periods. The fourth input terminal of the first driving unit is connected to the fourth input terminal of the second driving unit to receive the second control signal; the second control signal is complementary to the first control signal. The effective levels of the current target stage transmission signals output by several gate drive modules within a frame period do not have a blanking period, and the effective levels of the clock control signals within a frame period do not have a blanking period.

[0006] In one embodiment, the first driving unit includes: a first transistor, a second transistor, a third transistor, and a first capacitor; The first terminal of the first transistor and the second transistor serve as the first input terminal of the first driving unit to receive the first target stage transmission signal output by the front-stage gate driving module or to receive the first control signal corresponding to the first target stage transmission signal; the second terminal of the first transistor serves as the second input terminal of the first driving unit to receive the first display driving signal output by the front-stage gate driving module. The second terminals of the first transistor and the second transistor are connected to the control terminal of the third transistor. The first terminal of the third transistor serves as the third input terminal of the first driving unit to receive the clock control signal. The second terminal of the third transistor serves as the output terminal of the first driving unit and is connected to the corresponding display gate line on the display panel to output the second display driving signal to the display gate line, so as to drive the pixel unit corresponding to the display gate line to display the normal image. The control terminal of the second transistor serves as the fourth input terminal of the first driving unit to receive the second control signal. The first capacitor is connected between the control terminal of the third transistor and the second terminal of the third transistor.

[0007] In one embodiment, the second driving unit includes: a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitor; The first terminals of the fourth and fifth transistors serve as the first input terminals of the second driving unit to receive the first target stage transmission signal output by the front-end gate driving module or to receive the first control signal corresponding to the first target stage transmission signal; the control terminal of the fifth transistor serves as the second input terminal of the second driving unit to receive the third display driving signal output by the front-end gate driving module. The second terminals of the fourth and fifth transistors are connected to the control terminal of the sixth transistor. The first terminal of the sixth transistor serves as the third input terminal of the second driving unit to receive the clock control signal. The second terminal of the sixth transistor serves as the output terminal of the second driving unit and is connected to the corresponding black gate line on the display panel to output the fourth display driving signal to the black gate line to drive the pixel unit corresponding to the black gate line to display a black screen. The control terminal of the fourth transistor serves as the fourth input terminal of the second driving unit to receive the second control signal. The second capacitor is connected between the control terminal of the sixth transistor and the second terminal of the sixth transistor.

[0008] In one embodiment, each gate drive module further includes a pull-up unit; The first terminal of the pull-up unit receives the first target stage transmission signal output by the front-stage gate drive module, and the second terminal of the pull-up unit is connected to the first input terminal of the first drive unit and the first input terminal of the second drive unit. The control terminal of the pull-up unit receives the first target level transmission signal, and the pull-up unit is configured to output the corresponding first control signal according to the first target level transmission signal.

[0009] In one embodiment, the pull-up unit includes: a seventh transistor; The control terminal of the seventh transistor serves as the control terminal of the pull-up unit to receive the first target stage transmission signal. The first terminal of the seventh transistor serves as the first terminal of the pull-up unit to receive the first target stage transmission signal output by the front gate drive module. The second terminal of the seventh transistor serves as the second terminal of the pull-up unit and is connected to the first input terminal of the first drive unit and the first input terminal of the second drive unit.

[0010] In one embodiment, each gate driving module further includes a pull-down unit; The first end of the pull-down unit is connected to the output end of the first drive unit, the second end of the pull-down unit is connected to the output end of the second drive unit, the third end of the pull-down unit is grounded, and the control end of the pull-down unit is used to receive the second target stage transmission signal output by the subsequent gate drive module. The pull-down unit is configured to: control the connection between the first and third terminals of the pull-down unit to pull down the second display drive signal according to the effective level of the second target level transmission signal; and control the connection between the second and third terminals of the pull-down unit to pull down the fourth display drive signal.

[0011] In one embodiment, the pull-down unit includes an eighth transistor, a ninth transistor, and a tenth transistor; The control terminals of the eighth, ninth, and tenth transistors are connected in sequence. The control terminal of the eighth transistor serves as the control terminal of the pull-down unit and is used to receive the second target stage transmission signal output by the subsequent gate drive module. The first terminal of the eighth transistor is connected to the output terminal of the second driving unit as the second terminal of the pull-down unit, the first terminal of the ninth transistor is connected to the output terminal of the first driving unit as the first terminal of the pull-down unit, and the first terminal of the tenth transistor is used to output the first control signal corresponding to the second target stage transmission signal. The second terminals of the eighth, ninth, and tenth transistors are all grounded.

[0012] In one embodiment, each gate drive module further includes: a current target stage signal output unit; The first terminal of the current target-level signal output unit is used to receive clock control signals; The control terminal of the current target stage signal output unit receives the first control signal corresponding to the first target stage signal output by the front gate drive module; the second terminal of the current target stage signal output unit serves as the output terminal. The current target-level transmission signal output unit is configured to output the current target-level transmission signal based on the first control signal and clock control signal corresponding to the target-level transmission signal output by the front-stage gate drive module.

[0013] In one embodiment, the current target level signal output unit includes an eleventh transistor and a third capacitor; The first terminal of the eleventh transistor serves as the first terminal of the current target stage signal output unit for receiving clock control signals. The control terminal of the eleventh transistor, as the control terminal of the current target level transmission signal output unit, receives the first control signal corresponding to the first target level transmission signal output by the front gate driving module; the second terminal of the eleventh transistor, as the second terminal of the current target level transmission signal output unit, serves as the output terminal, and outputs the current target level transmission signal based on the first control signal and clock control signal corresponding to the target level transmission signal output by the front gate driving module. The third capacitor is connected between the control terminal of the eleventh transistor and the second terminal of the eleventh transistor.

[0014] To solve the above-mentioned technical problems, the second technical solution adopted in this application is: to provide a display panel, the display panel including: pixel circuit and gate driving circuit; The pixel circuit includes: multiple pixel units arranged in an array; Display gate lines, each display gate line is set and electrically connected to a row of pixel units; Insert black gate lines, each black gate line is set and electrically connected to a row of pixel units; The gate driving circuit is connected to the display gate line and the black gate line respectively, and the gate driving circuit is the gate driving circuit in the first technical solution mentioned above.

[0015] The beneficial effects of this application are as follows: Unlike existing technologies, the gate driving circuit of the display panel provided in this application, by setting the first driving unit and the second driving unit to share a clock control signal, enables the same gate driving module to output a second display driving signal and a fourth display driving signal with a phase difference. Utilizing the second and fourth display driving signals to achieve alternating display of the screen and black-and-white frames reduces the space occupied by the gate driving circuit on the display panel, which is beneficial for reducing the bezel width of the display panel and simplifying the circuit. Furthermore, by having the first and second driving units respectively receive complementary first and second control signals, the effective levels of the second and fourth display driving signals are at different time periods, thereby achieving seamless switching between normal screen display and black-and-white display, improving dynamic display quality. Additionally, since the effective levels of the current target level transmission signals output by several gate driving modules within a frame period do not have blanking periods, and the effective levels between clock control signals within a frame period do not have blanking periods, the transmission of the second and fourth display driving signals is continuous. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of an embodiment of the gate driving circuit and pixel circuit for displaying images in a display panel in the related art; Figure 2 This is a schematic diagram of an embodiment of the gate driving circuit and pixel circuit for realizing self-interpolation of black pixels in a display panel in the related art; Figure 3 for Figure 2 A timing diagram of an embodiment of the output waveform requirements of the gate drive circuit; Figure 4 This is a schematic diagram of an embodiment of a gate drive circuit in the related art; Figure 5 for Figure 4 A schematic diagram of the structure of one embodiment of the unfolded view of each unit of the gate drive circuit; Figure 6 A schematic diagram of the structure of a first embodiment of the gate driving circuit for a display panel provided in this application; Figure 7 A schematic diagram of the structure of a second embodiment of the gate driving circuit for the display panel provided in this application; Figure 8 A schematic diagram of the structure of a third embodiment of the gate driving circuit for a display panel provided in this application; Figure 9 A timing waveform diagram of an embodiment of the clock control signal in the gate drive circuit of the display panel provided in this application; Figure 10 A timing waveform diagram of an embodiment of the target stage signal transmission in the gate drive circuit of the display panel provided in this application; Figure 11 A timing waveform diagram of each participating signal in an embodiment of the gate driving circuit of the display panel provided in this application when implementing self-black insertion; Figure 12 A schematic diagram of the structure of an embodiment of the display panel provided in this application.

[0018] Reference numerals: Display panel 10000, Gate drive circuit 1000, Gate drive module 100, First drive unit 110, Second drive unit 120, Display gate line 210, Pixel unit 220, Black gate line 230, Pull-up unit 200, Pull-down unit 300, Current target level signal output unit 400, Output unit 600, Reset unit 700, Noise reduction unit 900, First transistor T1, Second transistor T2, Third transistor T3, Fourth transistor T4, Fifth transistor T5, Sixth transistor T6 The following transistors are listed: seventh transistor T7, eighth transistor T8, ninth transistor T9, tenth transistor T10, eleventh transistor T11, first capacitor C1, second capacitor C2, third capacitor C3, clock control signal CK, first control signal Qn, second control signal Pn, first display drive signal Gn-j, second display drive signal Gn, third display drive signal Dis_Gn-j, fourth display drive signal Dis_Gn, first target level transmission signal Fn-j, second target level transmission signal Fn+i, and current target level transmission signal Fn. Detailed Implementation

[0019] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0020] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0021] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0023] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0024] See Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the gate driving circuit 1000 and pixel circuit 500 for displaying images in a display panel 10000 in the related art. In this embodiment, each pixel unit 220 requires only one set of gate driving circuit 1000 to output a display driving signal to turn on the thin-film transistor (TFT) to achieve image display.

[0025] In the specific implementation process, when the display panel 10000 performs dynamic image switching, a ghosting phenomenon will occur. Generally, black is inserted between the display intervals of one frame to complete the initialization before the next frame is displayed, reducing or eliminating the visual persistence of the human eye on the previous frame. This achieves the purpose of eliminating ghosting, improving dynamic clarity, improving dynamic response, and improving the dynamic display quality of the display panel 10000.

[0026] Based on this, see Figure 2 , Figure 2 This is a schematic diagram of an embodiment of a gate drive circuit 1000 and pixel circuit 500 for implementing self-placing black bars in a display panel 10000 in related technologies. In this scheme, a single pixel unit 220 requires two different types of display drive signals for control, namely... Figure 2The display gate driving module 101 outputs a display driving signal to the thin-film transistor TFT1 connected to the display gate line 210 to control the display panel 10000 to display a normal image, thus achieving the display of a normal image. The black gate driving module 102 outputs a display driving signal to the thin-film transistor TFT2 connected to the black gate line 230 to control the display panel 10000 to display a black image, thus achieving the display of a black image. However, outputting two different types of display driving signals requires arranging two sets of gate driving circuits 1000, which will increase the bezel width of the display panel 10000.

[0027] See Figure 1 and Figure 2 The pixel unit 220 also includes multiple data lines D, gate lines G, and thin-film transistors (TFTs), as well as electrode capacitors, common capacitors, and ground terminals connected to the thin-film transistors (TFTs).

[0028] It should be noted that the gate drive circuit 1000 in this solution and related technologies is arranged inside the display panel 10000, symmetrical about the pixel circuit 500 and located outside the pixel circuit 500.

[0029] See Figure 3 As shown in the figure, the display drive signals used to display normal images and black images when the display panel 10000 implements self-interpolation have the same output waveforms as the display drive signals driving individual pixel units 220 when the display panel 10000 implements image display. The scanning process is also the same. However, the phase of the display drive signal used to display black images needs to be delayed compared to the display drive signal used to display normal images to satisfy the inter-frame black insertion function. The delay time can be manually adjusted. Figure 3 Take 1 / 2 frame as an example.

[0030] Figure 3 The waveforms of G1~Gend are the required waveforms of the display drive signal for a normal display screen; Dis_G1~Dis_Gend are the required waveforms of the display drive signal for a black screen. Figure 3 The serial numbers "①, ②, ③" represent the scanning order. That is, when half of the frames of the normally displayed screen are scanned, the frames of the black screen are scanned, and the display time of the frames of the normally displayed screen and the frames of the black screen are the same.

[0031] Another approach uses single-sided driving, where one side outputs a display drive signal for displaying a normal image, and the other side outputs a display drive signal for displaying a black image. However, the driving capability of single-sided driving limits the size of the display panel to 10,000, making this method unsuitable for large-size panels.

[0032] See Figure 4 and Figure 5 , Figure 4 This is a basic component of a commonly used gate drive circuit in related technologies. Figure 5 for Figure 4 This is a schematic diagram of an embodiment of the expanded view of the gate drive circuit units. The gate drive circuit 1000 includes a pull-up unit 200, a pull-down unit 300, an output unit 600, a noise reduction unit 900, and a reset unit 700. The pull-up unit 200 and the pull-down unit 300 are respectively responsible for pulling up and pulling down the Q point in the circuit. The pull-up and pull-down are controlled by the target stage transmission signals from the preceding and following stages, respectively. According to the signal of the Q point, the corresponding transistor in the output unit 600 (e.g., Figure 5 The T2 signal in the circuit is used for noise reduction. The output signal is based on the clock control signal CK and the display drive signal output by the front gate drive module 100. The noise reduction unit 900 performs noise reduction processing on important signals in the circuit. The reset unit 700 performs pull-down reset on the Q point signal in each frame.

[0033] Figure 4 The Gn signal is the display drive signal that controls the display panel 10000 to display a normal image. Gn-j is the display drive signal output by the front gate drive module 100. Fn is the current target stage transmission signal. Fn-j is the first target stage transmission signal output by the front gate drive module 100. Fn+i is the second target stage transmission signal output by the rear gate drive module 100. The Reset signal is the reset signal. LC1 / LC2 are a pair of reverse control signals.

[0034] It should be noted that in the above signal representation, j is a positive integer greater than 0 and less than n, and i is a positive integer greater than 0.

[0035] Understandable. Figure 4 This is one of two sets of gate drive circuits 1000 used in the related technology to output two different types of display drive signals. Specifically, it is a gate drive circuit 1000 used to output a gate drive circuit 10000 to control the display panel 10000 to display a normal image. Correspondingly, in the execution of the related technology, it is also necessary to arrange a set of gate drive circuits 1000 used to output a gate drive circuit 10000 to control the display panel 10000 to display a black image.

[0036] Figure 5 VSS in the diagram is the ground terminal. Additionally, in order to achieve... Figure 5 Chinese correspondence Figure 4 The working effect of each unit in the gate drive circuit 1000 is also reflected in the basic structure, which includes multiple transistors and resistive devices.

[0037] In a specific embodiment, the two sets of gate driving circuits 1000 in the related technology will cause the bezel width of the display panel 10000 to increase.

[0038] Based on this, referring to the following embodiments, this application provides a display panel 10000 and its gate driving circuit 1000, which can reduce the space occupancy rate of the gate driving circuit 10000 on the display panel 10000.

[0039] like Figure 6 As shown, Figure 6 This is a schematic diagram of an embodiment of the gate driving circuit for a display panel provided in this application. The gate driving circuit 1000 specifically includes: multiple cascaded gate driving modules 100; each gate driving module 100 includes a first driving unit 110 and a second driving unit 120. The first input terminal of the first driving unit 110 receives a first target stage transmission signal Fn-j output by the preceding gate driving module 100 or receives a first control signal Qn corresponding to the first target stage transmission signal Fn-j; the second input terminal of the first driving unit 110 receives a first display driving signal Gn-j output by the preceding gate driving module 100; the third input terminal of the first driving unit 110 receives a clock control signal CK; the output terminal of the first driving unit 110 is connected to the corresponding display gate line 210 on the display panel 10000; the output terminal of the first driving unit 110 is used to output a second display driving signal Gn to the display gate line 210 to drive the pixel unit 220 corresponding to the display gate line 210 to display a normal image; wherein, the first display driving signal Gn-j and the second display driving signal Gn have the same function.

[0040] The first input terminal of the second driving unit 120 receives the first target stage transmission signal Fn-j output by the front-stage gate driving module 100 or receives the first control signal Qn corresponding to the first target stage transmission signal Fn-j. The second input terminal of the second driving unit 120 receives the third display driving signal Dis_Gn-j output by the front-stage gate driving module 100. The third input terminal of the second driving unit 120 receives the clock control signal CK. The output terminal of the second driving unit 120 is connected to the corresponding black gate line 230 on the display panel 10000. The output terminal of the second driving unit 120 is used to output the fourth display driving signal Dis_Gn to the black gate line 230 to drive the pixel unit 220 corresponding to the black gate line 230 to display a black screen. The third display driving signal Dis_Gn-j and the fourth display driving signal Dis_Gn have the same function. The effective level of the second display driving signal Gn and the effective level of the fourth display driving signal Dis_Gn are in different time periods.

[0041] It should be noted that the gate driving circuit 1000 includes multiple gate driving modules 100, each corresponding to two gate lines: a display gate line 210 and a black screen gate line 230. The first display driving signal Gn-j and the second display driving signal Gn both drive the pixel unit 220 corresponding to the display gate line 210 to display a normal image. The third display driving signal Dis_Gn-j and the fourth display driving signal Dis_Gn both drive the pixel unit 220 corresponding to the black screen gate line 230 to display a black screen. The effective levels of the second display driving signal Gn and the fourth display driving signal Dis_Gn are at different time intervals. It can be understood that the first driving unit 110 and the second driving unit 120 work alternately, meaning that the display of a normal image and a black screen is alternately implemented. Specifically, when the second display driving signal Gn is at a high level (effective level), the fourth display driving signal Dis_Gn is at a low level.

[0042] See Figure 7 In one embodiment, the first driving unit 110 outputs a second display driving signal Gn to the display gate line 210 in the display panel 10000 based on the first control signal Qn corresponding to the first target transmission signal Fn-j, the first display driving signal Gn-j output by the front gate driving module 100, and the clock control signal CK, so that when the second display driving signal Gn has an effective level (high level), the pixel unit 220 corresponding to the display gate line 210 is driven to display a normal image; the second driving unit 120 outputs a fourth display driving signal Dis_Gn to the black gate line 230 in the display panel 10000 based on the first control signal Qn corresponding to the first target transmission signal Fn-j, the third display driving signal Dis_Gn-j output by the front gate driving module 100, and the clock control signal CK, so that when the fourth display driving signal Dis_Gn has an effective level (high level), the pixel unit 220 corresponding to the black gate line 230 is driven to display a black image.

[0043] See Figure 8In another embodiment, the first driving unit 110 outputs a second display driving signal Gn to the display gate line 210 in the display panel 10000 based on the first target stage transmission signal Fn-j, the first display driving signal Gn-j, and the clock control signal CK received from the front-stage gate driving module 100. When the second display driving signal Gn has an effective level (high level), the pixel unit 220 corresponding to the display gate line 210 is driven to display a normal image. The second driving unit 120 outputs a fourth display driving signal Dis_Gn to the black gate line 230 in the display panel 10000 based on the first target stage transmission signal Fn-j, the third display driving signal Dis_Gn-j, and the clock control signal CK received from the front-stage gate driving module 100. When the fourth display driving signal Dis_Gn has an effective level (high level), the pixel unit 220 corresponding to the black gate line 230 is driven to display a black image.

[0044] In a specific embodiment, the fourth input terminal of the first driving unit 110 and the fourth input terminal of the second driving unit 120 are connected to receive the second control signal Pn; the second control signal Pn is complementary to the first control signal Qn.

[0045] It should be noted that the fourth input terminal of the first driving unit 110 is connected to the fourth input terminal of the second driving unit 120. It can be understood that the gate driving module 100 in this embodiment includes both the first driving unit 110 and the second driving unit 120, and the first driving unit 110 and the second driving unit 120 work alternately to ensure that the same gate driving module 100 can continuously and alternately output the second display driving signal Gn and the fourth display driving signal Dis_Gn to the display gate line 210 and the black insertion gate line 230 of the display panel 10000, thereby realizing the self-insertion black display of the display panel 10000.

[0046] The gate driving circuit 1000 provided in this embodiment also includes a noise reduction unit 900. The noise reduction unit 900 is used to output a second control signal Pn. The second control signal Pn is complementary to the first control signal Qn. That is, when the first control signal Qn is high (active level), the second control signal Pn is low; when the first control signal Qn is low, the second control signal Pn is high (active level).

[0047] In a specific embodiment, the effective level of the current target transmission signal Fn output by several gate driving modules 100 within a frame period does not have a blanking period, and the effective level of the clock control signal CK within a frame period also does not have a blanking period. The blanking period can be understood as the period during which the clock control signal CK remains at a low level.

[0048] See Figure 9 and Figure 10 In a specific embodiment, there is no blanking period for the effective level between clock control signals CK, that is, the clock control signal CK is continuously output between frames. Therefore, there is no blanking period for the effective level of the current target level transmission signal Fn output by several gate driving modules 100 within a frame period. This ensures that the current target level transmission signal Fn output by the last gate driving module 100 corresponding to the first frame of the display screen is connected end to end with the current target level transmission signal Fn output by the first gate driving module 100 corresponding to the second frame of the display screen. Moreover, during the scanning process, the next scan is not performed after the previous scan ends, but rather after a period of time has passed since the start of the previous scan.

[0049] In this embodiment, there is no restriction on when the next scan should begin after the previous scan has started. This embodiment will be illustrated by starting the next scan in the middle of the previous scan.

[0050] In a specific embodiment, to start the next round of scanning in the middle of the previous scan, it is necessary to change the frequency of the previous stage trigger signal from triggering at the beginning of frame 1 to triggering at the beginning of frame 1 / 2.

[0051] This embodiment sets the first driving unit 110 and the second driving unit 120 to share the clock control signal CK, enabling the same gate driving module 100 to output a second display driving signal Gn and a fourth display driving signal Dis_Gn with a phase difference. This allows for alternating displays of the screen and black-and-white frames, reducing the bezel width of the display panel 10000 and simplifying the circuitry. By having the first driving unit 110 and the second driving unit 120 receive complementary first control signals Qn and Pn respectively, the effective levels of the second display driving signal Gn and the fourth display driving signal Dis_Gn are at different time intervals, achieving seamless switching between normal and black-and-white displays and improving dynamic display quality. Eliminating the blanking periods of the clock control signal CK and the target stage transmission signal Fn ensures continuous signal transmission.

[0052] See Figure 7 and Figure 8In one embodiment, the first driving unit 110 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1; the first terminals of the first transistor T1 and the second transistor T2 serve as the first input terminals of the first driving unit 110, receiving a first target stage transmission signal Fn-j output by the front-stage gate driving module 100 or receiving a first control signal Qn corresponding to the first target stage transmission signal Fn-j; the second terminal of the first transistor T1 serves as the second input terminal of the first driving unit 110, receiving a first display driving signal Gn-j output by the front-stage gate driving module 100; the second terminals of the first transistor T1 and the second transistor T2 are connected to a third crystal. The control terminal of transistor T3, the first terminal of the third transistor T3 serves as the third input terminal of the first driving unit 110 to receive the clock control signal CK; the second terminal of the third transistor T3 serves as the output terminal of the first driving unit 110 and is connected to the corresponding display gate line 210 on the display panel 10000, for outputting the second display driving signal Gn to the display gate line 210 to drive the pixel unit 220 corresponding to the display gate line 210 to display a normal image; the control terminal of the second transistor T2 serves as the fourth input terminal of the first driving unit 110 to receive the second control signal Pn; the first capacitor C1 is connected between the control terminal of the third transistor T3 and the second terminal of the third transistor T3.

[0053] It should be noted that the first capacitor C1 is the bootstrap capacitor of the third transistor T3. It can be understood that the function of the first capacitor C1 is to fully turn on the third transistor T3. At this time, the resistance is at its minimum, and the voltage through the control terminal of the third transistor T3 will become higher. Based on this, the stable output of the second display drive signal Gn is ensured to achieve the display of the normal picture.

[0054] In a specific embodiment, when the first transistor T1 is high (active) in response to the first target stage transmission signal Fn-j output by the front-stage gate driving module 100 or the first control signal Qn corresponding to the first target stage transmission signal Fn-j, it further receives the first display driving signal Gn-j output by the front-stage gate driving module 100, thereby turning on and outputting the first display driving signal Gn-j through the third transistor T3. At this time, the noise reduction unit 900 responds to the first target stage transmission signal Fn-j output by the front-stage gate driving module 100 or the first control signal Qn corresponding to the first target stage transmission signal Fn-j. The first control signal Qn undergoes noise reduction processing, specifically by setting the first target stage transmission signal Fn-j output by the front-end gate drive module 100 or the first control signal Qn corresponding to the first target stage transmission signal Fn-j to a low level, and outputting a second control signal Pn complementary to the first control signal Qn. In response to the second control signal Pn being a high-level signal, the second transistor T2 is turned on, further enabling the third transistor T3 to turn on, receiving the clock control signal CK, and outputting a second display drive signal Gn to the display gate line 210 to drive the pixel unit 220 corresponding to the display gate line 210 to display a normal image. During this process, the first capacitor C1 replenishes the charge of the control terminal of the third transistor T3 to prevent voltage drops.

[0055] This embodiment, by setting the specific connection relationship of the first transistor T1, the second transistor T2, the third transistor T3, and the first capacitor C1, enables the first driving unit 110 to use the third transistor T3 as an output switch and achieve a bootstrap function with the cooperation of the first capacitor C1. This ensures that the second display driving signal Gn output to the display gate line 210 has a stable driving capability, which is beneficial to improving the opening efficiency of the pixel unit 220. The first transistor T1 and the first transistor T2 respectively receive the first target stage transmission signal Fn-j output by the front-stage gate driving module 100 or receive the first control signal Qn corresponding to the first target stage transmission signal Fn-j, allowing the first driving unit 110 to flexibly respond to different triggering sequences. The second transistor T2 receives the second control signal Pn, making the internal logic of the first driving unit 110 more complete, which helps prevent signal conflicts or false triggering and improves the reliability of circuit operation.

[0056] In one embodiment, the second driving unit 120 includes: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a second capacitor C2; the first terminals of the fourth transistor T4 and the fifth transistor T5 serve as the first input terminals of the second driving unit 120, receiving a first target stage transmission signal Fn-j output by the front-stage gate driving module 100 or receiving a first control signal Qn corresponding to the first target stage transmission signal Fn-j; the control terminal of the fifth transistor T5 serves as the second input terminal of the second driving unit 120, receiving a third display driving signal Dis_Gn-j output by the front-stage gate driving module 100; the second terminals of the fourth transistor T4 and the fifth transistor T5 are connected to the sixth crystal. The control terminal of transistor T6, the first terminal of the sixth transistor T6 serves as the third input terminal of the second driving unit 120 to receive the clock control signal CK; the second terminal of the sixth transistor T6 serves as the output terminal of the second driving unit 120 and is connected to the corresponding black gate line 230 on the display panel 10000, for outputting the fourth display driving signal Dis_Gn to the black gate line 230 to drive the pixel unit 220 corresponding to the black gate line 230 to display a black screen; the control terminal of the fourth transistor T4 serves as the fourth input terminal of the second driving unit 120 to receive the second control signal Pn; the second capacitor C2 is connected between the control terminal of the sixth transistor T6 and the second terminal of the sixth transistor T6.

[0057] It should be noted that the second capacitor C2 is the bootstrap capacitor of the sixth transistor T6. It can be understood that the function of the second capacitor C2 is to fully turn on the sixth transistor T6. At this time, the resistance is at its minimum, and the voltage through the control terminal of the gate of the sixth transistor T6 will become higher. Based on this, the stable output high level amplitude of the fourth display drive signal Dis_Gn is sufficient to drive the pixel unit 220 to display a black screen.

[0058] In a specific embodiment, when the fifth transistor T5 is high (active) in response to the first target stage transmission signal Fn-j output by the front-stage gate driving module 100 or the first control signal Qn corresponding to the first target stage transmission signal Fn-j, it further receives the third display driving signal Dis_Gn-j output by the front-stage gate driving module 100, thereby turning on. The sixth transistor T6 then outputs the third display driving signal Dis_Gn-j. At this time, the noise reduction unit 900 responds to the first target stage transmission signal Fn-j output by the front-stage gate driving module 100 or the first control signal Qn corresponding to the first target stage transmission signal Fn-j. The corresponding first control signal Qn undergoes noise reduction processing, that is, the first target stage transmission signal Fn-j output by the front-end gate drive module 100 or the first control signal Qn corresponding to the first target stage transmission signal Fn-j is set to a low level, and a second control signal Pn complementary to the first control signal Qn is output. In response to the second control signal Pn being a high level signal, the fourth transistor T4 is turned on, which further turns on the sixth transistor T6, receives the clock control signal CK, and outputs the fourth display drive signal Dis_Gn to the black gate line 230 to drive the pixel unit 220 corresponding to the black gate line 230 to display a black screen. The second capacitor C2 replenishes the charge of the control terminal of the sixth transistor T6 during this process to prevent voltage drop.

[0059] This embodiment, by setting the specific connection relationship of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the second capacitor C2, enables the second driving unit 120 to use the sixth transistor T6 as an output switch and achieve a bootstrap function with the cooperation of the second capacitor C2. This ensures that the fourth display driving signal Dis_Gn output to the black gate line 230 has stable driving capability, which is beneficial to improving the opening efficiency of the pixel unit 220. The first terminals of the fourth transistor T4 and the fifth transistor T5 respectively receive the first target stage transmission signal Fn-j output by the front-stage gate driving module 100 or receive the first control signal Qn corresponding to the first target stage transmission signal Fn-j, allowing the second driving unit 120 to flexibly respond to different triggering sequences. The fourth transistor T4 receives the second control signal Pn, making the internal logic of the second driving unit 120 more complete, which helps prevent signal conflicts or false triggering and improves the reliability of circuit operation.

[0060] In one embodiment, each gate driving module 100 further includes a pull-up unit 200; the first terminal of the pull-up unit 200 receives a first target stage transmission signal Fn-j output by the preceding gate driving module 100, and the second terminal of the pull-up unit 200 is connected to the first input terminal of the first driving unit 110 and the first input terminal of the second driving unit 120; the control terminal of the pull-up unit 200 receives the first target stage transmission signal Fn-j, and the pull-up unit 200 is configured to output a corresponding first control signal Qn according to the first target stage transmission signal Fn-j.

[0061] In a specific embodiment, when the first target stage transmission signal Fn-j output by the front gate drive module 100 is high (effective level), the control terminal of the pull-up unit 200 controls the first terminal and the second terminal of the pull-up unit 200 to conduct, thereby pulling up the first control signal Qn of point Q.

[0062] This embodiment, by setting up a pull-up unit 200, enables the first driving unit 110 and the second driving unit 120 to receive complementary control signals, thereby ensuring that the effective levels of the second display driving signal Gn and the fourth display driving signal Dis_Gn are in different time periods, achieving timing separation between normal display and black-out display. The pull-up unit 200 outputs a first control signal Qn based on the first target stage transmission signal Fn-j, allowing complementary signals to be generated within the gate driving circuit 1000 without additional external logic circuitry, simplifying the circuit structure and reducing manufacturing costs and complexity. The pull-up unit 200 receives the first target stage transmission signal Fn-j at its first end and connects to the first input terminals of the two driving units at its second end, achieving efficient signal distribution and conversion, which improves the integration of the gate driving circuit 1000 and further reduces the bezel width of the display panel 10000.

[0063] In one embodiment, the pull-up unit 200 includes: a seventh transistor T7; the control terminal of the seventh transistor T7 serves as the control terminal of the pull-up unit 200 to receive the first target stage transmission signal Fn-j, the first terminal of the seventh transistor T7 serves as the first terminal of the pull-up unit 200 to receive the first target stage transmission signal Fn-j output by the front-stage gate driving module 100, and the second terminal of the seventh transistor T7 serves as the second terminal of the pull-up unit 200 connected to the first input terminal of the first driving unit 110 and the first input terminal of the second driving unit 120.

[0064] In a specific embodiment, when the first target stage transmission signal Fn-j output by the current stage gate drive module 100 is high (effective level), the seventh transistor T7 is turned on and outputs the first control signal Qn.

[0065] In this embodiment, the first target transmission signal Fn-j is received through the first terminal and control terminal of the seventh transistor T7, and the second terminal is connected to the first input terminal of the first driving unit 110 and the second driving unit 120, thereby realizing efficient signal sharing and distribution, and further reducing the space occupied by the gate driving circuit 1000 on the display panel 10000.

[0066] In one embodiment, each gate driving module 100 further includes a pull-down unit 300, the first end of which is connected to the output of the first driving unit 110, the second end of which is connected to the output of the second driving unit 120, and the third end of which is grounded. The control terminal of the pull-down unit 300 is used to receive the second target stage transmission signal Fn+i output by the subsequent gate driving module 100. The pull-down unit 300 is configured to: control the connection between the first end and the third end of the pull-down unit 300 to pull down the second display driving signal Gn according to the effective level of the second target stage transmission signal Fn+i; and control the connection between the second end and the third end of the pull-down unit 300 to pull down the fourth display driving signal Dis_Gn.

[0067] It should be noted that the level of the second target stage transmission signal Fn+i output by the subsequent gate drive module 100 reflects the scanning state of the subsequent stage.

[0068] In a specific embodiment, when the control terminal of the pull-down unit 300 receives a high level (effective level) second target stage transmission signal Fn+i from the subsequent gate drive module 100, the pull-down unit 300 is turned on, connecting the first terminal and the second terminal to the third terminal respectively, thereby controlling the output terminal of the first drive unit 110 to be grounded and pulling the second display drive signal Gn down to a low level; at the same time, controlling the output terminal of the second drive unit 120 to be grounded and pulling the fourth display drive signal Dis_Gn down to a low level.

[0069] In this embodiment, the pull-down unit 300 is configured such that its first terminal is connected to the output terminal of the first driving unit 110, its second terminal is connected to the output terminal of the second driving unit 120, and its third terminal is grounded. Controlled by the second target stage transmission signal Fn+i output from the subsequent stage, the second display driving signal Gn and the fourth display driving signal Dis_Gn output by the current stage gate driving module 100 can be pulled down to a low level, which helps eliminate signal residue and ensures clear waveforms. By using the second target stage transmission signal Fn+i output from the subsequent stage gate driving module 100 as the control signal, the additional reset unit 700 is eliminated, simplifying the circuit structure of the gate driving module 100 and reducing its footprint.

[0070] In one embodiment, the pull-down unit 300 includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; the control terminals of the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are connected in sequence, the control terminal of the eighth transistor T8 serves as the control terminal of the pull-down unit 300, and is used to receive the second target stage transmission signal Fn+i output by the subsequent gate drive module 100; the first terminal of the eighth transistor T8 serves as the second terminal of the pull-down unit 300 and is connected to the output terminal of the second drive unit 120, the first terminal of the ninth transistor T9 serves as the first terminal of the pull-down unit 300 and is connected to the output terminal of the first drive unit 110, and the first terminal of the tenth transistor T10 is used to output a first control signal Qn corresponding to the second target stage transmission signal Fn+i; the second terminals of the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all grounded.

[0071] It should be noted that the control terminal of the eighth transistor T8 receives the second target stage transmission signal Fn+i output by the subsequent gate drive module 100. When the second target stage transmission signal Fn+i is high (active level), the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned on. The first terminal of the ninth transistor T9 is connected to the output terminal of the first drive unit 110 and is used to pull down the second display drive signal Gn. The first terminal of the eighth transistor T8 is connected to the output terminal of the second drive unit 120 and is used to pull down the fourth display drive signal Dis_Gn. The first terminal of the tenth transistor T10 outputs a first control signal Qn corresponding to the second target stage transmission signal Fn+i. This first control signal Qn can be used to drive the next stage circuit, namely the first drive unit 110 and the second drive unit 120.

[0072] In this embodiment, the pull-down unit 300 includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10 connected in sequence. The first terminal of the eighth transistor T8 is connected to the output terminal of the second driving unit 120, and the first terminal of the ninth transistor T9 is connected to the output terminal of the first driving unit 110. Both transistors have their second terminals grounded via a series path. This allows the second display driving signal Gn output by the first driving unit 110 and the fourth display driving signal Dis_Gn output by the second driving unit 120 to be pulled down to a low level when the second target stage transmission signal Fn+i is high, thereby eliminating signal residue and ensuring waveform integrity. The first terminal of the tenth transistor T10 outputs a first control signal Qn corresponding to the second target stage transmission signal Fn+i. This allows the pull-down unit 300 to not only perform a pull-down function but also transmit control states to subsequent circuits, simplifying inter-stage signal transmission paths, reducing additional signal lines, and further reducing the wiring complexity and footprint of the gate driving circuit 1000.

[0073] In one embodiment, each gate driving module 100 further includes: a current target level transmission signal output unit 400; a first terminal of the current target level transmission signal output unit 400 is used to receive a clock control signal CK; a control terminal of the current target level transmission signal output unit 400 receives a first control signal Qn corresponding to the first target level transmission signal Fn-j output by the previous gate driving module 100; a second terminal of the current target level transmission signal output unit 400 is used as an output terminal; the current target level transmission signal output unit 400 is configured to output the current target level transmission signal Fn based on the first control signal Qn corresponding to the target level transmission signal Fn output by the previous gate driving module 100 and the clock control signal CK.

[0074] The current target level transmission signal output unit 400 is configured to generate the current target level transmission signal Fn when the received first control signal Qn and clock control signal CK are both high (active level).

[0075] It should be noted that each gate drive module 100 can accurately generate the current target stage transmission signal Fn for triggering the next gate drive module 100 based on the state of the first target stage transmission signal and the clock control signal output by the previous gate drive module, thus ensuring the continuous transmission of the target stage transmission signal.

[0076] This embodiment configures the current target stage transmission signal output unit 400 to output the current target stage transmission signal Fn based on the first control signal Qn and the clock control signal CK. This enables the gate driving module 100 to accurately generate and transmit the target stage transmission signal, ensuring the continuity and timing accuracy of the cascaded driving process. The absence of a blanking period in the clock control signal CK allows the current target stage transmission signal output unit 400 to continuously respond to changes in the control signal, which improves the efficiency and stability of signal transmission.

[0077] In one embodiment, the current target level signal output unit 400 includes an eleventh transistor T11 and a third capacitor C3; the first terminal of the eleventh transistor T11 serves as the first terminal of the current target level signal output unit 400 to receive a clock control signal CK; the control terminal of the eleventh transistor T11 serves as the control terminal of the current target level signal output unit 400 to receive a first control signal Qn corresponding to the first target level signal Fn-j output by the front-stage gate driving module 100; the second terminal of the eleventh transistor T11 serves as the second terminal of the current target level signal output unit 400 as the output terminal, and outputs the current target level signal Fn based on the first control signal Qn corresponding to the target level signal Fn output by the front-stage gate driving module 100 and the clock control signal CK; the third capacitor C3 is connected between the control terminal of the eleventh transistor T11 and the second terminal of the eleventh transistor T11.

[0078] It should be noted that the third capacitor C3 is the bootstrap capacitor of the eleventh transistor T11. Understandably, the function of the third capacitor C3 is to fully turn on the eleventh transistor T11. At this time, the resistance is at its minimum, and the voltage through the control terminal of the eleventh transistor T11 will become higher, keeping it in a fully conducting state, thereby reducing the level loss during signal transmission.

[0079] In a specific embodiment, when the first control signal Qn corresponding to the first target stage transmission signal Fn-j output by the front gate drive module 100 is at a high level (effective level), the eleventh transistor T11 is turned on, receives the clock control signal CK, and generates the current target stage transmission signal Fn based on the first control signal Qn and the clock control signal CK.

[0080] In this embodiment, by connecting a third capacitor C3 between the control terminal and the second terminal of the eleventh transistor T11, a bootstrap boost is achieved on the control terminal potential of the eleventh transistor T11. This allows the eleventh transistor T11 to maintain a low on-resistance when outputting a high level, thereby reducing level drops during clock control signal transmission and improving the output amplitude and waveform quality of the current target stage transmission signal Fn. The eleventh transistor T11 is turned on based on the first control signal Qn and receives the clock control signal CK, ensuring the generation of the current target stage transmission signal Fn.

[0081] In one embodiment, the waveform of the gate drive circuit 1000 provided in this application during operation is as follows: Figure 11 As shown, the signal waveforms of the first target-level transmission signal Fn-j, the second target-level transmission signal Fn+i, the first control signal Qn, the second control signal Pn, the current target-level transmission signal Fn, the second display drive signals Gn and Qan, the first display drive signal Gn-j, the fourth display drive signals Dis_Gn and Qbn, and the third display drive signal Dis_Gn-j, displayed in sequence, are shown.

[0082] In a specific embodiment, combined with Figure 7 and Figure 11 Explanation: At time t1, the first target stage transmission signal Fn-j transitions from low to high (active level), transistor T7 is turned on, and the first control signal Qn is pulled up by the first target stage transmission signal Fn-j, causing Qn to transition from low to high (active level). At this time, the front-end gate drive module 100 outputs the first display drive signal Gn-j, which transitions from low to high (active level), turning on the first transistor T1, thus connecting point Q and point Qa, thereby charging point Qa and pulling up the level of point Qa to complete the pre-charging (e.g., Figure 11As shown, at time t1, Qan transitions from low to high (effective level). This, combined with the clock control signal CK, allows the third transistor T3 to output the second display drive signal Gn to the display gate line 210. This output process is simultaneously supported by the first capacitor C1 for bootstrapping. At time t2, the first control signal Qn is pulled down to low by the high level of the second target stage transmission signal Fn+i. At this time, noise reduction processing begins through the noise reduction unit 900. Because the first control signal Qn and the second control signal Pn are complementary, the second control signal Pn is at a high level. The high level of the second control signal Pn turns on the second transistor T2, causing point Qa to conduct with point Q. Point Qa is pulled down to a low level, and noise reduction continues simultaneously. This completes the process of outputting a high-level second display drive signal Gn to the display gate line 210 for the corresponding duration between times t1 and t2.

[0083] In the above embodiment, the third display drive signal Dis_Gn-j is in the low level stage, so the fifth transistor T5 is not turned on, and there is no signal input at point Qb. Therefore, the fourth display drive signal Dis_Gn is in the low level stage.

[0084] Similarly, at time t3, the first target stage transmission signal Fn-j transitions from low to high (effective level), the seventh transistor T7 is turned on, and the first control signal Qn is pulled up by the first target stage transmission signal Fn-j, transitioning from low to high (effective level). At this time, the third display drive signal Dis_Gn-j transitions from low to high (effective level), turning on the fifth transistor T5, connecting point Q and point Qb, thus charging point Qb and pulling up the level of point Qb to complete the pre-charge. Then, in conjunction with the clock control signal CK, the fourth display drive signal Dis_Gn can be output to the black gate line 230 through the sixth transistor T6, and its output process is simultaneously used in conjunction with the second capacitor C2 for bootstrapping. At time t4, the first control signal Qn is pulled down to low by the high level of the second target stage transmission signal Fn+i, and noise reduction processing begins through the noise reduction unit 900. Since the first control signal Qn and the second control signal Pn are complementary, the second control signal Pn is at a high level at this time. The high level of the second control signal Pn can turn on the fourth transistor T4, making Qb point and Q point conduct. Qb point can then be pulled down to a low level, and noise reduction can be performed continuously at the same time. This completes the output of the fourth display drive signal Dis_Gn, which is of a corresponding high level, to the black gate line 230 during the period from t3 to t4.

[0085] exist Figure 11 In the diagram, identifiers ① and ② can represent different scanning rounds. Figure 11In this process, the phase difference between two scanning cycles is 1 / 2 frame. By controlling the phase difference between two independent trigger signals, the phase difference between the two scanning cycles can be achieved. At the same time, the phase difference between the second display drive signal Gn and the fourth display drive signal Dis_Gn can be controlled, so that the black insertion time can be arbitrarily adjusted and is not limited to 1 / 2 frame.

[0086] This embodiment requires that the output of the current target level transmission signal Fn be continuous; otherwise, the waveform at the discontinuity will be reflected in the discontinuity between the second display driving signal Gn and the fourth display driving signal Dis_Gn, affecting the display. However, the output quantity of the second display driving signal Gn and the fourth display driving signal Dis_Gn is not limited to the number of scan lines. The number of scan lines used only for scanning and not for display can be appropriately increased to ensure that the output signal is not affected by the independent trigger signal in the above embodiment, thus facilitating the stable output of the second display driving signal Gn and the fourth display driving signal Dis_Gn.

[0087] See Figure 12 The display panel 10000 includes a pixel circuit 500 and a gate driving circuit 1000. The pixel circuit 500 includes a plurality of pixel units 220 arranged in an array, a display gate line 210, a black gate line 230, and a gate driving circuit 1000. Each display gate line 210 is correspondingly disposed and electrically connected to a row of pixel units 220. Each black gate line 230 is correspondingly disposed and electrically connected to a row of pixel units 220. The gate driving circuit 1000 is connected to the display gate line 210 and the black gate line 230 respectively. The gate driving circuit 1000 is the gate driving circuit 1000 in any of the above embodiments.

[0088] In this embodiment, the gate driving circuit 1000 in the display panel 10000 includes multiple gate driving modules 100 cascaded on the left and right sides of the display panel 10000. Each gate driving module 100 is respectively connected to a display gate line 210 and a black gate line 230.

[0089] In a specific embodiment, each display gate line 210 is correspondingly configured and electrically connected to a row of pixel units 220, and is used to receive a second display driving signal Gn to control the pixel unit 220 to display a normal image; each black gate line 230 is correspondingly configured and electrically connected to a row of pixel units 220, and is used to receive a fourth display driving signal Dis_Gn to control the pixel unit 220 to display a black image.

[0090] In this embodiment, a second display driving signal Gn and a fourth display driving signal Dis_Gn with a preset phase difference are output from the same gate driving module 100 to display normal and black screen images respectively. This eliminates the need for two independent gate driving circuits 1000 on the display panel 10000, thus significantly reducing the space occupied by the gate driving circuits 10000. Using only one set of clock control signal CK for driving further reduces the number of clock traces, which helps reduce the space occupied by the gate driving circuits 10000 on the display panel 10000. This facilitates the self-insertion black screen function of the large-size display panel 10000, while ensuring the dynamic display quality of the display panel 10000 and eliminating ghosting during screen transitions.

[0091] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0092] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0093] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A gate driving circuit for a display panel, characterized in that, include: Multiple cascaded gate drive modules; Each of the gate drive modules includes: A first driving unit has a first input terminal that receives a first target stage transmission signal output by a front-stage gate driving module or receives a first control signal corresponding to the first target stage transmission signal; a second input terminal that receives a first display driving signal output by the front-stage gate driving module; and a third input terminal that receives a clock control signal. The output terminal of the first driving unit is connected to a corresponding display gate line on the display panel, and is used to output a second display driving signal to the display gate line to drive the pixel unit corresponding to the display gate line to display a normal image. The first display driving signal and the second display driving signal have the same function. The second driving unit has a first input terminal that receives the first target stage transmission signal output by the front-stage gate driving module or receives the first control signal corresponding to the first target stage transmission signal; a second input terminal that receives the third display driving signal output by the front-stage gate driving module; and a third input terminal that receives the clock control signal. The output terminal of the second driving unit is connected to the corresponding black-pin gate line on the display panel, and is used to output a fourth display driving signal to the black-pin gate line to drive the pixel unit corresponding to the black-pin gate line to display a black screen. The third and fourth display driving signals have the same function. The effective levels of the second and fourth display driving signals are at different time periods. The second and fourth display driving signals have a phase difference, thereby using the second and fourth display driving signals to achieve alternating appearances of the displayed image and the black-pin image. The fourth input terminal of the first driving unit and the fourth input terminal of the second driving unit are connected to receive a second control signal; the second control signal is complementary to the first control signal. The effective level of the current target transmission signal output by several gate drive modules within a frame period does not have a blanking period, and the effective level of the clock control signal within a frame period does not have a blanking period.

2. The gate driving circuit according to claim 1, characterized in that, The first driving unit includes: a first transistor, a second transistor, a third transistor, and a first capacitor; The first terminal of the first transistor and the second transistor serve as the first input terminal of the first driving unit to receive the first target stage transmission signal output by the front-stage gate driving module or to receive the first control signal corresponding to the first target stage transmission signal; the second terminal of the first transistor serves as the second input terminal of the first driving unit to receive the first display driving signal output by the front-stage gate driving module. The second terminals of the first transistor and the second transistor are connected to the control terminal of the third transistor. The first terminal of the third transistor serves as the third input terminal of the first driving unit to receive the clock control signal. The second terminal of the third transistor serves as the output terminal of the first driving unit and is connected to the corresponding display gate line on the display panel to output the second display driving signal to the display gate line, thereby driving the pixel unit corresponding to the display gate line to display a normal image. The control terminal of the second transistor serves as the fourth input terminal of the first driving unit to receive the second control signal. The first capacitor is connected between the control terminal of the third transistor and the second terminal of the third transistor.

3. The gate driving circuit according to claim 1, characterized in that, The second driving unit includes: a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitor; The first terminals of the fourth transistor and the fifth transistor serve as the first input terminals of the second driving unit to receive the first target stage transmission signal output by the front-stage gate driving module or to receive the first control signal corresponding to the first target stage transmission signal; the control terminal of the fifth transistor serves as the second input terminal of the second driving unit to receive the third display driving signal output by the front-stage gate driving module. The second terminals of the fourth and fifth transistors are connected to the control terminal of the sixth transistor. The first terminal of the sixth transistor serves as the third input terminal of the second driving unit to receive the clock control signal. The second terminal of the sixth transistor serves as the output terminal of the second driving unit and is connected to the corresponding black gate line on the display panel to output the fourth display driving signal to the black gate line, thereby driving the pixel unit corresponding to the black gate line to display a black screen. The control terminal of the fourth transistor serves as the fourth input terminal of the second driving unit to receive the second control signal. The second capacitor is connected between the control terminal of the sixth transistor and the second terminal of the sixth transistor.

4. The gate driving circuit according to claim 1, characterized in that, Each of the gate drive modules further includes a pull-up unit; The first end of the pull-up unit receives the first target stage transmission signal output by the front-stage gate drive module, and the second end of the pull-up unit is connected to the first input end of the first drive unit and the first input end of the second drive unit. The control terminal of the pull-up unit receives the first target level transmission signal, and the pull-up unit is configured to output the corresponding first control signal according to the first target level transmission signal.

5. The gate driving circuit according to claim 4, characterized in that, The pull-up unit includes: a seventh transistor; The control terminal of the seventh transistor serves as the control terminal of the pull-up unit, receiving the first target stage transmission signal. The first terminal of the seventh transistor serves as the first terminal of the pull-up unit, receiving the first target stage transmission signal output by the front-stage gate drive module. The second terminal of the seventh transistor serves as the second terminal of the pull-up unit, connecting the first input terminal of the first drive unit and the first input terminal of the second drive unit.

6. The gate driving circuit according to claim 1, characterized in that, Each of the gate drive modules further includes: a pull-down unit; The first end of the pull-down unit is connected to the output end of the first driving unit, the second end of the pull-down unit is connected to the output end of the second driving unit, the third end of the pull-down unit is grounded, and the control end of the pull-down unit is used to receive the second target stage transmission signal output by the subsequent gate driving module. The pull-down unit is configured to: control the connection between the first and third terminals of the pull-down unit to pull down the second display drive signal according to the effective level of the second target level transmission signal; and control the connection between the second and third terminals of the pull-down unit to pull down the fourth display drive signal.

7. The gate driving circuit according to claim 6, characterized in that, The pull-down unit includes an eighth transistor, a ninth transistor, and a tenth transistor; The control terminals of the eighth, ninth and tenth transistors are connected in sequence. The control terminal of the eighth transistor serves as the control terminal of the pull-down unit and is used to receive the second target stage transmission signal output by the subsequent gate drive module. The first terminal of the eighth transistor is connected to the output terminal of the second driving unit as the second terminal of the pull-down unit, the first terminal of the ninth transistor is connected to the output terminal of the first driving unit as the first terminal of the pull-down unit, and the first terminal of the tenth transistor is used to output a first control signal corresponding to the second target stage transmission signal. The second terminals of the eighth, ninth, and tenth transistors are all grounded.

8. The gate driving circuit according to claim 1, characterized in that, Each of the gate drive modules further includes: a current target stage signal output unit; The first terminal of the current target level signal output unit is used to receive the clock control signal; The control terminal of the current target stage signal output unit receives the first control signal corresponding to the first target stage signal output by the front-stage gate driving module; the second terminal of the current target stage signal output unit serves as the output terminal. The current target level transmission signal output unit is configured to output the current target level transmission signal based on the first control signal corresponding to the target level transmission signal output by the front-stage gate drive module and the clock control signal.

9. The gate driving circuit according to claim 8, characterized in that, The current target level signal output unit includes an eleventh transistor and a third capacitor; The first terminal of the eleventh transistor serves as the first terminal of the current target stage signal output unit for receiving the clock control signal. The control terminal of the eleventh transistor serves as the control terminal of the current target level transmission signal output unit, receiving the first control signal corresponding to the first target level transmission signal output by the front gate driving module; the second terminal of the eleventh transistor serves as the second terminal of the current target level transmission signal output unit, serving as the output terminal, and outputs the current target level transmission signal based on the first control signal corresponding to the target level transmission signal output by the front gate driving module and the clock control signal. The third capacitor is connected between the control terminal of the eleventh transistor and the second terminal of the eleventh transistor.

10. A display panel, the display panel comprising: Pixel circuit and gate drive circuit; The pixel circuit includes: Multiple pixel units arranged in an array; Display gate lines, each of the display gate lines is configured and electrically connected to a row of pixel units; Each black gate line is configured and electrically connected to a row of pixel units; The gate driving circuit is connected to the display gate line and the black insertion gate line respectively, and the gate driving circuit is the gate driving circuit as described in any one of claims 1 to 9.

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