Power supply circuit and memory

Abstract

The application provides a power supply circuit and a memory, and relates to the technical field of semiconductors. The power supply circuit comprises: a selection signal generation circuit, which is used for generating a voltage selection signal in a first state in the case that a word line in a target memory array is opened and closed multiple times, and generating a voltage selection signal in a second state in the case that the word line in the target memory array remains closed; a selection circuit, which is electrically connected with the selection signal generation circuit, a first power supply, a second power supply and a main word line driving circuit, and is used for selecting the first power supply to supply power to the main word line driving circuit in the case that the voltage selection signal is in the first state, and selecting the second power supply to supply power to the main word line driving circuit in the case that the voltage selection signal is in the second state; and the main word line driving circuit is used for outputting a first main word line driving signal to a sub word line driving circuit, and the voltage provided by the first power supply is greater than the voltage provided by the second power supply.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a power supply circuit and a memory. Background Technology

[0002] With the development of memory technology, memory incorporates multiple power supplies providing different voltages to meet performance and power consumption requirements. However, when word lines in the memory array are frequently turned on and off, the repeated switching between high and low voltage power supplies leads to high power consumption in the sub-word line drive circuit. Summary of the Invention

[0003] The following is an overview of the subject matter of this invention described in detail. This overview is not intended to limit the scope of the claims.

[0004] This invention provides a power supply circuit and a memory.

[0005] According to a first aspect of the present invention, a power supply circuit is provided, the power supply circuit comprising: A selection signal generation circuit is configured to generate a voltage selection signal in a first state when word lines in the target memory array are repeatedly turned on and off; and to generate the voltage selection signal in a second state when word lines in the target memory array remain off. The selection circuit is electrically connected to the selection signal generation circuit, the first power supply, the second power supply, and the main word line driving circuit. The selection circuit is used to select the first power supply to power the main word line driving circuit when the voltage selection signal is in the first state; and to select the second power supply to power the main word line driving circuit when the voltage selection signal is in the second state. The main word line driving circuit is used to output a first main word line driving signal to the sub-word line driving circuit, wherein the voltage provided by the first power supply is greater than the voltage provided by the second power supply.

[0006] According to some embodiments of the present invention, the selection signal generating circuit receives an address signal of a memory array, and the selection signal generating circuit is configured to generate the voltage selection signal in the first state when the address signal points to the target memory array; and to generate the voltage selection signal in the second state when the address signal points to a memory array other than the target memory array.

[0007] According to some embodiments of the present invention, the selection signal generation circuit includes: A logic circuit that receives the address signal and performs logical processing on the address signal to obtain an intermediate signal. The state of the intermediate signal is used to characterize whether the address signal points to the target memory array. A signal processing circuit is electrically connected to the logic circuit and the selection circuit, and receives a word line control signal. The signal processing circuit processes the word line control signal and the intermediate signal to obtain the voltage selection signal. The word line control signal is valid when the word line of any memory array in the target repository is enabled. The target repository includes the target memory array.

[0008] According to some embodiments of the present invention, the signal processing circuit includes: A latch circuit is electrically connected to the logic circuit and the selection circuit, and receives the word line control signal. The latch circuit is used to latch the intermediate signal under the trigger of the word line control signal to obtain the voltage selection signal.

[0009] According to some embodiments of the present invention, the latch circuit further receives a repository control signal, which is in an enabled state when word lines of any memory array in the target repository are turned on. The repository control signal is used to set the voltage selection signal to the second state before word lines in the target memory array are turned on for the first time, or when the target memory array is the last memory array in the target repository and word lines in the target memory array are turned off.

[0010] According to some embodiments of the present invention, the signal processing circuit includes: A first switching circuit, wherein the first input terminal of the first switching circuit is electrically connected to the logic circuit, and the output terminal of the first switching circuit is electrically connected to the selection circuit; A second switching circuit, wherein the first input terminal of the second switching circuit is electrically connected to the output terminal of the first switching circuit, the second input terminal of the second switching circuit receives the word line control signal, and the output terminal of the second switching circuit is electrically connected to the second input terminal of the first switching circuit; The first switching circuit and the second switching circuit are used to latch the intermediate signal with the word line control signal and to convert the voltage domain of the intermediate signal to obtain the voltage selection signal.

[0011] According to some embodiments of the present invention, the first switching circuit includes: A first transistor, wherein a first terminal of the first transistor is electrically connected to the first power supply, a second terminal of the first transistor is electrically connected to the selection circuit to output the voltage selection signal, and a control terminal of the first transistor is electrically connected to the logic circuit. The second transistor has its first terminal electrically connected to the second terminal of the first transistor. The third transistor has a first terminal electrically connected to the second terminal of the second transistor, the second terminal of the third transistor electrically connected to a bias power supply, and a control terminal of the third transistor electrically connected to the logic circuit. The fourth transistor has a first terminal electrically connected to the first power supply, a second terminal electrically connected to the second terminal of the first transistor, and a control terminal of the fourth transistor receiving the inverted signal of the voltage selection signal. The second switching circuit includes: The fifth transistor has a first terminal electrically connected to the third power supply and a second terminal electrically connected to the control terminal of the second transistor. The control terminal of the fifth transistor receives the word line control signal. The sixth transistor has its first terminal electrically connected to the second terminal of the fifth transistor, and its control terminal receives the word line control signal. A seventh transistor, wherein the first terminal of the seventh transistor is electrically connected to the second terminal of the sixth transistor, the second terminal of the seventh transistor is electrically connected to the bias power supply, and the control terminal of the seventh transistor is electrically connected to the second terminal of the first transistor; The eighth transistor has its first terminal electrically connected to the third power supply, its second terminal electrically connected to the second terminal of the fifth transistor, and its control terminal electrically connected to the second terminal of the first transistor.

[0012] According to some embodiments of the present invention, the second switching circuit further includes: The ninth transistor is electrically connected between the sixth transistor and the seventh transistor, and the control terminal of the ninth transistor receives the storage control signal; The tenth transistor has its first terminal electrically connected to the third power supply, its second terminal electrically connected to the second terminal of the fifth transistor, and its control terminal receiving the storage control signal. Wherein, the repository control signal is in an enabled state when the word line of any memory array in the target repository is turned on, and the repository control signal is used to put the voltage selection signal in the second state before the word line in the target memory array is turned on for the first time, or when the target memory array is the last memory array in the target repository and the word line in the target memory array is turned off.

[0013] According to some embodiments of the present invention, the address signal includes a first address signal and a second address signal, wherein the first address signal is used to select a target storage array group from the target repository, and the second address signal is used to select the target storage array from the target storage array group.

[0014] According to some embodiments of the present invention, the selection circuit includes: An inverting circuit is electrically connected to the selection signal generation circuit, and the inverting circuit is used to invert the voltage selection signal. The eleventh transistor has its first terminal electrically connected to the first power supply, its second terminal electrically connected to the main word line drive circuit, and its control terminal electrically connected to the inverting circuit to be controlled by the inverted voltage selection signal. The twelfth transistor has its first terminal electrically connected to the second power supply, its second terminal electrically connected to the second terminal of the eleventh transistor, and its control terminal electrically connected to the output terminal of the selection signal generation circuit, so as to be controlled by the voltage selection signal.

[0015] According to some embodiments of the present invention, when the first word line of the target memory array changes from a closed state to an open state, the voltage selection signal switches from the second state to the first state; when the last word line of the target memory array changes from an open state to a closed state, the voltage selection signal switches from the first state to the second state.

[0016] According to some embodiments of the present invention, when the target storage array is in the refresh process, the voltage selection signal is in the first state; when the target storage array is not refreshed or the refresh is completed, the voltage selection signal is in the second state.

[0017] A second aspect of the present invention provides a memory including a power supply circuit as described above.

[0018] In the power supply circuit and memory provided in this embodiment of the invention, the power supply circuit includes a selection signal generation circuit and a selection circuit. The selection signal generation circuit generates a voltage selection signal related to the operation of word lines in the target memory array. The selection circuit selects the corresponding power supply to power the main word line driving circuit according to the voltage selection signal. By combining the voltage selection signal related to the operation of the word lines to select the power supply of the main word line driving circuit, on the one hand, it avoids the introduction of additional power consumption due to frequent switching of the power supply of the main word line driving circuit when the word lines are repeatedly turned on and off. On the other hand, it provides power to the main word line driving circuit with a lower voltage when the word lines are kept off, thereby reducing the power consumption of the sub-word line driving circuit.

[0019] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the invention, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0021] Figure 1 This is a schematic diagram of a sub-word line driving circuit; Figure 2 It is a waveform diagram of a signal in a sub-word line driving circuit; Figure 3 This is a schematic diagram of a power supply circuit according to a first exemplary embodiment; Figure 4 This is a schematic diagram of a power supply circuit according to a second exemplary embodiment; Figure 5 This is a schematic diagram of a selection signal generation circuit according to a first exemplary embodiment; Figure 6 This is a schematic diagram of a selection signal generation circuit according to a second exemplary embodiment; Figure 7 This is a schematic diagram of a power supply circuit according to a third exemplary embodiment; Figure 8 This is a schematic diagram of a selection signal generation circuit according to a third exemplary embodiment; Figure 9 This is a schematic diagram of the structure of a signal processing circuit according to an exemplary embodiment; Figure 10This is a schematic diagram of a selection circuit according to an exemplary embodiment; Figure 11 This is a timing diagram of signals in a power supply circuit according to an exemplary embodiment.

[0022] In the diagram: 10: Selection signal generation circuit; 11: Logic circuit; 12: Signal processing circuit; 20: Selection circuit; 21: Inverting circuit; 30: Main word line drive circuit; 121: Latch circuit; 122: Voltage domain conversion circuit; 123: First switching circuit; 124: Second switching circuit; TU: Pull-up transistor; TD1: First pull-down transistor; TD2: Second pull-down transistor; T1: First transistor; T2: Second transistor; T3: Third transistor; T4: Fourth transistor; T5: Fifth transistor; T6: Sixth transistor; T7: Seventh transistor; T8: Eighth transistor; T9: Ninth transistor; T10: Tenth transistor; T11: Eleventh transistor; T12: Twelfth transistor; Tm : Matching transistor; WL: Word line; NAND: NAND gate; NOT: NOT gate; LRS: RS latch; V1: First power supply; V2: Second power supply; V3: Third power supply; V4: Fourth power supply; Vwln: Negative power supply; Vbb: Bias power supply; PhDec: First sub-word line drive signal; PhDecN: Second sub-word line drive signal; GrDecN: First main word line drive signal; Sel, Sel1, Sel2: Voltage selection signals; Add: Address signal; Add1: First address signal; Add2: Second address signal; Mid: Intermediate signal; GrEn: Word line control signal; Bnk: Repository control signal; SelN: First inverting signal; GrEnN: Second inverting signal. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be arbitrarily combined with each other. It should also be understood that the term "and / or" as used herein refers to any or all possible combinations including one or more associated listed items.

[0024] With the development of memory technology, the read and write speeds of memory have gradually increased, while power consumption has gradually decreased. To meet the requirements of performance and power consumption, memory is equipped with multiple power supplies that provide different voltages, switching the optimal power supply to power the corresponding circuits under different operating conditions.

[0025] For subword line driving circuits in memory, such as Figure 1 As shown, Figure 1 A schematic diagram of a sub-word line driving circuit is shown. The sub-word line driving circuit includes a pull-up transistor TU, a first pull-down transistor TD1, and a second pull-down transistor TD2. The first terminal of the pull-up transistor TU receives a first sub-word line driving signal PhDec, and its second terminal is electrically connected to the first terminals of the first pull-down transistor TD1 and the second pull-down transistor TD2, as well as the word line WL. The control terminal receives a first main word line driving signal GrDecN. The first main word line driving signal GrDecN is the inverted signal of the second main word line driving signal GrDec. In some embodiments, the word line WL is only turned on when the first main word line driving signal GrDecN is low. The second terminal of the first pull-down transistor TD1 is electrically connected to a negative power supply Vwln, and the control terminal receives the first main word line driving signal GrDecN. The second terminal of the second pull-down transistor TD2 is also electrically connected to the negative power supply Vwln, and the control terminal receives the second sub-word line driving signal PhDecN, which is the inverted signal of the first sub-word line driving signal PhDec. Specifically, the voltage of the first main word line drive signal GrDecN when it is high is provided by a first power supply and a second power supply, respectively, with the voltage provided by the first power supply being greater than the voltage provided by the second power supply. For example... Figure 2 As shown, Figure 2The diagram illustrates the waveforms of signals in a sub-word line driving circuit. When word line WL needs to switch from an off state to an on state, the level of the first sub-word line driving signal PhDec changes from low to high, and the level of the second sub-word line driving signal PhDecN changes from high to low. The voltage of the first main word line driving signal GrDecN, initially supplied by the second power supply V2, rises to the voltage supplied by the first power supply V1, and then decreases to the voltage supplied by the reference power supply Vss or a negative voltage. Conversely, when word line WL needs to switch from an on state to an off state, the level of the first sub-word line driving signal PhDec changes from high to low, and the level of the second sub-word line driving signal PhDecN changes from low to high. The voltage of the first main word line driving signal GrDecN, initially supplied by the reference power supply Vss, rises to the voltage supplied by the first power supply V1, and then decreases to the voltage supplied by the second power supply V2. When word line WL is in the off state, the voltage of the first master word line drive signal GrDecN is the lower voltage of the second power supply V2 instead of the higher voltage of the first power supply V1, reducing the power consumption of the sub-word line drive circuit. However, when word line WL switches from the off state to the on state, the voltage of the first master word line drive signal GrDecN needs to be switched to the voltage provided by the first power supply V1 to ensure stable operation of the sub-word line drive circuit. When word line WL in the memory array is off for a long time and then turned on for the first time, the gate-indrain leakage (GIDL) current of the pull-up transistor TU generates a high spike. Subsequently, when word line WL in the memory array is frequently turned on and off (such as during the refresh process), the voltage of the first master word line drive signal GrDecN repeatedly switches between the voltages provided by the first power supply V1 and the second power supply V2, causing the gate-indrain leakage current of the pull-up transistor TU to continuously generate certain spikes, resulting in high power consumption of the sub-word line drive circuit. Here, IG represents the gate-indrain leakage current of the pull-up transistor TU.

[0026] Based on this, the present invention provides a power supply circuit that, by setting a selection signal generation circuit and a selection circuit, can select the appropriate power supply to power the main word line driving circuit in combination with the operation performed on the word lines in the target memory array. The voltage of the first main word line driving signal does not need to be repeatedly switched between the voltages provided by the first power supply and the second power supply to reduce the power consumption of the sub-word line driving circuit.

[0027] An exemplary embodiment of the present invention provides a power supply circuit, such as... Figure 3 As shown, Figure 3A schematic diagram of a power supply circuit according to an exemplary embodiment of the present invention is shown. The power supply circuit includes a selection signal generation circuit 10 and a selection circuit 20. The selection signal generation circuit 10 generates a voltage selection signal Sel in a first state when word lines WL in the target memory array are repeatedly turned on and off. When word lines WL in the target memory array remain off, it generates a voltage selection signal Sel in a second state. The selection circuit 20 is electrically connected to the selection signal generation circuit 10, a first power supply V1, a second power supply V2, and a main word line driving circuit 30. When the voltage selection signal Sel is in the first state, it selects the first power supply V1 to supply power to the main word line driving circuit 30. When the voltage selection signal Sel is in the second state, it selects the second power supply V2 to supply power to the main word line driving circuit 30. The main word line driving circuit 30 outputs a first main word line driving signal GrDecN to the sub-word line driving circuit. The voltage provided by the first power supply V1 is greater than the voltage provided by the second power supply V2, and both the voltage values ​​provided by the first power supply V1 and the second power supply V2 are greater than the voltage value of ground (0V).

[0028] In this embodiment, the power supply circuit includes a selection signal generation circuit 10 and a selection circuit 20. The selection signal generation circuit 10 generates a voltage selection signal Sel related to the operation of word lines WL in the target memory array. The selection circuit 20 selects the corresponding power supply to power the main word line driving circuit 30 according to the voltage selection signal Sel. By combining the voltage selection signal Sel related to the operation of word lines WL to select the power supply of the main word line driving circuit 30, on the one hand, it avoids the introduction of additional power consumption by frequently switching the power supply of the main word line driving circuit 30 when word lines WL are turned on and off multiple times. On the other hand, it supplies power to the main word line driving circuit 30 with a lower voltage when word lines WL are kept off, thereby reducing the power consumption of the sub-word line driving circuit. For example, when word lines WL in the target memory array are turned on and off multiple times, the voltage when the first main word line driving signal GrDecN is at a high level is no longer as... Figure 2 Instead of repeatedly switching between the voltages provided by the first power supply V1 and the second power supply V2, the voltage provided by the first power supply V1 is maintained. In this case, the voltage at the control terminal of the pull-up transistor TU in the sub-word line drive circuit will only change between the voltage (or negative voltage) provided by the first power supply V1 and the reference power supply Vss, avoiding current spikes caused by switching to the voltage provided by the second power supply V2, thus reducing the power consumption of the sub-word line drive circuit.

[0029] For example, the memory includes multiple memory arrays, and the target memory array is one of these arrays. A memory array can be, for example, a section or a bank. By dividing the arrayed memory cells in the memory into multiple sections or banks, hierarchical access to the memory cells is possible. Each access only requires activating the desired section or bank, thereby improving data read / write speed and reducing power consumption during data read / write. Multiple on / off cycles of word lines (WL) in the target memory array refer to the time interval between each on / off cycle of a word line (WL) in the target memory array being less than a preset interval. The preset interval can range from, for example, 45 ns to 10 μs, and can be, for example, 3.9 μs, 7.8 μs, etc. Multiple on / off cycles of word lines (WL) in the target memory array can refer to the same word line (WL) being on and off multiple times, or to different word lines (WL) being on and off multiple times (e.g., different word lines (WL) being on and off sequentially). The word lines (WL) in the target memory array remain off, which can mean that all word lines (WL) in the target memory array are off and not on for a certain period of time. The state of the voltage selection signal (Sel) can be reflected by the level of the voltage selection signal Sel. For example, a high level for the voltage selection signal Sel indicates the first state, and a low level indicates the second state; or, a low level for the voltage selection signal Sel indicates the first state, and a high level indicates the second state.

[0030] When the voltage selection signal Sel is in the first state, the selection circuit 20 can connect the first power supply V1 to the main word line drive circuit 30 and disconnect the second power supply V2 from the main word line drive circuit 30, thereby selecting the first power supply V1 to power the main word line drive circuit 30. When the voltage selection signal Sel is in the second state, the selection circuit 20 can connect the second power supply V2 to the main word line drive circuit 30 and disconnect the first power supply V1 from the main word line drive circuit 30, thereby selecting the second power supply V2 to power the main word line drive circuit 30. Selecting a power supply to power the main word line drive circuit 30 means selecting the voltage provided by the selected power supply as the voltage when the first main word line drive signal GrDecN is at a high level.

[0031] When the word line WL in the target memory array switches from a closed state to an open state, the power supply of the main word line drive circuit 30 switches from the second power supply V2 to the first power supply V1. When the word line WL in the target memory array switches from an open state to a closed state, the power supply of the main word line drive circuit 30 switches from the first power supply V1 to the second power supply V2. When the word line WL in the target memory array is repeatedly turned on and off, the power supply of the main word line drive circuit 30 remains at the first power supply V1. When the word line WL in the target memory array remains closed, the power supply of the main word line drive circuit 30 remains at the second power supply V2. The voltage provided by the first power supply V1 is greater than the voltage provided by the second power supply V2.

[0032] In one embodiment, such as Figure 4 As shown, Figure 4 A schematic diagram of a power supply circuit according to an exemplary embodiment of the present invention is shown. A selection signal generation circuit 10 receives an address signal Add from a memory array and generates a voltage selection signal Sel in a first state when the address signal Add points to a target memory array. When the address signal Add points to a memory array other than the target memory array, it generates a voltage selection signal Sel in a second state.

[0033] In this embodiment, since the address signal Add is used to point to the memory array to be operated on, the selection signal generation circuit 10 can determine whether the target memory array is selected based on the received address signal Add, and thus determine whether to operate on the word line WL in the target memory array. By combining the address signal Add to generate a voltage selection signal Sel with a corresponding state, the state of the voltage selection signal Sel can correspond to the operation of the word line WL in the target memory array, thereby improving the reliability of the power supply circuit.

[0034] For example, depending on the method of partitioning the storage array, the number of address signals Add can be one or more. When the address signal Add points to the target storage array, the level of each address signal Add received by the target storage array is high. When the address signal Add points to a storage array other than the target storage array, the level of at least one address signal Add received by the target storage array is low. Therefore, it can be determined whether the address signal Add points to the target storage array by combining the level of the address signal Add received by the target storage array.

[0035] In one embodiment, such as Figure 5 As shown, Figure 5A schematic diagram of a selection signal generation circuit according to an exemplary embodiment of the present invention is shown. The selection signal generation circuit 10 includes a logic circuit 11 and a signal processing circuit 12. The logic circuit 11 receives an address signal Add and performs logical processing on the address signal Add to obtain an intermediate signal Mid. The state of the intermediate signal Mid is used to characterize whether the address signal Add points to the target memory array. The signal processing circuit 12 is electrically connected to the logic circuit 11 and the selection circuit 20, and receives a word line control signal GrEn. It processes the word line control signal GrEn and the intermediate signal Mid to obtain a voltage selection signal Sel. The word line control signal GrEn is valid when the word line WL of any memory array in the target memory repository is enabled. The target memory repository includes the target memory array.

[0036] In this embodiment, since the address signal Add needs to comprehensively reflect whether it points to the target memory array, a logic circuit 11 is set up to perform logical processing on the address signal Add, and the state of the resulting intermediate signal Mid characterizes whether the address signal Add points to the target memory array. Since the state of the word line control signal GrEn reflects whether the word line WL of any memory array in the target memory array is on, a signal processing circuit 12 is set up to process the intermediate signal Mid and the word line control signal GrEn, and the state of the resulting voltage selection signal Sel characterizes whether the word line WL of the target memory array has been repeatedly turned on and off. By setting the logic circuit 11 and the signal processing circuit 12 in the selection signal generation circuit 10, the voltage selection signal Sel can be generated by comprehensively considering both the pointing of the address signal Add and the operation of the word line WL to avoid selecting the wrong power supply to power the main word line drive circuit 30, thereby improving the reliability of the power supply circuit.

[0037] For example, the structure of logic circuit 11 is determined based on the number of address signals Add and the direction of their voltage levels. For instance, if there are two address signals Add (e.g., a first address signal Add1 and a second address signal Add2) and both are high-level and pointing to the target memory array, logic circuit 11 may include a NAND gate to perform NAND logic processing on the two address signals Add to obtain the intermediate signal Mid. If there is only one address signal Add and it is high-level and pointing to the target memory array, logic circuit 11 may include a NOT gate to perform inversion logic processing on the address signal Add to obtain the intermediate signal Mid. Logic circuit 11 can be an additional circuit set in the memory or an inherent circuit in the memory's row decoding circuit. That is, the row decoding circuit can be reused, and the intermediate signal Mid can be directly obtained by decoding the address signals Add through the row decoding circuit, thereby reducing the complexity of the power supply circuit structure.

[0038] When the word line WL of any memory array in the target repository is enabled, the word line control signal GrEn is active (either high or low). When the word lines WL of any memory array in the target repository are disabled, the word line control signal GrEn is inactive (either low or high). When the intermediate signal Mid indicates that the address signal Add points to the target memory array and the word line control signal GrEn is active, the multiple on / off cycles of the word lines WL in the target memory array result in the voltage selection signal Sel being in its first state. When the intermediate signal Mid indicates that the address signal Add does not point to the target memory array and / or the word line control signal GrEn is inactive, the word lines WL in the target memory array remain disabled, and the voltage selection signal Sel is in its second state. Note that when the word lines WL in the target memory array are repeatedly on and off, the word line control signal GrEn does not remain consistently high or low, but rather varies between high and low levels. With word lines WL in the target memory array kept off, the word line control signal GrEn remains at a high or low level.

[0039] In one embodiment, such as Figure 6 As shown, Figure 6 A schematic diagram of a selection signal generation circuit according to an exemplary embodiment of the present invention is shown. The signal processing circuit 12 includes a latch circuit 121. The latch circuit 121 is electrically connected to the logic circuit 11 and the selection circuit 20, and receives a word line control signal GrEn. It is used to latch the intermediate signal Mid under the trigger of the word line control signal GrEn to obtain a voltage selection signal Sel1.

[0040] In this embodiment, because the address signal Add does not always maintain a fixed level when pointing to the target memory array but varies between two different levels, the state of the intermediate signal Mid changes. To prevent the state of the generated voltage selection signal Sel1 from changing in real time with the state of the intermediate signal Mid, a latch circuit 121 is provided. The word line control signal GrEn is used as a trigger signal to latch the intermediate signal Mid to obtain the voltage selection signal Sel1. By latching the intermediate signal Mid through the latch circuit 121, the voltage selection signal Sel1 can always be in the first state when the address signal Add points to the target memory array, and always in the second state when the address signal Add does not point to the target memory array, thereby improving the reliability of the power supply circuit.

[0041] For example, depending on the triggering method of the latch circuit 121 and the level of the word line control signal GrEn when it is in an active state, it may be necessary to set up a logic gate to perform logical processing on the word line control signal GrEn, and output the logically processed word line control signal GrEn as a trigger signal to the latch circuit 121. For example, when the latch circuit 121 is triggered by a falling edge and the level of the word line control signal GrEn when it is in an active state is high, it is necessary to set up a NOT gate to perform inversion logic processing on the word line control signal GrEn. In this case, the latch circuit 121 latches the intermediate signal Mid under the trigger of the logically processed word line control signal GrEn. The latch circuit 121 can be, for example, an RS latch LRS, etc.

[0042] In one embodiment, the latch circuit 121 further receives a repository control signal Bnk, which is enabled when word lines WL of any memory array in the target repository are turned on. The repository control signal Bnk is used to set the voltage selection signal Sel1 to a second state before word lines WL in the target memory array are turned on for the first time, or when the target memory array is the last memory array in the target repository and word lines WL in the target memory array are turned off.

[0043] In this embodiment, before the word line WL in the target memory array is first turned on, the address signal Add does not point to the target memory array and the word line control signal GrEn is in an inactive state. Therefore, the voltage selection signal Sel1 output by the latch circuit 121 is in an uncertain state and may select the wrong power supply to power the main word line drive circuit 30. The latch circuit 121 receives the repository control signal Bnk, causing the voltage selection signal Sel1 to change from an uncertain state to a second state, thereby selecting the second power supply V2 to power the main word line drive circuit 30. Since the word line control signal GrEn is in an inactive state and cannot latch the address signal Add when the word line WL of the last memory array in the target repository is turned off, the voltage selection signal Sel1 remains in the first state. The latch circuit 121 receives the repository control signal Bnk, causing the voltage selection signal Sel1 to change from the first state to the second state, thereby switching the second power supply V2 to power the main word line drive circuit 30. By receiving the repository control signal Bnk, it is possible to prevent the main word line drive circuit 30 from being powered by the first power supply V1 while the word line WL remains closed, thereby reducing the power consumption of the sub-word line drive circuit.

[0044] For example, when the level of the repository control signal Bnk is high, the repository control signal Bnk is in an enabled state. When the level of the repository control signal Bnk is low, the repository control signal Bnk is in a disabled state. Unlike the word line control signal GrEn, when the word lines WL of the memory array in the target repository are repeatedly turned on and off, the level of the repository control signal Bnk remains high and does not change between high and low levels. When the word line WL of the last memory array in the target repository is turned off, after a preset time following the arrival of the last precharge signal, the level of the repository control signal Bnk changes from high to low.

[0045] For example, such as Figure 7 As shown, Figure 7 A schematic diagram of a power supply circuit according to an exemplary embodiment of the present invention is shown. The signal processing circuit 12 further includes a voltage domain conversion circuit 122. The voltage domain conversion circuit 122 is electrically connected between the latch circuit 121 and the selection circuit 20, and is used to convert the voltage domain of the voltage selection signal Sel1 to obtain a voltage domain-converted voltage selection signal Sel2, so as to prevent the selection circuit 20 from being unable to select the corresponding power supply according to the voltage selection signal Sel1. That is, when the signal processing circuit 12 does not include the voltage domain conversion circuit 122, the voltage selection signal Sel generated by the selection signal generation circuit 10 is the voltage selection signal Sel1. When the signal processing circuit 12 includes the voltage domain conversion circuit 122, the voltage selection signal Sel generated by the selection signal generation circuit 10 is the voltage selection signal Sel2.

[0046] In one embodiment, such as Figure 8 As shown, Figure 8 A schematic diagram of a selection signal generation circuit according to an exemplary embodiment of the present invention is shown. The latch circuit 121 includes a first switch circuit 123 and a second switch circuit 124. The first input terminal of the first switch circuit 123 is electrically connected to the logic circuit 11, and the output terminal is electrically connected to the selection circuit 20. The first input terminal of the second switch circuit 124 is electrically connected to the output terminal of the first switch circuit 123, the second input terminal receives the word line control signal GrEn, and the output terminal is electrically connected to the second input terminal of the first switch circuit 123. The first switch circuit 123 and the second switch circuit 124 are used to latch the intermediate signal Mid with the word line control signal GrEn, and to convert the voltage domain of the intermediate signal Mid to obtain the voltage selection signal Sel2.

[0047] In this embodiment, by setting a first switch circuit 123 and a second switch circuit 124 with the input and output terminals electrically connected to each other, the voltage domain of the intermediate signal Mid can be converted while the intermediate signal Mid is latched by the word line control signal GrEn. This achieves the dual functions of latching and voltage domain conversion without the need for an additional voltage domain conversion circuit 122, thereby reducing the complexity of the power supply circuit structure.

[0048] For example, the input and output terminals of the first switching circuit 123 and the second switching circuit 124 are electrically connected to each other, and respectively receive the intermediate signal Mid and the word line control signal GrEn to achieve the latching function through cross-coupling. The first switching circuit 123 and the second switching circuit 124 can be electrically connected to different power supplies, such as a first power supply V1 and a third power supply, to achieve the voltage domain switching function by connecting different power supplies. The first switching circuit 123 and the second switching circuit 124 may include multiple transistors, and the latching and voltage domain switching functions are achieved by controlling the switching on and off of the transistors.

[0049] In one embodiment, such as Figure 9 As shown, Figure 9 A schematic diagram of a signal processing circuit according to an exemplary embodiment of the present invention is shown. The first switching circuit 123 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first terminal of the first transistor T1 is electrically connected to a first power supply V1, and the second terminal is electrically connected to a selection circuit 20 to output a voltage selection signal Sel2. Its control terminal is electrically connected to a logic circuit 11. The first terminal of the second transistor T2 is electrically connected to the second terminal of the first transistor T1. The first terminal of the third transistor T3 is electrically connected to the second terminal of the second transistor T2, and the second terminal is electrically connected to a bias power supply Vbb. Its control terminal is also electrically connected to the logic circuit 11. The first terminal of the fourth transistor T4 is electrically connected to the first power supply V1, and the second terminal is electrically connected to the second terminal of the first transistor T1. Its control terminal receives an inverted signal (such as a first inverted signal SelN) of the voltage selection signal Sel2.

[0050] The second switching circuit 124 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The first terminal of the fifth transistor T5 is electrically connected to the third power supply V3, and the second terminal is electrically connected to the control terminal of the second transistor T2, which receives the word line control signal GrEn. The first terminal of the sixth transistor T6 is electrically connected to the second terminal of the fifth transistor T5, and its control terminal also receives the word line control signal GrEn. The first terminal of the seventh transistor T7 is electrically connected to the second terminal of the sixth transistor T6, and its second terminal is electrically connected to the bias power supply Vbb. Its control terminal is electrically connected to the second terminal of the first transistor T1. The first terminal of the eighth transistor T8 is electrically connected to the third power supply V3, the second terminal is electrically connected to the second terminal of the fifth transistor T5, and its control terminal is electrically connected to the second terminal of the first transistor T1.

[0051] In this embodiment, by setting multiple transistors in the first switch circuit 123 and the second switch circuit 124 respectively and connecting them electrically in the manner described above, the functions of latching and voltage domain switching can be realized simultaneously with fewer electrical components, thereby reducing the area occupied by the power supply circuit.

[0052] For example, the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are P-type transistors, and the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are N-type transistors. The word line control signal GrEn received by the fifth transistor T5 and the sixth transistor T6 can be the signal after being inverted by the NOT gate described above (such as the second inverted signal GrEnN).

[0053] With the intermediate signal Mid at a low level, the address signal Add points to the target memory array, the first transistor T1 is turned on and the third transistor T3 is turned off. The voltage selection signal Sel2 is at a high level and is in the first state, the seventh transistor T7 is turned on and the eighth transistor T8 is turned off, and the level of the control terminal of the second transistor T2 is controlled by the level of the word line control signal GrEn. Since the level of the word line control signal GrEn is high when the word line WL is on, it becomes low after being processed by inversion logic, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, causing the second transistor T2 to turn on.

[0054] When the intermediate signal Mid is high, the address signal Add either does not point to the target memory array or points to the target memory array and the word line WL of the target memory array switches. The first transistor T1 is off and the third transistor T3 is on. The voltage selection signal Sel2 depends on whether the second transistor T2 is on. Since the word line control signal GrEn is low when the word line WL is off, it becomes high after inversion logic. The fifth transistor T5 is off and the sixth transistor T6 is on, causing the second transistor T2 to turn off. At this time, the voltage selection signal Sel2 remains unchanged at its previous high level to achieve the latching function.

[0055] In one embodiment, the second switching circuit 124 further includes a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 is electrically connected between the sixth transistor T6 and the seventh transistor T7, and its control terminal receives the storage repository control signal Bnk. The first terminal of the tenth transistor T10 is electrically connected to the third power supply V3, and its second terminal is electrically connected to the second terminal of the fifth transistor T5. Its control terminal also receives the storage repository control signal Bnk. The storage repository control signal Bnk is enabled when the word line WL of any memory array in the target storage repository is turned on. The storage repository control signal Bnk is used to set the voltage selection signal Sel2 to a second state before the word line WL in the target memory array is first turned on, or when the target memory array is the last memory array in the target storage repository and the word line WL in the target memory array is turned off.

[0056] In this embodiment, by setting the ninth transistor T9 and the tenth transistor T10 in the second switching circuit 124, the main word line drive circuit 30 can be powered by the first power supply V1 while the word line WL is kept closed by using the storage control signal Bnk, thereby reducing the power consumption of the sub-word line drive circuit.

[0057] For example, before the word line WL in the target memory array is first turned on, the address signal Add is not pointing to the target memory array, and the level of the intermediate signal Mid is high. The third transistor T3 is turned on, and the level of the voltage selection signal Sel2 depends on whether the second transistor T2 is turned on. Since the level of the storage control signal Bnk is low, the tenth transistor T10 is turned on, causing the second transistor T2 to turn on, and the level of the voltage selection signal Sel2 is low (in the second state) to select the second power supply V2 to power the main word line drive circuit 30.

[0058] When the target memory array is the last memory array in the target memory repository and the word line WL in the target memory array is not enabled, the address signal Add does not point to the target memory array, and the level of the intermediate signal Mid is high. The third transistor T3 is turned on, and the level of the voltage selection signal Sel2 depends on whether the second transistor T2 is turned on. As the level of the repository control signal Bnk changes from high to low, the tenth transistor T10 turns on, causing the second transistor T2 to turn on, and the level of the voltage selection signal Sel2 is low to select the second power supply V2 to power the main word line drive circuit 30.

[0059] For example, the first switching circuit 123 further includes a matching transistor Tm. The matching transistor Tm is electrically connected between the first transistor T1 and the second transistor T2, and its control terminal is electrically connected to a fourth power supply V4. Under the action of the fourth power supply V4, the matching transistor Tm remains on. Thus, when the second switching circuit 124 includes a ninth transistor T9, the matching transistor Tm can adjust the timing of the first switching circuit 123 to match the timing of the second switching circuit 124. The matching transistor Tm can be an N-type transistor.

[0060] In one embodiment, such as Figure 5 As shown, the address signal Add includes a first address signal Add1 and a second address signal Add2. The first address signal Add1 is used to select a target storage array group from the target repository, and the second address signal Add2 is used to select a target storage array from the target storage array group.

[0061] In this embodiment, since the storage repository is divided into multiple storage array groups, and each storage array group includes multiple storage arrays, the target storage array needs to be selected from largest to smallest. By making the address signal Add include the first address signal Add1 and the second address signal Add2, the system avoids locating storage arrays with the same address in other storage array groups or other storage arrays in the target storage array group, thereby improving the reliability of the power supply circuit.

[0062] For example, when the storage array is a storage section, the storage array group can be a storage section group. The first address signal Add1 and the second address signal Add2 can both be high when pointing to the target storage array, and at least one of them can be low when pointing to a storage array other than the target storage array.

[0063] In one embodiment, such as Figure 10 As shown, Figure 10A schematic diagram of a selection circuit according to an exemplary embodiment of the present invention is shown. The selection circuit 20 includes an inverting circuit 21, an eleventh transistor T11, and a twelfth transistor T12. The inverting circuit 21 is electrically connected to the selection signal generation circuit 10 and is used to invert the voltage selection signal Sel. The first terminal of the eleventh transistor T11 is electrically connected to a first power supply V1, the second terminal is electrically connected to a main word line drive circuit 30, and the control terminal is electrically connected to the inverting circuit 21 to be controlled by the inverted voltage selection signal Sel. The first terminal of the twelfth transistor T12 is electrically connected to a second power supply V2, the second terminal is electrically connected to the second terminal of the eleventh transistor T11, and the control terminal is electrically connected to the output terminal of the selection signal generation circuit 10 to be controlled by the voltage selection signal Sel.

[0064] In this embodiment, since it is necessary to select one of the first power supply V1 and the second power supply V2 to power the main word line driving circuit 30, and it is not possible to select both power supplies to power the main word line driving circuit 30 simultaneously, it is necessary to select the two power supplies separately using two inverted signals. By setting an inverting circuit 21, an eleventh transistor T11, and a twelfth transistor T12 in the selection circuit 20, the corresponding power supply to power the main word line driving circuit 30 can be selected by selectively turning on one of the eleventh transistor T11 and the twelfth transistor T12, thereby improving the reliability of the power supply circuit.

[0065] For example, the eleventh transistor T11 and the twelfth transistor T12 can be P-type transistors. In the first state, when the voltage selection signal Sel is high, the eleventh transistor T11 is turned on and the twelfth transistor T12 is turned off, selecting the first power supply V1 to power the main word line drive circuit 30. In the second state, when the voltage selection signal Sel is low, the twelfth transistor T12 is turned on and the eleventh transistor T11 is turned off, selecting the second power supply V2 to power the main word line drive circuit 30. The inverted signal of the voltage selection signal Sel (i.e., the first inverted signal SelN) received at the control terminal of the fourth transistor T4 can be output through the inverting circuit 21.

[0066] It is understandable that the structure of the selection circuit 20 is not limited to the structure described above, but depends on the level of the voltage selection signal Sel when it is in the first state and the level when it is in the second state. For example, when the voltage selection signal Sel is in the first state when it is low and in the second state when it is high, the control terminal of the eleventh transistor T11 is electrically connected to the output terminal of the selection signal generation circuit 10, and the control terminal of the twelfth transistor T12 is electrically connected to the inverting circuit 21.

[0067] In one embodiment, when the first word line WL of the target memory array changes from an off state to an on state, the voltage selection signal Sel switches from a second state to a first state. When the last word line WL of the target memory array changes from an on state to an off state, the voltage selection signal Sel switches from the first state to the second state.

[0068] In this embodiment, when the first word line WL of the target memory array changes from a closed state to an open state, operation on the word line WL of the target memory array begins, and the voltage selection signal Sel switches from a second state to a first state to select the first power supply V1 to power the main word line drive circuit 30. When the last word line WL of the target memory array changes from an open state to a closed state, operation on the word line WL of the target memory array ends, and the voltage selection signal Sel switches from a first state to a second state to select the second power supply V2 to power the main word line drive circuit 30. By adjusting the state of the voltage selection signal Sel in conjunction with the states of the first and last word lines WL of the target memory array, it is possible to distinguish whether the word lines WL of the target memory array are frequently switched on and off or remain closed, thereby improving the reliability of the power supply circuit.

[0069] For example, such as Figure 11 As shown, Figure 11A timing diagram of signals in a power supply circuit according to an exemplary embodiment of the present invention is shown. Before time t0, word lines WL in the target memory array remain off, and the level of the storage repository control signal Bnk changes from low to high in preparation for turning on word line WL. At time t0, one word line WL in the target memory array turns on, and the levels of the first address signal Add1 and the second address signal Add2 change from low to high, followed by the level of the word line control signal GrEn changing from low to high. To avoid the voltage selection signal Sel's delayed change affecting the power supply selection, the level of the voltage selection signal Sel is changed from low to high before the level of the word line control signal GrEn changes from low to high at time t0 to select the first power supply V1 to power the main word line drive circuit 30. At time t1, the current word line WL in the target memory array turns off, and the levels of the first address signal Add1 and the second address signal Add2 change from high to low, while the level of the word line control signal GrEn changed from high to low before this. Due to the influence of latch circuit 121, the voltage selection signal Sel remains high. At time t2, another word line WL in the target memory array is turned on, and the levels of the first address signal Add1, the second address signal Add2, and the word line control signal GrEn change as at time t0. At time t3, the current word line WL in the target memory array is turned off, and the levels of the first address signal Add1, the second address signal Add2, and the word line control signal GrEn change as at time t1. Due to the influence of latch circuit 121, the voltage selection signal Sel remains high. At time t4, the word line WL in the target memory array remains off, while the word lines WL of other memory arrays in the target memory array are turned on. The triggering of the word line control signal GrEn causes the voltage selection signal Sel to change from high to low to select the second power supply V2 to power the main word line drive circuit 30. After adopting the power supply circuit provided by this invention, Figure 2 The gate-induced drain leakage current no longer generates spikes when the word line WL is frequently turned on and off, thereby reducing the power consumption of the sub-word line drive circuit.

[0070] In one embodiment, when the target storage array is in the refresh process, the voltage selection signal Sel is in a first state. When the target storage array is not refreshed or the refresh is complete, the voltage selection signal Sel is in a second state.

[0071] In this embodiment, since each word line WL of the target memory array needs to be turned on and off sequentially during the refresh process, the voltage selection signal Sel is in a first state during the refresh process and in a second state outside the refresh process. By setting the state of the voltage selection signal Sel in conjunction with whether the refresh process is in progress, the power supply to the main word line driving circuit 30 is avoided from frequently switching during the refresh process, thereby reducing the power consumption of the sub-word line driving circuit.

[0072] An exemplary embodiment of the present invention provides a memory, which includes the power supply circuit described above. The memory is disposed in an electronic device and connected to an external device (such as a processor) within the electronic device for storing data. The electronic device may be, for example, a computer, a mobile phone, a smart wearable device, etc. The power supply circuit may, for example, be disposed in the row decoding circuit of the memory.

[0073] In this invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the article or device comprising said element.

[0074] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0075] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, the intent of this invention also includes these modifications and variations.

Claims

1. A power supply circuit, characterized in that, The power supply circuit includes: A selection signal generation circuit is configured to generate a voltage selection signal in a first state when word lines in the target memory array are repeatedly turned on and off; and to generate the voltage selection signal in a second state when word lines in the target memory array remain off. The selection circuit is electrically connected to the selection signal generation circuit, the first power supply, the second power supply, and the main word line driving circuit. The selection circuit is used to select the first power supply to power the main word line driving circuit when the voltage selection signal is in the first state; and to select the second power supply to power the main word line driving circuit when the voltage selection signal is in the second state. The main word line driving circuit is used to output a first main word line driving signal to the sub-word line driving circuit, wherein the voltage provided by the first power supply is greater than the voltage provided by the second power supply.

2. The power supply circuit according to claim 1, characterized in that, The selection signal generation circuit receives the address signal of the memory array. The selection signal generation circuit is used to generate the voltage selection signal in the first state when the address signal points to the target memory array, and to generate the voltage selection signal in the second state when the address signal points to a memory array other than the target memory array.

3. The power supply circuit according to claim 2, characterized in that, The selection signal generation circuit includes: A logic circuit that receives the address signal and performs logical processing on the address signal to obtain an intermediate signal. The state of the intermediate signal is used to characterize whether the address signal points to the target memory array. A signal processing circuit is electrically connected to the logic circuit and the selection circuit, and receives a word line control signal. The signal processing circuit processes the word line control signal and the intermediate signal to obtain the voltage selection signal. The word line control signal is valid when the word line of any memory array in the target repository is enabled. The target repository includes the target memory array.

4. The power supply circuit according to claim 3, characterized in that, The signal processing circuit includes: A latch circuit is electrically connected to the logic circuit and the selection circuit, and receives the word line control signal. The latch circuit is used to latch the intermediate signal under the trigger of the word line control signal to obtain the voltage selection signal.

5. The power supply circuit according to claim 4, characterized in that, The latch circuit also receives a repository control signal, which is enabled when word lines of any memory array in the target repository are turned on. The repository control signal is used to set the voltage selection signal to the second state before word lines in the target memory array are turned on for the first time, or when the target memory array is the last memory array in the target repository and word lines in the target memory array are turned off.

6. The power supply circuit according to claim 3, characterized in that, The signal processing circuit includes: A first switching circuit, wherein the first input terminal of the first switching circuit is electrically connected to the logic circuit, and the output terminal of the first switching circuit is electrically connected to the selection circuit; A second switching circuit, wherein the first input terminal of the second switching circuit is electrically connected to the output terminal of the first switching circuit, the second input terminal of the second switching circuit receives the word line control signal, and the output terminal of the second switching circuit is electrically connected to the second input terminal of the first switching circuit; The first switching circuit and the second switching circuit are used to latch the intermediate signal with the word line control signal and to convert the voltage domain of the intermediate signal to obtain the voltage selection signal.

7. The power supply circuit according to claim 6, characterized in that, The first switching circuit includes: A first transistor, wherein a first terminal of the first transistor is electrically connected to the first power supply, a second terminal of the first transistor is electrically connected to the selection circuit to output the voltage selection signal, and a control terminal of the first transistor is electrically connected to the logic circuit. The second transistor has its first terminal electrically connected to the second terminal of the first transistor. The third transistor has a first terminal electrically connected to the second terminal of the second transistor, the second terminal of the third transistor electrically connected to a bias power supply, and a control terminal of the third transistor electrically connected to the logic circuit. The fourth transistor has a first terminal electrically connected to the first power supply, a second terminal electrically connected to the second terminal of the first transistor, and a control terminal of the fourth transistor receiving the inverted signal of the voltage selection signal. The second switching circuit includes: The fifth transistor has a first terminal electrically connected to the third power supply and a second terminal electrically connected to the control terminal of the second transistor. The control terminal of the fifth transistor receives the word line control signal. The sixth transistor has its first terminal electrically connected to the second terminal of the fifth transistor, and its control terminal receives the word line control signal. A seventh transistor, wherein the first terminal of the seventh transistor is electrically connected to the second terminal of the sixth transistor, the second terminal of the seventh transistor is electrically connected to the bias power supply, and the control terminal of the seventh transistor is electrically connected to the second terminal of the first transistor; The eighth transistor has its first terminal electrically connected to the third power supply, its second terminal electrically connected to the second terminal of the fifth transistor, and its control terminal electrically connected to the second terminal of the first transistor.

8. The power supply circuit according to claim 7, characterized in that, The second switching circuit also includes: The ninth transistor is electrically connected between the sixth transistor and the seventh transistor, and the control terminal of the ninth transistor receives the storage control signal; The tenth transistor has its first terminal electrically connected to the third power supply, its second terminal electrically connected to the second terminal of the fifth transistor, and its control terminal receiving the storage control signal. Wherein, the repository control signal is in an enabled state when the word line of any memory array in the target repository is turned on, and the repository control signal is used to put the voltage selection signal in the second state before the word line in the target memory array is turned on for the first time, or when the target memory array is the last memory array in the target repository and the word line in the target memory array is turned off.

9. The power supply circuit according to claim 2, characterized in that, The address signal includes a first address signal and a second address signal. The first address signal is used to select a target storage array group from the target repository, and the second address signal is used to select the target storage array from the target storage array group.

10. The power supply circuit according to claim 1, characterized in that, The selection circuit includes: An inverting circuit is electrically connected to the selection signal generation circuit, and the inverting circuit is used to invert the voltage selection signal. The eleventh transistor has its first terminal electrically connected to the first power supply, its second terminal electrically connected to the main word line drive circuit, and its control terminal electrically connected to the inverting circuit to be controlled by the inverted voltage selection signal. The twelfth transistor has its first terminal electrically connected to the second power supply, its second terminal electrically connected to the second terminal of the eleventh transistor, and its control terminal electrically connected to the output terminal of the selection signal generation circuit, so as to be controlled by the voltage selection signal.

11. The power supply circuit according to any one of claims 1 to 10, characterized in that, When the first word line of the target memory array changes from the off state to the on state, the voltage selection signal switches from the second state to the first state; when the last word line of the target memory array changes from the on state to the off state, the voltage selection signal switches from the first state to the second state.

12. The power supply circuit according to any one of claims 1 to 10, characterized in that, When the target storage array is in the refresh process, the voltage selection signal is in the first state; when the target storage array is not refreshed or the refresh is complete, the voltage selection signal is in the second state.

13. A memory, characterized in that, The memory includes a power supply circuit as described in any one of claims 1 to 12.

Images