Radiation-hardened SRAM memory cell circuit based on assist feedback

Abstract

The application relates to an anti-radiation SRAM memory cell circuit based on auxiliary feedback, wherein first and second memory nodes are surrounded by NMOS transistors, third and fourth memory nodes are surrounded by PMOS transistors, a polarity reinforcement structure is formed, a read-write control module adopts a double-word line mode of writing a word line to control the NMOS transistors and a low-effective read-write word line to control the PMOS transistors, an auxiliary feedback module contains four auxiliary recovery paths formed by series connection of PMOS and NMOS, two gates of each path are connected to two different memory nodes respectively, and a double-variable feedback network is formed. When single-node flipping occurs at the memory nodes or predetermined-direction double-node flipping occurs at a predetermined node pair, the auxiliary feedback module recovers the flipping nodes to correct logic values by using state combinations of other stable nodes. The circuit combines the polarity reinforcement and the auxiliary feedback mechanism, can effectively resist single particle flipping and double-node flipping, and is suitable for high-reliability storage applications such as spaceflight.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology and relates to a radiation-resistant SRAM memory cell circuit based on auxiliary feedback. Background Technology

[0002] With the rapid development of the integrated circuit industry, Static Random Access Memory (SRAM) has become a key component in high-performance integrated circuits. In aerospace electronic equipment, integrated circuit chips are exposed to space radiation environments for extended periods. When high-energy particles from cosmic rays, solar particle events, or Earth's radiation belts collide with the sensitive nodes of SRAM memory cells, a large number of electron-hole pairs are generated in the semiconductor device. These charge carriers are collected by the sensitive nodes under the influence of an electric field, forming transient current pulses. When the collected charge exceeds the node's critical charge, the memory node potential may flip, leading to a single-event upset (SWE). As CMOS process nodes continue to shrink, the capacitance and power supply voltage of SRAM memory nodes gradually decrease, and the critical charge of the memory nodes decreases accordingly, making SRAM cells more susceptible to SWE. Simultaneously, the distance between adjacent memory nodes is constantly decreasing, enhancing the charge-sharing effect. A single high-energy particle event may simultaneously affect two or even more sensitive nodes, causing dual-node or multi-node flips. Compared to single-node flips, dual-node flips simultaneously disrupt the potential states of multiple memory nodes, affecting the internal feedback recovery conditions of the cell, thus making self-recovery more difficult to achieve.

[0003] To reduce the impact of SEU on SRAM cells and improve the SEU resistance of memory cells, existing technologies mainly include the following solutions: (1) such as Figure 1 The circuit shown is a basic 6TSRAM memory cell, which consists of two PMOS transistors and four NMOS transistors. This memory cell uses the fewest number of transistors and therefore has the smallest area, but the circuit does not have any single-event upset capability.

[0004] (2) such as Figure 2 The circuit shown is a Soft Error Tolerant 10T SRAM BitCell (Quatro 10T) circuit proposed by Shah M. Jahinuzzamandeng and David J. Rennie in 2009. It consists of four PMOS transistors and six NMOS transistors, two of which are used as transmission transistors. This circuit has poor write capability, high write delay, and poor tolerance for single-node flip-flops.

[0005] (3) such as Figure 3The circuit shown is the RHSC14T cell designed by Soumya Sengupta et al. in 2025. It can recover from full node SNU and partial DNU, but DNU fault tolerance is limited to Q-S0 node pairs. Other node pairs still need to rely on a layout spacing of more than 2μm to suppress charge sharing.

[0006] (4) such as Figure 4 The circuit shown is the RH14T cell proposed by Deming Zhang et al. in 2025. This cell consists of 6 PMOS transistors and 8 NMOS transistors. It adopts a polarity hardening method to achieve full node SEU tolerance and improve write speed and power consumption. However, it can only recover the SEU of the S0-S1 node pair. Other dual-node flips cannot be self-recovered at the cell level.

[0007] (5) such as Figure 5 The circuit shown is the RT20T cell proposed by Soumya Sengupta et al. in 2025. This cell consists of 8 PMOS transistors, 8 NMOS transistors, and 4 access transistors. This structure includes four memory nodes: Q, QB, S0, and S1. It has a relatively small number of sensitive nodes, enabling full-node SNU self-recovery and sensitive node DNU self-recovery, and features fast read / write speeds and low leakage power consumption. However, this cell has a large number of transistors, resulting in a large area overhead and relatively low read stability. Summary of the Invention

[0008] To address the problems existing in the above-mentioned traditional methods, this invention proposes a radiation-resistant SRAM memory cell circuit based on auxiliary feedback, which can improve the single-event fault tolerance of SRAM memory cells and improve the recovery capability in some dual-node fault cases.

[0009] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a radiation-resistant SRAM memory cell circuit based on auxiliary feedback is provided, comprising: The storage node module contains four storage nodes; wherein the first and second storage nodes are surrounded only by NMOS transistors, and the third and fourth storage nodes are surrounded only by PMOS transistors.

[0010] The read / write control module uses a dual-word line approach, where the write word line controls the NMOS transistor and the low-active read / write word line controls the PMOS transistor. This allows the data from the first and second bit lines to be written to the storage node module during a write operation, and the storage node data to be output to the first and second bit lines during a read operation.

[0011] The pull-up holding module is connected between the power supply and the third and fourth storage nodes, and is controlled by the first and second storage nodes. It is used to cooperate with the feedback network to maintain the complementary logic states of the third and fourth storage nodes, and to provide pull-up holding for the nodes in the third and fourth storage nodes that are in a high-level state. The pull-down holding module is connected between the first storage node, the second storage node and the ground terminal. It uses a cross-coupled structure composed of two NMOS transistors to maintain the complementary logic states of the first storage node and the second storage node, and provides pull-down holding for the node in the first storage node and the second storage node that is in a low level state.

[0012] The auxiliary feedback module includes four auxiliary recovery paths. Each auxiliary recovery path consists of a PMOS transistor and an NMOS transistor connected in series and is respectively connected to the corresponding memory node and power supply or ground terminal of the memory node module. The control terminals of the auxiliary recovery paths are respectively connected to different memory nodes. When a single node flips or a predetermined pair of nodes flips in a predetermined direction, the flipped node is restored to the correct logic value through the corresponding auxiliary recovery path by using the state combination of other stable memory nodes.

[0013] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned radiation-hardened SRAM memory cell circuit based on auxiliary feedback features a polarity-hardened structure where the first and second memory nodes are surrounded only by NMOS transistors, and the third and fourth memory nodes are surrounded only by PMOS transistors. The read / write control module employs a dual-word-line approach, controlling the NMOS transistors with the write word line and the PMOS transistors with the low-activity read / write word line. The auxiliary feedback module includes four auxiliary recovery paths composed of PMOS and NMOS transistors connected in series. Each path's two gates are connected to two different memory nodes, forming a bivariate feedback network. When a single-node flip occurs, or a predetermined node pair experiences a double-node flip in a predetermined direction, the auxiliary feedback module uses the state combination of other stable nodes to restore the flipped node to the correct logic value. This circuit, combining polarity hardening and auxiliary feedback mechanisms, effectively resists single-event upsets and double-node flips, making it suitable for high-reliability storage applications such as aerospace. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a 6TSRAM circuit in the prior art; Figure 2 This is a schematic diagram of the existing Quatro 10T circuit. Figure 3 This is a schematic diagram of the existing RHSC14T circuit. Figure 4 This is a schematic diagram of the existing RH14T circuit. Figure 5 This is a schematic diagram of the existing RT20T circuit. Figure 6 This is a schematic diagram of a radiation-resistant SRAM memory cell circuit based on auxiliary feedback in one embodiment; Figure 7 This is a timing waveform diagram of a radiation-resistant SRAM memory cell based on auxiliary feedback in one embodiment; Figure 8 This is a simulation diagram of the transient waveform of a radiation-resistant SRAM memory cell based on auxiliary feedback under different times and at different nodes in one embodiment, when it is subjected to pulse injection from a double exponential current source. Figure 9 This is a comparison diagram of the noise margin of an irradiated SRAM memory cell circuit based on auxiliary feedback in one embodiment and that of an existing cell. Figure 10 This is a simulation result of read interference under read operation conditions for a radiation-resistant SRAM memory cell based on auxiliary feedback in one embodiment. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0018] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0019] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0020] In one embodiment, such as Figure 6 As shown, a radiation-resistant SRAM memory cell circuit based on auxiliary feedback is provided, comprising: The storage node module contains four storage nodes; wherein the first storage node A and the second storage node B are surrounded only by NMOS transistors, and the third storage node C and the fourth storage node D are surrounded only by PMOS transistors.

[0021] Specifically, the storage node module includes: a first storage node A, a second storage node B, a third storage node C, and a fourth storage node D. These four nodes together constitute a redundant feedback storage structure. The first and second storage nodes B are surrounded by NMOS transistors, while the third and fourth storage nodes D are surrounded by PMOS transistors, forming a polarity-hardened structure. This limits the effective disturbance direction of the storage nodes and reduces the number of sensitive nodes. By combining the polarity-hardened structure with an auxiliary recovery path, the direction of node disturbance can be limited, and the conduction of the recovery path can be controlled using undisturbed nodes, thereby improving the self-recovery capability after node disturbance.

[0022] The first storage node A and the second storage node B are surrounded by NMOS transistors, and when subjected to a single event, the main potential flip occurs from high level to low level; the third storage node C and the fourth storage node D are surrounded by PMOS transistors, and when subjected to a single event, the main potential flip occurs from low level to high level; thus forming a polarity hardening structure to limit the flip direction of the storage nodes and reduce the number of effective sensitive nodes.

[0023] The read / write control module adopts a dual-word line approach, where the write word line WWL controls the NMOS transistor and the low-active read / write word line RWWLB controls the PMOS transistor. This enables the data on the first bit line BL and the second bit line BLB to be written to the storage node module during a write operation, and the storage node data to be output to the first bit line BL and the second bit line BLB during a read operation.

[0024] Specifically, during the data holding phase, the write word line WWL is at a low level, and the active low read / write word line RWWLB is at a high level; during the data writing phase, the write word line WWL is at a high level, and the active low read / write word line RWWLB is at a low level; during the data reading phase, the write word line WWL is at a low level, the active low read / write word line RWWLB is at a low level, and the first bit line BL and the second bit line BLB are precharged to a high level.

[0025] The pull-up holding module is connected between the power supply and the third and fourth storage nodes, and is controlled by the first and second storage nodes. It is used to cooperate with the feedback network to maintain the complementary logic states of the third and fourth storage nodes, and to provide pull-up holding for the nodes in the third and fourth storage nodes that are in a high-level state. The pull-down holding module is connected between the first storage node, the second storage node and the ground terminal. It uses a cross-coupled structure composed of two NMOS transistors to maintain the complementary logic states of the first storage node and the second storage node, and provides pull-down holding for the node in the first storage node and the second storage node that is in a low level state.

[0026] Specifically, according to the polarity hardening requirements, the first storage node A and the second storage node B are surrounded by NMOS transistors, so that when subjected to a single-event disturbance, they mainly exhibit a switching trend from high level to low level; the third storage node C and the fourth storage node D are surrounded by PMOS transistors, so that when subjected to a single-event disturbance, they mainly exhibit a switching trend from low level to high level, thus forming a polarity hardening structure.

[0027] The auxiliary feedback module includes four auxiliary recovery paths. Each auxiliary recovery path consists of a PMOS transistor and an NMOS transistor connected in series and is respectively connected to the corresponding memory node and power supply or ground terminal of the memory node module. The control terminals of the auxiliary recovery paths are respectively connected to different memory nodes. When a single node flips or a predetermined pair of nodes flips in a predetermined direction, the flipped node is restored to the correct logic value through the corresponding auxiliary recovery path by using the state combination of other stable memory nodes.

[0028] Specifically, the four auxiliary recovery paths include at least one pull-up recovery path connected between the power supply terminal (VDD) and the first storage node A or the second storage node B, and a pull-down recovery path connected between the third storage node C or the fourth storage node D and the ground terminal (GND). Both the pull-up recovery path and the pull-down recovery path are PMOS transistors and NMOS transistors connected in series.

[0029] The auxiliary recovery paths all adopt a PMOS+NMOS series path, which can recover by pulling down when the node is pulled high and by pulling up when the node is pulled low (through different transistor conduction combinations), while the path of a single type of transistor can only recover in one direction.

[0030] Each PMOS+NMOS series path has two gates controlled by different storage nodes, forming a bivariate feedback. The recovery condition depends on the state of the two stable nodes, resulting in higher recovery reliability. It is not sensitive to interference with a single control node, so even if one control node is disturbed, the other control node may still ensure that the recovery path is correctly turned on, thus enhancing robustness.

[0031] The aforementioned radiation-hardened SRAM memory cell circuit based on auxiliary feedback features a polarity-hardened structure where the first and second memory nodes are surrounded only by NMOS transistors, and the third and fourth memory nodes are surrounded only by PMOS transistors. The read / write control module employs a dual-word-line approach, controlling the NMOS transistors with the write word line and the PMOS transistors with the low-activity read / write word line. The auxiliary feedback module includes four auxiliary recovery paths composed of PMOS and NMOS transistors connected in series. Each path's two gates are connected to two different memory nodes, forming a bivariate feedback network. When a single-node flip occurs, or a predetermined node pair experiences a double-node flip in a predetermined direction, the auxiliary feedback module uses the state combination of other stable nodes to restore the flipped node to the correct logic value. This circuit, combining polarity hardening and auxiliary feedback mechanisms, effectively resists single-event upsets and double-node flips, making it suitable for high-reliability storage applications such as aerospace.

[0032] In one embodiment, the read / write control module includes two PMOS transistors P1 and P2, and two NMOS transistors N1 and N2.

[0033] The sources of P1 and N1 are both connected to the second bit line. The drain of P1 is connected to the third memory node C. The gates of P1 and P2 are both connected to the low active read / write word line. The drain of N1 is connected to the second memory node. The sources of P2 and N2 are both connected to the first bit line. The gates of N1 and N2 are both connected to the write word line. The drain of P2 is connected to the fourth memory node. The drain of N2 is connected to the first memory node.

[0034] Specifically, PMOS transistor P1 is connected between the second bit line BLB and the third memory node C, and PMOS transistor P2 is connected between the first bit line BL and the fourth memory node D. The gates of both PMOS transistors P1 and PMOS transistor P2 are connected to the low active read / write word line RWWLB. NMOS transistor N1 is connected between the second bit line BLB and the second memory node B, and NMOS transistor N2 is connected between the first bit line BL and the first memory node A. The gates of both NMOS transistors N1 and NMOS transistor N2 are connected to the write word line WWL.

[0035] PMOS transistors P1 and P2 serve as read / write access transistors. The gate of PMOS transistor P1 is connected to the low-active read / write word line RWWLB, and its source and drain are connected to the second bit line BLB and the third memory node C, respectively. Similarly, the gate of PMOS transistor P2 is connected to the low-active read / write word line RWWLB, and its source and drain are connected to the first bit line BL and the fourth memory node D, respectively. NMOS transistors N1 and N2 serve as write access transistors. The gate of NMOS transistor N1 is connected to the write word line WWL, and its source and drain are connected to the second bit line BLB and the second memory node B, respectively. The gate of NMOS transistor N2 is connected to the write word line WWL, and its source and drain are connected to the first bit line BL and the first memory node A, respectively.

[0036] In one embodiment, during hold operation, the write word line WWL is at a low level and the active low read / write word line RWWLB is at a high level, which cuts off N1, N2, P1, and P2, and isolates the first storage node A, the second storage node B, the third storage node C, and the fourth storage node D from the first bit line BL and the second bit line BLB.

[0037] During a read operation, the write word line WWL is low, which turns off N1 and N2. The active low read / write word line RWWLB is low, which turns on P1 and P2. The third storage node forms a read path with the second bit line through P1, and the fourth storage node forms a read path with the first bit line through P2.

[0038] During a write operation, the write word line WWL is high and the active low read / write word line RWWLB is low, turning on N1, N2, P1, and P2. When the first bit line BL is low and the second bit line BLB is high, the first storage node A and the fourth storage node D are written to a low level, and the second storage node B and the third storage node C are written to a high level. When the first bit line BL is high and the second bit line BLB is low, the first storage node A and the fourth storage node D are written to a high level, and the second storage node B and the third storage node C are written to a low level.

[0039] Specifically, during the write phase, the write word line WWL is high (VDD), and the low active read / write word line RWWLB is low (GND). At this time, NMOS transistors N1 and N2 are turned on, and PMOS transistors P1 and P2 are also turned on. The first bit line BL and the second bit line BLB are set to complementary levels to write complementary data to memory nodes A and D, and memory nodes B and C, respectively, forming four independent write paths between the bit lines and the memory nodes.

[0040] During the read phase, the first bit line BL and the second bit line BLB are precharged to a high level (VDD). Then, the active low read / write word line RWWLB is low, the write word line WWL is low, NMOS transistors N1 and N2 are turned off, the first memory node A and the second memory node B are isolated from the bit lines, and PMOS transistors P1 and P2 are turned on. The read operation is completed through the third memory node C and the fourth memory node D, thereby reducing the interference of the bit lines to the core memory nodes during the read operation.

[0041] The read operation depends on the discharge path of the state alignment bit line of the memory node. Since the first memory node A and the second memory node B are surrounded only by NMOS, and the third memory node C and the fourth memory node D are surrounded only by PMOS, a differential voltage needs to be generated using the discharge path in the auxiliary feedback module during the read operation.

[0042] During writing, data can be written to four storage nodes simultaneously, ensuring the complete establishment of node states under the polarity-hardened structure; during reading, a discharge path is formed by the series transistors in the auxiliary feedback path, eliminating the need for an additional read port.

[0043] The low-active-read-write word line RWWLB is matched with a PMOS transistor, avoiding level shifting or inverters and simplifying the word line drive circuit.

[0044] During the write operation, a high level is written to the nodes (C, D) surrounded by PMOS transistors through PMOS transistors, and a low level is written to the nodes (A, B) surrounded by NMOS transistors through NMOS transistors. This fully utilizes the transmission characteristics of different transistors for different levels (PMOS strongly transmits high, NMOS strongly transmits low), thus improving the write margin.

[0045] In one embodiment, the pull-up holding module includes four PMOS transistors P3, P4, P5, and P6.

[0046] The sources of P3 and P4 are connected to the power supply terminal. The drain of P3 is connected to the source of P5. The drain of P5 is connected to the third memory node. The gate of P3 is connected to the first memory node. The gate of P5 is connected to the fourth memory node. The drain of P4 is connected to the source of P6. The drain of P6 is connected to the fourth memory node. The gate of P4 is connected to the second memory node. The gate of P6 is connected to the third memory node.

[0047] Specifically, PMOS transistor P3 is located in the pull-up network of the branch where the third storage node C is located, and the gate of PMOS transistor P3 is connected to the first storage node A; PMOS transistor P4 is located in the pull-up network of the branch where the fourth storage node D is located, and the gate of PMOS transistor P4 is connected to the second storage node B; PMOS transistor P5 and PMOS transistor P6 are located in the feedback hold branches where the third storage node C and the fourth storage node D are located, respectively.

[0048] PMOS transistor P3 adjusts the pull-up conduction state of the branch containing the third storage node C according to the potential of the first storage node A, and PMOS transistor P4 adjusts the pull-up conduction state of the branch containing the fourth storage node D according to the potential of node B. During the write operation, PMOS transistors P3 and P4 are used to weaken the competition between the pull-up network of the branch containing the third storage node C and the fourth storage node D and the bit line write drive, so as to reduce the write competition current and dynamic power consumption. During the hold operation, PMOS transistors P3 and P4 form a series stacked structure with the PMOS transistors in the corresponding pull-up branches to reduce the subthreshold leakage current in the hold state. During the recovery process after a single-event flip, PMOS transistors P3 and P4 are used to adjust the pull-up state of the branch containing the third storage node C and the fourth storage node D, so as to cooperate with PMOS transistors P9, NMOS transistor N3, PMOS transistor P7 and NMOS transistor N7 to complete the node recovery.

[0049] In one embodiment, the first auxiliary recovery path in the auxiliary feedback module includes a PMOS transistor P9 and an NMOS transistor N3; the source of N3 is connected to the ground terminal, the drain of N3 is connected to the drain of P9, the source of P9 is connected to the third memory node, the gate of N3 is connected to the fourth memory node, and the gate of P9 is connected to the second memory node.

[0050] Specifically, PMOS transistor P9 and NMOS transistor N3 form a first auxiliary recovery path, which is connected between the third storage node C and the ground terminal GND. The first conducting terminal of PMOS transistor P9 is connected to the third storage node C, and the second conducting terminal of PMOS transistor P9 is connected to the first conducting terminal of NMOS transistor N3. The second conducting terminal of NMOS transistor N3 is connected to the ground terminal GND. The gate of PMOS transistor P9 is connected to the second storage node B, and the gate of NMOS transistor N3 is connected to the fourth storage node D. When the first storage node A and the third storage node C simultaneously undergo a predetermined direction flip, and the first storage node A flips from high level to low level and the third storage node C flips from low level to high level, the second storage node B remains at a low level and the fourth storage node D remains at a high level. PMOS transistor P9 is turned on under the control of the second storage node B, and NMOS transistor N3 is turned on under the control of node D, so that the third storage node C discharges to the ground terminal GND through PMOS transistor P9 and NMOS transistor N3, so that the third storage node C recovers to a low level first.

[0051] When a dual-node flip occurs between the first storage node A and the third storage node C, the second storage node B and the fourth storage node D temporarily maintain their original logic states. The third storage node C first discharges to the ground terminal GND through the first auxiliary recovery path composed of PMOS transistor P9 and NMOS transistor N3 to recover. After the third storage node C recovers, it further controls the second auxiliary recovery path composed of PMOS transistor P7 and NMOS transistor N7 to charge the first storage node A from the power supply terminal VDD to recover, thereby realizing the cascade recovery of the first storage node A and the third storage node C.

[0052] The second auxiliary recovery path includes a PMOS transistor P7 and an NMOS transistor N7; the source of P7 is connected to the power supply terminal, the drain of P7 is connected to the drain of N7, the source of N7 is connected to the first memory node, the gate of P7 is connected to the third memory node, and the gate of N7 is connected to the fourth memory node.

[0053] Specifically, PMOS transistor P7 and NMOS transistor N7 form a second auxiliary recovery path, which is connected between the power supply terminal VDD and the first storage node A. The first conducting terminal of PMOS transistor P7 is connected to the power supply terminal VDD, and the second conducting terminal of PMOS transistor P7 is connected to the first conducting terminal of NMOS transistor N7. The second conducting terminal of NMOS transistor N7 is connected to the first storage node A. The gate of PMOS transistor P7 is connected to the third storage node C, and the gate of NMOS transistor N7 is connected to the fourth storage node D. After the first storage node A and the third storage node C simultaneously undergo a predetermined direction flip, the third storage node C recovers to a low level via the first auxiliary recovery path. PMOS transistor P7 is turned on under the control of the third storage node C. At the same time, the fourth storage node D remains at a high level and controls NMOS transistor N7 to turn on, so that the first storage node A is assisted in charging by the power supply terminal VDD via PMOS transistor P7 and NMOS transistor N7, so that the first storage node A recovers to a high level.

[0054] When a dual-node flip occurs between the first storage node A and the third storage node C, the second storage node B and the fourth storage node D temporarily maintain their original logic states. The third storage node C first discharges to the ground terminal GND through the first auxiliary recovery path composed of PMOS transistor P9 and NMOS transistor N3 to recover. After the third storage node C recovers, it further controls the second auxiliary recovery path composed of PMOS transistor P7 and NMOS transistor N7 to charge the first storage node A from the power supply terminal VDD to recover, thereby realizing the cascade recovery of the first storage node A and the third storage node C.

[0055] The third auxiliary recovery path includes PMOS transistor P8 and NMOS transistor N8; the source of P8 is connected to the power supply terminal, the drain of P8 is connected to the drain of N8, the source of N8 is connected to the second memory node, the gate of P8 is connected to the fourth memory node, and the gate of N8 is connected to the third memory node.

[0056] The fourth auxiliary recovery path includes a PMOS transistor P10 and an NMOS transistor N4; the source of N4 is connected to ground, the drain of N4 is connected to the drain of P10, the source of P10 is connected to the fourth memory node, the gate of N4 is connected to the second memory node, and the gate of P10 is connected to the first memory node.

[0057] Specifically, the third storage node C is connected to the ground terminal through a first auxiliary recovery path consisting of PMOS transistor P9 and NMOS transistor N3, and the first storage node A is connected to the power supply terminal through a second auxiliary recovery path consisting of PMOS transistor P7 and NMOS transistor N7. When the first storage node A and the third storage node C undergo a predetermined direction flip, the third storage node C first recovers through the first auxiliary recovery path via assisted discharge, and then the first storage node A recovers through the second auxiliary recovery path via assisted charging.

[0058] PMOS transistor P10 and NMOS transistor N4 are connected in series between the fourth memory node D and the ground terminal GND. The gate of PMOS transistor P10 is connected to the first memory node A, and the gate of NMOS transistor N4 is connected to node B. PMOS transistor P8 and NMOS transistor N8 are connected in series between the power supply terminal VDD and the second memory node B. The gate of PMOS transistor P8 is connected to the fourth memory node D, and the gate of NMOS transistor N8 is connected to the third memory node C.

[0059] PMOS transistor P9 and NMOS transistor N3 form the first auxiliary recovery path, PMOS transistor P7 and NMOS transistor N7 form the second auxiliary recovery path, PMOS transistor P8 and NMOS transistor N8 form the third auxiliary recovery path, and PMOS transistor P10 and NMOS transistor N4 form the fourth auxiliary recovery path. These auxiliary recovery paths, in the hold state, work with the feedback network to maintain the complementary state of the nodes and provide an auxiliary recovery path after a single node disturbance. The first and second auxiliary recovery paths are also used to form a cascaded recovery path where C recovers first and A recovers later when two nodes flip in the predetermined AC direction. PMOS transistor P10, NMOS transistor N4, PMOS transistor P8, and NMOS transistor N8 are located in the auxiliary feedback module to work with storage nodes A, B, C, and D to maintain complementary logic states and improve recovery stability after flipping. The gate of PMOS transistor P3 is connected to the first memory node A, and its source and drain are connected to the power supply terminal VDD and the pull-up network of the branch containing the third memory node C, respectively. The gate of PMOS transistor P4 is connected to the second memory node B, and its source and drain are connected to the power supply terminal VDD and the pull-up network of the branch containing the fourth memory node D, respectively. During write operations, PMOS transistors P3 and P4 adjust the conduction state of their corresponding pull-up branches according to the potentials of nodes A and B to reduce the competition between the pull-up network and the bit line write drive and improve the write speed. In the hold state, PMOS transistors P3 and P4, together with their corresponding pull-up transistors, form a transistor stack structure to reduce subthreshold leakage current. When a single node flip occurs, PMOS transistors P3 and P4 improve the recovery margin after node disturbance by adjusting the conduction state of the pull-up branches containing nodes C and D, which helps to increase the critical charge for single node flip.

[0060] In one embodiment, the pull-down holding module includes two NMOS transistors N5 and N6.

[0061] The drain of N5 and the gate of N6 are both connected to the first memory node, the source of N5 and the source of N6 are connected to the ground terminal, and the gate of N5 and the drain of N6 are both connected to the second memory node.

[0062] Specifically, NMOS transistors N5 and NMOS transistors N6 are respectively located in the feedback hold branch where the first storage node A and the second storage node B are located.

[0063] When the first storage node A is low and the second storage node B is high, N5 is turned on to latch the first storage node A at a low level; when the first storage node A is high and the second storage node B is low, N6 is turned on to latch the second storage node B at a low level.

[0064] In one specific embodiment, the gate width / gate length of NMOS transistors N3 and N4 is 280nm / 30nm; the gate width / gate length of NMOS transistors N5 and N6 is 250nm / 30nm; the gate width / gate length of PMOS transistors P3, P4, P5, and P6 is 140nm / 30nm; and the gate width / gate length of PMOS transistors P1, P2, P7, P8, P9, P10, and NMOS transistors N1, N2, N7, and N8 is 100nm / 30nm. It should be noted that the above transistor dimensions are a preferred embodiment, and those skilled in the art can adapt the transistor dimensions according to specific process nodes, supply voltages, and performance requirements. The transistor dimensions do not constitute a limitation on the scope of protection of this invention.

[0065] In one specific embodiment, such as Figure 6 As shown, an auxiliary feedback-based radiation-hardened SRAM memory cell circuit (RHB18T) is provided. Its structure mainly includes 10 PMOS transistors and 8 NMOS transistors. The 10 PMOS transistors are defined as P1, P2, P3, P4, P5, P6, P7, P8, P9, and P10; the 8 NMOS transistors are defined as N1, N2, N3, N4, N5, N6, N7, and N8. The memory cell includes a first memory node A, a second memory node B, a third memory node C, and a fourth memory node D. The first and second memory nodes A and B are surrounded by NMOS transistors, and the third and fourth memory nodes C and D are surrounded by PMOS transistors, thus forming a polarity-hardened structure. PMOS transistors P1 and P2 serve as read / write access transistors, and NMOS transistors N1 and N2 serve as write access transistors. PMOS transistor P9 and NMOS transistor N3 are connected in series to form a first auxiliary recovery path, connected between the third memory node C and the ground terminal GND. PMOS transistor P7 and NMOS transistor N7 are connected in series to form a second auxiliary recovery path, which is connected between the power supply terminal VDD and the first memory node A. PMOS transistors P3 and P4 serve as branch control transistors, which work in conjunction with the auxiliary recovery path to enhance recovery capability, reduce write contention, and reduce leakage power consumption in the hold state.

[0066] The specific structure of this radiation-resistant SRAM memory cell circuit based on auxiliary feedback includes: the drain of PMOS transistor P5, the gate of PMOS transistor P7, the gate of PMOS transistor P6, the gate of NMOS transistor N8, and the source of PMOS transistor P9 are electrically connected to the third memory node C; the source of PMOS transistor P10, the drain of PMOS transistor P6, the gate of PMOS transistor P5, the gate of PMOS transistor P8, the gate of NMOS transistor N7, and the gate of NMOS transistor N3 are electrically connected to the fourth memory node D; and the drain of NMOS transistor N5 and NMOS transistor P9 are electrically connected to the third memory node C. The source of transistor N7, the gate of PMOS transistor P10, the gate of PMOS transistor P3, and the gate of NMOS transistor N6 are electrically connected to memory node A. The drain of NMOS transistor N6, the source of NMOS transistor N8, the gate of NMOS transistor N5, the gate of PMOS transistor P9, the gate of PMOS transistor P4, and the gate of NMOS transistor N4 are electrically connected to the second memory node B. The first memory node A and the second memory node B are surrounded by NMOS transistors, and the third memory node C and the fourth memory node D are surrounded by PMOS transistors. This constitutes a polarity-reinforced structure. The source of PMOS transistor P3 is connected to VDD, and the drain of PMOS transistor P3 is electrically connected to the source of PMOS transistor P5; the source of PMOS transistor P4 is connected to VDD, and the drain of PMOS transistor P4 is electrically connected to the source of PMOS transistor P6; the source of PMOS transistor P7 is connected to VDD, and the drain of PMOS transistor P7 is electrically connected to the drain of NMOS transistor N7; the source of PMOS transistor P8 is connected to VDD, and the drain of PMOS transistor P8 is electrically connected to the drain of NMOS transistor N8. Connections: The source of NMOS transistor N3 is grounded, and the drain of NMOS transistor N3 is electrically connected to the drain of PMOS transistor P9; the source of NMOS transistor N5 is grounded, and the drain of NMOS transistor N5 is electrically connected to the source of NMOS transistor N7; the source of NMOS transistor N6 is grounded, and the drain of NMOS transistor N6 is electrically connected to the source of NMOS transistor N8; the source of NMOS transistor N4 is grounded, and the drain of NMOS transistor N4 is electrically connected to the drain of PMOS transistor P10.The gate of PMOS transistor P1 is electrically connected to the low-active read / write word line RWWLB, the drain is electrically connected to the memory node C, and the source is electrically connected to the second bit line BLB; the gate of PMOS transistor P2 is electrically connected to the low-active read / write word line RWWLB, the drain is electrically connected to the memory node D, and the source is electrically connected to the first bit line BL; the gate of NMOS transistor N1 is electrically connected to the write control word line WWL, the drain of NMOS transistor N1 is electrically connected to the second memory node B, and the source of NMOS transistor N1 is electrically connected to the second bit line BLB; the gate of NMOS transistor N2 is electrically connected to the write control word line WWL, the drain of NMOS transistor N2 is electrically connected to the memory node A, and the source of NMOS transistor N2 is electrically connected to the first bit line BL; that is, NMOS transistors N1, NMOS transistor N2, PMOS transistor P1, and PMOS transistor P2 act as transmission transistors.

[0067] Compared with the prior art, the present invention includes 10 PMOS transistors and 8 NMOS transistors. The first storage node A and the second storage node B are surrounded by NMOS transistors, and the third storage node C and the fourth storage node D are surrounded by PMOS transistors, forming a polarity-hardened structure. At the same time, the present invention uses PMOS transistor P9 and NMOS transistor N3 to form a first auxiliary recovery path and PMOS transistor P7 and NMOS transistor N7 to form a second auxiliary recovery path, which improves the self-recovery capability of the storage nodes after a single event flip and improves the recovery capability in some dual-node flip cases. In addition, the present invention reduces write contention and hold-state leakage power consumption through PMOS transistors P3 and P4, and reduces read interference through read-write separation access. Therefore, the present invention can improve radiation resistance while taking into account write speed, read stability and power consumption.

[0068] In the radiation-hardened SRAM memory cell circuit based on auxiliary feedback, the gate length of all NMOS transistors and all PMOS transistors is 30nm; the gate width of NMOS transistors N3 and N4 is 280nm, and the gate width of NMOS transistors N5 and N6 is 250nm; the gate width of PMOS transistors P3, P4, P5, and P6 is 140nm; and the gate width of PMOS transistors P1, P2, P7, P8, P9, P10, NMOS transistors N1, N2, N7, and N8 is 100nm. The NMOS transistors N3 and N4 employ larger gate widths to enhance the pull-down drive capability during the dual-node flip-over recovery process, accelerating the discharge of the flip-over node to ground. The PMOS transistors P3 and P4 use intermediate sizes to achieve a balance between suppressing write competition current and controlling leakage current in the hold-state. The remaining transistors use the smallest possible size to control the total unit area. Using NMOS and PMOS transistors of the above dimensions allows the RHB18T cell to achieve a good trade-off between radiation resistance, read / write speed, power consumption, and area. It should be noted that the above transistor dimensions are only a preferred embodiment; those skilled in the art can adapt the transistor dimensions according to specific process nodes, supply voltages, and performance requirements. Furthermore, the working principle of the radiation-resistant SRAM memory cell based on auxiliary feedback proposed in this application is as follows: (1) During the hold phase, the low active read / write word line RWWLB is high, the write word line WWL is low, and NMOS transistors N1, NMOS transistor N2, PMOS transistors P1, and PMOS transistor P2 are all off. The first storage node A, the second storage node B, the third storage node C, and the fourth storage node D are isolated from the first bit line BL and the second bit line BLB. The cell maintains a steady state through a cross-coupling structure. Assuming the stored data is "1" (nodes A=1, B=0, C=0, D=1), the feedback network and auxiliary recovery path inside the storage cell jointly maintain the corresponding node potentials, keeping the first storage node A and the fourth storage node D at a high level, and the second storage node B and the third storage node C at a low level.

[0069] (2) During the data writing stage, the low active read / write word line RWWLB is at a low level, the write word line WWL is at a high level, and PMOS transistors P1 and P2, NMOS transistors N1 and NMOS transistor N2 are all turned on.

[0070] When data "0" is written, the first bit line BL is set to low level by the write drive circuit, the second bit line BLB is set to high level by the write drive circuit, the first storage node A and the fourth storage node D are written to low level via NMOS transistor N2 and PMOS transistor P2 respectively, and the second storage node B and the third storage node C are written to high level via NMOS transistor N1 and PMOS transistor P1 respectively.

[0071] When the data "1" is written, the first bit line BL is set to high level by the write drive circuit, the second bit line BLB is set to low level by the write drive circuit, the first storage node A and the fourth storage node D are written to high level via NMOS transistor N2 and PMOS transistor P2 respectively, and the second storage node B and the third storage node C are written to low level via NMOS transistor N1 and PMOS transistor P1 respectively.

[0072] During the writing process, PMOS transistors P3 and PMOS transistor P4 adjust the conduction state of the corresponding pull-up branches according to the potentials of the first storage node A and the second storage node B, thereby reducing the competition between the pull-up network and the bit line write driver, thus reducing the write competition current and dynamic power consumption, and improving the write speed.

[0073] (3) During the data reading phase, the active read / write word line RWWLB is low, the write word line WWL is low, NMOS transistors N1 and N2 are off, and PMOS transistors P1 and PMOS transistor P2 are on. The first bit line BL and the second bit line BLB are precharged to high.

[0074] Assuming the cell stores data "1", i.e., storage nodes A=1, B=0, C=0, D=1, and the third storage node C is at a low level, the second bit line BLB forms a readout path with the third storage node C through the PMOS transistor P1. The pre-charge on the second bit line BLB is transferred to node C, causing the voltage of the second bit line BLB to drop. The first bit line BL is connected to the high-level fourth storage node D, and its voltage remains essentially at the pre-charge high level. Once a voltage difference that can be detected by a sensitive amplifier is formed between the bit lines, the data readout is completed.

[0075] Since NMOS transistors N1 and N2 are turned off during read operations, the first core storage node A and the second core storage node B are isolated from the bit lines. Therefore, the disturbance to the core storage state caused by the bit line readout process is effectively suppressed, thereby improving the stability of read operations.

[0076] (4) In terms of resistance to single-event upsets, a polarity-reinforced structure is adopted: the first storage node A and the second storage node B are surrounded by NMOS transistors, and only a flip from high level to low level ("1"→"0") may occur during a single-event upset; the third storage node C and the fourth storage node D are surrounded by PMOS transistors, and only a flip from low level to high level ("0"→"1") may occur during a single-event upset. Taking the storage of "1" (A=1, B=0, C=0, D=1) as an example, if the first storage node A flips to "0" due to a SNU caused by high-energy particle bombardment, at this time, NMOS transistor N6 is cut off, and PMOS transistors P3 and P10 are turned on, but the second storage node B, the third storage node C and the fourth storage node D are not affected. Since the fourth storage node D remains "1", NMOS transistor N7 continues to be turned on; at the same time, the gate of PMOS transistor P7 is connected to the third storage node C (remaining "0"), and P7 is in the on state. Therefore, the power supply VDD charges the first storage node A via the second auxiliary recovery path formed by PMOS transistor P7 and NMOS transistor N7, restoring the first storage node A to "1". If the third storage node C experiences a SNU and flips to "1", PMOS transistors P6 and P7 are turned off, and NMOS transistor N8 is turned on, while other nodes are unaffected. Since the second storage node B remains "0", PMOS transistor P9 is turned on; and the fourth storage node D remains "1", NMOS transistor N3 is turned on. Therefore, the third storage node C discharges to the ground terminal GND via the first auxiliary recovery path formed by PMOS transistor P9 and NMOS transistor N3, restoring node C to "0". Similarly, when storing data "0" (nodes A=0, B=1, C=1, D=0), the second storage node B and the fourth storage node D are the sensitive nodes under the corresponding polarity. If the second storage node B flips from high to low, the fourth storage node D and the third storage node C maintain their original logic states. The feedback branch containing PMOS transistor P8 and NMOS transistor N8 provides an auxiliary charging recovery path for the second storage node B, allowing it to return to a high level. If the fourth storage node D flips from low to high, the feedback branch containing PMOS transistor P10 and NMOS transistor N4 provides an auxiliary discharging recovery path for node D, allowing it to return to a low level. Therefore, this invention can improve the self-recovery capability of each storage node after a single node flip in both storage states.

[0077] In the case of dual-node switching, taking the simultaneous switching of node A and the third storage node C when storing data "1" as an example, the first storage node A switches from high to low, and the third storage node C switches from low to high. At this time, the second storage node B and the fourth storage node D maintain their original logic states for a short period of time, i.e., B=0 and D=1. The third storage node C first discharges to the ground terminal GND through the first auxiliary recovery path composed of PMOS transistor P9 and NMOS transistor N3; when the third storage node C recovers to the low level, PMOS transistor P7 turns on, and at the same time, the fourth storage node D remains at a high level, causing NMOS transistor N7 to turn on. The first storage node A recovers through the second auxiliary recovery path composed of PMOS transistor P7 and NMOS transistor N7, receiving auxiliary charging from the power supply terminal VDD. Thus, the first storage node A and node C can achieve cascaded recovery through two-stage auxiliary recovery paths.

[0078] It should be noted that this application primarily improves the tolerance to single-node flips and some dual-node or multi-node flips, especially applicable to situations where the first storage node A and the third storage node C simultaneously flip in a predetermined direction. For multi-node flips under different data states and different node combinations, the recovery capability can be determined through simulation or testing based on specific circuit dimensions, process conditions, and flip intensity.

[0079] Compared with existing technologies, the radiation-hardened SRAM memory cell based on auxiliary feedback proposed in this application, when only considering the improvement of the circuit structure's radiation resistance performance, if the memory nodes of the circuit are bombarded by particles, since the first memory node A and the second memory node B are surrounded by NMOS transistors, and the third memory node C and the fourth memory node D are surrounded by PMOS transistors, according to the polarity hardening principle, when spatial particles bombard sensitive nodes, the nodes surrounded by NMOS transistors only generate a voltage pulse from "1" to "0", and the nodes surrounded by PMOS transistors only generate a voltage pulse from "0" to "1", thereby restricting single-particle flipping to a single direction and significantly reducing the number of equivalent sensitive nodes. Based on this, the present invention further introduces an auxiliary feedback recovery path: when node A undergoes a "1" to "0" flip, it is charged back to "1" through a second auxiliary recovery path composed of P7 and N7; when node C undergoes a "0" to "1" flip, it is discharged back to "0" through a first auxiliary recovery path composed of P9 and N3. For critical memory nodes undergoing dual-node flips to AC, two-stage auxiliary recovery paths are cascaded and work together to complete the recovery sequentially. This enables the circuit to achieve self-recovery after a single-node flip under simulation conditions and exhibits fault-tolerant characteristics for some dual-node or multi-node flips. Simultaneously, through the branch control of PMOS transistors P3 and P4, competing current paths are weakened during the write process to reduce write power consumption. In the hold state, transistor stacking is formed to suppress subthreshold leakage current. When a dual-node flip occurs, the conduction state of relevant feedback branches is adjusted. Combined with a read-write separation architecture, read interference is reduced. Therefore, while improving radiation resistance, write speed is improved, power consumption is reduced, and high read stability is achieved.

[0080] The following is about... Figure 1 The prior art shown includes a 6TSRAM circuit, such as... Figure 2 The Quatro10T circuit shown in the prior art, such as Figure 3 The prior art shown includes the RHSC14T circuit, such as... Figure 4 The RH14T circuit shown in the prior art, such as Figure 5 The RT20T circuit shown in the prior art is similar to... Figure 6 The radiation-resistant SRAM memory cell circuit based on auxiliary feedback shown is analyzed in the following performance comparison: (1) The radiation-resistant SRAM memory cell circuit based on auxiliary feedback proposed in this application was simulated (simulation conditions: Corner: TT; Temperature: 25℃; VDD: 0.9V), and the results are as follows: Figure 7 The timing waveform diagram is shown below. Figure 7It can be seen that the radiation-resistant SRAM memory cell based on auxiliary feedback proposed in this application can realize the normal memory node to perform operations of writing "1", reading "1", writing "0" and reading "0".

[0081] (2) The radiation-resistant SRAM memory cell circuit based on auxiliary feedback proposed in this application was simulated (simulation conditions: VDD: 0.9V), and the results are as follows: Figure 8 The diagram shows a transient waveform simulation of a radiation-hardened SRAM memory cell based on auxiliary feedback, subjected to pulse injections from a double exponential current source at different times and nodes. Figure 8 It can be seen that under the above simulation conditions, the radiation-resistant SRAM memory cell circuit based on auxiliary feedback proposed in this application can achieve self-recovery after a single node flip and exhibits good tolerance to some multi-node flips.

[0082] (3) For example Figure 1 The prior art shown includes a 6TSRAM circuit, such as... Figure 2 The Quatro10T circuit shown in the prior art, such as Figure 3 The prior art shown includes the RHSC14T circuit, such as... Figure 4 The RH14T circuit shown in the prior art, such as Figure 5 The RT20T circuit shown in the prior art is similar to... Figure 6 The radiation-resistant SRAM memory cell circuit based on auxiliary feedback shown was simulated and compared. The simulation conditions were: Corner: TT; Temperature: 25℃; VDD: 0.9V, resulting in the following... Figure 9 The comparison charts shown are for HSNM, RSNM, and WSNM. (From...) Figure 9 It can be seen that the radiation-resistant SRAM memory cell circuit based on auxiliary feedback proposed in this application has a high static noise margin, indicating that its operational stability is good.

[0083] like Figure 10 As shown, under read operation conditions, when a voltage noise disturbance is applied to the third memory node C or the fourth memory node D, the core memory nodes A or B may experience a certain voltage change. This is because the potential change of the read node alters the conduction state of the relevant feedback transistor, causing a change in the equivalent impedance of the corresponding feedback branch. However, within the noise scan range, no irreversible state flipping occurs in the memory cell. This result indicates that because NMOS transistors N1 and N2 are turned off during read operations, core memory nodes A and B are isolated from the bit lines, effectively suppressing the influence of the bit line readout process on the core memory state, thereby significantly reducing read interference and improving read stability.

[0084] (4) For example Figure 1The prior art shown includes a 6TSRAM circuit, such as... Figure 2 The Quatro10T circuit shown in the prior art, such as Figure 3 The prior art shown includes the RHSC14T circuit, such as... Figure 4 The RH14T circuit shown in the prior art, such as Figure 5 The RT20T circuit shown in the prior art is similar to... Figure 6 The radiation-resistant SRAM memory cell based on auxiliary feedback is simulated and compared (simulation conditions: Corner: TT; Temperature: 25℃; VDD: 0.9V), and the simulation comparison results of circuit area, read / write time and power consumption are shown in Table 1 below.

[0085] Table 1. Simulation comparison results of circuit area, read / write time, and power consumption.

[0086] As can be seen from Table 1, compared with the five SRAM memory cell circuits in the prior art, the radiation-hardened SRAM memory cell based on auxiliary feedback proposed in this application has the lowest retention power consumption and lower dynamic power consumption. Moreover, the write operation speed proposed in this application is comparable to that of the RHSC14T circuit in the prior art, slightly lower than that of the 6TSRAM circuit, and far better than the other existing SRAM memory cell circuits. Therefore, the embodiments of the present invention can improve the write operation speed and reduce the memory cell power consumption compared with some existing hardened SRAM memory cells by appropriately increasing the cell area and sacrificing some read operation speed.

[0087] (5) For example Figure 1 The prior art shown includes a 6TSRAM circuit, such as... Figure 2 The Quatro10T circuit shown in the prior art, such as Figure 3 The prior art shown includes the RHSC14T circuit, such as... Figure 4 The RH14T circuit shown in the prior art, such as Figure 5 The RT20T circuit shown in the prior art is similar to... Figure 6 The critical charge comparison results of the radiation-resistant SRAM memory cell circuit based on auxiliary feedback shown are obtained by simulation (simulation conditions: Corner: TT; Temperature: 25℃; VDD: 0.9V). Table 2 below shows the critical charge comparison results.

[0088] Table 2 Comparison results of critical charge

[0089] As can be seen from Table 2, compared with the five SRAM memory cell circuits in the prior art, the radiation-resistant SRAM memory cell based on auxiliary feedback proposed in this application has a higher single-node flip critical charge and a higher double-node flip critical charge, indicating that the radiation-resistant SRAM memory cell circuit based on auxiliary feedback proposed in this application has a strong resistance to single-event disturbances under the above simulation conditions.

[0090] In summary, this invention limits the disturbance direction of memory nodes through a polarity-reinforced structure and provides auxiliary recovery for predetermined node flips via a first and second auxiliary recovery path. This improves the single-event fault tolerance of SRAM memory cells and enhances self-recovery capabilities in some dual-node flip scenarios. Furthermore, this invention reduces pull-up contention and hold-state leakage during write operations using PMOS transistors P3 and P4, and reduces read interference by isolating core memory nodes A and B during read operations. Therefore, this invention achieves a good overall balance between radiation resistance, read / write speed, stability, and power consumption.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.

Claims

1. A radiation-resistant SRAM memory cell circuit based on auxiliary feedback, characterized in that, include: The storage node module contains four storage nodes; wherein the first and second storage nodes are surrounded only by NMOS transistors, and the third and fourth storage nodes are surrounded only by PMOS transistors; The read / write control module adopts a dual-word line method, where the write word line controls the NMOS transistor and the low-active read / write word line controls the PMOS transistor. This enables the data from the first bit line and the second bit line to be written to the storage node module during a write operation, and the storage node data to be output to the first bit line and the second bit line during a read operation. The pull-up holding module is connected between the power supply and the third and fourth storage nodes, and is controlled by the first and second storage nodes. It is used to cooperate with the feedback network to maintain the complementary logic states of the third and fourth storage nodes, and to provide pull-up holding for the nodes in the third and fourth storage nodes that are in a high-level state. The pull-down holding module is connected between the first storage node, the second storage node and the ground terminal. It uses a cross-coupled structure composed of two NMOS transistors to maintain the complementary logic states of the first storage node and the second storage node, and provides pull-down holding for the node in the first storage node and the second storage node that is in a low level state. The auxiliary feedback module includes four auxiliary recovery paths. Each auxiliary recovery path consists of a PMOS transistor and an NMOS transistor connected in series, and is respectively connected to the corresponding memory node and power supply or ground terminal of the memory node module. The control terminals of the auxiliary recovery paths are respectively connected to different memory nodes. When a single memory node flips or a predetermined pair of memory nodes flips in a predetermined direction, the flipped node is restored to the correct logic value through the corresponding auxiliary recovery path using the state combination of other stable memory nodes. The predetermined pair of memory nodes includes a pair consisting of a first memory node and a third memory node.

2. The radiation-resistant SRAM memory cell circuit based on auxiliary feedback according to claim 1, characterized in that, The read / write control module includes: two PMOS transistors P1 and P2, and two NMOS transistors N1 and N2; The sources of P1 and N1 are both connected to the second bit line. The drain of P1 is connected to the third memory node C. The gates of P1 and P2 are both connected to the low active read / write word line. The drain of N1 is connected to the second memory node. The sources of P2 and N2 are both connected to the first bit line. The gates of N1 and N2 are both connected to the write word line. The drain of P2 is connected to the fourth memory node. The drain of N2 is connected to the first memory node.

3. The radiation-resistant SRAM memory cell circuit based on auxiliary feedback according to claim 2, characterized in that, During hold operation, the write word line is at a low level, and the active low read / write word line is at a high level, which cuts off N1, N2, P1, and P2, isolating the four memory nodes from the first bit line and the second bit line. During a read operation, the write word line WWL is low, which cuts off N1 and N2. The active low read / write word line is low, which turns on P1 and P2. The third storage node forms a read path with the second bit line through P1, and the fourth storage node forms a read path with the first bit line through P2. During a write operation, the write word line is high and the active low read / write word line is low, turning on N1, N2, P1, and P2. When the first bit line is low and the second bit line is high, the first and fourth memory nodes are written to a low level, and the second and third memory nodes are written to a high level. When the first bit line is high and the second bit line is low, the first and fourth memory nodes are written to a high level, and the second and third memory nodes are written to a low level.

4. The radiation-resistant SRAM memory cell circuit based on auxiliary feedback according to claim 1, characterized in that, The pull-up holding module includes four PMOS transistors: P3, P4, P5, and P6. The sources of P3 and P4 are connected to the power supply terminal. The drain of P3 is connected to the source of P5. The drain of P5 is connected to the third memory node. The gate of P3 is connected to the first memory node. The gate of P5 is connected to the fourth memory node. The drain of P4 is connected to the source of P6. The drain of P6 is connected to the fourth memory node. The gate of P4 is connected to the second memory node. The gate of P6 is connected to the third memory node.

5. The radiation-resistant SRAM memory cell circuit based on auxiliary feedback according to claim 1, characterized in that, The second auxiliary recovery path in the auxiliary feedback module includes PMOS transistor P7 and NMOS transistor N7; the third auxiliary recovery path includes PMOS transistor P8 and NMOS transistor N8; the first auxiliary recovery path includes PMOS transistor P9 and NMOS transistor N3; and the fourth auxiliary recovery path includes PMOS transistor P10 and NMOS transistor N4. The source of P7 is connected to the power supply terminal, the drain of P7 is connected to the drain of N7, the source of N7 is connected to the first memory node, the gate of P7 is connected to the third memory node, and the gate of N7 is connected to the fourth memory node. The source of P8 is connected to the power supply terminal, the drain of P8 is connected to the drain of N8, the source of N8 is connected to the second memory node, the gate of P8 is connected to the fourth memory node, and the gate of N8 is connected to the third memory node. The source of N3 is connected to the ground terminal, the drain of N3 is connected to the drain of P9, the source of P9 is connected to the third memory node, the gate of N3 is connected to the fourth memory node, and the gate of P9 is connected to the second memory node. The source of N4 is connected to the ground terminal, the drain of N4 is connected to the drain of P10, the source of P10 is connected to the fourth memory node, the gate of N4 is connected to the second memory node, and the gate of P10 is connected to the first memory node.

6. The radiation-resistant SRAM memory cell circuit based on auxiliary feedback according to claim 1, characterized in that, The pull-down holding module includes two NMOS transistors N5 and N6; The drain of N5 and the gate of N6 are both connected to the first memory node, the source of N5 and the source of N6 are connected to the ground terminal, and the gate of N5 and the drain of N6 are both connected to the second memory node.

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