A simple and low-cost n-ary fast switching power supply square wave modulation circuit

Abstract

This application relates to a simple and low-cost n-ary fast-switching power supply square wave modulation circuit. It mainly includes at least one stage of binary basic modulation circuit, which includes a PMOS transistor and a pull-down resistor. The source (S) and gate (G) of the PMOS transistor are both connected to the first level terminal V1, the drain (D) is connected to the second level terminal V2, and the gate (G) is connected to one end of the pull-down resistor, while the other end of the pull-down resistor is grounded. When the binary basic modulation circuit has multiple stages, these stages are cascaded sequentially. In each newly added stage, the drain (D) of the PMOS transistor is connected to a new level terminal. The output level values ​​of all level terminals decrease sequentially along the cascading direction, realizing the switching of the output terminal Vout between multiple levels and completing the n-ary square wave modulation. This application solves the technical problems of existing technologies that cannot simultaneously meet the requirements of fast modulation speed, good waveform integrity, convenient expansion to multiple levels, low cost, and low complexity.

Description

Technical Field

[0001] This application relates to the field of square wave modulation technology, and in particular to a simple and low-cost n-ary fast switching power supply square wave modulation circuit. Background Technology

[0002] Square wave power modulation is a modulation method that controls the rapid step change of power supply magnitude over time. This can be a single level change or a multi-state level change. When used in the gate of a power amplifier, the rapid changes in different levels control the output power, giving the amplifier duty cycle characteristics. When used in the control terminal of an attenuator, different levels can set different attenuation values, and the different signal attenuations give the attenuator AM (Amplitude Modulation) characteristics. When used in simple digital modulation for transmitting information, combinations of high and low levels can be directly mapped to a binary data stream, realizing basic modulation modes such as ASK (Amplitude Shift Keying), thereby completing wireless information transmission. Because square wave modulation is easy to generate and demodulate, and its hardware implementation is simple, it is often used in low-power, low-cost communication systems. (Reference) Figure 1 The modulation example diagram shows that level V1 represents digital 1 and level V2 represents digital 0.

[0003] Generally speaking, the designed square wave power supply modulation scheme needs to meet one or more of the following requirements: firstly, the modulation speed requirement, refer to... Figure 2 This is a schematic diagram of modulation speed, which includes the speed of the square wave's rising edge, falling edge, and delay, etc., affecting the square wave's rectangularity; secondly, there is the requirement for the square wave's waveform integrity, as referenced... Figure 3 The diagram illustrates waveform integrity, specifically whether there is rising edge overshoot and falling edge overshoot during square wave formation. Excessive overshoot can affect the setting of the judgment threshold, leading to misjudgment. Thirdly, it addresses the need for easy expansion to multi-ary systems, using binary as the basic circuit and making slight modifications to extend it to an n-ary circuit modulation, enabling the random occurrence of multi-bit n-ary square waves along the time axis. (Refer to...) Figure 4 The diagram shows a multi-level circuit modulation scheme; fourthly, there is the requirement for hardware circuit cost and complexity, that is, to implement square wave modulation with a simple and low-cost circuit.

[0004] Currently, there is no solution that simultaneously meets all four requirements. For example, commonly used square wave power modulation schemes include: 1. Single-channel DAC (digital-to-analog converter) is configured to quickly output different level values ​​through MCU (microcontroller unit): This type of circuit is the simplest and can easily achieve different level outputs. However, the DAC needs to configure internal registers to generate different levels, which is relatively slow. The modulation speed is also slow. At the same time, the cost of DAC is relatively high. The price of a commercial nanoDAC is about 30 yuan, which does not meet the low-cost requirement.

[0005] 2. Single-pole multi-throw electronic switch with fast output switching: This type of circuit can switch different levels at the common terminal of the electronic switch. Its switching speed is on the order of 10-20ns, which can realize the waveform quickly and with good waveform integrity. However, the faster the switching speed, the higher the cost. High-speed electronic low-frequency switches are generally around 20 yuan.

[0006] 3. Multi-channel relay network cascading to achieve n-ary multi-level switching: For this type of relay network, different levels of output are achieved by turning different relays on and off. The implementation cost is low, but the switching characteristics of the relays are relatively slow and cannot meet the requirements of fast modulation speed.

[0007] 4. Multiple MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) can be implemented through reasonable circuit design: By controlling the timing of the drive circuit, it can satisfy fast and distortion-free square wave modulation. However, the scheme for expanding from binary to multi-level is complex, requiring several cascaded binary circuit modules, as well as driver circuit design. Consequently, the complexity of the expansion scheme leads to a relatively higher cost. (Refer to...) Figure 5 The diagram shows the implementation of MOSFET switching modulation and multi-level expansion.

[0008] Each of the above solutions has its own advantages and disadvantages, and none of them can simultaneously meet the requirements of fast modulation speed, good waveform integrity, convenient expansion to multi-level, low cost and low complexity.

[0009] Therefore, how to overcome the technical problem that existing technologies cannot simultaneously meet the requirements of fast modulation speed, good waveform integrity, convenient expansion to multiple bases, low cost and low complexity is a problem to be solved in this technical field. Summary of the Invention

[0010] To address the aforementioned deficiencies or improvement needs of existing technologies, and to solve the technical problem that existing technologies cannot simultaneously meet the requirements of fast modulation speed, good waveform integrity, convenient expansion to multiple bases, low cost, and low complexity, this application provides a simple and low-cost n-ary fast-switching power supply square wave modulation circuit. This circuit uses a PMOS transistor as the core device, innovatively utilizing its body diode conduction characteristics and combining them with gate-source voltage control logic. It achieves fast switching of binary levels with a single PMOS transistor, eliminating the need for traditional drive circuit design. Furthermore, the circuit does not include energy storage components such as capacitors and inductors. Based on this... The basic modulation circuit adopts a direct replication cascade method. It can be easily expanded into an n-ary modulation circuit by simply ensuring that the level values ​​of the cascaded level terminals decrease sequentially. The high-speed switching characteristics of PMOS transistors at the ns level ensure the modulation speed. The design without energy storage components avoids waveform overshoot in principle to ensure waveform integrity. The simplified structure of binary and cascaded replication expansion to n-ary is achieved with a single transistor to reduce circuit complexity. At the same time, the use of low-cost PMOS transistors and a small number of resistive components achieves multiple technical goals such as fast modulation speed, good waveform integrity, easy expansion to multiple ary levels, low cost and low complexity.

[0011] The embodiments of this application adopt the following technical solutions: This application provides a simple and low-cost n-ary fast-switching power supply square wave modulation circuit, including at least one stage of binary basic modulation circuit. The binary basic modulation circuit includes a PMOS transistor and a pull-down resistor. The source (S) and gate (G) of the PMOS transistor are both connected to a first level terminal V1, and the drain (D) is connected to a second level terminal V2. The gate (G) is connected to one end of the pull-down resistor, and the other end of the pull-down resistor is grounded. The output level value of the first level terminal V1 is greater than the output level value of the second level terminal V2. By switching the first level terminal V1 on and off, combined with the body diode characteristics of the PMOS transistor, the output terminal Vout is switched between the first level V1 and the second level V2. When the binary basic modulation circuit is multi-stage, the multi-stage binary basic modulation circuits are cascaded one after another. In each newly added binary basic modulation circuit, the drain D of the PMOS transistor is connected to a new level terminal. The output level values ​​of all level terminals decrease sequentially along the cascading direction, realizing the switching of the output terminal Vout between multiple levels and completing the n-ary square wave modulation.

[0012] By adopting the above technical solution, a core framework of a binary basic modulation circuit based on a single PMOS transistor and pull-down resistors was constructed. Simultaneously, an n-ary expansion rule was established, which involves direct cascading of identical modules and sequentially decreasing level values ​​along the cascading direction. The core design was completed from both the basic circuit structure and the multi-ary expansion logic, effectively solving the technical problems of existing square wave modulation circuits that cannot simultaneously meet the requirements of high modulation speed, good waveform integrity, convenient multi-ary expansion, low cost, and low complexity. It not only lays the foundation for high-speed modulation through the device characteristics of PMOS transistors, but also achieves low cost and low complexity through a minimalist binary structure without additional components. Furthermore, the modular direct cascading expansion method allows for n-ary expansion without complex modifications, while providing a basic circuit structure guarantee for waveform distortion-free operation. This achieves the integrated fulfillment of the four major technical requirements, laying a complete and reliable core architecture foundation for subsequent circuit function refinement and performance improvement.

[0013] In some implementations, the pull-down resistor is used to pull the gate G potential of the PMOS transistor to 0V when the first level terminal V1 is not input, so that the PMOS transistor remains in the default on state.

[0014] By adopting the above technical solution, the core function of the pull-down resistor is clarified, ensuring the default conduction state of the PMOS transistor when there is no first level input, allowing the circuit's level switching logic to form a fixed and reliable initial state, avoiding circuit malfunctions caused by uncertain gate potential, and improving the working stability of the binary basic modulation circuit.

[0015] In some embodiments, the body diode of the PMOS transistor is turned on along the drain D to source S. When the first level terminal V1 is not input, the level of the second level terminal V2 is conducted to the source S of the PMOS transistor through the body diode, and the gate G is kept at 0V through the pull-down resistor to turn on the PMOS transistor. The output terminal Vout outputs the second level V2.

[0016] By adopting the above technical solution, the conduction direction of the PMOS transistor body diode and the circuit operation logic when there is no first level input are refined. The effective output of the second level is achieved by relying on the inherent characteristics of the body diode. No additional switching element is required, which simplifies the hardware structure of binary level switching and ensures the effectiveness of level conduction.

[0017] In some implementations, when the first level terminal V1 is input, the body diode of the PMOS transistor is turned off, and the potentials of the source S and the gate G are the same, causing the PMOS transistor to turn off, and the output terminal Vout outputs the first level V1.

[0018] By adopting the above technical solution, the dual turn-off logic of the PMOS transistor body diode and the transistor itself when there is a first level input is clarified, which realizes the accurate and interference-free switching between the first and second levels, avoids waveform distortion caused by level superposition, and ensures the waveform integrity of binary square wave modulation.

[0019] In some implementations, in an n-ary modulation circuit formed by cascading multiple levels of the binary basic modulation circuits, the drain D of the PMOS transistor of the nth level binary basic modulation circuit is connected to the nth level terminal Vn, and satisfies V1>V2>……>Vn, where n is a positive integer greater than or equal to 2.

[0020] By adopting the above technical solution, the level configuration rules of the n-ary modulation circuit are quantified, the relationship between the level values ​​of the cascaded circuit and the range of n values ​​are clarified, so that the expansion of n-ary has a clear and unified hardware configuration standard, avoiding level logic confusion during cascading, and providing a feasible parameter basis for multi-ary expansion.

[0021] In some implementations, when multiple stages of the binary basic modulation circuits are cascaded, the output of the upper-level binary basic modulation circuit is connected to the output of the lower-level binary basic modulation circuit. When the upper-level level is input, the PMOS transistors of this stage and all lower stages are turned off, and the output Vout outputs the upper-level level.

[0022] By adopting the above technical solution, the physical connection method and level priority rules of the multi-level binary basic modulation circuit are clarified, realizing the effective shutdown and priority output of the upper level to the lower level, allowing the switching of n levels to have orderly logical control, and ensuring the accuracy and speed of level switching of n-ary square wave modulation.

[0023] In some embodiments, the PMOS transistor is a nanosecond-level high-speed switching transistor, with its charge / discharge delay, rise edge delay, and fall edge delay all on the order of 10 nanoseconds.

[0024] By adopting the above technical solution, the high-speed switching parameters of the PMOS transistor are limited, allowing the circuit to rely on the nanosecond-level delay characteristics of the PMOS transistor to achieve rapid step changes in square wave modulation, thereby improving the modulation speed of the circuit, meeting the high-speed requirements of square wave modulation for rising edge, falling edge and delay speed, and ensuring the rectangularity of the square wave.

[0025] In some implementations, the binary basic modulation circuit and the n-ary modulation circuit formed by multi-stage cascading are both composed of PMOS transistors, pull-down resistors and corresponding level terminals, and square wave modulation is achieved only by switching the levels of each level terminal.

[0026] By adopting the above technical solution, it is clear that all components of the circuit are only PMOS transistors, pull-down resistors, and level terminals, without any other additional energy storage or switching components. Furthermore, modulation is achieved solely through level switching. This simplifies the circuit structure from both hardware composition and modulation method perspectives, reducing hardware costs and circuit complexity, while also avoiding the overcharging problem caused by energy storage components.

[0027] In some implementations, the conduction and turn-off of the PMOS transistor are directly achieved by the magnitude relationship of the output voltage levels at each voltage level and the on / off state of each voltage level.

[0028] By adopting the above technical solution, the direct control method of PMOS transistors is clarified. There is no need to design independent drive circuits and complex timing logic. The transistor can be turned on and off simply by controlling the voltage level and the on / off state of the voltage terminals. This greatly simplifies the control logic of the circuit, further reduces the design and hardware costs of the circuit, and improves the response speed of level switching.

[0029] In some implementations, when the second level terminal V2 outputs a periodic pulse square wave, the pulse change of the second level terminal V2 controls the switching on and off of the first level V1, thereby achieving modulation of the power supply square wave; when multiple levels are cascaded, the lower level terminal outputs a periodic pulse square wave to achieve modulation of the upper level.

[0030] By adopting the above technical solution, the actual modulation application method of the circuit in the pulse square wave input scenario is clarified. The dynamic modulation of the upper level is realized by relying on the change of the periodic pulse square wave, so that the basic level switching function is transformed into the actual square wave modulation function. It is suitable for practical application scenarios such as power amplifier gate power control, attenuator adjustment, and digital modulation communication, thereby improving the practicality and adaptability of the circuit.

[0031] In summary, this application includes at least the following beneficial technical effects: 1. Using a PMOS transistor as the core device, this innovative design leverages its body diode conduction characteristics and gate-source voltage control logic to achieve rapid switching of binary levels with a single PMOS transistor, eliminating the need for traditional drive circuit designs. Furthermore, the circuit eliminates the need for energy storage components such as capacitors and inductors. Based on this binary modulation circuit, a direct replication and cascading approach is adopted. Simply ensuring that the level values ​​at the cascaded terminals decrease sequentially allows for easy expansion into an n-ary modulation circuit. The high-speed switching characteristics of the PMOS transistor at the nanosecond level guarantee modulation speed. The design, devoid of energy storage components, avoids waveform overshoot in principle, ensuring waveform integrity. The simplified structure of binary and cascaded replication expansion to n-ary levels using a single transistor reduces circuit complexity. Simultaneously, the use of low-cost PMOS transistors and a small number of resistive components achieves multiple technical goals simultaneously, including fast modulation speed, good waveform integrity, easy expansion to multiple levels, low cost, and low complexity. 2. The core function of the pull-down resistor is clarified, ensuring the default conduction state of the PMOS transistor when there is no first level input, so that the level switching logic of the circuit forms a fixed and reliable initial state, avoiding abnormal circuit operation caused by uncertain gate potential, and improving the working stability of the binary basic modulation circuit. 3. The physical connection method and level priority rules of the multi-level binary basic modulation circuit were clarified, realizing the effective shutdown and priority output of the upper level to the lower level, so that the switching of n levels has orderly logical control, ensuring the accuracy and speed of level switching of n-ary square wave modulation. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 The modulation example diagram provided in this application; Figure 2 A schematic diagram of the modulation speed provided in this application; Figure 3 A waveform integrity diagram provided for this application; Figure 4 This is a schematic diagram of the modulation of a multi-level circuit provided in this application; Figure 5 A schematic diagram illustrating the implementation of MOSFET switching modulation and multi-level expansion provided in this application; Figure 6 A schematic diagram of a binary fast-switching power supply square wave modulation circuit implemented by a single PMOS provided in this application; Figure 7 A schematic diagram of a multi-level fast-switching power supply square wave modulation circuit provided in this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Furthermore, the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other.

[0035] This application provides a simple and low-cost n-ary fast switching power supply square wave modulation circuit, aiming to solve the technical problem that the prior art cannot simultaneously meet the requirements of fast modulation speed, good waveform integrity, convenient expansion to multiple bases, low cost and low complexity. The application will be described in detail below with reference to the accompanying drawings and embodiments. Example 1

[0036] refer to Figure 6 As shown, for the simple and low-cost n-ary fast-switching power supply square wave modulation circuit provided in this application, this embodiment 1 provides an implementation scheme in which a single PMOS implements a binary fast-switching power supply square wave modulation circuit, that is, a specific implementation scheme of a single-stage binary basic modulation circuit. Its core consists of a PMOS transistor and a pull-down resistor. The specific circuit connection relationship and working logic are as follows: Circuit connection: The source (S) and gate (G) of the PMOS transistor are both connected to the first level terminal V1, and the drain (D) of the PMOS transistor is connected to the second level terminal V2; the gate (G) is electrically connected to one end of the pull-down resistor, and the other end of the pull-down resistor is grounded; wherein, the voltage level output by the first level terminal V1 is greater than the voltage level output by the second level terminal V2, and the function of the pull-down resistor is to pull the potential of the gate (G) of the PMOS transistor to 0V when there is no input voltage at the first level terminal V1, so that the PMOS transistor remains in the default on state.

[0037] The PMOS transistor's body diode characteristic is utilized: the PMOS transistor's body diode conducts along the drain (D) to source (S) direction, which is the core basis for this circuit to achieve single-transistor level switching; when the first level terminal V1 has no input level, the level of the second level terminal V2 is conducted to the source (S) of the PMOS transistor through the body diode, and the gate (G) is kept at 0V through the pull-down resistor to keep the PMOS transistor conducting. At this time, the output terminal Vout stably outputs the second level V2.

[0038] Level switching logic: When the first level terminal V1 is input, since V1 > V2, the body diode of the PMOS transistor is reverse biased and turned off, and the potential of the source S and the gate G of the PMOS transistor are the same, so the PMOS transistor itself is turned off. The level of the second level terminal V2 cannot be conducted to the output terminal. At this time, the output terminal Vout stably outputs the first level V1.

[0039] Circuit core parameters and composition: The PMOS transistor used in this embodiment is a high-speed switching transistor in the nanosecond range. Its charging and discharging delay, rising edge delay and falling edge delay are all in the order of 10ns, which meets the speed requirements of fast square wave modulation. The entire binary basic modulation circuit consists only of PMOS transistor, pull-down resistor, first level terminal V1 and second level terminal V2. There are no other components such as capacitors and inductors. The level switching is achieved only by turning the first level terminal V1 on and off, thereby completing the square wave modulation.

[0040] Control method: In this embodiment, the conduction and turn-off of the PMOS transistor do not require a separate driving circuit to provide a driving signal. They are directly achieved by the relationship between the level values ​​of the first level terminal V1 and the second level terminal V2, as well as the on / off state of the first level terminal V1, which simplifies the circuit control logic.

[0041] Practical modulation application: When the second level terminal V2 outputs a periodic pulse square wave, the on and off changes of the pulse of V2 can be used to realize the dynamic control of the first level V1 being turned off and on, thereby forming a square wave modulation waveform that meets the requirements at the output terminal Vout, and completing the basic power supply square wave modulation.

[0042] The binary modulation circuit in this embodiment 1, compared to the traditional MOSFET design which requires two switching circuits to achieve binary level switching, only requires one PMOS transistor and one pull-down resistor to achieve precise switching of V1 and V2. The unit price of a commercial PMOS transistor is only 2 yuan, which greatly reduces the hardware cost. At the same time, relying on the high-speed switching characteristics of the PMOS transistor, a modulation delay on the order of 10ns is achieved, which ensures the square wave modulation speed. Moreover, the circuit has no energy storage components, which avoids waveform overshoot in principle and ensures waveform integrity. Example 2

[0043] refer to Figure 7 As shown, for the simple and low-cost n-ary fast-switching power supply square wave modulation circuit provided in this application, this embodiment 2 provides an implementation scheme for the multi-ary fast-switching power supply square wave modulation circuit, specifically a ternary fast-switching power supply square wave modulation circuit, which is built on the binary basic modulation circuit of embodiment 1. The specific implementation scheme is as follows: Circuit cascading design: After the binary basic modulation circuit (first stage) in Example 1, a binary basic modulation circuit (second stage) with the same structure is directly cascaded to form a ternary modulation circuit; wherein, the first stage binary basic modulation circuit is the complete circuit of Example 1, and the drain D of the PMOS transistor of the second stage binary basic modulation circuit is connected to the third level terminal V3, and the level values ​​of V1 > V2 > V3 are satisfied.

[0044] Cascaded connection: The output terminal of the first-stage binary basic modulation circuit is connected to the output terminal of the second-stage binary basic modulation circuit to form the overall output terminal Vout; the PMOS transistors of both stages are equipped with independent pull-down resistors, and the connection method and function of the pull-down resistors are completely consistent with those in Example 1, ensuring the stability of the initial conduction state of each stage circuit.

[0045] Ternary level switching logic: The level output of a multi-stage cascaded circuit follows the rule of priority of the upper level. When the upper level input level is low, the PMOS transistors of this stage and all lower stages will be turned off, realizing the independent output of the upper level level. Specifically: When neither the first level terminal V1 nor the second level terminal V2 has an input level, and only the third level terminal V3 has an input level, both PMOS transistors remain in the conducting state. The third level V3 is conducted to the output terminal through the body diode and the PMOS transistor channel, and Vout outputs V3. When the first level terminal V1 is not input, and the second level terminal V2 is input, the second level V2 will cause the body diode of the second stage PMOS transistor to be reverse biased and turned off, and the second stage PMOS transistor itself will be turned off. The third level V3 cannot be conducted, and Vout outputs V2 at this time. When the first level V1 is input, the first-stage PMOS transistor is turned off. At the same time, the first level V1 will cause the body diode of the second-stage PMOS transistor to be reverse biased and turned off, and the transistor itself will be turned off. The second level V2 and the third level V3 cannot be conducted. At this time, Vout outputs V1.

[0046] Circuit parameters, composition and control method: In this embodiment, the PMOS transistor used in the second-stage binary basic modulation circuit is exactly the same as that in the first stage. Both are high-speed switching transistors in the nanosecond range, with charging / discharging, rising edge, and falling edge delays all in the order of 10ns, ensuring the overall speed of ternary modulation. The entire ternary modulation circuit consists of only 2 PMOS transistors, 2 pull-down resistors, a first level terminal V1, a second level terminal V2, and a third level terminal V3. There are no other energy storage components or independent driving circuits. The switching control of the PMOS transistors is achieved solely through the relationship between the level values ​​of each level terminal and their on / off states.

[0047] Practical modulation application: When both the second level terminal V2 and the third level terminal V3 output periodic pulse square waves, the pulse changes of V2 and V3 can be used to dynamically modulate the first level V1 and the second level V2 respectively, thereby forming a ternary square wave modulation waveform at the output terminal Vout, thus completing the ternary power supply square wave modulation.

[0048] The ternary modulation circuit in this embodiment 2 is implemented by directly copying and cascading the basic binary modulation circuit. No structural modifications to the basic circuit are required, nor are additional circuits such as driving circuits and timing control circuits needed. This greatly reduces the complexity and cost of multi-level expansion, while maintaining the core advantages of high-speed modulation and waveform distortion-free operation. Example 3

[0049] Regarding the simple and low-cost n-ary fast-switching power supply square wave modulation circuit provided in this application, Embodiment 3 provides an implementation scheme for the n-ary fast-switching power supply square wave modulation circuit, where n is a positive integer greater than or equal to 2. It is a generalized extension based on Embodiments 1 and 2, and the specific implementation is as follows: General Cascading Design: Based on the binary basic modulation circuit of Example 1, an n-stage binary basic modulation circuit is built by direct copying and cascading, forming an n-ary fast-switching power supply square wave modulation circuit. The output terminals of the first to the (n-1)th stage binary basic modulation circuits are connected to the output terminals of the next stage circuit in sequence. The drain D of the PMOS transistor of the nth stage binary basic modulation circuit is connected to the nth level terminal Vn, and the output level values ​​of all level terminals decrease sequentially along the cascading direction, satisfying the core rule V1 > V2 > ... > Vn.

[0050] General level switching logic: The entire n-ary modulation circuit follows the highest level priority rule, that is, when any level input is at a certain level, the PMOS transistors of this level and all lower levels will be turned off, and only the level of this level will be conducted to the output Vout; when a higher level input is at a certain level, the conduction of the lower level will be directly turned off, so as to achieve the priority output of the high level.

[0051] General circuit parameters and design: The PMOS transistors used in the n-level binary basic modulation circuit are high-speed switching transistors of the same specification in the ns range. The charging and discharging delay, rising edge delay, and falling edge delay are all in the order of 10ns, ensuring the overall speed and waveform consistency of the n-level modulation. The entire n-level modulation circuit consists of only n PMOS transistors, n pull-down resistors, and n level terminals. There are no energy storage components such as capacitors and inductors, nor any independent PMOS transistor driving circuits. The conduction and cutoff of all PMOS transistors are directly achieved by the relationship between the level values ​​of each level terminal and the on / off state.

[0052] General modulation application: When periodic pulse square waves are output from the 2nd to the nth level terminals, dynamic modulation of the corresponding upper level can be achieved by changing the pulses at each lower level terminal, thereby forming an n-ary square wave modulation waveform at the output terminal Vout, thus completing the n-ary power supply square wave modulation.

[0053] The n-ary modulation circuit in this embodiment 3 achieves seamless expansion from binary to any n-ary system. The expansion process only requires copying the basic module and matching the level values, without the need for complex circuit modifications and designs, which greatly reduces the technical threshold and hardware cost of multi-ary expansion. At the same time, the entire n-ary circuit maintains a minimalist structural design. Relying on the high-speed switching characteristics of PMOS transistors and the design without energy storage components, it achieves the technical effects of fast modulation speed and good waveform integrity, solving the technical problems that existing technologies cannot simultaneously meet the requirements of fast modulation speed, good waveform integrity, convenient expansion to multiple ary systems, low cost, and low complexity.

[0054] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A simple and low-cost n-ary fast-switching power supply square wave modulation circuit, characterized in that, It includes at least one stage of binary basic modulation circuit, which includes a PMOS transistor and a pull-down resistor; the source (S) and gate (G) of the PMOS transistor are both connected to a first level terminal V1, the drain (D) is connected to a second level terminal V2, the gate (G) is connected to one end of the pull-down resistor, and the other end of the pull-down resistor is grounded; the level value output by the first level terminal V1 is greater than the level value output by the second level terminal V2. By switching the first level terminal V1 on and off, combined with the body diode characteristics of the PMOS transistor, the output terminal Vout can be switched between the first level V1 and the second level V2. When the binary basic modulation circuit is multi-stage, the multi-stage binary basic modulation circuits are cascaded one after another. In each newly added binary basic modulation circuit, the drain D of the PMOS transistor is connected to a new level terminal. The output level values ​​of all level terminals decrease sequentially along the cascading direction, realizing the switching of the output terminal Vout between multiple levels and completing the n-ary square wave modulation.

2. The simple, low-cost n-ary fast-switching power supply square wave modulation circuit according to claim 1, characterized in that, The pull-down resistor is used to pull the gate G potential of the PMOS transistor to 0V when the first level terminal V1 is not input, so that the PMOS transistor remains in the default on state.

3. The simple, low-cost n-ary fast-switching power supply square wave modulation circuit according to claim 1, characterized in that, The body diode of the PMOS transistor is turned on along the drain D to the source S. When the first level terminal V1 is not input, the level of the second level terminal V2 is conducted to the source S of the PMOS transistor through the body diode, and the gate G is kept at 0V through the pull-down resistor to turn on the PMOS transistor. The output terminal Vout outputs the second level V2.

4. The simple, low-cost n-ary fast-switching power supply square wave modulation circuit according to claim 3, characterized in that, When the first level terminal V1 is input, the body diode of the PMOS transistor is turned off, and the potentials of the source S and the gate G are the same, causing the PMOS transistor to turn off, and the output terminal Vout outputs the first level V1.

5. The simple, low-cost n-ary fast-switching power supply square wave modulation circuit according to claim 1, characterized in that, In the n-ary modulation circuit formed by cascading multiple binary basic modulation circuits, the drain D of the PMOS transistor of the nth binary basic modulation circuit is connected to the nth level terminal Vn, and satisfies V1>V2>……>Vn, where n is a positive integer greater than or equal to 2.

6. The simple, low-cost n-ary fast-switching power supply square wave modulation circuit according to claim 5, characterized in that, When multiple binary basic modulation circuits are cascaded, the output terminal of the upper-level binary basic modulation circuit is connected to the output terminal of the lower-level binary basic modulation circuit. When the upper-level input level is high, the PMOS transistors of this level and all lower levels are turned off, and the output terminal Vout outputs the upper-level level.

7. The simple, low-cost n-ary fast-switching power supply square wave modulation circuit according to any one of claims 1-6, characterized in that, The PMOS transistor is a high-speed switching transistor in the nanosecond range, with its charging / discharging delay, rising edge delay, and falling edge delay all in the order of 10 nanoseconds.

8. The simple, low-cost n-ary fast-switching power supply square wave modulation circuit according to any one of claims 1-6, characterized in that, The binary basic modulation circuit and the n-ary modulation circuit formed by multi-stage cascading are both composed of PMOS transistors, pull-down resistors and corresponding level terminals, and square wave modulation is achieved only by switching the level of each level terminal.

9. The simple, low-cost n-ary fast-switching power supply square wave modulation circuit according to any one of claims 1-6, characterized in that, The conduction and turn-off of the PMOS transistor are directly achieved by the magnitude relationship of the output voltage levels at each voltage level and the on / off state of each voltage level.

10. The simple, low-cost n-ary fast-switching power supply square wave modulation circuit according to any one of claims 1-6, characterized in that, When the second level terminal V2 outputs a periodic pulse square wave, the pulse change of the second level terminal V2 controls the switching on and off of the first level V1, thereby achieving modulation of the power supply square wave; when multiple levels are cascaded, the lower level terminal outputs a periodic pulse square wave, thereby achieving modulation of the upper level.

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