Multilevel conversion circuit, power supply adjustment circuit, and electronic device

Abstract

The application discloses a multi-level conversion circuit, a power supply regulating circuit and an electronic device. The multi-level conversion circuit comprises: an input inductor coupled with an alternating current power supply; a power switch circuit coupled with the input inductor; a flying capacitor circuit comprising at least two flying capacitor groups coupled with the power switch circuit; a charging circuit comprising input and output side charging sub-circuits, each input side charging sub-circuit being coupled with the power switch circuit, and the output side charging sub-circuit being coupled with the flying capacitor group adjacent thereto and the input side charging sub-circuit; and a bus capacitor circuit coupled with the power switch circuit and the output side charging sub-circuit. In a non-controlled rectification stage, the power switch circuit, each input side charging sub-circuit and the output side charging sub-circuit are configured to receive the alternating current input sent by the input inductor to charge the bus capacitor circuit and each flying capacitor group. In the above manner, the multi-level conversion circuit can effectively protect the capacitor and the switch device from overvoltage failure.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a multilevel conversion circuit, a power regulation circuit, and an electronic device. Background Technology

[0002] Currently, with the rapid development of medium- and high-voltage, high-power applications such as renewable energy power generation, electric vehicles, data center power supply, and industrial drives, multilevel converters are widely used due to their significant advantages, including high output waveform quality, low voltage stress on switching devices, and low electromagnetic interference. Among them, the flying capacitor multilevel converter, as an important topology, generates multilevel voltages by introducing a floating flying capacitor, eliminating the need for complex power frequency transformers or a large number of independent DC power supplies, resulting in a compact structure.

[0003] However, multilevel flying capacitor topologies in related technologies generally suffer from a power-on pre-charging problem, meaning that all flying capacitors have an initial voltage of zero before system startup. If put into operation directly, the DC bus voltage will cause a momentary large current surge to the flying capacitors through the switching devices, which can easily lead to capacitor damage and overcurrent and overvoltage failure of the power switching devices. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a multilevel conversion circuit, a power regulation circuit, and an electronic device that can solve the problem that multilevel conversion circuits in the prior art are prone to capacitor damage and power switching device overcurrent and overvoltage failure.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a multi-level conversion circuit, wherein the multi-level conversion circuit includes: an input inductor for coupling with an AC power supply; a power switching circuit coupled to the input inductor and for coupling with a drive control circuit; a flying capacitor circuit including at least two flying capacitor groups, each flying capacitor group being coupled to the power switching circuit; a charging circuit including an input-side charging sub-circuit and an output-side charging sub-circuit, each input-side charging sub-circuit being coupled to every two adjacent flying capacitor groups and coupled to the power switching circuit, and the output-side charging sub-circuit being directly coupled to the adjacent flying capacitor group and the adjacent input-side charging sub-circuit; a bus capacitor circuit coupled to the power switching circuit and the output-side charging sub-circuit; wherein, in the uncontrolled rectification stage, the input inductor is configured to receive AC input provided by the AC power supply; the power switching circuit, each input-side charging sub-circuit, and the output-side charging sub-circuit are configured to receive AC input transmitted by the input inductor, so as to charge the bus capacitor circuit and each flying capacitor group using the AC input.

[0006] During the startup phase of the drive control circuit, the power switch circuit is configured to receive the corresponding drive control signal sent by the drive control circuit and change the switching state in response to the drive control signal, so as to cooperate with each input-side charging sub-circuit and output-side charging sub-circuit to charge each flying capacitor bank using the bus voltage of the bus capacitor circuit.

[0007] The bus capacitor circuit includes N bus capacitors, the power switch circuit includes 2N switching transistors, the number of flying capacitor banks is N-1, and the number of input-side charging electronic circuits is N-2; where N is a positive integer greater than 2.

[0008] The power switching circuit includes an upper switching sub-circuit and a lower switching sub-circuit, and at least two flying capacitor banks, including a first-stage flying capacitor bank and a second-stage flying capacitor bank. The first terminal of the input inductor is coupled to the AC power supply, and the second terminal of the input inductor is coupled to the first terminal of the upper switching sub-circuit and the first terminal of the lower switching sub-circuit. The second terminal of the upper switching sub-circuit is coupled to the first terminal of the first-stage flying capacitor bank and the first terminal of the input-side charging sub-circuit. The second terminal of the lower switching sub-circuit is coupled to the second terminal of the first-stage flying capacitor bank and the second terminal of the input-side charging sub-circuit. The first terminal of the upper switching sub-circuit... The three-terminal circuit is coupled to the first terminal of the second-stage flying capacitor bank. The third terminal of the lower switch circuit is coupled to the second terminal of the second-stage flying capacitor bank. The third terminal of the input-side charging circuit is coupled to the third terminal of the second-stage flying capacitor bank and the third terminal of the output-side charging circuit. The fourth terminal of the upper switch circuit is coupled to the first terminal of the bus capacitor circuit. The fourth terminal of the lower switch circuit is coupled to the second terminal of the bus capacitor circuit. The first and second terminals of the output-side charging circuit are coupled to the third and fourth terminals of the bus capacitor circuit, respectively. The control terminals of the upper and lower switch circuits are coupled to the drive control circuit.

[0009] The first-stage flying capacitor bank includes a first flying capacitor, and the second-stage flying capacitor bank includes a second flying capacitor and a third flying capacitor. The first terminal of the first flying capacitor is coupled to the second terminal of the upper-side switching sub-circuit and the first terminal of the input-side charging sub-circuit. The second terminal of the first flying capacitor is coupled to the second terminal of the lower-side switching sub-circuit and the second terminal of the input-side charging sub-circuit. The first terminal of the second flying capacitor is coupled to the third terminal of the upper-side switching sub-circuit. The second terminal of the second flying capacitor is coupled to the third terminal of the input-side charging sub-circuit, the first terminal of the third flying capacitor, and the third terminal of the output-side charging sub-circuit. The second terminal of the third flying capacitor is coupled to the third terminal of the lower-side switching sub-circuit.

[0010] The bus capacitor circuit includes a first bus capacitor, a second bus capacitor, and a third bus capacitor. The first terminal of the first bus capacitor is coupled to the fourth terminal of the upper switch sub-circuit. The second terminal of the first bus capacitor is coupled to the first terminal of the output side charging sub-circuit and the first terminal of the second bus capacitor. The second terminal of the second bus capacitor is coupled to the second terminal of the output side charging sub-circuit and the first terminal of the third bus capacitor. The second terminal of the third bus capacitor is coupled to the fourth terminal of the lower switch sub-circuit.

[0011] The upper-side switching sub-circuit includes a first upper-side switching transistor, a second upper-side switching transistor, and a third upper-side switching transistor; the lower-side switching sub-circuit includes a first lower-side switching transistor, a second lower-side switching transistor, and a third lower-side switching transistor. The first terminal of the first upper-side switching transistor is coupled to the second terminal of the input inductor and the second terminal of the first lower-side switching transistor. The second terminal of the first upper-side switching transistor is coupled to the first terminal of the second upper-side switching transistor, the first terminal of the first flying capacitor, and the first terminal of the input-side charging sub-circuit. The first terminal of the first lower-side switching transistor is coupled to the second terminal of the second lower-side switching transistor, the second terminal of the first flying capacitor, and the second terminal of the input-side charging sub-circuit. The second terminal of the second upper-side switching transistor is coupled to the third upper-side switching transistor. The first terminal of the first switch transistor and the first terminal of the second flying capacitor are coupled to the first terminal of the third flying capacitor, the third terminal of the input-side charging electronic circuit, and the third terminal of the output-side charging electronic circuit. The first terminal of the second lower switch transistor is coupled to the second terminal of the third lower switch transistor and the second terminal of the third flying capacitor. The second terminal of the third upper switch transistor is coupled to the first terminal of the first bus capacitor. The first terminal of the third lower switch transistor is coupled to the second terminal of the third bus capacitor. The third terminals of each of the first upper switch transistor, the second upper switch transistor, the third upper switch transistor, the first lower switch transistor, the second lower switch transistor, and the third lower switch transistor are all coupled to the drive control circuit.

[0012] The upper-side switching sub-circuit further includes a fourth upper-side switching transistor, and the lower-side switching sub-circuit further includes a fourth lower-side switching transistor. At least two flying capacitor banks also include a third-stage flying capacitor bank, which includes a fourth, fifth, and sixth flying capacitor. The input-side charging sub-circuit includes a first-stage charging sub-circuit and a second-stage charging sub-circuit. The first-stage charging sub-circuit includes a first charging unit sub-circuit, and the second-stage charging sub-circuit includes a second and a third charging unit sub-circuit. The output-side charging sub-circuit includes a fourth and a fifth charging unit circuit. The bus capacitor circuit also includes… Includes a fourth bus capacitor; wherein, the first terminal of the first charging unit sub-circuit is coupled to the first terminal of the first flying capacitor, the second terminal of the first upper switch transistor, and the second terminal of the second lower switch transistor; the second terminal of the first charging unit sub-circuit is coupled to the second terminal of the first flying capacitor, the first terminal of the first lower switch transistor, and the second terminal of the second lower switch transistor; the first terminal of the second charging unit sub-circuit is coupled to the first terminal of the second flying capacitor, the second terminal of the second upper switch transistor, and the first terminal of the third upper switch transistor; the second terminal of the second charging unit sub-circuit is coupled to the second terminal of the second flying capacitor, the third terminal of the first charging unit sub-circuit, and the third flying capacitor. The first terminal of the first and third charging unit sub-circuits, the second terminal of the third charging unit sub-circuit is coupled to the first terminal of the second lower switch transistor, the second terminal of the third lower switch transistor, and the second terminal of the third flying capacitor, the first terminal of the fourth flying capacitor is coupled to the second terminal of the third upper switch transistor, the first terminal of the fourth upper switch transistor, the second terminal of the fourth upper switch transistor is coupled to the first terminal of the first bus capacitor, the second terminal of the fourth flying capacitor is coupled to the third terminal of the second charging unit sub-circuit, the first terminal of the fifth flying capacitor, the third terminal of the fourth charging unit sub-circuit, the second terminal of the fifth flying capacitor is coupled to the third terminal of the third charging unit sub-circuit, and the sixth... The first terminal of the flying capacitor and the third terminal of the fifth charging unit sub-circuit are coupled to the first terminal of the third lower-position switch and the second terminal of the fourth lower-position switch. The first terminal of the fourth charging unit sub-circuit is coupled to the second terminal of the first bus capacitor and the first terminal of the second bus capacitor. The second terminal of the fourth charging unit sub-circuit is coupled to the first terminal of the fifth charging unit sub-circuit, the second terminal of the second bus capacitor, and the first terminal of the third bus capacitor. The second terminal of the fifth charging unit sub-circuit is coupled to the second terminal of the third bus capacitor and the first terminal of the fourth bus capacitor. The first terminal of the fourth lower-position switch is coupled to the second terminal of the fourth bus capacitor.

[0013] Each of the first, second, third, fourth, and fifth charging unit sub-circuits includes a first diode, a second diode, and a first current-limiting resistor. The second end of the first diode forms the first end of the charging unit sub-circuit. The first end of the first diode is coupled to the second end of the second diode and the first end of the first current-limiting resistor. The first end of the second diode forms the second end of the charging unit sub-circuit, and the second end of the first current-limiting resistor forms the third end of the charging unit sub-circuit.

[0014] Each of the first, second, third, fourth, and fifth charging unit sub-circuits includes a first charging switch, a second charging switch, and a second current-limiting resistor. The second end of the first charging switch forms the first end of the charging unit sub-circuit. The first end of the first charging switch is coupled to the second end of the second charging switch and the first end of the first current-limiting resistor. The first end of the second charging switch forms the second end of the charging unit sub-circuit, and the second end of the first current-limiting resistor forms the third end of the charging unit sub-circuit.

[0015] The charging unit sub-circuit in the first, second, third, fourth, and fifth charging unit sub-circuit includes a third current-limiting resistor, a fourth current-limiting resistor, a third diode, and a fourth diode. The first end of the third current-limiting resistor constitutes the first end of the charging unit sub-circuit. The second end of the third current-limiting resistor is coupled to the second end of the third diode. The first end of the third diode is coupled to the second end of the fourth diode and constitutes the third end of the charging unit sub-circuit. The first end of the fourth diode is coupled to the first end of the fourth current-limiting resistor. The second end of the fourth current-limiting resistor constitutes the second end of the charging unit sub-circuit.

[0016] Each of the first, second, third, fourth, and fifth charging unit sub-circuits includes a fifth diode, a sixth diode, a fifth current-limiting resistor, and a sixth current-limiting resistor. The second end of the fifth diode forms the first end of the charging unit sub-circuit. The first end of the fifth diode is coupled to the first end of the fifth current-limiting resistor. The second end of the fifth current-limiting resistor is coupled to the first end of the sixth current-limiting resistor and forms the third end of the charging unit sub-circuit. The second end of the sixth current-limiting resistor is coupled to the second end of the sixth diode. The first end of the sixth diode forms the second end of the charging unit sub-circuit.

[0017] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a power supply regulation circuit, wherein the power supply regulation circuit includes a multi-level conversion circuit, an inverter resonant circuit, and a transformer rectifier output circuit, wherein the inverter resonant circuit is coupled to the multi-level conversion circuit and the transformer rectifier output circuit, and the transformer rectifier output circuit is used to couple with the load operating circuit; wherein the multi-level conversion circuit is the multi-level conversion circuit as described in any of the above claims.

[0018] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide an electronic device, wherein the electronic device includes a housing and a multilevel conversion circuit connected to the housing; wherein the multilevel conversion circuit is the multilevel conversion circuit as described in any of the above claims.

[0019] The beneficial effects of this application are as follows: Unlike the prior art, the multi-level conversion circuit provided by this application, in the uncontrolled rectification stage, receives the AC input provided by the AC power supply through the input inductor, and forms a charging circuit through the power switching circuit, each input-side charging sub-circuit, and the output-side charging sub-circuit. It receives the AC input sent by the input inductor and uses the AC input to charge the bus capacitor circuit and each flying capacitor group through the charging circuit. This allows for effective pre-charging of each flying capacitor group before the drive control circuit starts working, thereby reducing the voltage difference between each switching device in the switching circuit between each flying capacitor group and the bus capacitor circuit. This effectively protects each capacitor and each switching device from overvoltage, overcurrent failure, or damage, and also effectively achieves voltage equalization among the capacitors in the bus capacitor circuit. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a schematic diagram of the structure of the first embodiment of the multilevel conversion circuit of this application; Figure 2 This is a schematic diagram of the structure of the second embodiment of the multilevel conversion circuit of this application; Figure 3 yes Figure 2 A schematic diagram of the structure of the first embodiment of the multi-level converter circuit in the uncontrolled rectification stage and the AC input positive half-cycle charging path; Figure 4 yes Figure 2 A schematic diagram of the second embodiment of the multi-level converter circuit in the uncontrolled rectification stage and the charging path of the negative half-cycle of the AC input; Figure 5 yes Figure 2 A schematic diagram of the charging path of a multi-level conversion circuit during the startup phase in one embodiment; Figure 6 This is a schematic diagram of the structure of the third embodiment of the multilevel conversion circuit of this application; Figure 7 yes Figure 6 A schematic diagram of the first embodiment of each charging unit sub-circuit in the multi-level conversion circuit; Figure 8 yes Figure 6 A schematic diagram of the second embodiment of each charging unit sub-circuit in the multi-level conversion circuit; Figure 9 yes Figure 6 A schematic diagram of the third embodiment of each charging unit sub-circuit in the multi-level conversion circuit; Figure 10 yes Figure 6 A schematic diagram of the fourth embodiment of each charging unit sub-circuit in the multi-level conversion circuit; Figure 11 yes Figure 6 A schematic diagram of the structure of the first embodiment of the multi-level converter circuit in the uncontrolled rectification stage and the AC input positive half-cycle charging path; Figure 12 yes Figure 6 A schematic diagram of the second embodiment of the multi-level converter circuit in the uncontrolled rectification stage and the charging path of the negative half-cycle of the AC input; Figure 13 yes Figure 6 A schematic diagram of the charging path of a multi-level conversion circuit during the startup phase in one embodiment; Figure 14 This is a schematic diagram of one embodiment of the power conditioning circuit of this application; Figure 15 This is a schematic diagram of one embodiment of the electronic device of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0023] In this document, the term "implementation" means that a specific feature, structure, or characteristic described in connection with an implementation may be included in at least one implementation of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same implementation, nor is it a separate or alternative implementation mutually exclusive with other implementations. It will be explicitly and implicitly understood by those skilled in the art that the implementations described herein can be combined with other implementations.

[0024] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the multilevel conversion circuit of this application. In this embodiment, the first multilevel conversion circuit 10 includes a first input inductor 11, a first power switch circuit 12, a first flying capacitor circuit 13, a first charging circuit 14, and a first bus capacitor circuit 15.

[0026] The first multilevel converter circuit 10 provided in this application is a power electronic topology that utilizes a first flying capacitor circuit 13 to achieve multilevel output. It is widely used in high-voltage, high-power scenarios, such as photovoltaic inverters, electric vehicle drives, and battery energy storage systems. Its core advantage lies in achieving multi-level stepped output voltage through the charging and discharging control of the first bus capacitor circuit 15, thereby reducing harmonic distortion, minimizing device voltage stress, and improving power quality. By connecting the first flying capacitor circuit 13 between different switching nodes and precisely controlling the switching sequence, the first bus capacitor circuit 15 can be charged, discharged, or output in series at different stages, thus forming multiple voltage levels (such as three-level, five-level, and seven-level) at the load end. For example, in a three-level converter, the output can present three states: +Vdc (Direct Current), 0, and -Vdc. Of course, in other embodiments, this first multilevel converter circuit 10 can also be applied to medium-voltage drives, industrial power management, or other reasonable electronic devices; this embodiment does not limit this application.

[0027] It is worth noting that the term "coupled" in this article refers to any direct or indirect connection. Therefore, if the article describes a first circuit coupled to a second circuit, it means that the first circuit can be directly connected to the second circuit via electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly connected to the second circuit via other circuits or connection methods via electrical connection or signal connection.

[0028] Specifically, the first input inductor 11 is used to couple with the AC power supply 101 to receive the AC input provided by the AC power supply 101, and to filter and limit the rate of change of current.

[0029] The first power switch circuit 12 is coupled to the first input inductor 11 and is used to be coupled to the drive control circuit 102 so as to be controlled by the drive control circuit 102 to perform main power conversion, thereby realizing corresponding current regulation and charging path adjustment.

[0030] The first flying capacitor circuit 13 includes at least two first flying capacitor groups 131, each group possibly consisting of one or more capacitors, to provide intermediate potential nodes in a multi-level topology and realize a multi-stage stepped waveform of the output voltage. Each first flying capacitor group 131 is coupled to the first power switching circuit 12.

[0031] The first charging circuit 14 includes a first input-side charging sub-circuit 141 and a first output-side charging sub-circuit 142. Each first input-side charging sub-circuit 141 is connected between two adjacent first flying capacitor groups 131 and is also connected to a first power switch circuit 12 for balancing or transferring energy in a specific switching state. The first output-side charging sub-circuit 142 is directly connected to the adjacent first flying capacitor group 131 and the adjacent first input-side charging sub-circuit 141 for auxiliary charging or voltage regulation.

[0032] The first bus capacitor circuit 15 is coupled to the first power switch circuit 12 and the first output side charging electronic circuit 142. It is used to stabilize the DC bus voltage, absorb / release pulsating power, realize multi-level stepping of the output voltage, and thus form multiple voltage levels (such as three-level, five-level, seven-level, etc.) at the load end.

[0033] When the drive control circuit 102 is not in operation (e.g., during startup, fault protection, or standby), i.e., during the uncontrolled rectification stage, the first power switch circuit 12 is in a non-active control state (e.g., the body diode is on or the switch is off but relies on parasitic paths). The system relies on the natural zero-crossing characteristics of the AC power supply 101 for rectification and charging, meaning the first power switch circuit 12 degenerates into a diode uncontrolled rectifier bridge. At this time, the first input inductor 11 receives the AC input provided by the AC power supply 101, and the first power switch circuit 12 interacts with each first input-side charging sub-circuit 14. The first input inductor 11 and the first output charging circuit 142 form a charging loop to receive the AC input sent by the first input inductor 11. The AC input is used to charge each first flying capacitor group 131 and the first bus capacitor circuit 15 alternately during the positive and negative half-cycles of the AC input. Through the coordinated design of the first input charging circuit 141 and the first output charging circuit 142, effective pre-charging of multiple first flying capacitor groups 131 can be achieved even in the rectification stage without active switching control, thus avoiding the problem of capacitor voltage imbalance when traditional flying capacitor multilevel converters start up.

[0034] In some embodiments, the drive control circuit 102 includes one or more of any reasonable circuit units with signal processing functions, such as a control chip, a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a microcontroller, a field-programmable gate array, a programmable logic device, discrete gate or transistor logic devices, or discrete hardware. This application does not limit the scope of the application.

[0035] The above scheme constructs a charging circuit through a first power switch circuit 12, each first input-side charging sub-circuit 141, and a first output-side charging sub-circuit 142. This circuit uses AC input to charge the first bus capacitor circuit 15 and each first flying capacitor group 131. This allows for effective pre-charging of each first flying capacitor group 131 before the drive control circuit 102 starts operating. This reduces the voltage difference between the switching devices in the switching circuit between each first flying capacitor group 131 and the first bus capacitor circuit 15, effectively protecting each capacitor and each switching device from overvoltage, overcurrent failure, or damage. It also effectively achieves voltage equalization among the capacitors in the first bus capacitor circuit 15.

[0036] Furthermore, startup reliability is improved: no additional pre-charging circuit is required; initial charging of the flying capacitor and bus capacitor is automatically completed during the uncontrolled rectification stage. High structural integration: the charging function is embedded in the main power topology, reducing external components. Suitable for high-level topologies: supports two or more first flying capacitor groups 131, expandable to five-level, seven-level, etc. Reduced control complexity: control strategies are simplified during startup or fault recovery phases.

[0037] In some embodiments, the voltage across each capacitor in each of the first flying capacitor groups 131 will be in a set ratio to the voltage across the first bus capacitor circuit 15, and the ratio is specifically determined by the number of bus capacitors connected in series in the first bus capacitor circuit 15. This application does not limit this ratio.

[0038] In some embodiments, during the startup phase of the drive control circuit 102, when the drive control circuit 102 sends a drive control signal to the first power switch circuit 12, it triggers the internal switching transistors of the first power switch circuit 12 to change their on / off states in order to regulate and convert the AC input. The triggered on switching transistors cooperate with each first input-side charging sub-circuit 141 and the first output-side charging sub-circuit 142 to form another charging circuit, so as to use the bus voltage of the first bus capacitor circuit 15 to charge each first flying capacitor group 131.

[0039] Understandably, during the startup phase, the voltage across each capacitor in each of the first flying capacitor groups 131 will again be in a set ratio with the voltage across the first bus capacitor circuit 15, thereby providing a good charging circuit before and after the drive control circuit 102 starts working, protecting the switching transistors from overvoltage and overcurrent failure and damage, and achieving voltage equalization among the multiple capacitors in the first bus capacitor circuit 15 by controlling the voltage across each capacitor in each of the first flying capacitor groups 131.

[0040] In some embodiments, the first control signal may be one or more of any reasonable control signal such as a PWM (Pulse Width Modulation) signal or a PFM (Pulse Frequency Modulation) signal, and this application does not limit it.

[0041] In some embodiments, the first bus capacitor circuit 15 includes N bus capacitors, the first power switch circuit 12 includes 2*N switching transistors, the number of the first flying capacitor group 131 is (N-1), and the number of the first input side charging electronic circuit 141 is (N-2).

[0042] Wherein, N is a positive integer greater than 2, such as 3, 4 or 5, or any reasonable number. That is, the voltage across each capacitor in each of the first flying capacitor groups 131 will eventually be in the ratio of 1 / N to the voltage across the first bus capacitor circuit 15 during the uncontrolled rectification stage and the start-up operation stage. This application does not limit this.

[0043] For ease of understanding, taking at least two first flying capacitor groups 131, including first flying capacitor group 1, first flying capacitor group 2, ..., first flying capacitor group n (n is a positive integer greater than 2), as an example, the first charging circuit 14 includes a first input-side charging sub-circuit 1, a first input-side charging sub-circuit 2, ..., a first input-side charging sub-circuit (n-1) and a first output-side charging sub-circuit 142. The first input-side charging sub-circuit 1 is coupled between the first flying capacitor group 1 and the first flying capacitor group 2, the first input-side charging sub-circuit 2 is coupled between the first flying capacitor group 2 and the first flying capacitor group 3, and so on. The first input-side charging sub-circuit (n-1) is coupled between the first flying capacitor group (n-1) and the first flying capacitor group n, and the first output-side charging sub-circuit 142 is coupled to the first flying capacitor group n and the first input-side charging sub-circuit (n-1). This will not be elaborated further here.

[0044] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the multilevel conversion circuit of this application. The difference between the multilevel conversion circuit in this embodiment and the first embodiment of the multilevel conversion circuit provided in this application is that the second power switch circuit 22 in the second multilevel conversion circuit 20 specifically includes a first upper switch sub-circuit 221 and a first lower switch sub-circuit 222, and the at least two second flying capacitor groups 231 in the second flying capacitor circuit 23 include a first-stage flying capacitor group 2311 and a second-stage flying capacitor group 2312.

[0045] Wherein, the first end of the second input inductor 21 (also denoted as L) is used to couple with the AC power supply 101, the second end of the second input inductor 21 is coupled to the first end of the first upper switch sub-circuit 221 and the first end of the first lower switch sub-circuit 222, the second end of the first upper switch sub-circuit 221 is coupled to the first end of the first stage flying capacitor group 2311 and the first end of the second input side charging sub-circuit 241, the second end of the first lower switch sub-circuit 222 is coupled to the second end of the first stage flying capacitor group 2311 and the second end of the second input side charging sub-circuit 241, the third end of the first upper switch circuit 221 is coupled to the first end of the second stage flying capacitor group 2312, and the first lower switch circuit 222 is coupled to the first end of the second stage flying capacitor group 2312. The third terminal of 22 is coupled to the second terminal of the second-stage flying capacitor group 2312. The third terminal of the second input-side charging sub-circuit 241 is coupled to the third terminal of the second-stage flying capacitor group 2312 and the third terminal of the second output-side charging sub-circuit 242. The fourth terminal of the first upper switch sub-circuit 221 is coupled to the first terminal of the second bus capacitor circuit 25. The fourth terminal of the first lower switch sub-circuit 222 is coupled to the second terminal of the second bus capacitor circuit 25. The first and second terminals of the second output-side charging sub-circuit 242 are coupled to the third and fourth terminals of the second bus capacitor circuit 25, respectively. The control terminals of the first upper switch sub-circuit 221 and the first lower switch sub-circuit 222 are coupled to the drive control circuit 102.

[0046] In some embodiments, the first-stage flying capacitor group 2311 includes a first flying capacitor Cf1, and the second-stage flying capacitor group 2312 includes a second flying capacitor Cf2 and a third flying capacitor Cf3. The first terminal of the first flying capacitor Cf1 is coupled to the second terminal of the first upper-side switching sub-circuit 221 and the first terminal of the second input-side charging sub-circuit 241. The second terminal of the first flying capacitor Cf1 is coupled to the second terminal of the first lower-side switching sub-circuit 222 and the second terminal of the second input-side charging sub-circuit 241. The first terminal of the second flying capacitor Cf2 is coupled to the third terminal of the first upper-side switching sub-circuit 221. The second terminal of the second flying capacitor Cf2 is coupled to the third terminal of the second input-side charging sub-circuit 241, the first terminal of the third flying capacitor Cf3, and the third terminal of the second output-side charging sub-circuit 242 (also referred to as OUTC). The second terminal of the third flying capacitor Cf3 is coupled to the third terminal of the first lower-side switching sub-circuit 222.

[0047] In some embodiments, the second bus capacitor circuit 25 includes a first bus capacitor Cbus1, a second bus capacitor Cbus2, and a third bus capacitor Cbus3. The first terminal of the first bus capacitor Cbus1 is coupled to the fourth terminal of the first upper-side switch sub-circuit 221. The second terminal of the first bus capacitor Cbus1 is coupled to the first terminal of the second output-side charging sub-circuit 242 and the first terminal of the second bus capacitor Cbus2. The second terminal of the second bus capacitor Cbus2 is coupled to the second terminal of the second output-side charging sub-circuit 242 and the first terminal of the third bus capacitor Cbus3. The second terminal of the third bus capacitor Cbus3 is coupled to the fourth terminal of the first lower-side switch sub-circuit 222.

[0048] In some embodiments, the first upper switch sub-circuit 221 specifically includes a first upper switch transistor S1u, a second upper switch transistor S2u, and a third upper switch transistor S3u, and the first lower switch sub-circuit 222 specifically includes a first lower switch transistor S1d, a second lower switch transistor S2d, and a third lower switch transistor S3d; wherein, the first terminal of the first upper switch transistor S1u is coupled to the second terminal of the second input inductor 21 and the second terminal of the first lower switch transistor S1d, the second terminal of the first upper switch transistor S1u is coupled to the first terminal of the second upper switch transistor S2u, the first terminal of the first flying capacitor Cf1, and the first terminal of the second input-side charging sub-circuit 241, the first terminal of the first lower switch transistor S1d is coupled to the second terminal of the second lower switch transistor S2d, the second terminal of the first flying capacitor Cf1, and the second terminal of the second input-side charging sub-circuit 241, the first terminal of the first lower switch transistor S1d is coupled to the second terminal of the second lower switch transistor S2d, the second terminal of the first flying capacitor Cf1, and the second terminal of the second input-side charging sub-circuit 241, and the second terminal of the second upper switch transistor S2u is coupled to the second terminal of the second upper switch transistor S2u. The first terminal of the third upper switch S3u is coupled to the first terminal of the second flying capacitor Cf2. The second terminal of the second flying capacitor Cf2 is coupled to the first terminal of the third flying capacitor Cf3, the third terminal of the second input-side charging electronic circuit 241, and the third terminal of the second output-side charging electronic circuit 242. The first terminal of the second lower switch S2d is coupled to the second terminal of the third lower switch S3d and the second terminal of the third flying capacitor Cf3. The second terminal of the third upper switch S3u is coupled to the first terminal of the first bus capacitor Cbus1. The first terminal of the third lower switch S3d is coupled to the second terminal of the third bus capacitor Cbus3. The third terminal of each of the following switches is coupled to the drive control circuit 102: the first upper switch S1u, the second upper switch S2u, the third upper switch S3u, the first lower switch S1d, the second lower switch S2d, and the third lower switch S3d.

[0049] In some embodiments, each switch in this document may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a transistor, a thin-film transistor, a field-effect transistor, or any other reasonable switch, and this application does not limit it.

[0050] It is worth noting that, to distinguish the two ends of each switching transistor except for the control terminal, one terminal is referred to as the first terminal and the other as the second terminal. When each switching transistor is a bipolar junction transistor (BJT), the control terminal, i.e., the third terminal, can specifically be the base, the first terminal as the collector, and the second terminal as the emitter; or, the third terminal can specifically be the base, the first terminal as the emitter, and the second terminal as the collector.

[0051] When the switching transistors mentioned above are MOSFETs, thin-film transistors, or field-effect transistors, the third terminal can be the gate, the first terminal is the drain, and the second terminal is the source; or, the third terminal can also be the gate, the first terminal is the source, and the second terminal is the drain.

[0052] In particular, when each switching transistor is a MOSFET, a thin film transistor, or a field-effect transistor, it can also be a composite transistor or a single transistor, which is not limited in this application.

[0053] Please continue reading. Figure 3 and Figure 4 ,in, Figure 3 yes Figure 2 A schematic diagram of the structure of the multi-level converter circuit in the first embodiment during the uncontrolled rectification stage and the positive half-cycle charging path of the AC input. Figure 4 yes Figure 2 A schematic diagram of the second embodiment of the multi-level converter circuit in the uncontrolled rectification stage and the charging path of the negative half-cycle of the AC input.

[0054] It is worth noting that after the second multi-level conversion circuit 20 is powered on, during the uncontrolled rectification stage, the AC power supply 101 connected to the inductor side will charge the second bus capacitor circuit 25 through the second power switch circuit 22, and simultaneously charge each flying capacitor through the second power switch circuit 22, each second input side charging sub-circuit 241 and the second output side charging sub-circuit 242.

[0055] In the uncontrolled rectification stage, the charging paths for the positive and negative half-cycles of the AC input are as follows: Figure 3 and Figure 4 As shown, the voltages across the first flying capacitor Cf1, the second flying capacitor Cf2, and the third flying capacitor Cf3 will eventually be 1 / 3 of the bus voltage.

[0056] Please continue reading. Figure 5 , Figure 5 yes Figure 2 A schematic diagram of the charging path of a multi-level conversion circuit during the startup phase, according to one embodiment.

[0057] It is worth noting that when the drive control circuit 102 starts working (the switching transistors start operating), i.e., during the startup phase, the second bus capacitor circuit 25 can still charge the first flying capacitor Cf1 through the conduction of the high-side switching transistors (the third upper switching transistor S3u and the second upper switching transistor S2u); when the low-side switching transistors are turned on, the second bus capacitor circuit 25 charges the third flying capacitor Cf3 through the conduction of the low-side switching transistors (the second lower switching transistor S2d and the third lower switching transistor S3d); finally, the voltages across the first flying capacitor Cf1 and the third flying capacitor Cf3 will be charged to be close to the voltages across the first bus capacitor Cbus1 and the third bus capacitor Cbus3 (i.e., 1 / 3 of the bus voltage).

[0058] Specifically, when the third upper switch S3u is turned on, the first bus capacitor Cbus1 and the second flying capacitor Cf2 form a charging circuit (which can be understood as the first bus capacitor Cbus1 and the second flying capacitor Cf2 being connected in parallel). When the third upper switch S3u and the second upper switch S2u are turned on, the first bus capacitor Cbus1, the first flying capacitor Cf1, and the second flying capacitor Cf2 form a charging circuit (which can be understood as the first bus capacitor Cbus1, the first flying capacitor Cf1, and the second flying capacitor Cf2 being connected in parallel).

[0059] Similarly, when the low-side switch, i.e., the third lower-side switch S3d, is turned on, the third bus capacitor Cbus3 and the third flying capacitor Cf3 form a charging circuit. When the second lower-side switch S2d and the third lower-side switch S3d are turned on, the third bus capacitor Cbus3, the first flying capacitor Cf1, and the third flying capacitor Cf3 form a charging circuit. Ultimately, the voltages across the first flying capacitor Cf1 and the third flying capacitor Cf3 will be charged to levels close to the voltages across the first bus capacitor Cbus1 and the third bus capacitor Cbus3, i.e., 1 / 3 of the bus voltage. The voltage across each switch will also be 1 / 3 of the bus voltage.

[0060] In summary, each flying capacitor is charged by the inductor side input before the drive control circuit 102 starts working. After the drive control circuit 102 starts working, it is charged by the bus voltage through the operation of the switching transistor. These charging paths still exist after steady-state operation, which is of great benefit to the bus voltage balance.

[0061] Please see Figure 6 , Figure 6This is a schematic diagram of the structure of the third embodiment of the multilevel conversion circuit of this application. The difference between the multilevel conversion circuit in this embodiment and the second embodiment of the multilevel conversion circuit provided in this application is that the second upper switch sub-circuit 321 in the third power switch circuit 32 of the third multilevel conversion circuit 30 specifically includes a fourth upper switch transistor S4u, and the second lower switch sub-circuit 322 includes a fourth lower switch transistor S4d.

[0062] Furthermore, the third flying capacitor circuit 33 includes at least two third flying capacitor groups 331, and also includes a third-stage flying capacitor group 3313. The third-stage flying capacitor group 3313 includes a fourth flying capacitor Cf4, a fifth flying capacitor Cf5, and a sixth flying capacitor Cf6. The third input-side charging sub-circuit 341 in the third charging circuit 34 includes a first-stage charging sub-circuit 3411 and a second-stage charging sub-circuit 3412. The first-stage charging sub-circuit 3411 includes a first charging unit sub-circuit Cu1, and the second-stage charging sub-circuit 3412 includes a second charging unit sub-circuit Cu2 and a third charging unit sub-circuit Cu3. The third output-side charging sub-circuit 342 includes a fourth charging unit sub-circuit Cu4 and a fifth charging unit sub-circuit Cu5. The third bus capacitor circuit 35 also includes a fourth bus capacitor Cbus4.

[0063] The first terminal of the third input inductor 31 (also denoted as L) is coupled to the AC power supply 101. The second terminal of the third input inductor 31 is coupled to the first terminal of the first upper switch S1u and the second terminal of the first lower switch S1d. The first terminal of the first charging unit sub-circuit Cu1 is coupled to the first terminal of the first flying capacitor Cf1, the second terminal of the first upper switch S1u, and the second terminal of the second lower switch S2d. The second terminal of the first charging unit sub-circuit Cu1 is coupled to the second terminal of the first flying capacitor Cf1, the first terminal of the first lower switch S1d, and the second terminal of the second lower switch S2d. The first terminal of the second charging unit sub-circuit Cu2 is coupled to the second flying capacitor Cf1. The first terminal of the cross capacitor Cf2, the second terminal of the second upper switch S2u, and the first terminal of the third upper switch S3u are coupled to the second terminal of the second charging unit sub-circuit Cu2, the third terminal of the first charging unit sub-circuit Cu1, the first terminal of the third flying cross capacitor Cf3, and the first terminal of the third charging unit sub-circuit Cu3. The second terminal of the third charging unit sub-circuit Cu3 is coupled to the first terminal of the second lower switch S2d, the second terminal of the third lower switch S3d, and the second terminal of the third flying cross capacitor Cf3. The first terminal of the fourth flying cross capacitor Cf4 is coupled to the second terminal of the third upper switch S3u and the second terminal of the fourth upper switch S4u. The first terminal, the second terminal of the fourth upper-side switch S4u is coupled to the first terminal of the first bus capacitor Cbus1; the second terminal of the fourth flying capacitor Cf4 is coupled to the third terminal of the second charging unit sub-circuit Cu2, the first terminal of the fifth flying capacitor Cf5, and the third terminal of the fourth charging unit sub-circuit Cu4; the second terminal of the fifth flying capacitor Cf5 is coupled to the third terminal of the third charging unit sub-circuit Cu3, the first terminal of the sixth flying capacitor Cf6, and the third terminal of the fifth charging unit sub-circuit Cu5; the second terminal of the sixth flying capacitor Cf6 is coupled to the first terminal of the third lower-side switch S3d and the second terminal of the fourth lower-side switch S4d; the first terminal of the fourth charging unit sub-circuit Cu4 is coupled to... The second terminal of the first bus capacitor Cbus1 and the first terminal of the second bus capacitor Cbus2 are connected. The second terminal of the fourth charging unit sub-circuit Cu4 is coupled to the first terminal of the fifth charging unit sub-circuit Cu5, the second terminal of the second bus capacitor Cbus2, and the first terminal of the third bus capacitor Cbus3. The second terminal of the fifth charging unit sub-circuit Cu5 is coupled to the second terminal of the third bus capacitor Cbus3 and the first terminal of the fourth bus capacitor Cbus4. The first terminal of the fourth lower switch S4d is coupled to the second terminal of the fourth bus capacitor Cbus4. The third terminals of the fourth upper switch S4u and the third terminals of the fourth lower switch S4d are coupled to the drive control circuit 102.

[0064] Please continue reading. Figure 7 , Figure 7 yes Figure 6 A schematic diagram of the structure of each charging unit sub-circuit in the multi-level conversion circuit according to the first embodiment.

[0065] In some embodiments, each of the first charging unit sub-circuit Cu1, the second charging unit sub-circuit Cu2, the third charging unit sub-circuit Cu3, the fourth charging unit sub-circuit Cu4, and the fifth charging unit sub-circuit Cu5 includes a first diode D1, a second diode D2, and a first current-limiting resistor Rx1. The second end of the first diode D1 constitutes the first end of the charging unit sub-circuit. The first end of the first diode D1 is coupled to the second end of the second diode D2 and the first end of the first current-limiting resistor Rx1. The first end of the second diode D2 constitutes the second end of the charging unit sub-circuit, and the second end of the first current-limiting resistor Rx1 constitutes the third end of the charging unit sub-circuit.

[0066] Please continue reading. Figure 8 , Figure 8 yes Figure 6 A schematic diagram of the second embodiment of each charging unit sub-circuit in the multi-level conversion circuit.

[0067] In other embodiments, each charging unit sub-circuit may further include a first charging switch Qc1, a second charging switch Qc2, and a second current-limiting resistor Rx2. The second terminal of the first charging switch Qc1 forms the first terminal of the charging unit sub-circuit. The first terminal of the first charging switch Qc1 is coupled to the second terminal of the second charging switch Qc2 and the first terminal of the first current-limiting resistor Rx1. The first terminal of the second charging switch Qc2 forms the second terminal of the charging unit sub-circuit, and the second terminal of the first current-limiting resistor Rx1 forms the third terminal of the charging unit sub-circuit.

[0068] Please continue reading. Figure 9 , Figure 9 yes Figure 6 A schematic diagram of the third embodiment of each charging unit sub-circuit in the multi-level conversion circuit.

[0069] In some other embodiments, each charging unit sub-circuit may further include a third current-limiting resistor Rx3, a fourth current-limiting resistor Rx4, a third diode D3, and a fourth diode D4. The first end of the third current-limiting resistor Rx3 forms the first end of the charging unit sub-circuit, the second end of the third current-limiting resistor Rx3 is coupled to the second end of the third diode D3, the first end of the third diode D3 is coupled to the second end of the fourth diode D4 and forms the third end of the charging unit sub-circuit, the first end of the fourth diode D4 is coupled to the first end of the fourth current-limiting resistor Rx4, and the second end of the fourth current-limiting resistor Rx4 forms the second end of the charging unit sub-circuit.

[0070] Please continue reading. Figure 10 , Figure 10 yes Figure 6A schematic diagram of the fourth embodiment of each charging unit sub-circuit in the multi-level conversion circuit.

[0071] In some other embodiments, each charging unit sub-circuit may further include a fifth diode D5, a sixth diode D6, a fifth current-limiting resistor Rx5, and a sixth current-limiting resistor Rx6. The second terminal of the fifth diode D5 constitutes the first terminal of the charging unit sub-circuit. The first terminal of the fifth diode D5 is coupled to the first terminal of the fifth current-limiting resistor Rx5. The second terminal of the fifth current-limiting resistor Rx5 is coupled to the first terminal of the sixth current-limiting resistor Rx6 and constitutes the third terminal of the charging unit sub-circuit. The second terminal of the sixth current-limiting resistor Rx6 is coupled to the second terminal of the sixth diode D6. The first terminal of the sixth diode D6 constitutes the second terminal of the charging unit sub-circuit.

[0072] Please continue reading. Figure 11 and Figure 12 ,in, Figure 11 yes Figure 6 A schematic diagram of the structure of the multi-level converter circuit in the first embodiment during the uncontrolled rectification stage and the positive half-cycle charging path of the AC input. Figure 12 yes Figure 6 A schematic diagram of the second embodiment of the multi-level converter circuit in the uncontrolled rectification stage and the charging path of the negative half-cycle of the AC input.

[0073] It is worth noting that after the third multi-level converter circuit 30 is powered on, during the uncontrolled rectification stage, the charging paths for the positive and negative half-cycles of the AC input are as follows: Figure 7 and Figure 8 As shown, the voltages across the first flying capacitor Cf1, the second flying capacitor Cf2, the third flying capacitor Cf3, the fourth flying capacitor Cf4, the fifth flying capacitor Cf5, and the sixth flying capacitor Cf6 will eventually be 1 / 4 of the bus voltage.

[0074] Please continue reading. Figure 13 , Figure 13 yes Figure 6 A schematic diagram of the charging path of a multi-level conversion circuit during the startup phase, according to one embodiment.

[0075] It is worth noting that when the drive control circuit 102 starts working (the switching transistors begin to operate), i.e., during the startup phase, the high-side switching transistors are turned on, and each bus capacitor can charge its corresponding flying capacitor through the conduction of the high-side switching transistors (the second upper switching transistor S2u, the third upper switching transistor S3u, and the fourth upper switching transistor S4u). When the low-side switching transistors are turned on, each bus capacitor charges its corresponding flying capacitor through the conduction of the low-side switching transistors (the second lower switching transistor S2d, the third lower switching transistor S3d, and the fourth lower switching transistor S4d). Ultimately, the voltage across each flying capacitor will be charged to a level close to (or one-third of) the voltage across each bus capacitor.

[0076] Specifically, when the fourth upper switch S4u is turned on, the first bus capacitor Cbus1 and the fourth flying capacitor Cf4 form a charging circuit (which can be understood as the first bus capacitor Cbus1 and the fourth flying capacitor Cf4 being connected in parallel). When the second upper switch S2u, the third upper switch S3u, and the fourth upper switch S4u are turned on, the first bus capacitor Cbus1, the second flying capacitor Cf2, and the fourth flying capacitor Cf4 form a charging circuit.

[0077] Similarly, when the low-side switch, i.e. the fourth lower switch S4d, is turned on, the fourth bus capacitor Cbus4 and the sixth flying capacitor Cf6 form a charging circuit. When the third lower switch S3d and the fourth lower switch S4d are turned on, the fourth bus capacitor Cbus4, the third flying capacitor Cf3, and the sixth flying capacitor Cf6 form a charging circuit. When the second lower switch S2d, the third lower switch S3d, and the fourth lower switch S4d are turned on, the fourth bus capacitor Cbus4, the first flying capacitor Cf1, the third flying capacitor Cf3, and the sixth flying capacitor Cf6 form a charging circuit.

[0078] In addition to the above paths, the number of charging circuits increases with the number of voltage levels. For example, when the fourth upper switch S4u is turned on, the first bus capacitor Cbus1 and the second bus capacitor Cbus2 are connected in series with the fourth flying capacitor Cf4 and the fifth flying capacitor Cf5 to form a charging circuit. When the fourth upper switch S4u and the third upper switch S3u are turned on, the first bus capacitor Cbus1 and the second bus capacitor Cbus2 are connected in series with the second flying capacitor Cf2 and the third flying capacitor Cf3 to form a charging circuit. When the fourth lower switch S4d is turned on, the third bus capacitor Cbus3 and the fourth bus capacitor Cbus4 are connected in series with the fifth flying capacitor Cf5 and the sixth flying capacitor Cf6 to form a charging circuit. When the third lower switch S3d and the fourth lower switch S4d are turned on, the third bus capacitor Cbus3 and the fourth bus capacitor Cbus4 are connected in series with the second flying capacitor Cf2 and the third flying capacitor Cf3 to form a charging circuit.

[0079] This application also employs a power regulation circuit; please refer to [link / reference needed]. Figure 14 , Figure 14 This is a schematic diagram of one embodiment of the power supply regulation circuit of this application. In this embodiment, the power supply regulation circuit 40 includes a fourth multi-level conversion circuit 41, an inverter resonant circuit 42, and a transformer rectifier output circuit 43.

[0080] The inverter resonant circuit 42 is coupled to the fourth multi-level conversion circuit 41 and the transformer rectifier output circuit 43. The transformer rectifier output circuit 43 is used to be coupled to the load working circuit 103. The fourth multi-level conversion circuit 41 is used to be coupled to the AC power supply 101. The fourth multi-level conversion circuit 41, the inverter resonant circuit 42, and the transformer rectifier output circuit 43 are used to be coupled to the drive control circuit 102.

[0081] In some embodiments, the fourth multi-level conversion circuit 41 may specifically correspond to any reasonable circuit topology such as a power factor correction circuit, a buck converter circuit, or a boost converter circuit, while the power supply regulation circuit 40 corresponds to a resonant converter circuit. This application does not limit this.

[0082] It should be noted that the fourth multilevel conversion circuit 41 described in this embodiment is any of the first multilevel conversion circuit 10, the second multilevel conversion circuit 20, or the third multilevel conversion circuit 30 described in the above embodiments. Please refer to [link / reference] for details. Figures 1-13 The relevant textual content will not be elaborated upon here.

[0083] This application also employs an electronic device; please refer to [link / reference needed]. Figure 15 , Figure 15 This is a schematic diagram of one embodiment of the electronic device of this application. In this embodiment, the electronic device 50 includes a housing 51 and a fifth multilevel conversion circuit 52 connected to the housing 51.

[0084] It should be noted that the multilevel conversion circuit 52 described in this embodiment is any of the first multilevel conversion circuit 10, the second multilevel conversion circuit 20, or the third multilevel conversion circuit 30 described in the above embodiments. Please refer to [link / reference] for details. Figures 1-13 The relevant textual content will not be elaborated upon here.

[0085] The beneficial effects of this application are as follows: Unlike the prior art, the multi-level conversion circuit provided by this application, in the uncontrolled rectification stage, receives the AC input provided by the AC power supply through the input inductor, and forms a charging circuit through the power switching circuit, each input-side charging sub-circuit, and the output-side charging sub-circuit. It receives the AC input sent by the input inductor and uses the AC input to charge the bus capacitor circuit and each flying capacitor group through the charging circuit. This allows for effective pre-charging of each flying capacitor group before the drive control circuit starts working, thereby reducing the voltage difference between each switching device in the switching circuit between each flying capacitor group and the bus capacitor circuit. This effectively protects each capacitor and each switching device from overvoltage, overcurrent failure, or damage, and also effectively achieves voltage equalization among the capacitors in the bus capacitor circuit.

[0086] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A multi-level conversion circuit, characterized in that, The multilevel conversion circuit includes: Input inductor, used for coupling with AC power supply; A power switching circuit, coupled to the input inductor, is used to couple with the drive control circuit; A flying capacitor circuit includes at least two flying capacitor groups, each of which is coupled to the power switching circuit. The charging circuit includes an input-side charging sub-circuit and an output-side charging sub-circuit. Each input-side charging sub-circuit is coupled to each of two adjacent flying capacitor groups and is also coupled to the power switching circuit. The output-side charging sub-circuit is directly coupled to the adjacent flying capacitor group and the adjacent input-side charging sub-circuit. The bus capacitor circuit is coupled to the power switch circuit and the output-side charging electronic circuit. In the uncontrolled rectification stage, the input inductor is configured to receive the AC input provided by the AC power supply; the power switching circuit, each of the input-side charging sub-circuits, and the output-side charging sub-circuit are configured to receive the AC input sent by the input inductor, so as to use the AC input to charge the bus capacitor circuit and each of the flying capacitor banks.

2. The multilevel conversion circuit according to claim 1, characterized in that, During the startup phase of the drive control circuit, the power switch circuit is configured to receive the corresponding drive control signal sent by the drive control circuit and change the switch state in response to the drive control signal, so as to cooperate with each of the input-side charging sub-circuits and the output-side charging sub-circuits to charge each of the flying capacitor banks using the bus voltage of the bus capacitor circuit.

3. The multilevel conversion circuit according to claim 2, characterized in that, The bus capacitor circuit includes N bus capacitors, the power switch circuit includes 2N switching transistors, the number of flying capacitor banks is N-1, and the number of input-side charging electronic circuits is N-2; where N is a positive integer greater than 2.

4. The multilevel conversion circuit according to claim 3, characterized in that, The power switching circuit includes an upper switch sub-circuit and a lower switch sub-circuit, and the at least two flying capacitor groups include a first-stage flying capacitor group and a second-stage flying capacitor group. Wherein, the first terminal of the input inductor is used to couple with the AC power supply; the second terminal of the input inductor is coupled to the first terminal of the upper switch sub-circuit and the first terminal of the lower switch sub-circuit; the second terminal of the upper switch sub-circuit is coupled to the first terminal of the first-stage flying capacitor group and the first terminal of the input-side charging sub-circuit; the second terminal of the lower switch sub-circuit is coupled to the second terminal of the first-stage flying capacitor group and the second terminal of the input-side charging sub-circuit; the third terminal of the upper switch sub-circuit is coupled to the first terminal of the second-stage flying capacitor group; and the third terminal of the lower switch sub-circuit... The input-side charging sub-circuit is coupled to the second terminal of the second-stage flying capacitor bank. The third terminal of the input-side charging sub-circuit is coupled to the third terminal of the second-stage flying capacitor bank and the third terminal of the output-side charging sub-circuit. The fourth terminal of the upper switch sub-circuit is coupled to the first terminal of the bus capacitor circuit. The fourth terminal of the lower switch sub-circuit is coupled to the second terminal of the bus capacitor circuit. The first and second terminals of the output-side charging sub-circuit are coupled to the third and fourth terminals of the bus capacitor circuit, respectively. The control terminals of the upper switch sub-circuit and the lower switch sub-circuit are coupled to the drive control circuit.

5. The multilevel conversion circuit according to claim 4, characterized in that, The first-stage flying capacitor bank includes a first flying capacitor, and the second-stage flying capacitor bank includes a second flying capacitor and a third flying capacitor. The first terminal of the first flying capacitor is coupled to the second terminal of the upper-side switching sub-circuit and the first terminal of the input-side charging sub-circuit. The second terminal of the first flying capacitor is coupled to the second terminal of the lower-side switching sub-circuit and the second terminal of the input-side charging sub-circuit. The first terminal of the second flying capacitor is coupled to the third terminal of the upper-side switching sub-circuit. The second terminal of the second flying capacitor is coupled to the third terminal of the input-side charging sub-circuit, the first terminal of the third flying capacitor, and the third terminal of the output-side charging sub-circuit. The second terminal of the third flying capacitor is coupled to the third terminal of the lower-side switching sub-circuit.

6. The multilevel conversion circuit according to claim 5, characterized in that, The bus capacitor circuit includes a first bus capacitor, a second bus capacitor, and a third bus capacitor. The first terminal of the first bus capacitor is coupled to the fourth terminal of the upper switch sub-circuit. The second terminal of the first bus capacitor is coupled to the first terminal of the output-side charging sub-circuit and the first terminal of the second bus capacitor. The second terminal of the second bus capacitor is coupled to the second terminal of the output-side charging sub-circuit and the first terminal of the third bus capacitor. The second terminal of the third bus capacitor is coupled to the fourth terminal of the lower switch sub-circuit.

7. The multilevel conversion circuit according to claim 6, characterized in that, The upper switch sub-circuit includes a first upper switch transistor, a second upper switch transistor, and a third upper switch transistor; the lower switch sub-circuit includes a first lower switch transistor, a second lower switch transistor, and a third lower switch transistor. Wherein, the first terminal of the first upper-mounted switch is coupled to the second terminal of the input inductor and the second terminal of the first lower-mounted switch; the second terminal of the first upper-mounted switch is coupled to the first terminal of the second upper-mounted switch, the first terminal of the first flying capacitor, and the first terminal of the input-side charging circuit; the first terminal of the first lower-mounted switch is coupled to the second terminal of the second lower-mounted switch, the second terminal of the first flying capacitor, and the second terminal of the input-side charging circuit; the second terminal of the second upper-mounted switch is coupled to the first terminal of the third upper-mounted switch and the first terminal of the second flying capacitor; the second terminal of the second flying capacitor is coupled to the third flying capacitor... The first terminal of the cross capacitor, the third terminal of the input-side charging electronic circuit, and the third terminal of the output-side charging electronic circuit; the first terminal of the second lower switch is coupled to the second terminal of the third lower switch and the second terminal of the third flying cross capacitor; the second terminal of the third upper switch is coupled to the first terminal of the first bus capacitor; the first terminal of the third lower switch is coupled to the second terminal of the third bus capacitor; and the third terminals of each of the first upper switch, the second upper switch, the third upper switch, the first lower switch, the second lower switch, and the third lower switch are all coupled to the drive control circuit.

8. The multilevel conversion circuit according to claim 7, characterized in that, The upper switch sub-circuit further includes a fourth upper switch transistor, the lower switch sub-circuit further includes a fourth lower switch transistor, at least two flying capacitor groups further include a third-stage flying capacitor group, the third-stage flying capacitor group includes a fourth flying capacitor, a fifth flying capacitor, and a sixth flying capacitor, the input-side charging sub-circuit includes a first-stage charging sub-circuit and a second-stage charging sub-circuit, the first-stage charging sub-circuit includes a first charging unit sub-circuit, the second-stage charging sub-circuit includes a second charging unit sub-circuit and a third charging unit sub-circuit, the output-side charging sub-circuit includes a fourth charging unit sub-circuit and a fifth charging unit sub-circuit, and the bus capacitor circuit further includes a fourth bus capacitor; Wherein, the first terminal of the first charging unit sub-circuit is coupled to the first terminal of the first flying capacitor, the second terminal of the first upper switch, and the second terminal of the second lower switch; the second terminal of the first charging unit sub-circuit is coupled to the second terminal of the first flying capacitor, the first terminal of the first lower switch, and the second terminal of the second lower switch; the first terminal of the second charging unit sub-circuit is coupled to the first terminal of the second flying capacitor, the second terminal of the second upper switch, and the first terminal of the third upper switch; the second terminal of the second charging unit sub-circuit is coupled to the second terminal of the second flying capacitor, the third terminal of the first charging unit sub-circuit, the first terminal of the third flying capacitor, and the first terminal of the third charging unit sub-circuit; the second terminal of the third charging unit sub-circuit is coupled to the first terminal of the second lower switch, the second terminal of the third lower switch, and the second terminal of the third flying capacitor; the first terminal of the fourth flying capacitor is coupled to the second terminal of the third upper switch and the first terminal of the fourth upper switch; the fourth... The second terminal of the upper-mounted switching transistor is coupled to the first terminal of the first bus capacitor. The second terminal of the fourth flying capacitor is coupled to the third terminal of the second charging unit sub-circuit, the first terminal of the fifth flying capacitor, and the third terminal of the fourth charging unit sub-circuit. The second terminal of the fifth flying capacitor is coupled to the third terminal of the third charging unit sub-circuit, the first terminal of the sixth flying capacitor, and the third terminal of the fifth charging unit sub-circuit. The second terminal of the sixth flying capacitor is coupled to the first terminal of the third lower-mounted switching transistor and the second terminal of the fourth lower-mounted switching transistor. The first terminal of the fourth charging unit sub-circuit is coupled to the second terminal of the first bus capacitor and the first terminal of the second bus capacitor. The second terminal of the fourth charging unit sub-circuit is coupled to the first terminal of the fifth charging unit sub-circuit, the second terminal of the second bus capacitor, and the first terminal of the third bus capacitor. The second terminal of the fifth charging unit sub-circuit is coupled to the second terminal of the third bus capacitor and the first terminal of the fourth bus capacitor. The first terminal of the fourth lower-mounted switching transistor is coupled to the second terminal of the fourth bus capacitor.

9. The multilevel conversion circuit according to claim 8, characterized in that, Each of the first, second, third, fourth, and fifth charging unit sub-circuits includes a first diode, a second diode, and a first current-limiting resistor. The second end of the first diode forms the first end of the charging unit sub-circuit. The first end of the first diode is coupled to the second end of the second diode and the first end of the first current-limiting resistor. The first end of the second diode forms the second end of the charging unit sub-circuit. The second end of the first current-limiting resistor forms the third end of the charging unit sub-circuit.

10. The multilevel conversion circuit according to claim 9, characterized in that, Each of the first, second, third, fourth, and fifth charging unit sub-circuits includes a first charging switch, a second charging switch, and a second current-limiting resistor. The second terminal of the first charging switch forms the first terminal of the charging unit sub-circuit. The first terminal of the first charging switch is coupled to the second terminal of the second charging switch and the first terminal of the first current-limiting resistor. The first terminal of the second charging switch forms the second terminal of the charging unit sub-circuit, and the second terminal of the first current-limiting resistor forms the third terminal of the charging unit sub-circuit.

11. The multilevel conversion circuit according to claim 8, characterized in that, Each of the first, second, third, fourth, and fifth charging unit sub-circuits includes a third current-limiting resistor, a fourth current-limiting resistor, a third diode, and a fourth diode. The first end of the third current-limiting resistor constitutes the first end of the charging unit sub-circuit. The second end of the third current-limiting resistor is coupled to the second end of the third diode. The first end of the third diode is coupled to the second end of the fourth diode and constitutes the third end of the charging unit sub-circuit. The first end of the fourth diode is coupled to the first end of the fourth current-limiting resistor. The second end of the fourth current-limiting resistor constitutes the second end of the charging unit sub-circuit.

12. The multilevel conversion circuit according to claim 8, characterized in that, Each of the first, second, third, fourth, and fifth charging unit sub-circuits includes a fifth diode, a sixth diode, a fifth current-limiting resistor, and a sixth current-limiting resistor. The second end of the fifth diode forms the first end of the charging unit sub-circuit. The first end of the fifth diode is coupled to the first end of the fifth current-limiting resistor. The second end of the fifth current-limiting resistor is coupled to the first end of the sixth current-limiting resistor and forms the third end of the charging unit sub-circuit. The second end of the sixth current-limiting resistor is coupled to the second end of the sixth diode. The first end of the sixth diode forms the second end of the charging unit sub-circuit.

13. A power supply regulation circuit, characterized in that, The power regulation circuit includes a multi-level conversion circuit, an inverter resonant circuit, and a transformer rectifier output circuit. The inverter resonant circuit is coupled to the multi-level conversion circuit and the transformer rectifier output circuit. The transformer rectifier output circuit is used to couple with the load operating circuit. The multilevel conversion circuit is the multilevel conversion circuit as described in any one of claims 1-12.

14. An electronic device, characterized in that, The electronic device includes a housing and a multilevel conversion circuit connected to the housing; The multilevel conversion circuit is the multilevel conversion circuit as described in any one of claims 1-12.

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