Control circuit of bridgeless PFC and electronic device

Abstract

The embodiment of the application discloses a control circuit of a bridgeless PFC and electronic equipment, and relates to the technical field of power factor correction. The control circuit is applied to a bridgeless PFC containing an inductor and a bidirectional switch module, an auxiliary winding coupled with the inductor is arranged, a detection signal representing voltage change of the auxiliary winding is output by a voltage change detection module, a switch tube drain-source resonant voltage rising / falling moment and an alternating voltage direction of the bridgeless PFC input alternating current are identified from the detection signal by a detection signal analysis module, and a valley bottom conduction moment is determined by selecting a voltage rising moment / falling moment corresponding to the alternating voltage direction. A control module controls the bidirectional switch module to be turned on at the valley bottom conduction moment, and the conduction duration is determined based on a difference between an output end voltage and a preset reference voltage. The application can realize precise control of the valley bottom conduction of the bridgeless PFC by only one set of auxiliary windings, has simple circuit structure, occupies small volume and has low manufacturing cost.

Description

Technical Field

[0001] This application relates to the field of power factor correction technology, specifically to a bridgeless PFC control circuit and electronic device. Background Technology

[0002] Bridgeless PFC circuits, by eliminating the rectifier bridge in traditional bridged PFC circuits, significantly reduce power loss and improve power conversion efficiency, and are widely used in various power electronic devices such as power adapters and power control ICs. The core control challenge of bridgeless PFC circuits lies in valley conduction control. Valley conduction refers to turning on the switching transistor when the drain-source voltage of the switching transistor reaches its minimum value, thereby reducing the switching transistor's turn-on loss and further improving circuit efficiency.

[0003] In existing valley conduction control schemes for bridgeless PFC, since the input power of bridgeless PFC is AC, valley conduction control needs to be processed according to the AC voltage direction of the input AC power. In practical applications, valley conduction control of bridgeless PFC generally adopts two sets of auxiliary windings with opposite polarities. By using a switching device to switch the output of the other set of auxiliary windings as the valley conduction detection signal when the AC voltage direction of the AC power changes, valley conduction under different input AC voltage directions can be achieved.

[0004] However, the existing solution has obvious drawbacks: it requires the addition of multiple sets of auxiliary windings and a large number of detection and winding switching devices, resulting in a complex circuit structure, high hardware costs, and additional components occupying a lot of space, which is not conducive to the design of miniaturized electronic devices such as power adapters. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a bridgeless PFC control circuit and electronic device, improving upon the situation where related technologies require two sets of auxiliary windings, which complicates the circuit.

[0006] In a first aspect, embodiments of this application provide a control circuit for a bridgeless power distribution (PFC). The bridgeless PFC includes at least an inductor and a bidirectional switching module. The control circuit includes an auxiliary winding, a voltage change detection module, a detection signal parsing module, and a control module. The auxiliary winding is coupled to the inductor. The voltage change detection module is connected to the auxiliary winding and configured to output a detection signal based on the voltage across the auxiliary winding, the detection signal representing a change in the voltage across the auxiliary winding. The detection signal parsing module is connected to the voltage change detection module and configured to parse the voltage rise time, voltage fall time, and AC voltage direction from the detection signal, and to determine the AC voltage direction based on the AC voltage. The voltage direction is selected by choosing either the voltage rise time or the voltage fall time, and the valley conduction time is determined based on the selected time; wherein, the voltage rise time is the rise time of the drain-source resonant voltage of the switching transistor, the voltage fall time is the fall time of the drain-source resonant voltage of the switching transistor, and the AC voltage direction is the AC voltage direction of the input AC current of the bridgeless PFC; the control module is connected to the detection signal analysis module, the bidirectional switching module, and the output terminal of the bridgeless PFC; wherein, the control module is configured to control the bidirectional switching module to conduct at the valley conduction time, and the conduction duration is determined based on the difference between the output terminal voltage and the preset reference voltage; the output terminal voltage is the output terminal voltage of the bridgeless PFC.

[0007] Optionally, when the drain-source voltage of the switching transistor increases, the voltage across the auxiliary winding increases synchronously, and the voltage change detection module samples a pulse voltage with a positive amplitude. When the drain-source voltage of the switching transistor decreases, the voltage across the auxiliary winding decreases synchronously, and the voltage change detection module samples a pulse voltage with a negative amplitude. The detection signal records the time of occurrence of the pulse voltage, as well as the magnitude and direction of the pulse voltage.

[0008] Optionally, the detection signal parsing module includes: a detection signal splitting unit, connected to the voltage change detection module, configured to output a first judgment signal when a pulse voltage with a positive amplitude is detected in the detection signal, and to output a second judgment signal when a pulse voltage with a negative amplitude is detected in the detection signal; and a mode judgment unit, connected to the detection signal splitting unit, configured to start detection when the bidirectional switch module is turned off, and to continuously output a third judgment signal until the next detection start when a pulse voltage with a positive amplitude or the first judgment signal is detected in the detection signal, and to continuously output a fourth judgment signal until the next detection start when a pulse voltage with a negative amplitude or the second judgment signal is detected in the detection signal. The valley conduction timing design unit, connected to the detection signal splitting unit and the mode judgment unit, is configured to output a valley conduction signal after a preset time delay when both a first judgment signal and a fourth judgment signal are detected simultaneously; and to output a valley conduction signal after a preset time delay when both a second judgment signal and a third judgment signal are detected simultaneously. The times at which the first and second judgment signals are output correspond to the voltage rise and voltage fall times, respectively. Assuming the input terminal of the bridgeless PFC is connected to the inductor on one side as the live wire and the other side as the neutral wire, then: the third judgment signal corresponds to the AC voltage direction from the live wire to the neutral wire; the fourth judgment signal corresponds to the AC voltage direction from the neutral wire to the live wire.

[0009] Optionally, the detection signal splitting unit includes: a hysteresis comparator, a rising edge detector, and a falling edge detector; the valley conduction timing design unit includes: a first AND gate, a second AND gate, a first OR gate, and a pulse delay unit; wherein, the first input terminal of the hysteresis comparator is connected to the voltage change detection module, the second input terminal is connected to a preset high voltage reference value and a low voltage reference value, and the output terminal of the hysteresis comparator is connected to the input terminals of the rising edge detector and the falling edge detector, respectively; the falling edge detector outputs a first judgment signal, and the output terminal of the falling edge detector is connected to the mode judgment unit and the valley conduction timing design unit, respectively. The input terminal of the bottom conduction timing design unit is connected; the rising edge detector outputs a second judgment signal, and the output terminal of the rising edge detector is connected to the input terminals of the mode judgment unit and the valley conduction timing design unit, respectively; the input terminal of the first AND logic gate is connected to the second judgment signal and the third judgment signal, respectively; the input terminal of the second AND logic gate is connected to the first judgment signal and the fourth judgment signal, respectively; the input terminal of the first OR logic gate is connected to the output terminals of the first AND logic gate and the second AND logic gate, respectively; the output terminal of the first OR logic gate is connected to the input terminal of the pulse delay unit, and the output terminal of the pulse delay unit is connected to the control module.

[0010] Optionally, the detection signal analysis module further includes an anomaly correction unit, configured to output a valley conduction signal when the off-time of the bidirectional switch module exceeds a preset maximum off-time and no valley conduction signal is detected during the off-time.

[0011] Optionally, the mode determination unit further includes a counting subunit, configured to count the number of times the first determination signal and the second determination signal are detected within a preset n switching cycles. If the number of times the first determination signal is detected is greater than or equal to a preset number, the mode determination unit outputs a third determination signal; otherwise, the mode determination unit does not output a third determination signal. If the number of times the second determination signal is detected is greater than or equal to a preset number, the mode determination unit outputs a fourth determination signal; otherwise, the mode determination unit does not output a fourth determination signal. Wherein, n is a positive integer.

[0012] Optionally, the voltage change detection module includes a capacitor and a resistor; the first end of the auxiliary winding is grounded, the second end of the auxiliary winding is connected to the first end of the capacitor, the second end of the capacitor is connected to the first end of the resistor and the detection signal parsing module respectively, and the second end of the resistor is grounded.

[0013] Optionally, the detection signal records the occurrence time, magnitude, and direction of the pulse voltage at the connection point between the voltage change detection module and the detection signal analysis module.

[0014] Optionally, the control module includes: a voltage sampler, a voltage loop, a PWM modulator, an RS flip-flop, and a drive control unit; the input terminal of the voltage sampler is connected to the output terminal of the bridgeless PFC, and the output terminal is connected to the input terminal of the voltage loop; the output terminal of the voltage loop is connected to the first input terminal of the PWM modulator, wherein a preset reference voltage is set in the voltage loop, and the voltage loop outputs a conduction time modulation signal based on the preset reference voltage; the second input terminal of the PWM modulator is connected to the PWM modulation carrier, and the output terminal is connected to the first input terminal of the RS flip-flop; the second input terminal of the RS flip-flop is connected to the output terminal of the detection signal analysis module, and the output terminal of the RS flip-flop is connected to the input terminal of the drive control unit; the drive control unit is connected to the bidirectional switch module and is configured to control the bidirectional switch module to turn on or off based on the output signal of the RS flip-flop.

[0015] In a second aspect, embodiments of this application provide an electronic device, including: a microcontroller and a bridgeless PFC control circuit, wherein the microcontroller is configured to output an enable signal, and the control module in the bridgeless PFC control circuit is electrically connected to the microcontroller.

[0016] The beneficial effects of the control circuit of the bridgeless PFC provided in this application embodiment are as follows: The inductor is the core energy storage element of the bridgeless PFC. Its voltage change directly reflects key control information such as the change of the drain-source resonant voltage of the switching transistor and the direction of the input AC voltage. In this application embodiment, the voltage change of the inductor is transmitted through the auxiliary winding coupled with the bridgeless PFC inductor. The voltage change detection module converts it into a resolvable detection signal. The detection signal analysis module can accurately analyze the voltage rise and fall time and the direction of the input AC voltage. Based on the AC voltage direction, the valley conduction time is adaptively determined. The control module combines the feedback state of the output voltage and the valley conduction time to realize the on and off control of the bidirectional switching module. The entire circuit does not need to set two sets of auxiliary windings with opposite polarities, nor does it need to design complex winding switching devices. This effectively reduces the number of components used in the circuit, simplifies the circuit structure, and significantly reduces the hardware cost. At the same time, it reduces the space occupied by the components, which is conducive to the miniaturization design of electronic devices such as power adapters. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 A schematic diagram of a bridgeless PFC control circuit structure provided in an embodiment of this application; Figure 2 A schematic diagram of a detection signal parsing module circuit structure is provided for another embodiment of this application; Figure 3 Another embodiment of this application provides a control circuit structure for a bridgeless PFC; Figure 4 A current flow diagram for AC-Switch PFC input with positive polarity provided in another embodiment of this application; Figure 5 A current flow diagram for an AC-Switch PFC input with negative polarity provided in another embodiment of this application; Figure 6 This is a diagram showing the main waveform of PWM modulation provided in another embodiment of this application; Figure 7 A waveform diagram of the main signal for a first type of valley opening control provided in another embodiment of this application; Figure 8 This application provides a current flow diagram for a Totem-Pole PFC input voltage with positive polarity, as shown in another embodiment. Figure 9This application provides a current flow diagram for a Totem-Pole PFC input voltage with negative polarity, as another embodiment of the present application. Figure 10 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application; Figure 11 The control circuit for the Totem-Pole PFC provided in another embodiment of this application; Figure 12 This is a block diagram of the VIN_PHASE circuit provided in yet another embodiment of this application; Figure 13 The second type of valley opening control main signal waveform diagram is provided for another embodiment of this application. Detailed Implementation

[0019] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "electrically connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. Furthermore, technical features involved in the different embodiments of this application described below may be combined with each other as long as they do not conflict with each other.

[0021] Bridgeless PFC circuits, as highly efficient power factor correction circuits, are widely used in power electronic devices such as power adapters and power control ICs. Their core requirement is to achieve valley-level conduction to reduce switching losses while ensuring stable output voltage. However, existing valley-level conduction control schemes require multiple auxiliary windings and complex detection and switching circuits, resulting in high circuit cost and large size.

[0022] Therefore, this application provides a bridgeless PFC control circuit. Please refer to [link to relevant documentation]. Figure 1 A bridgeless PFC includes at least: an inductor And a bidirectional switch module, wherein the bidirectional switch module includes several switching transistors. Please refer to... Figure 1 The control circuit 100 of the bridgeless PFC includes an auxiliary winding 200, a voltage change detection module 300, a detection signal analysis module 400, and a control module 500.

[0023] Auxiliary winding 200 and inductor Coupling. Inductance. It is the core energy storage component of the bridgeless PFC, and its voltage change directly reflects key control information such as the change of the drain-source resonant voltage of the switching transistor and the direction of the input AC voltage; the auxiliary winding 200 is connected to the inductor Coupling can transmit inductance through the principle of electromagnetic induction. The voltage changes provide the original physical signal for subsequent analysis of the valley conduction time, and the coupling design ensures the real-time and accuracy of signal acquisition. No additional main circuit is required, and it does not affect the normal operation of the bridgeless PFC main circuit.

[0024] The voltage change detection module 300 is connected to the auxiliary winding 200 and is configured to output a detection signal based on the voltage across the auxiliary winding 200. Detection signal This characterizes the change in voltage across the auxiliary winding 200. Because the drain-source voltage of the switching transistor... During the on / off and resonant states of the switching transistor, a rise / fall phenomenon will occur, and the on / off times of the switching transistor can be known. Therefore, by detecting the signal... The rise / fall times of the drain-source resonant voltage of the switching transistor can be analyzed.

[0025] The detection signal analysis module 400 is connected to the voltage change detection module 300 and is configured to analyze the detection signal. The system analyzes the voltage rise time, voltage fall time, and AC voltage direction, and selects the voltage rise time or voltage fall time based on the AC voltage direction. The valley conduction time is determined based on the selected time. Since the time from the start of the rise / fall to the valley is within a certain range, the valley conduction time can be determined by analyzing the moment when the resonant voltage starts to rise / fall to the valley. Whether the resonant voltage rises to the valley or falls to the valley depends on the AC voltage direction of the input AC current. Therefore, by knowing the AC voltage direction and the voltage rise / fall time, the valley conduction time can be analyzed.

[0026] The control module 500 is connected to the detection signal analysis module, the bidirectional switch module, and the output terminal of the bridgeless PFC; wherein, the control module 500 is configured to control the bidirectional switch module to conduct at the valley conduction moment, and the conduction duration is based on the output terminal voltage. The difference between the voltage and the preset reference voltage is determined; the output voltage is the output voltage of the bridgeless PFC.

[0027] In this embodiment, the auxiliary winding 200 is connected to the inductor of the bridgeless PFC. Coupling, when inductor When the current in the auxiliary winding 200 changes, an induced voltage is generated across the auxiliary winding 200. The voltage change detection module 300 directly or indirectly detects the change in voltage across the auxiliary winding 200 in real time and outputs a detection signal based on the rate of change of this voltage. The detection signal analysis module 400 is used to analyze the detection signal. The key information (voltage rise time, voltage fall time, and AC voltage direction) is used to determine the valley conduction time, and then the control module 500 controls the conduction and cutoff of the bidirectional switch module.

[0028] In general, the bridgeless PFC control circuit 100 provided in this application embodiment can transmit inductance through a single auxiliary winding 200. The voltage change is analyzed to determine the final valley conduction time. This eliminates the need for multiple sets of auxiliary windings with opposite polarities in traditional solutions, as well as the need for a matching input voltage polarity detection circuit and winding switching device. This significantly reduces the number of components used, simplifies the circuit architecture, lowers hardware costs, and reduces the circuit space required, making it suitable for the design needs of miniaturized electronic devices such as power adapters.

[0029] Optionally, the drain-source voltage of the switching transistor When the voltage increases, the voltage across the auxiliary winding... As the voltage increases synchronously, the voltage change detection module 300 samples a pulse voltage with a positive amplitude, which is then applied to the drain-source voltage of the switching transistor. When the voltage decreases, the voltage across the auxiliary winding... As the voltage decreases synchronously, the voltage change detection module 300 samples a pulse voltage with a negative amplitude. Detection signal The record includes the time of occurrence of the pulse voltage, as well as the magnitude and direction of the pulse voltage.

[0030] It should be noted that the voltage change detection module 300 can also be configured to detect the drain-source voltage of the switching transistor. When the amplitude increases, a pulse voltage with a negative amplitude is sampled, which is related to the drain-source voltage of the switching transistor. When the voltage decreases, the purpose of the voltage change detection module 300, which samples a pulse voltage with a positive amplitude, is to make the detection signal... The recorded pulse voltage can reflect the drain-source voltage of the switching transistor. The specific logical judgment method for increasing / decreasing should not be a limitation of this application.

[0031] Optionally, please refer to Figure 2 The detection signal analysis module 400 includes: The detection signal splitting unit 410, connected to the voltage change detection module 300, is configured to detect a detection signal. When a pulse voltage with a positive amplitude is present, the first judgment signal (vs_neg=1) is output, indicating that the detection signal has been detected. When a pulse voltage with a negative amplitude exists, a second judgment signal (vs_pos=1) is output. The mode determination unit 420, connected to the detection signal splitting unit 410, is configured to initiate detection when the bidirectional switch module is turned off, and to detect a detection signal. If a pulse voltage with a positive amplitude is present or a first judgment signal is present, a third judgment signal (lmode=1) is continuously output until the next detection is initiated. If a pulse voltage with a negative amplitude or a second judgment signal is present, the fourth judgment signal (nmode=1) will be continuously output until the next detection is started. The valley conduction timing design unit 430, connected to the detection signal splitting unit 410 and the mode judgment unit 420, is configured to output a valley conduction signal after a preset time delay when the first judgment signal (vs_neg=1) and the fourth judgment signal (nmode=1) are detected to be present simultaneously; and to output a valley conduction signal after a preset time delay when the second judgment signal (vs_pos=1) and the third judgment signal (lmode=1) are detected to be present simultaneously. The times when the first judgment signal and the second judgment signal are output correspond to the times when the voltage rises and the times when the voltage falls, respectively. The direction of the AC voltage corresponding to the third judgment signal is from the live wire to the neutral wire. The fourth judgment signal corresponds to the direction of the AC voltage from the neutral wire to the live wire.

[0032] Optionally, please refer to Figure 2 The detection signal splitting unit 410 includes: a hysteresis comparator CMP1, a rising edge detector, and a falling edge detector; The valley conduction timing design unit 430 includes: a first AND gate AND1, a second AND gate AND2, a first OR gate OR1, and a pulse delay unit DLY; In this circuit, the first input terminal of the hysteresis comparator CMP1 is connected to the voltage change detection module 300, and the second input terminal is connected to the preset voltage reference. The hysteresis comparator corresponds to two reference values: a high reference value and a low reference value. and low voltage reference value The output of the hysteresis comparator CMP1 is connected to the input of the rising edge detector and the falling edge detector, respectively. As an example, the hysteresis comparator CMP1 used here employs an inverted output, that is, when... Greater than When, the output vs_cmp of CMP1 switches from high level to low level, Less than When the output vs_cmp of CMP1 switches from low to high, the output of the hysteresis comparator CMP1 is connected to the input of the rising edge detector and the falling edge detector, respectively.

[0033] It is understandable that the hysteresis comparator CMP1 can also use a non-inverting output, and the relevant logic can be modified adaptively afterwards. A non-inverting output means: when... Greater than When, the output vs_cmp of CMP1 switches from low to high level, Less than At that time, the output vs_cmp of CMP1 switches from high level to low level.

[0034] The falling edge detector outputs a first judgment signal (vs_neg=1), and the output terminal of the falling edge detector is connected to the input terminal of the mode judgment unit and the valley conduction time design unit 430, respectively. The rising edge detector outputs a second judgment signal (vs_pos=1), and the output terminal of the rising edge detector is connected to the input terminal of the mode judgment unit and the valley conduction time design unit 430, respectively. The input terminals of the first AND logic gate AND1 are connected to the second judgment signal and the third judgment signal (lmode=1), respectively; The input terminals of the second AND logic gate AND2 are connected to the first judgment signal and the fourth judgment signal (nmode=1), respectively; The input of the first OR gate OR1 is connected to the output of the first AND gate AND1 and the second AND gate AND2, respectively; the output of the first OR gate OR1 is connected to the input of the pulse delay unit DLY, and the output of the pulse delay unit DLY is connected to the control module 500.

[0035] It is understandable that the first judgment signal corresponds to the detection signal. The rising moment of the positive pulse is the falling edge of the comparator CMP1 output vs_cmp, corresponding to vs_neg and the second judgment signal. The moment the negative pulse falls is the rising edge of the comparator CMP1 output vs_cmp, which is vs_pos.

[0036] In one possible implementation, the first input of the hysteresis comparator CMP1 is a non-inverting input, and the second input is an inverting input. The hysteresis comparator CMP1 will detect the signal. This analog signal is converted into a digital signal, vs_cmp. The transition of vs_cmp from high to low (falling edge) corresponds to the detection signal. The positive pulse, the transition from low to high (rising edge) of vs_cmp corresponds to the detection signal. A negative pulse. When the falling edge detector detects a falling edge of vs_cmp, a high level is output. (First judgment signal), otherwise output If the rising edge detector detects a rising edge of vs_cmp, output... (Second judgment signal), otherwise output The mode judgment unit 420 detects the first and second judgment signals within a preset time after the bidirectional switch module is turned off, thus determining the direction of the AC input voltage. Within this preset time, if vs_neg=1 is detected, the direction of the AC output voltage is determined to be from the previously assumed live wire L to the neutral wire N, and a third judgment signal, lmode=1, is output. Within a preset time after the gate is turned off, if vs_pos=1 is detected, the direction of the AC output voltage is determined to be from the previously assumed neutral wire N to the live wire L, and a fourth judgment signal, nmode=1, is output. This achieves the determination of the AC input voltage direction.

[0037] In this embodiment, the analog signal is converted into a digital signal using a hysteresis comparator CMP1, and then detected using a rising / falling edge detector. The rising / falling moments are determined, and the direction of the AC voltage of the input AC power is determined using the mode determination unit 420, because the AC voltage direction is from the live wire L to the neutral wire N ( In the case of ), The resonance drops to its lowest point, and the direction of the AC voltage changes from the neutral wire (N) to the live wire (L). In the case of ), The resonance rises to the bottom, so logic gates are used to select... and The moment / and The moment, that is The moment when the price drops / rises to the bottom.

[0038] Optionally, please refer to Figure 3The auxiliary winding 200 is an inductor. The voltage change detection module 300 includes: a capacitor and a resistor; inductance The first terminal is grounded, inductor The second end of the capacitor is connected to the first end of the capacitor. The second end of the capacitor is connected to the first end of the resistor and the detection signal analysis module 400. The second end of the resistor is grounded.

[0039] This embodiment is based on the principle of RC differentiating circuit, and the inductor The continuous voltage signal is converted into a pulse signal (i.e., a detection signal) that reflects the rate of voltage change.

[0040] Optionally, the control module 500 includes: a voltage sampler VSENSE, a voltage loop VLOOP, a PWM modulator, an RS flip-flop, and a drive control unit DRIVER; As an example, the PWM modulator may be a comparator CMP2.

[0041] The input of the voltage sampler VSENSE is connected to the output of the bridgeless PFC, and the output is connected to the input of the voltage loop VLOOP. The output of the voltage loop VLOOP is connected to the first input of the comparator CMP2. A preset reference voltage is set within the voltage loop VLOOP, and the voltage loop VLOOP outputs a conduction time modulation signal based on this preset reference voltage. ; The second input of comparator CMP2 is connected to the PWM modulation carrier, and its output is connected to the first input of the RS flip-flop. The second input terminal of the RS flip-flop is connected to the output terminal of the detection signal analysis module 400, and the output terminal of the RS flip-flop is connected to the input terminal of the drive control unit DRIVER. The drive control unit (DRIVER) is connected to the bidirectional switch module and the drive signal transmission unit, and is configured to control the bidirectional switch module to turn on or off based on the output signal gate of the RS trigger.

[0042] As an example, the control module 500, on the one hand, controls the bidirectional switch module to turn on based on the valley conduction signal output by the detection signal analysis module 400; on the other hand, it detects the output voltage and compares it with a preset reference voltage to obtain an error voltage, which is then used for voltage loop compensation and PWM modulation to control the on-time of the bidirectional switch module, i.e., to control the off-time of the bidirectional switch module. If the detected output voltage value is lower than the preset reference voltage, V... C The on-time of the bidirectional switch module is increased to raise the output voltage; when the detected output voltage value is higher than the preset reference voltage, V CThe conduction time of the bidirectional switch module is reduced, thereby lowering the output voltage and ultimately stabilizing the output voltage in a closed-loop control near the set value.

[0043] In one possible implementation, please refer to Figure 3 The first input of comparator CMP2 is the inverting input, and the second input is the non-inverting input. The PWM modulation carrier is represented by time on the x-axis and voltage on the y-axis. The ramp function, the first input terminal of the RS flip-flop is the R terminal, and the second input terminal is the S terminal. When the output voltage is lower than the reference voltage, the voltage loop VLOOP causes... As the ramp value increases, the ramp time of the ramp function becomes longer. This means the time elapsed since the gate was turned on (reset signal output by comparator CMP2) increases, resulting in a longer high-level output from the gate. Conversely, a decrease in the ramp value results in a shorter high-level output from the gate. Increase and grow, with By reducing and shortening the time, the on-time of the bidirectional switch is adjusted based on the error between the output voltage and the reference voltage, so that the output voltage is stabilized at the set value, thus achieving closed-loop control.

[0044] In one possible implementation, the voltage sampler VSENSE outputs the voltage. The calculation formulas include:

[0045] In the formula, Indicates the sampling ratio. This indicates the output voltage of the bridgeless PFC.

[0046] In one possible implementation, the mode determination unit 420 determines the conduction state of the switch transistor through the gate. A high level on the gate corresponds to the switch transistor being on, and a low level on the gate corresponds to the switch transistor being off.

[0047] Optionally, the detection signal analysis module 400 further includes an anomaly correction unit, configured to output a valley conduction signal when the off-time of the bidirectional switch module exceeds a preset maximum off-time and no valley conduction signal is detected during the off-time.

[0048] In one possible implementation, the anomaly correction unit includes: a maximum shutdown time timing circuit TOFF_MAX and a second OR logic gate or2, wherein the input of TOFF_MAX is connected to the control module 500, the output of TOFF_MAX is connected to the first input of or2, and the second input of or2 is connected to the output of DLY.

[0049] In this embodiment, TOFF_MAX uses the turn-on and turn-off signals (gate) output by the control module 500 to determine whether the turn-off time of the bidirectional switch module is abnormal. If the valley turn-on signal is not detected continuously, TOFF_MAX generates a pulse toff_max and sets zcd=1 to re-turn on the bidirectional switch module.

[0050] Optionally, the mode judgment unit 420 further includes a counting subunit, configured to count the number of times the first judgment signal and the second judgment signal are detected within a preset n switching cycles respectively. If the number of times the first judgment signal is detected is greater than or equal to the preset number, the mode judgment unit 420 outputs a third judgment signal; otherwise, the mode judgment unit 420 does not output a third judgment signal. If the number of times the second judgment signal is detected is greater than or equal to the preset number, the mode judgment unit 420 outputs the fourth judgment signal; otherwise, the mode judgment unit 420 does not output the fourth judgment signal. Where n is a positive integer.

[0051] Optionally, detect signal The system records the occurrence time, magnitude, and direction of the pulse voltage at the connection point between the voltage change detection module 300 and the detection signal analysis module 400.

[0052] In this embodiment, the voltage change at the aforementioned connection point is selected as the detection signal. , making The direction of the pulse voltage is consistent with the direction of the voltage change rate, thus achieving a precise conversion between "voltage change amount - pulse signal".

[0053] In one possible implementation, The calculation formulas include:

[0054] In the formula, The resistance value indicates the resistance of the resistor. This indicates the capacitance value of the capacitor. Indicates the voltage across the auxiliary winding The differential, Indicates time The differential.

[0055] In summary, the bridgeless PFC control circuit 100 provided in this application embodiment has at least the following technical effects: 1) Simplify circuit structure and reduce hardware cost: The voltage change signal is collected by only a single auxiliary winding 200 coupled with a bridgeless PFC inductor. This eliminates the need for multiple auxiliary windings with opposite polarities in traditional solutions, as well as the need for the matching input voltage polarity detection circuit and winding switching device. This greatly reduces the number of components used, simplifies the circuit architecture, reduces hardware cost, and reduces the circuit space occupied, making it suitable for the design requirements of miniaturized electronic devices such as power adapters.

[0056] 2) Strong anti-interference capability and high working stability: The detection signal analysis module has a built-in counting subunit, which filters out instantaneous interference through multi-cycle signal statistics, improving the accuracy of AC voltage direction judgment; at the same time, an abnormality correction unit is added. When the circuit resonance is abnormal and the valley conduction signal cannot be detected, the switch can be forcibly triggered to conduct through the preset maximum turn-off time to avoid circuit shutdown or output instability, and ensure the continuous and stable operation of the bridgeless PFC system.

[0057] As another aspect of this application, this application provides an electronic device. Please refer to... Figure 10 The electronic device 600 includes a microcontroller 700 and a bridgeless PFC control circuit 100 as described in the above embodiments. The control module 500 in the bridgeless PFC control circuit 100 is electrically connected to the microcontroller 700.

[0058] The microcontroller 700 sends an enable signal to the control module 500 according to the control command, causing the control module 500 to enter the working state. The control circuit 100 of the bridgeless PFC is used to control the turn-on and turn-off of the valley conduction bidirectional switch module by the control module 500, so as to achieve precise valley conduction control.

[0059] In one possible implementation, please refer to Figure 3 The bridgeless PFC is an AC-Switch PFC (AC switching power factor correction circuit). Figure 3 Includes: includes communication input ( EMI filtering and protection circuits (EMI & Safety), PFC output filter circuits (Filter), AC-Switch PFC circuits and control circuits for bridgeless PFC, Figure 3 The auxiliary winding in the middle is an inductor , For the AC input voltage, and for ease of description later, this invention is provided with an inductor L connected. PFC One side is the live wire (L), and the other side is the neutral wire (N). When the voltage of the live wire (L) is greater than the voltage of the neutral wire (N), When the polarity is positive, the voltage at line L is less than the voltage at line N. It has a negative polarity.

[0060] EMI & Safety mainly refers to EMI filtering devices and safety protection devices, which will not be detailed here.

[0061] AC-Switch PFC is the bridgeless PFC main circuit topology used in the embodiments of this application. For example... Figure 4 As shown, when the PFC input voltage polarity is positive and Q1 and Q2 are turned on, the current flows through the red arrow. Q1 and Q2 are in the excitation stage, and the current value increases. When Q1 and Q2 are turned off, the current flows through D1 and D4, which is called the demagnetization stage, and the current decreases. When the current drops to 0, it enters the resonance stage. Q1 and Q2 are turned on again when the voltage between the two drains of Q1 and Q2 drops to the minimum, which is called valley conduction. Figure 5 The diagram shows the current flow when the PFC input voltage polarity is negative. When Q1 and Q2 are turned on, the excitation current value initially increases, but the direction of the AC voltage is opposite to that when the input is positive. After Q1 and Q2 are turned off, the demagnetization stage begins, and the current decreases. At this time, D3 and D2 are turned on.

[0062] The drive control unit (DRIVER) is used to drive the two floating switches Q1 and Q2, and the voltage sampler (VSENSE) uses the output voltage as the voltage loop control input.

[0063] In this embodiment, the on-time of the gate is controlled by sampling the output voltage and passing it through a voltage loop and PWM modulation, and the valley on-time signal zcd is obtained by detecting the voltage change of the auxiliary winding.

[0064] To illustrate the method proposed in this invention, such as Figure 6 The diagram shown is a main waveform of PWM modulation. Figure 6 The horizontal axis represents time. It is the output of the voltage loop VLOOP. When the output voltage is lower than the reference voltage, Increase, according to Figure 6 It can be seen that the conduction time of the gate at this time is... Follow Increases when the voltage increases, and conversely, decreases when the output voltage is higher than the reference voltage. Reduce the gate's conduction time. Follow The output voltage is reduced by decreasing, thus achieving closed-loop control.

[0065] like Figure 7 The waveform diagram shows the main signal for valley floor opening control. Figure 7 The horizontal axis represents time. Figure 7The left and right halves of the diagram represent the waveforms captured over several switching cycles when the input voltage is positive and negative, respectively. The left half of the diagram shows the waveform for positive polarity, and the right half shows the waveform for negative polarity.

[0066] like Figure 7 On the left half, when the positive polarity is input, At this moment, the gate turns off Q1 and Q2, and the demagnetization phase begins. The voltage between the two drains (Q1D, Q2D) of Q1 and Q2... Rise to At the same time, the voltage of the auxiliary winding increases accordingly. A positive pulse was recorded.

[0067] like Figure 7 On the right half, when inputting negative polarity, At this moment, the gate turns off Q1 and Q2, and the demagnetization phase begins. The voltage between the two drains (Q1D, Q2D) of Q1 and Q2... Descend to - At the same time, the voltage of the auxiliary winding also decreases. A negative pulse was recorded.

[0068] Therefore, according to the gate being turned off Detecting either a positive or negative pulse determines the polarity of the current input voltage. When PFC starts working, the gate turns on, and the loop control controls the on-time. After the gate turns off, mode selection begins. If a positive or negative pulse is detected... A positive pulse (vs_neg=1) indicates lmode (positive polarity of the input voltage). If this occurs... A negative pulse (vs_pos=1) is nmode (negative polarity of input voltage).

[0069] In lmode, vs_pos will be selected as the valley-opening signal zcdpre; in nmode, vs_neg will be selected as the valley-opening signal zcdpre. According to... Figure 7 As shown in the waveform, the valley-turn-on signal zcdpre is delayed by a pulse delay circuit (DLY). Then, the valley-level conduction time (vly.1, vly.2) will be obtained. Conducting at these times will enable valley-level activation. In actual PFC operation, methods such as maximum frequency limiting or frequency reduction control are added to control PFC to conduct at the nth valley (n=1, 2, 3...). Figure 5 The example only illustrates the case where the second valley (vly.2) is conducting.

[0070] After the gate is turned off The type of pulse (lmode) or type (nmode) is determined by whether it is a positive or negative pulse. To obtain a stable judgment, a counting judgment can be added. For example, if a positive or negative pulse can be continuously detected for n consecutive switching cycles, it can be judged as lmode or nmode.

[0071] like Figure 7 The waveform shown is At a certain moment, the inductor current drops to 0, entering the resonance phase, and the resonance state can be detected, such as... The waveform shown. When the resonant voltage decreases, When a negative pulse is obtained, the resonant voltage rises. A positive pulse is obtained. After passing through the hysteresis comparator CMP1, vs_cmp is obtained, when... When vs_cmp transitions from high to low, When vs_cmp transitions from low to high, the rising edge detection circuit outputs a pulse voltage vs_pos; when vs_cmp transitions from high to low, the falling edge detection circuit outputs a pulse voltage vs_neg.

[0072] When the valley-level conduction signal ZCD is not detected, the maximum off-time timing circuit will control the output pulse Toff_max to turn on the gate, and the maximum off-time will be [not specified]. It can be reasonably configured according to the actual design, taking effect in abnormal conditions and not taking effect during normal operation.

[0073] As an example, Figure 3 In and The same-name and different-name terminals can be configured differently according to the actual application. When different configurations are adopted, the judgment logic of subsequent modules needs to be adjusted.

[0074] In one possible implementation, the bridgeless PFC can be a Totem-Pole PFC. For a Totem-Pole PFC, the current flow direction is as follows: Figure 8 and Figure 9 As shown. When the input voltage is positive, Q2 acts as a switching transistor for the excitation current. When Q2 is turned on, the current is as follows: Figure 8 The red arrow indicates the excitation phase, where the current is rising; when Q2 is turned off, the current is as follows: Figure 8 The green arrow indicates that the demagnetizing current flows through the parasitic diode of Q1 and D4. When the input voltage is negative, Q1 acts as a switch for the excitation current; when Q1 is turned on, the current is as follows... Figure 9 The red arrow indicates the excitation phase, where the current is rising; when Q1 is turned off, the current is as follows: Figure 9The green arrow indicates that the demagnetizing current flows through the parasitic diode of Q2 and D3.

[0075] The circuit block diagram of this invention based on Totem-Pole PFC (Totem-Pole Power Factor Correction Circuit) is as follows: Figure 11 As shown. The control module 500 adds an input voltage phase detection module (VIN_PHASE), and the drive control unit (DRIVER) is divided into separate drives for switches Q1 and Q2. Among them, Figure 11 PL indicates connection to the inductor and then to the live wire (L) via filtering and EMI shielding. PN indicates connection to the neutral wire (N) via filtering and EMI shielding. AMP1 represents a differential operational amplifier; its output voltage is the voltage at the non-inverting input minus the voltage at the inverting input, yielding the sampled value of the input AC signal. The `phase_flag` indicates the polarity of the input voltage. When the voltage at terminal L is greater than the voltage at terminal N, that is, the voltage at terminal PL is greater than the voltage at terminal PN, therefore... When the input is positive, since the inverting terminal of CMP1 is grounded (i.e., the voltage is 0), phase_flag outputs a high level; similarly, when the voltage at the L terminal is less than the voltage at the N terminal, phase_flag outputs a low level. DRVL is the driver for Q2, and DRVH is the driver for Q1. DRVL and DRVH obtain signals that can directly drive Q1 / Q2 based on the input signals, controlling the on / off state of Q1 and Q2. When the input to DRVL is high, Q2 is turned on; when the input is low, Q2 is turned off, and the same applies to DRVH.

[0076] like Figure 12 The diagram shows the circuit block diagram of VIN_PHASE, which includes an operational amplifier circuit AMP1 and a comparator CMP1. It samples the input voltage and compares the samples to determine the polarity of the input voltage. When the polarity is positive, phase_flag outputs a high level; when the polarity is negative, phase_flag outputs a low level. That is, phase_flag represents the polarity (or phase) of the input voltage. When phase_flag=1, it indicates a positive AC input voltage; when phase_flag=0, it indicates a negative AC input voltage. Figure 13 The main operating waveforms for phase control and drive are as follows: when the polarity is positive, the gate output drives Q2 through DRVL; when the polarity is negative, the gate output drives Q1 through DRVH.

[0077] The principles of other parts are the same as those of the AC-Switch PFC part, so they will not be repeated here.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A control circuit for a bridgeless PFC, wherein the bridgeless PFC comprises at least: An inductor and a bidirectional switching module, wherein the bidirectional switching module includes a plurality of switching transistors, characterized in that it includes: An auxiliary winding is coupled to the inductor; A voltage change detection module, connected to the auxiliary winding, is configured to output a detection signal based on the voltage across the auxiliary winding, the detection signal representing the change in voltage across the auxiliary winding; The detection signal parsing module, connected to the voltage change detection module, is configured to parse the voltage rise time, voltage fall time, and AC voltage direction from the detection signal, and select the voltage rise time or voltage fall time according to the AC voltage direction, and determine the valley conduction time based on the selected time. Wherein, the voltage rise time is the rise time of the drain-source resonant voltage of the switching transistor, the voltage fall time is the fall time of the drain-source resonant voltage of the switching transistor, and the AC voltage direction is the AC voltage direction of the input AC power of the bridgeless PFC. The control module is connected to the detection signal analysis module, the bidirectional switch module, and the output terminal of the bridgeless PFC. The control module is configured as follows: The bidirectional switch module is controlled to turn on at the valley bottom conduction moment, and the conduction duration is determined based on the difference between the output voltage and the preset reference voltage; The output voltage is the output voltage of the bridgeless PFC.

2. The control circuit for bridgeless PFC according to claim 1, characterized in that, When the drain-source voltage of the switching transistor increases, the voltage across the auxiliary winding increases synchronously, and the voltage change detection module samples a pulse voltage with a positive amplitude. When the drain-source voltage of the switching transistor decreases, the voltage across the auxiliary winding decreases synchronously, and the voltage change detection module samples a pulse voltage with a negative amplitude. The detection signal records the time of occurrence of the pulse voltage, as well as the magnitude and direction of the pulse voltage.

3. The control circuit for bridgeless PFC according to claim 2, characterized in that, The detection signal parsing module includes: The detection signal splitting unit, connected to the voltage change detection module, is configured to output a first judgment signal when a pulse voltage with a positive amplitude is detected in the detection signal, and to output a second judgment signal when a pulse voltage with a negative amplitude is detected in the detection signal. The mode judgment unit, connected to the detection signal splitting unit, is configured to start detection when the bidirectional switch module is turned off. When a pulse voltage with a positive amplitude or a first judgment signal is detected in the detection signal, a third judgment signal is continuously output until the next detection is started. When a pulse voltage with a negative amplitude or a second judgment signal is detected in the detection signal, a fourth judgment signal is continuously output until the next detection is started. The valley conduction timing design unit, connected to the detection signal splitting unit and the mode judgment unit, is configured to output a valley conduction signal after a preset time delay when the first judgment signal and the fourth judgment signal are detected to exist simultaneously; and to output a valley conduction signal after a preset time delay when the second judgment signal and the third judgment signal are detected to exist simultaneously. The times at which the first judgment signal and the second judgment signal are output correspond to the times when the voltage rises and when the voltage falls, respectively. If the input terminal of the bridgeless PFC is connected to the inductor on one side as the live wire and the other side as the neutral wire, then: the direction of the AC voltage corresponding to the third judgment signal is from the live wire to the neutral wire. The fourth judgment signal corresponds to the direction of the AC voltage from the neutral wire to the live wire.

4. The control circuit for bridgeless PFC according to claim 3, characterized in that, The detection signal splitting unit includes: a hysteresis comparator, a rising edge detector, and a falling edge detector; The valley conduction timing design unit includes: a first AND gate, a second AND gate, a first OR gate, and a pulse delay unit; The first input terminal of the hysteresis comparator is connected to the voltage change detection module, the second input terminal is connected to the preset high voltage reference value and low voltage reference value, and the output terminal of the hysteresis comparator is connected to the input terminals of the rising edge detector and the falling edge detector, respectively. The falling edge detector outputs a first judgment signal, and the output terminal of the falling edge detector is connected to the input terminals of the mode judgment unit and the valley conduction time design unit, respectively. The rising edge detector outputs a second judgment signal, and the output terminal of the rising edge detector is connected to the input terminals of the mode judgment unit and the valley conduction time design unit, respectively. The input terminals of the first AND logic gate are connected to the second and third judgment signals, respectively; The input terminals of the second AND logic gate are connected to the first judgment signal and the fourth judgment signal, respectively; The input of the first OR logic gate is connected to the output of the first AND logic gate and the second AND logic gate, respectively; the output of the first OR logic gate is connected to the input of the pulse delay unit, and the output of the pulse delay unit is connected to the control module.

5. The control circuit for bridgeless PFC according to claim 3, characterized in that, The detection signal analysis module also includes an anomaly correction unit, which is configured to output a valley conduction signal when the off-time of the bidirectional switch module exceeds the preset maximum off-time and no valley conduction signal is detected during the off-time.

6. The control circuit for bridgeless PFC according to claim 3, characterized in that, The mode judgment unit further includes a counting subunit, which is configured to count the number of times the first judgment signal and the second judgment signal are detected within a preset n switching cycles. If the number of times the first judgment signal is detected is greater than or equal to the preset number, the mode judgment unit outputs a third judgment signal; otherwise, the mode judgment unit does not output a third judgment signal. If the number of times the second judgment signal is detected is greater than or equal to the preset number, the mode judgment unit outputs the fourth judgment signal; otherwise, the mode judgment unit does not output the fourth judgment signal. Where n is a positive integer.

7. The control circuit for bridgeless PFC according to any one of claims 1 to 6, characterized in that, The voltage change detection module includes: a capacitor and a resistor; The first end of the auxiliary winding is grounded, the second end of the auxiliary winding is connected to the first end of the capacitor, the second end of the capacitor is connected to the first end of the resistor and the detection signal analysis module, and the second end of the resistor is grounded.

8. The control circuit for bridgeless PFC according to claim 7, characterized in that, The detection signal record includes the occurrence time, magnitude, and direction of the pulse voltage at the connection point between the voltage change detection module and the detection signal analysis module.

9. The control circuit for bridgeless PFC according to any one of claims 1 to 6, characterized in that, The control module includes: a voltage sampler, a voltage loop, a PWM modulator, an RS flip-flop, and a drive control unit; The input terminal of the voltage sampler is connected to the output terminal of the bridgeless PFC, and the output terminal is connected to the input terminal of the voltage loop. The output terminal of the voltage loop is connected to the first input terminal of the PWM modulator. A preset reference voltage is set in the voltage loop, and the voltage loop outputs a conduction time modulation signal based on the preset reference voltage. The second input terminal of the PWM modulator is connected to the PWM modulation carrier, and the output terminal is connected to the first input terminal of the RS flip-flop. The second input terminal of the RS flip-flop is connected to the output terminal of the detection signal parsing module, and the output terminal of the RS flip-flop is connected to the input terminal of the drive control unit. The drive control unit is connected to the bidirectional switch module and is configured to control the bidirectional switch module to turn on or off based on the output signal of the RS trigger.

10. An electronic device, characterized in that, include: The microcontroller is configured to output an enable signal; The control circuit of the bridgeless PFC as described in claim 9, wherein the control module in the bridgeless PFC control circuit is electrically connected to the microcontroller.

Images