High-speed low-power hybrid dynamic comparator with low power supply voltage and low latency

Abstract

The application belongs to the field of integrated circuits, and discloses a high-speed low-power mixed dynamic comparator with low power supply voltage and low delay, which comprises: a pre-amplification part mainly composed of a first tail transistor M1, input transistors M3 and M4 and a transmission gate; and a latch part mainly composed of a second tail transistor M2, transistors M5 and M6 and cross-coupled transistors M7 and M8; the two parts are connected through differential nodes VOP and VON, and the conduction state of M1 and M2 is controlled by a clock signal. The comparator reduces the transistor stack number between the power supply and the ground, and is beneficial to work under low power supply voltage. The comparator amplifies the input differential signal in the first clock phase and directly stores it on the parasitic capacitance of the latch stage, directly enters the latch regeneration process in the second clock phase, shortens the delay from the clock to the output, and can maintain stable delay within a wide input common-mode voltage range.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a high-speed, low-power hybrid dynamic comparator that balances low power supply voltage and low latency. Background Technology

[0002] With the continuous evolution of integrated circuit technology towards deep submicron and ultra-deep submicron CMOS processes, and the rapid development of fields such as the Internet of Things, 5G communication, high-speed data acquisition, medical imaging, and automotive electronics, the application scenarios of high-speed analog-to-digital converters (ADCs) and various high-speed mixed-signal circuits are becoming increasingly widespread, placing increasingly stringent demands on the performance of core unit devices. As a key core unit in ADCs that realizes the conversion between analog and digital signals, the comparator's performance parameters directly determine the conversion accuracy, operating speed, power consumption, and reliability of the entire ADC and even the mixed-signal circuit system, making it one of the core bottlenecks affecting the upper limit of system performance.

[0003] Specifically, the comparator's key performance indicators, such as operating speed, response delay, input common-mode range, power consumption, and anti-interference capability, all have a decisive impact on the overall performance of the entire circuit system. In continuous-time pipelined ADCs, SAR ADCs (successive approximation ADCs), and other multi-stage analog-to-digital converters with strict timing requirements, the performance constraints of comparators are even more pronounced. These systems often require high-precision conversion under high-frequency sampling conditions. This necessitates that the comparator not only have a high operating frequency to adapt to high-speed sampling but also an extremely short clock-to-output delay. This allows for sufficient timing margins for signal transmission and processing in the preceding and following stages, effectively reducing the complexity of system-level timing design, avoiding conversion errors due to insufficient timing, and improving system stability and reliability. Simultaneously, with the widespread adoption of portable electronic devices, wearable devices, and low-power IoT terminals, low-voltage power supply has become an industry trend. This further requires comparators to maintain excellent performance under low-voltage operating conditions and possess low power consumption to extend device battery life and meet green and energy-saving design requirements.

[0004] Currently, various comparator structure designs have been proposed in the industry, but they still have shortcomings in achieving a balance between the three core performance indicators of speed, low voltage adaptability, and low power consumption. These shortcomings cannot fully meet the application requirements of current high-speed, low-power, and low-voltage mixed-signal circuits. Specific deficiencies can be further analyzed in conjunction with existing technical literature as follows: The StrongARM comparator, proposed in Behzad Razavi's paper "An 8-bit 150-MHz CMOS A / D converter," is a widely used dynamic comparator structure in the industry. It relies on a positive feedback mechanism to achieve fast signal comparison and possesses a certain high-speed performance. However, this structure has significant inherent drawbacks: due to its vertically stacked transistor layout and large number of stacked layers, it requires a high power supply voltage margin. In low-voltage supply scenarios, the transistors are prone to leaving the saturation region and entering the linear region, leading to decreased gain, increased noise, and significantly limited comparison accuracy and operating speed, making it unsuitable for low-voltage design requirements. Furthermore, its single-tail current structure means that changes in the input common-mode voltage directly affect the stability of the tail current, resulting in increased comparator response delay, decreased operating speed, and susceptibility to kickback noise. In scenarios with high common-mode voltage fluctuations, the comparison reliability is significantly reduced, making it difficult to adapt to applications with a wide common-mode range. In addition, the input common-mode voltage of the StrongARM comparator needs to be stable within a specific range. If the common-mode voltage is too high, the input transistors will enter the linear region and the gain will deteriorate. If the common-mode voltage is too low, it will significantly affect the comparison speed, further limiting its application range.

[0005] In his paper "A double-tail latch-type voltage senseamplifier with 18ps setup + hold time," Daniel Schinkel proposed a Schinkel comparator with a double-tail structure to address the shortcomings of StrongARM comparators. This structure reduces transistor stacking effects by setting independent tail currents for the pre-amplifier stage and latch stage, improving operating speed to some extent and expanding the input common-mode range, thus offering performance advantages in high-speed scenarios. However, this structure still suffers from significant power consumption drawbacks: its pre-amplifier and latch stages operate synchronously, meaning both stages are active throughout the entire comparison cycle. Even after the latch stage has latched the signal, the pre-amplifier stage continues to consume current, resulting in high overall power consumption and low energy efficiency during the comparison process, making it difficult to meet the design requirements of low-power systems. Furthermore, the voltage provided by its parasitic capacitance cannot ensure complete establishment of the input signal, further affecting comparison accuracy.

[0006] To address the power consumption and low voltage adaptability issues of the two aforementioned structures, Michiel van Elzakker proposed the Elzakker comparator in his paper "A 10-bit charge-redistribution ADC consuming 1.9 μW at 1 MS / s". This structure optimizes the energy consumption of the comparison process and reduces power consumption to some extent by delaying the latch stage's turn-on time, enabling the preamplifier stage and latch stage to operate asynchronously. However, this structure still suffers from incomplete energy optimization: after each comparison, the output node of the preamplifier still needs to be fully discharged before entering the next comparison cycle. This full discharge process consumes a large amount of unnecessary energy, failing to achieve further power consumption reduction. Especially in high-frequency sampling scenarios, frequent full discharges lead to a sharp increase in power consumption, making it difficult to adapt to the application requirements of high-speed, low-power applications. In addition, the dynamic bias scheme based on the Elzakker comparator also suffers from problems such as the lack of a DC path for the tail current source and the difficulty in fully establishing the input signal, affecting the comparator's resolution and reliability.

[0007] In summary, existing comparator designs, whether StrongARM, Schinkel, or Elzakker, all have their own performance limitations and cannot simultaneously meet the three core performance requirements of high speed, low voltage adaptability, and low power consumption. With the continuous advancement of integrated circuit technology and the expansion of application scenarios, existing comparator structures are no longer sufficient to meet the practical application needs of high-speed mixed-signal circuits, low-power portable devices, and other fields. Therefore, developing a comparator structure that can simultaneously achieve high-speed operation, low voltage adaptability, and low power consumption has become a pressing technical problem for those skilled in the art. Summary of the Invention

[0008] The purpose of this invention is to overcome at least one deficiency of the prior art and provide a high-speed, low-power hybrid dynamic comparator that balances low power supply voltage and low latency.

[0009] The technical solution adopted in this invention is: The first aspect of the present invention provides: A hybrid dynamic comparator that balances low supply voltage and low latency includes a pre-amplifier section and a latch section, wherein: The preamplifier section mainly consists of the first tail transistor M1, input transistors M3 and M4, and a transmission gate; The latching section mainly consists of the second tail transistor M2, transistors M5 and M6, and cross-coupled transistors M7 and M8; The pre-amplification section and the latching section are connected through differential nodes VOP and VON, and the conduction state of the first tail transistor M1 and the second tail transistor M2 is controlled by a clock signal. When the clock signal CLK is low, M1 is turned on and M2 is turned off. The comparator operates in amplification mode. After the input signal is amplified by M3 and M4, a differential voltage is directly established at the differential nodes VOP and VON and stored in the parasitic capacitance. When the clock signal CLK is high, M1 is off and M2 is on, the comparator enters latch regeneration mode, and latches the output directly based on the differential voltage established on VOP and VON.

[0010] In some instances, the pre-amplification section and the latch section share differential nodes VOP and VON, and the amplification result directly drives the latch regeneration without going through an intermediate stage.

[0011] In some instances, the source of the first tail transistor M1 is grounded to GND, the drain is connected to the source of M3 and M4, and the gate is connected to the inverted clock ICLK.

[0012] In some instances, M3 and M4 receive differential input signals VIP (positive input) and VIN (negative input), respectively. The drain of M3 is connected to node VON, and the drain of M4 is connected to node VOP. The voltage difference between VIP and VIN is converted into a drain current difference, which forms a pre-amplified differential voltage at VOP and VON.

[0013] In some instances, the source of the second tail transistor M2 is grounded to GND, the drain is connected to the source of M5 and M6, and the gate is connected to the clock CLK.

[0014] In some instances, the gate of M5 is connected to VOP, and the drain of M5 is connected to VON; The gate of M6 is connected to VON, and the drain of M6 is connected to VOP; The gates of M5 and M6 are respectively connected to the two ends of the transmission gate; M5 / M6 inputs the differential voltage stored on VOP / VON to the cross-coupled PMOS transistors M7 / M8.

[0015] In some instances, a transmission gate circuit controlled by an inverting clock ICLK is provided between the gates of M5 and M6, with its control terminal connected to ICLK. During the pre-amplification stage, ICLK is high, the transmission gate is turned on, and the differential nodes VOP and VON, while maintaining the gain, reset the logic level output to a level close to the common-mode voltage, eliminating the residual charge from the previous comparison. During the latching stage, ICLK is low, the transmission gate is turned off, and the differential voltage established by the pre-amplification is fully preserved, providing a stable input for latch regeneration.

[0016] In some instances, the cross-coupled transistors M7 and M8 form a positive feedback latch structure, with their sources connected to the power supply VDD; the gate of M7 is connected to VOP and the drain is connected to VON; the gate of M8 is connected to VON and the drain is connected to VOP.

[0017] In some instances, the clock signal is generated by a two-phase clock, so that the preamplifier section and the latch section do not conduct simultaneously, resulting in no overlapping power consumption.

[0018] These features can be combined arbitrarily as long as they do not conflict with each other.

[0019] A second aspect of the invention provides: an integrated circuit having the hybrid dynamic comparator described in the first aspect of the invention.

[0020] The beneficial effects of this invention are: The low-power hybrid dynamic comparator of some embodiments of the present invention combines a pre-amplification stage with a latch stage and employs dual-tailed transistors and two-phase clock control. This allows the comparator to amplify the input differential signal in the first clock phase and directly store the amplified result on the parasitic capacitance associated with the latch stage. In the second clock phase, it directly enters the latch regeneration process, thereby eliminating the output node discharge stage in the traditional StrongARM comparator and shortening the clock-to-output delay. At the same time, this structure reduces the number of transistors stacked between the power supply and ground, which is beneficial for operation under low power supply voltage and maintaining stable delay over a wide input common-mode voltage range.

[0021] Simulation results of some examples of the low-power hybrid dynamic comparator of this invention show that, under 28nm CMOS process and 1V power supply voltage conditions, a clock-to-output delay of 35ps can be achieved at a 6GHz sampling frequency and 1mV differential input; and it can maintain a low delay over a wide input common-mode voltage range, thereby achieving comprehensive optimization of high speed, low voltage, low delay and low power consumption. Attached Figure Description

[0022] Figure 1 These are transistor-level circuits for dynamic comparators in some examples of this invention.

[0023] Figure 2 This describes the operating states of the hybrid dynamic comparator in amplification mode and latching mode in some examples of the present invention.

[0024] Figure 3 These are waveform comparison diagrams of hybrid dynamic comparators and traditional StrongARM comparators in some examples of this invention.

[0025] Figure 4 This invention provides a comparison of the delay, differential input, and common-mode voltage of some examples of the hybrid dynamic comparator with those of the traditional StrongARM comparator.

[0026] Figure 5 This invention provides a power consumption comparison between some examples of the hybrid dynamic comparator and the traditional StrongARM comparator under different duty cycles and clock frequencies. Detailed Implementation

[0027] A hybrid dynamic comparator that balances low supply voltage and low latency includes a pre-amplifier section and a latch section, wherein: The preamplifier section mainly consists of the first tail transistor M1, input transistors M3 and M4, and a transmission gate; The latching section mainly consists of the second tail transistor M2, transistors M5 and M6, and cross-coupled transistors M7 and M8; The pre-amplification section and the latching section are connected through differential nodes VOP and VON, and the conduction state of the first tail transistor M1 and the second tail transistor M2 is controlled by a clock signal. When the clock signal CLK is low, M1 is turned on and M2 is turned off. The comparator operates in amplification mode. After the input signal is amplified by M3 and M4, a differential voltage is directly established at the differential nodes VOP and VON and stored in the parasitic capacitance. When the clock signal CLK is high, M1 is off and M2 is on, the comparator enters latch regeneration mode, and latches the output directly based on the differential voltage established on VOP and VON.

[0028] In some instances, the pre-amplification section and the latch section share differential nodes VOP and VON, and the amplification result directly drives the latch regeneration without going through an intermediate stage.

[0029] In some instances, the source of the first tail transistor M1 is grounded to GND, the drain is connected to the source of M3 and M4, and the gate is connected to the inverted clock ICLK.

[0030] In some instances, M3 and M4 receive differential input signals VIP (positive input) and VIN (negative input), respectively. The drain of M3 is connected to node VON, and the drain of M4 is connected to node VOP. The voltage difference between VIP and VIN is converted into a drain current difference, which forms a pre-amplified differential voltage at VOP and VON.

[0031] In some instances, the source of the second tail transistor M2 is grounded to GND, the drain is connected to the source of M5 and M6, and the gate is connected to the clock CLK.

[0032] In some instances, the gate of M5 is connected to VOP, and the drain of M5 is connected to VON; The gate of M6 is connected to VON, and the drain of M6 is connected to VOP; The gates of M5 and M6 are respectively connected to the two ends of the transmission gate; M5 / M6 inputs the differential voltage stored on VOP / VON to the cross-coupled PMOS transistors M7 / M8.

[0033] In some instances, a transmission gate circuit controlled by an inverting clock ICLK is provided between the gates of M5 and M6, with its control terminal connected to ICLK. During the pre-amplification stage, ICLK is high, the transmission gate is turned on, and the differential nodes VOP and VON, while maintaining the gain, reset the logic level output to a level close to the common-mode voltage, eliminating the residual charge from the previous comparison. During the latching stage, ICLK is low, the transmission gate is turned off, and the differential voltage established by the pre-amplification is fully preserved, providing a stable input for latch regeneration.

[0034] In some instances, the cross-coupled transistors M7 and M8 form a positive feedback latch structure, with their sources connected to the power supply VDD; the gate of M7 is connected to VOP and the drain is connected to VON; the gate of M8 is connected to VON and the drain is connected to VOP.

[0035] In some instances, the clock signal is generated by a two-phase clock, so that the preamplifier section and the latch section do not conduct simultaneously, resulting in no overlapping power consumption.

[0036] In some instances, power consumption is controlled by adjusting the clock duty cycle.

[0037] These features can be combined arbitrarily as long as they do not conflict with each other.

[0038] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0039] Figure 1 The transistor-level circuitry of the proposed dynamic comparator is shown. This comparator is a differential input structure, comprising a pre-amplifier section and a latch section, wherein: The pre-amplification section mainly consists of a first tail transistor M1, input transistors M3 and M4, and a transmission gate controlled by an inverting clock ICLK. The source of the first tail transistor M1 is grounded to GND, the drain is connected to the source of M3 and M4, and the gate is connected to the inverting clock ICLK. M3 and M4 receive differential input signals VIP (positive input) and VIN (negative input) respectively. The drain of M3 is connected to node VON, and the drain of M4 is connected to node VOP. The voltage difference between VIP and VIN is converted into a drain current difference, and the drain current difference forms a pre-amplified differential voltage at VOP and VON. The latching section mainly consists of a second tail transistor M2, transistors M5 and M6, and cross-coupled transistors M7 and M8. The source of the second tail transistor M2 is grounded to GND, the drain is connected to the source of M5 and M6, and the gate is connected to the clock CLK. The gate of M5 is connected to VOP, and the drain of M5 is connected to VON. The gate of M6 is connected to VON, and the drain of M6 is connected to VOP; The gates of M5 and M6 are respectively connected to the two ends of the transmission gate; The cross-coupled transistors M7 and M8 form a positive feedback latch structure, with their sources connected to the power supply VDD; the gate of M7 is connected to VOP and the drain is connected to VON; the gate of M8 is connected to VON and the drain is connected to VOP. M5 / M6 inputs the differential voltage stored on VOP / VON to the cross-coupled PMOS transistors M7 / M8. During the pre-amplification stage, ICLK is high, the transmission gate is turned on, and the differential nodes VOP and VON maintain their gain while resetting the logic level output to a level close to the common-mode voltage, eliminating the residual charge from the previous comparison. During the latching stage, ICLK is low, the transmission gate is turned off, and the differential voltage established by the pre-amplification is fully preserved, providing a stable input for latching regeneration. The conduction state of the first tail transistor M1 and the second tail transistor M2 is controlled by a two-phase clock signal; When the clock signal CLK is low, M1 is turned on and M2 is turned off. The comparator works in amplification mode. After the input signal is amplified by M3 and M4, a differential voltage is directly established at the differential nodes VOP and VON and stored in the parasitic capacitance. The amplification result is directly driven by the latch and regeneration without going through the intermediate stage. When the clock signal CLK is high, M1 is off and M2 is on, the comparator enters latch regeneration mode, and latches the output directly based on the differential voltage established on VOP and VON.

[0040] Figure 2This demonstrates the operation of the hybrid dynamic comparator described in this invention in amplification and latching modes. When the clock signal CLK is low, the first tail transistor M1 is turned on, the second tail transistor M2 is turned off, the transmission gate is turned on, and the comparator operates in amplification mode. At this time, input transistors M3 and M4 amplify the input differential signal and form corresponding differential voltages at differential nodes VOP and VON. Simultaneously, the transmission gate resets the output node level to a position close to the common-mode voltage. When the clock signal CLK transitions from low to high, the first tail transistor M1 is turned off, the second tail transistor M2 is turned on, and the comparator switches to latching mode. The differential voltage formed at nodes VOP and VON during the pre-amplification stage is stored in the relevant parasitic capacitance and serves as the initial differential signal for the latching section. This drives the latching circuit, composed of transistors M5 and M6 and cross-coupled transistors M7 and M8, to quickly enter the regeneration process, thereby outputting a full-swing logic signal. Since the pre-amplification result can be directly used for subsequent latch regeneration, this invention does not require the output node pre-discharge process in a traditional StrongARM comparator, thus effectively reducing the clock-to-output time.

[0041] Figure 3 The diagram shows a comparison of the operating waveforms of the hybrid dynamic comparator proposed in this invention and a traditional StrongARM comparator. Both comparators use a 1V supply voltage and a common-mode voltage of 0.6V, with a differential input of 3mV at a frequency of 3.2GHz. As shown in the figure, the comparator of this invention pre-amplifies the input differential signal when the clock signal is in the first phase, and directly establishes the resulting differential voltage on the latch-related node. When the clock switches to the second phase, the latch circuit can directly enter the regeneration process based on the differential voltage and output the decision result. In contrast, after the clock flips, the output node of the traditional StrongARM comparator usually needs to be discharged from the pre-charge level to the latch operating point before entering the regeneration amplification stage, thus introducing additional discharge time. Therefore, this invention effectively shortens the clock-to-output delay of the comparator by eliminating the pre-discharge process of the output node in the traditional structure.

[0042] Figure 4Simulation results of the proposed hybrid dynamic comparator and the traditional StrongARM comparator under different differential input voltages and different input common-mode voltages are shown. Under different differential input voltages, the delay of the comparator proposed in this invention is consistently less than that of the traditional StrongARM comparator. This indicates that the present invention can effectively shorten the clock-to-output delay by directly driving latch regeneration through pre-amplification and reducing the additional discharge process. Meanwhile, under fixed differential input conditions, the delay of the traditional StrongARM comparator fluctuates significantly with changes in the input common-mode voltage, especially at lower common-mode voltages. In contrast, the comparator proposed in this invention maintains relatively stable and low delay performance over a wider input common-mode voltage range, indicating that the present invention has better high-speed operation capability under low power supply voltage and wide input common-mode range conditions.

[0043] This invention underwent four simulations, varying the clock frequency, clock duty cycle, and comparator type to test the power consumption of the comparator's differential input from 1mV to 100mV. The results were as follows: this invention's scheme at a 3.2GHz clock frequency and 25% duty cycle; this invention's scheme at a 3.2GHz clock frequency and 50% duty cycle; the StrongARM comparator at a 3.2GHz clock frequency and 50% duty cycle; and this invention's scheme at a 6GHz clock frequency and 50% duty cycle. Figure 5 The power consumption comparison between the proposed solution and a traditional StrongARM comparator is presented. Since the proposed solution has quiescent current during the amplification stage, its power consumption can be controlled by reducing the clock duty cycle. Simulation results show that at 3.2 GHz, reducing the clock duty cycle can reduce the power consumption of the proposed solution, while the StrongARM comparator cannot function properly at 6 GHz.

[0044] Simulation results show that, under 28nm CMOS process and 1V power supply voltage conditions, the present invention can achieve a clock-to-output delay of 35ps at a sampling frequency of 6GHz and a differential input of 1mV; and can maintain a low delay over a wide input common-mode voltage range, thereby achieving comprehensive optimization of high speed, low voltage, low delay and low power consumption.

[0045] In another aspect, the present invention provides an integrated circuit having the hybrid dynamic comparator described in the first aspect of the present invention.

[0046] The above is a further detailed description of the present invention and should not be considered as a limitation on the specific implementation of the present invention. For those skilled in the art, simple deductions or substitutions without departing from the concept of the present invention are all within the protection scope of the present invention.

Claims

1. A hybrid dynamic comparator that balances low supply voltage and low delay, characterized in that, It includes a pre-amplification section and a latching section, wherein: The pre-amplifier section mainly consists of the first tail transistor M1, input transistors M3 and M4, and a transmission gate; The latching section mainly consists of the second tail transistor M2, transistors M5 and M6, and cross-coupled transistors M7 and M8; The pre-amplification section and the latching section are connected through differential nodes VOP and VON, and the conduction state of the first tail transistor M1 and the second tail transistor M2 is controlled by a clock signal. When the clock signal CLK is low, M1 is turned on and M2 is turned off. The comparator operates in amplification mode. After the input signal is amplified by M3 and M4, a differential voltage is directly established at the differential nodes VOP and VON and stored in the parasitic capacitance. When the clock signal CLK is high, M1 is off and M2 is on, the comparator enters latch regeneration mode, and latches the output directly based on the differential voltage established on VOP and VON.

2. The hybrid dynamic comparator according to claim 1, characterized in that, The pre-amplification section and the latching section share differential nodes VOP and VON, and the amplification result directly drives the latching regeneration without going through an intermediate stage.

3. The hybrid dynamic comparator according to claim 1, characterized in that, The source of the first tail transistor M1 is grounded to GND, the drain is connected to the source of M3 and M4, and the gate is connected to the inverted clock ICLK.

4. The hybrid dynamic comparator according to claim 3, characterized in that, M3 and M4 receive differential input signals VIP (positive input) and VIN (negative input) respectively. The drain of M3 is connected to node VON, and the drain of M4 is connected to node VOP. The voltage difference between VIP and VIN is converted into a drain current difference, and the drain current difference forms a pre-amplified differential voltage at VOP and VON.

5. The hybrid dynamic comparator according to claim 1, characterized in that, The source of the second tail transistor M2 is grounded to GND, the drain is connected to the source of M5 and M6, and the gate is connected to the clock CLK.

6. The hybrid dynamic comparator according to claim 5, characterized in that, The gate of M5 is connected to VOP, and the drain of M5 is connected to VON; The gate of M6 is connected to VON, and the drain of M6 is connected to VOP; The gates of M5 and M6 are respectively connected to the two ends of the transmission gate; M5 / M6 inputs the differential voltage stored on VOP / VON to the cross-coupled PMOS transistors M7 / M8.

7. The hybrid dynamic comparator according to claim 6, characterized in that, A transmission gate circuit controlled by the inverting clock ICLK is provided between the gates of M5 and M6, and its control terminal is connected to ICLK. During the pre-amplification stage, ICLK is high, the transmission gate is turned on, and the differential nodes VOP and VON maintain the gain while resetting the logic level output to a level close to the common-mode voltage, eliminating the residual charge of the previous comparison. During the latching stage, ICLK is low, the transmission gate is turned off, and the differential voltage established by the pre-amplification is fully preserved, providing a stable input for latching regeneration.

8. The hybrid dynamic comparator according to claim 1, characterized in that, The cross-coupled transistors M7 and M8 form a positive feedback latch structure, with their sources connected to the power supply VDD; the gate of M7 is connected to VOP and the drain is connected to VON; the gate of M8 is connected to VON and the drain is connected to VOP.

9. The hybrid dynamic comparator according to claim 1, characterized in that, The clock signal is generated by a two-phase clock, so that the preamplifier section and the latch section are not turned on at the same time, and there is no overlapping power consumption.

10. An integrated circuit, characterized in that, It has a hybrid dynamic comparator as described in any one of claims 1 to 9.

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