Negative voltage turn-off circuit for power switching device and negative voltage turn-off control method

Abstract

This application provides a negative voltage turn-off circuit and control method for power switching devices. The circuit describes a four-transistor diagonally interlocked full-bridge drive architecture. It requires only a unipolar power supply and a reference ground to natively synthesize a negative bias voltage between the gate and emitter of the power switching device during turn-off, completely eliminating reliance on bipolar power supplies and external DC-DC converters. It also eliminates the need for charge pump structures with large capacitor areas, significantly reducing chip area, manufacturing costs, and the withstand voltage design requirements of on-chip low-voltage circuits. The method describes achieving negative voltage turn-off through full-bridge architecture topology reconstruction, combined with segmented gate impedance switching control. This ensures highly reliable negative voltage turn-off, effectively suppresses false turn-on due to voltage change rate, and achieves an optimized balance between turn-off losses and voltage overshoot. The entire control process does not rely on additional negative voltage generation devices or complex peripheral circuits; negative voltage establishment and impedance switching response are rapid and the logic is stable.

Description

Technical Field

[0001] This application relates to the field of power switching device technology, and in particular to a negative voltage turn-off circuit and negative voltage turn-off control method for power switching devices. Background Technology

[0002] Monolithically integrated intelligent power drive chips belong to the category of high- and low-voltage compatible power integrated circuits. Internally, they highly integrate power switching devices (such as insulated-gate bipolar transistors), high-voltage drive circuits, and low-voltage logic circuits for fault detection, signal generation, and intelligent control onto a single silicon chip. High-end fields such as intelligent variable-frequency home appliances, new energy vehicles, and intelligent robots place increasingly stringent demands on the miniaturization and high reliability of motor drive systems. In these applications, monolithically integrated intelligent power drive chips have become core components due to their advantages such as high integration, low system cost, and minimal wiring interference.

[0003] High-frequency switching of power semiconductor devices under inductive load conditions generates extremely high rates of change of current (dI / dt) and voltage (dV / dt). These drastic switching transients cause severe electrical stress hazards, namely, current overshoot (IRR) during turn-on and voltage overshoot (Vov) during turn-off. In the design of monolithically integrated intelligent power drive chips, reducing power consumption (switching losses) and reducing electrical stress (voltage / current overshoot) are inherently contradictory in terms of physical mechanism. To reduce switching losses, the switching speed must be increased; however, excessively fast switching speeds inevitably lead to excessively high rates of change of current (dI / dt) and voltage (dV / dt), resulting in extremely high overshoot voltages on the circuit's parasitic inductance. To fundamentally suppress Miller false turn-on, negative bias turn-off technology is commonly used in engineering, which applies a negative bias voltage to the gate during turn-off, forcibly suppressing the gate potential below the threshold voltage.

[0004] To suppress false turn-on caused by voltage change rate noise and ensure reliable turn-off of power devices, traditional engineering solutions mainly include active suppression technology, active Miller clamping technology, and negative voltage turn-off technology.

[0005] Traditional negative voltage shutdown technology requires a bipolar power supply network or relies on an off-chip DC-DC converter to provide negative voltage. If the negative voltage generation circuit is integrated on-chip, it mostly adopts a charge pump structure with a large area of ​​capacitors. This not only significantly increases the chip area and manufacturing cost, but also increases the voltage withstand design requirements of the on-chip low-voltage circuit, resulting in a significant increase in the difficulty of monolithic integration and a decrease in system reliability. Summary of the Invention

[0006] The technical problem to be solved by this application is that traditional negative voltage shutdown technology requires a bipolar power supply network or relies on an off-chip DC-DC converter to provide negative voltage. If the negative voltage generation circuit is integrated on-chip, most of them adopt a charge pump structure containing a large area capacitor. This not only significantly increases the chip area and manufacturing cost, but also increases the withstand voltage design requirements of the on-chip low voltage circuit, resulting in a significant increase in the difficulty of monolithic integration and a decrease in system reliability.

[0007] To address the aforementioned issues, this application provides a negative voltage turn-off circuit and a negative voltage turn-off control method for power switching devices.

[0008] In a first aspect, the present invention discloses a negative voltage turn-off circuit for a power switching device, which includes a drive module and a control module, wherein the control module is connected to the drive module and the drive module is used to drive the power switching device. The driving module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a power supply, a reference ground, a first connection terminal, a second connection terminal, and a third connection terminal. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are arranged in a diagonally interlocked configuration to form a four-transistor full-bridge driving architecture. The power supply is connected to the first PMOS transistor and the first NMOS transistor, and the reference ground is connected to the second PMOS transistor and the second NMOS transistor. The first connection terminal is connected to the collector of the power switching device, the second connection terminal is connected to the gate of the power switching device, and the third connection terminal is connected to the second NMOS transistor. The control module includes a bandgap reference source unit and a drive control unit, which are connected together.

[0009] Preferably, the bandgap reference source unit outputs multiple reference threshold power supplies, which serve as reference thresholds for power supply comparison of each drive control unit.

[0010] Preferably, the drive control unit includes a probe subunit and a comparator subunit, the probe subunit is connected to the comparator subunit, and the probe subunit is connected to the first connection terminal.

[0011] Preferably, the drive control unit includes a first edge pulse generator subunit, a second edge pulse generator subunit, and an RS latch subunit. The first edge pulse generator subunit is connected to the reset terminal of the RS latch subunit, and the second edge pulse generator subunit is connected to the set terminal of the RS latch subunit.

[0012] Preferably, the first edge pulse generator subunit includes a first signal input terminal, a first inverter group and a first NOR gate. The first signal input terminal is connected to the input terminal of the first inverter group. The output terminal of the first inverter group and the first signal input terminal are respectively connected to the two input terminals of the first NOR gate. The output terminal of the first NOR gate is connected to the RS latch subunit.

[0013] Preferably, the second edge pulse generator subunit includes a second inverter group and a second NOR gate. The input terminal of the second inverter group is connected to the first connection terminal, the output terminal of the second inverter group and the second signal input terminal are respectively connected to the two input terminals of the second NOR gate, and the output terminal of the second NOR gate is connected to the RS latch subunit.

[0014] Preferably, the drive control unit includes a signal processing subunit, which is connected to the RS latch subunit.

[0015] Preferably, the drive control unit includes a resistor array subunit, which is connected to the signal processing subunit; The resistor array sub-unit includes a signal terminal, a third NMOS transistor, a first resistor, and a second resistor. The signal terminal is connected to the gate of the third NMOS transistor, the source of the third NMOS transistor is connected in series with the second resistor, the first resistor is connected in parallel with the second resistor, and the resistance value of the first resistor is greater than the resistance value of the second resistor.

[0016] Secondly, the present invention discloses a negative voltage turn-off control method for power switching devices, applicable to the aforementioned negative voltage turn-off circuit for power switching devices, comprising, Upon receiving a shutdown command, the first NMOS transistor and the second PMOS transistor are blocked, and the first PMOS transistor and the second NMOS transistor are turned on. The emitter of the power switching device is clamped to the positive power supply, and the gate is pulled down to the reference ground. The RS latch subunit of the drive control unit maintains the initial reset state and outputs a high level value to the resistor array subunit of the drive control unit. The third NMOS transistor of the drive control unit is turned on, and the gate of the power switching device enters a low impedance state and begins to exit the saturation region. When the collector voltage of the power switching device rises rapidly, the detection subunit of the drive control unit acquires the collector voltage change rate signal in real time. Before the collector voltage rises rapidly to the DC bus high voltage value, the collector voltage change rate is higher than the reference threshold. The comparator subunit of the drive control unit outputs a high level, and the gate of the power switching device remains in a low impedance state. When the collector voltage of the power switching device rises to the high voltage value of the DC bus, the collector voltage change rate signal decays rapidly, the collector voltage change rate gradually approaches 0, the collector voltage change rate is less than or equal to the reference threshold, the comparator subunit of the drive control unit outputs a falling edge, the power switching device completes de-protection, the third NMOS transistor of the drive control unit is turned off, and the gate of the power switching device switches from low impedance to high impedance in a step transition. The gate of the power switching device remains in a high impedance state, driving the RS latch subunit of the control unit to enter a logic self-locking state, waiting for the turn-on command of the next cycle to turn on the power switching device.

[0017] Preferably, the following steps are then included: Upon receiving the power-on command, the first NMOS transistor and the second PMOS transistor are turned on, the first PMOS transistor and the second NMOS transistor are blocked, and the power switching device is turned on.

[0018] The technical solution provided in this application has the following advantages compared with the prior art: The negative voltage turn-off circuit and negative voltage turn-off control method for power switching devices provided in this application, specifically the negative voltage turn-off circuit for power switching devices, mention that the drive module adopts a four-transistor diagonally interlocked full-bridge drive architecture. It only requires a unipolar power supply and a reference ground to natively synthesize a negative bias voltage between the gate and emitter of the power switching device during turn-off, thus completely eliminating the reliance on bipolar power supplies and external DC power supplies from a circuit structure perspective. This eliminates the reliance on DC converters and eliminates the need for charge pump structures with large-area capacitors, significantly reducing chip area, manufacturing costs, and the withstand voltage design requirements of on-chip low-voltage circuits. This greatly reduces the difficulty of monolithic integration and improves the overall reliability of the system.

[0019] The negative voltage turn-off control method for power switching devices mentions that negative voltage turn-off is achieved through full-bridge architecture topology reconstruction and combined with gate impedance segmented switching control. While ensuring high-reliability negative voltage turn-off and effectively suppressing false turn-on due to voltage change rate, it achieves an optimized balance between turn-off loss and voltage overshoot. The entire control process does not rely on additional negative voltage generation devices and complex peripheral circuits. The negative voltage establishment and impedance switching response are rapid and the logic is stable, further reducing integration complexity. While simplifying system implementation, it significantly improves the safety and operational reliability of the power switching device turn-off process. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A block diagram of a negative voltage turn-off circuit for a power switching device provided in this application; Figure 2 A circuit diagram of a drive module for a negative voltage turn-off circuit of a power switching device provided in this application; Figure 3A circuit diagram of a control module for a negative voltage turn-off circuit of a power switching device provided in this application; Figure 4 A circuit diagram of a bandgap reference source unit for a negative voltage turn-off circuit of a power switching device provided in this application; Figure 5 A circuit diagram of a drive control unit for a negative voltage turn-off circuit of a power switching device provided in this application; Figure 6 A circuit diagram of a first edge pulse generator subunit for a negative voltage turn-off circuit of a power switching device provided in this application; Figure 7 A circuit diagram of a second edge pulse generator subunit for a negative voltage turn-off circuit of a power switching device provided in this application; Figure 8 A flowchart illustrating the steps of a negative voltage turn-off control method for power switching devices provided in this application.

[0023] Explanation of reference numerals in the attached figures: 100. Negative voltage shutdown circuit for power switching devices; 1. Driver module; 11. First PMOS transistor; 12. Second PMOS transistor; 13. First NMOS transistor; 14. Second NMOS transistor; 15. Power supply; 16. Ground; 2. Control module; 21. Bandgap reference source element; 22. Drive control unit; 221. Detection subunit; 222. Comparator subunit; 223. First edge pulse generator subunit; 224. Second edge pulse generator subunit; 225. RS latch subunit; 226. Signal processing subunit; 2261. Schmitt trigger; 2262. Inverter; 227, Resistor array sub-unit; 2271, Third NMOS transistor; 2272, First resistor; 2273, Second resistor; 3. Power switching devices. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] Firstly, see Figures 1-7 This invention discloses a negative voltage turn-off circuit 100 for a power switching device 3, which is applicable to scenarios such as monolithic integrated intelligent power drive chips, motor drives, inverter systems and high-frequency power switch control systems. It can achieve high-reliability negative voltage turn-off under single power supply conditions, effectively suppress Miller false turn-on caused by voltage change rate and reduce turn-off overshoot. The negative voltage turn-off circuit includes a drive module 1 and a control module 2. The control module 2 is connected to the drive module 1, and the drive module 1 is used to drive the power switching device 3.

[0026] Specifically, the drive module 1 is used to construct a single-supply negative voltage drive path to realize the forward conduction drive and negative bias turn-off drive of the power switching device 3, and to dynamically switch the gate drive impedance according to the control signal. The control module 2 is used to detect the switching state of the power switching device 3 in real time, identify the desaturation critical point, and generate a timing-accurate control signal to realize adaptive segmented impedance adjustment during the turn-off process. Ultimately, while ensuring high immunity, it optimizes turn-off loss and voltage overshoot. In this embodiment, the power switching device 3 is an insulated gate bipolar transistor (IGBT).

[0027] The driving module 1 includes a first PMOS transistor 11, a second PMOS transistor 12, a first NMOS transistor 13, a second NMOS transistor 14, a power supply 15, and a reference ground 16. The first PMOS transistor 11, the second PMOS transistor 12, the first NMOS transistor 13, and the second NMOS transistor 14 are arranged in a diagonal cross-interlocked configuration to form a four-transistor full-bridge driving architecture. The power supply 15 is connected to the first PMOS transistor 11 and the first NMOS transistor 13, and the reference ground 16 is connected to the second PMOS transistor 12 and the second NMOS transistor 14.

[0028] Specifically, the drive module 1 adopts a full-bridge drive architecture with four tubes diagonally interlocked. It only requires a unipolar power supply 15 and a reference ground 16 to synthesize a negative bias voltage between the gate and emitter of the power switching device 3 when it is turned off. This completely eliminates the dependence on bipolar power supplies and off-chip DC-DC converters from the circuit structure perspective. At the same time, it eliminates the need for a charge pump structure with a large area of ​​capacitors, significantly reducing the chip area, reducing manufacturing costs, and lowering the withstand voltage design requirements of the on-chip low-voltage circuit. This greatly reduces the difficulty of single-chip integration and improves the overall reliability of the system.

[0029] It is understandable that the drive module 1 completely abandons the inherent unipolar voltage output limitation of the traditional half-bridge totem pole drive structure in terms of circuit topology. It adopts a four-transistor full-bridge drive architecture consisting of a first PMOS transistor 11, a second PMOS transistor 12, a first NMOS transistor 13, and a second NMOS transistor 14 arranged diagonally and interlocked. This network only needs to be connected to a single positive DC power supply 15 (VCC) and a system reference ground 16 (GND) at the energy input end. During the transient and steady-state conduction cycles when the power switching device 3 performs the turn-on action, the first NMOS transistor 13 and the second PMOS transistor 12 on the diagonal of the system's front-end logic control enter the conduction state, thereby establishing a positive drive charge injection path between the gate and emitter of the power switching device 3, which runs from the positive DC power supply 15 to the system reference ground 16, forming a steady-state turn-on bias electric field with an amplitude of +VCC. During the commutation cycle when the system performs the turn-off action, the differential output stage network completes topology reconstruction, forcibly blocks the original conduction link, and switches on the first PMOS transistor 11 and the second NMOS transistor 14. This topology reversal action forcibly reverses the direction of the drive current in the physical circuit, directly clamping the high potential of VCC into the emitter of the power switching device 3, and simultaneously pulling down the front stage of the gate drive circuit to the system reference ground 16. If the emitter dynamic potential is taken as the zero potential reference, the network natively synthesizes and establishes a reverse bias extraction electric field with an amplitude close to -VCC at both ends of the gate and emitter, thus structurally eliminating the dependence on on-chip charge pump and off-chip dual power supply.

[0030] The driving module 1 includes a first connection terminal P1, a second connection terminal P2, and a third connection terminal P3. The first connection terminal P1 is connected to the collector of the power switching device 3, the second connection terminal P2 is connected to the gate of the power switching device 3, and the third connection terminal P3 is connected to the second NMOS transistor 14.

[0031] Specifically, the driving module 1 is provided with three external connection ports: a first connection port P1, a second connection port P2, and a third connection port P3. The first connection port P1 is connected to the collector of the power switching device 3 to acquire the collector voltage signal and provide a status input for subsequent voltage change rate detection. The second connection port P2 is connected to the gate of the power switching device 3 to output the turn-on driving voltage, the negative voltage turn-off voltage, and the adaptively adjusted gate driving impedance to the gate. The third connection port P3 is connected to the second NMOS transistor 14 inside the driving module 1 to cooperate with the full-bridge architecture to complete the current path switching in the turn-off state and realize the stable establishment of negative bias.

[0032] It is understandable that in a traditional half-bridge drive structure, the physical limit of the lower IGBT when fully turned on is only enough to flatten the output node to ground potential. To overcome this limitation and combat the extremely severe Miller parasitic conduction effect under high voltage change rates, this application introduces a differential full-bridge push-pull reconfiguration technology. The drive module 1 adopts a full-bridge architecture, where the gate and emitter of the IGBT are not grounded at one end, but are respectively floated and connected to the two diagonal midpoints of the full-bridge topology. The transient process is as follows: When the system is in steady-state forward conduction, the internal logic drivers work together to turn on the diagonal transistor combination of the first NMOS transistor 13 and the second PMOS transistor 12, while simultaneously blocking the first PMOS transistor 11 and the second NMOS transistor 14. At this time, current flows out from the power supply VCC, passes through the channel of the first NMOS transistor 13, the externally connected turn-on current-limiting resistor, and is injected into the gate metal layer of the power switching device 3. After filling the gate oxide dielectric capacitance, it flows out through the emitter of the power switching device 3 and finally flows back to GND through the channel of the second PMOS transistor 12. Under this steady state, a stable +VCC electric field (such as +5V) is established between the gate and emitter, maintaining the strong inversion conduction layer of the power switching device 3.

[0033] The moment the controller issues the shutdown command, the system undergoes a reconfiguration after an extremely short nanosecond-level dead-time. The control logic rapidly closes the first PMOS transistor 11 and the second NMOS transistor 14, and disconnects the previously connected first NMOS transistor 13 and second PMOS transistor 12. At this time, the current drawn from VCC is injected through the first PMOS transistor 11. Due to the reversed path, the current is forced to flow into the emitter of the power switching device 3, travels in reverse through the internal structure of the device to the gate, and finally flows through the second NMOS transistor 14 to discharge to the reference ground 16GND. During this stage, with the emitter as the reference point, the relative potential of the gate is physically clamped to a strict -VCC (e.g., -5V). This natively synthesized deep negative bias barrier gives the power device extremely high disturbance rejection margin. Even if an extreme voltage change of up to 5000V / μs occurs at the collector during the turn-off process, the spike disturbance of a few volts or even tens of volts coupled through the Miller capacitance is insignificant in the face of the abyss of -5V. It can never touch the parasitic turn-on threshold of the power switching device of about 5V-6V, thus eliminating the possibility of catastrophic short circuit caused by bridge arm shoot-through from the physical level.

[0034] The control module 2 includes a bandgap reference source unit 21 and a drive control unit 22. The bandgap reference source unit 21 is connected to the drive control unit 22. Multiple drive control units 22 can be set in the control module 2. The bandgap reference source unit 21 outputs multiple reference threshold power supplies, which serve as reference thresholds for power supply comparison of each drive control unit 22.

[0035] Specifically, the control module 2 integrates a bandgap reference source unit 21 and a drive control unit 22. The signal output terminal of the bandgap reference source unit 21 is electrically connected to the reference input terminal of the drive control unit 22. The bandgap reference source unit 21 can generate multiple stable reference voltages that are not affected by process, voltage, or temperature drift, and output multiple reference threshold voltages with different amplitudes, which are supplied to each drive control unit 22. This provides accurate and fixed discrimination reference thresholds for the voltage comparison circuits inside each drive control unit 22, ensuring the consistency and stability of the voltage change rate detection time. Relying on the graded reference thresholds provided by the bandgap reference source unit 21, the drive control unit 22 completes real-time sampling of the voltage change rate, threshold comparison, edge pulse generation, and logic latch output during the turn-off process of the power switching device 3, realizing multi-level adaptive switching control of the gate impedance. Among them, the bandgap reference source unit 21 outputs four different reference voltages, namely Vref1, Vref2, Vref3, and Vref4, which provide different reference detection thresholds for voltage change rates for the comparators of each drive control unit 22, realizing multi-stage gate turn-off control instead of directly driving the power switching device 3. The voltage values ​​of the four reference thresholds Vref do not change with temperature or power supply voltage, ensuring that the dV / dt detection point remains stable under all operating conditions, and the control logic will not drift. They are all low-noise DC voltages, unaffected by high-frequency noise, avoiding false triggering.

[0036] The drive control unit 22 includes a detection subunit 221, a comparator subunit 222, a first edge pulse generator subunit 223, a second edge pulse generator subunit 224, a signal processing subunit 226, and an RS latch subunit 225. The detection subunit 221 is connected to the comparator subunit 222 and is connected to the first connection terminal P1. The first edge pulse generator subunit is connected to the reset terminal of the RS latch subunit 225, the second edge pulse generator subunit is connected to the set terminal of the RS latch subunit 225, and the signal processing subunit 226 is connected to the RS latch subunit 225. Specifically, the signal input terminal of the detection subunit 221 is electrically connected to the first connection terminal P1 of the drive module 1, the signal output terminal of the detection subunit 221 is connected to the input terminal of the comparator subunit 222, the first edge pulse generator subunit 223 and the second edge pulse generator subunit 224 are respectively connected to the reset terminal and the set terminal of the RS latch subunit 225, and the input terminal of the signal processing subunit 226 is electrically coupled to the output terminal of the RS latch subunit 225, thereby realizing step-by-step signal transmission and logic linkage control.

[0037] The detection subunit 221 acquires the collector voltage signal of the power switching device 3 under control in real time through the first connection terminal P1, completes high-voltage isolation, differential sampling and waveform conversion, and converts the physical characteristics of the voltage change rate into a standard analog electrical signal, providing the original sampling input for the subsequent threshold comparison. The comparator subunit 222 receives the reference threshold voltage provided by the bandgap reference source and performs real-time threshold comparison on the voltage change rate signal output by the detection subunit 221. According to the signal amplitude, it outputs the corresponding level and characteristic transition edge to achieve accurate identification of the desaturation state of the power device. The first edge pulse generator subunit 223 is used to capture the falling edge of the signal formed by the decay of the voltage change rate during the turn-off process, generate a nanosecond-level narrow pulse and send it to the RS latch subunit 22. 5. Reset terminal: completes the working logic reset trigger. The second edge pulse generator subunit 224 is used to identify the level transition edge of the system turn-on command, generate a set narrow pulse and send it to the set terminal of RS latch subunit 225 to realize the precise start of the turn-off control logic. RS latch subunit 225 receives the trigger signals of two edge pulse generators to realize reliable state setting, self-locking and holding, avoid logic metastability and illegal working state, and output a stable logic control level. Signal processing subunit 226 performs waveform shaping, noise filtering and drive capability enhancement on the control signal output by RS latch subunit 225, and outputs a clean, steep edge and sufficient drive capability control signal. The back-end drive gate resistor array completes the adaptive switching between low impedance and high impedance.

[0038] The detection subunit 221 includes a high-voltage isolation diode D1, a differential capacitor C1, and a sampling resistor R1. The detection subunit 221 is used to accurately extract the collector voltage change rate characteristic signal during the turn-off process of the power switching device 3 without bearing the risk of high-voltage breakdown.

[0039] In this circuit, the input terminal of the high-voltage isolation diode D1 is connected to the collector of the power switching device 3 through the first connection terminal P1. A differentiating capacitor C1 is connected in series with the back end of the high-voltage isolation diode D1, and a sampling resistor R1 is connected between the back end of the differentiating capacitor C1 and the system ground. The high-voltage isolation diode D1 provides high-voltage isolation and unidirectional conduction, blocking the hundreds of volts of high voltage from the bus during the power device's turn-off process, preventing direct high-voltage breakdown of the subsequent low-voltage logic circuit. Simultaneously, it only allows dynamic AC signals with voltage changes to be transmitted to the subsequent stage, isolating the DC high-voltage component and achieving safe isolation between high and low voltage circuits. The differentiating capacitor C1 is the core sampling differentiating element. Utilizing the characteristic that capacitor voltage cannot change abruptly, it differentiates the instantaneous change in collector voltage, converting the voltage change rate during the power device's turn-off process into a corresponding displacement current signal. This achieves the physical conversion between the voltage change rate and the current signal, providing the original dynamic characteristic signal for subsequent circuits to identify the turn-off stage and determine the desaturation state. The sampling resistor R1 is responsible for converting the displacement current signal output by the differentiating capacitor C1 into an analog voltage signal, completing the current... The voltage conversion outputs a detection voltage whose amplitude is positively correlated with the rate of voltage change, and stably supplies it to comparator subunit 222. This allows the comparator to accurately determine the power device's turn-off process and desaturation critical point based on a preset reference threshold. This passive detection structure requires no static power consumption, has minimal temperature drift, and a fast response speed, making it suitable for high-frequency, high-voltage, and wide-temperature power conversion applications.

[0040] Specifically, during system operation, the high-voltage isolation diode D1 blocks the high voltage of the DC bus, ensuring the safety of the low-voltage control circuit. The differentiating capacitor C1, utilizing its high-pass filtering characteristics, responds to the rapid rise in the collector voltage of the power switching device 3 during the initial turn-off commutation phase, generating a displacement current proportional to the rate of voltage rise. This displacement current flows through the ground sampling resistor R1, completing the current-to-voltage (IV) conversion and generating an analog sampling voltage for comparison on the low-voltage side. Subsequently, the high-speed comparator performs threshold discrimination and shaping on this sampling voltage, outputting the corresponding digital logic signal (VDET). As the collector voltage continues to rise and eventually reaches the DC bus voltage level, the voltage rise slope dVCE / dt of the device rapidly decays and approaches zero. At this point, the sharp decrease in displacement current causes the potential across the ground sampling resistor R1 to drop below the comparator's reference threshold. This causes the comparator to flip, and the VDET signal generates a distinct falling edge, reflecting the end of the desaturation process of the power switching device 3. The system uses this characteristic edge as the reference for triggering state transitions in the subsequent digital closed-loop state machine, thereby completely eliminating the dependence on analog RC delay parameters in the traditional control architecture.

[0041] The first edge pulse generator subunit 223 includes a first signal input terminal, a first inverter group and a first NOR gate. The first signal input terminal is connected to the input terminal of the first inverter group. The output terminal of the first inverter group and the first signal input terminal are respectively connected to the two input terminals of the first NOR gate. The output terminal of the first NOR gate is connected to the RS latch subunit.

[0042] Specifically, the first edge pulse generator subunit 223 is used to accurately capture the state transition signal during the power device turn-off process and generate a stable set trigger narrow pulse. The first signal input terminal is the external signal access port of the subunit and is electrically connected to the output terminal of the comparator subunit 222. It is used to receive the detection level signal characterizing the desaturation state of the power device. The first signal input terminal is also connected to the input terminal of the first inverter group. The first inverter group can perform delay, shaping and logic inversion processing on the input signal to form a delayed inverted signal. The output terminal of the first inverter group and the original signal of the first signal input terminal are respectively connected to the two input terminals of the first NOR gate. The logic operation is performed through the timing difference of the two signals. Only at the moment when the detection signal generates a characteristic falling edge, a nanosecond-level narrow pulse signal is output. This pulse signal is finally sent to the set terminal of the RS latch subunit to realize the accurate triggering of the gate impedance switching logic and effectively avoid the logic false triggering, signal jitter and metastability problems caused by continuous level. This unit is adapted to high-frequency power switching conditions and can accurately capture the desaturation critical point of power devices, providing precise timing trigger signals for segmented impedance turn-off control.

[0043] The second edge pulse generator subunit 224 includes a second inverter group and a second NOR gate. The input terminal of the second inverter group is connected to the first connection terminal P1. The output terminal of the second inverter group and the second signal input terminal are respectively connected to the two input terminals of the second NOR gate. The output terminal of the second NOR gate is connected to the RS latch subunit.

[0044] Specifically, the second edge pulse generator subunit 224 is used to capture the level transition of the system turn-on command, generate a narrow reset pulse, and complete the periodic reset of the control logic. The second signal input terminal is connected to the system turn-on control command signal, and the input terminal of the second inverter group is connected to the second signal input terminal to perform delay shaping and logic inversion processing on the turn-on command signal. The delayed output signal of the second inverter group and the original turn-on command signal of the second signal input terminal are respectively connected to the two input terminals of the second NOR gate. Logic operations are performed using the timing difference between the two signals, generating a nanosecond-level narrow reset pulse only at the instant of the turn-on command level transition. The pulse output terminal is electrically connected to the reset terminal of the RS latch subunit to clear the latch's self-locking state, restoring the circuit to its initial standby condition. This subunit can achieve precise reset of the switching cycle, ensuring that the gate impedance control logic is in an initial low-impedance standby state before each power device turn-on action, ensuring stable periodic circuit operation, and adapting to high-frequency continuous switching scenarios such as new energy inverters and motor frequency conversion drives.

[0045] The signal processing subunit 226 includes a Schmitt trigger 2261 and an inverter 2262. The Schmitt trigger 2261 is connected to an RS latch, and the inverter 2262 is connected to the Schmitt trigger 2261. Through the cascading cooperation of the Schmitt trigger 2261 and the inverter 2262, the signal processing subunit 226 achieves integrated signal processing functions such as noise filtering, waveform shaping, logic matching, and drive enhancement. It can provide stable, accurate, and sufficiently powerful control signals to the resistor array subunit 227 under strong interference and high dynamic conditions such as inverter frequency conversion, new energy power control, and high-frequency power drive, ensuring the reliable operation of the three-segment adaptive turn-off control of the power switching device.

[0046] Among them, the Schmitt trigger 2261 is the core device for signal shaping and anti-interference. It is used to receive the original logic level signal output by the RS latch subunit. Due to the high-frequency electromagnetic interference, power supply ripple and signal edge jitter in the power drive working environment, the latch output signal is prone to carrying glitches and unstable levels. The Schmitt trigger 2261, relying on its own hysteresis threshold characteristics, can effectively filter out high-frequency noise and jitter interference in the signal, and shape the original signal with smooth edges and distortion into a standard digital square wave with steep edges, stable level and no noise. This avoids noise causing the resistor array subunit 227 to switch erroneously, and ensures the accuracy and stability of the control logic. Inverter 2262 is a logic matching and drive enhancement device. On the one hand, it performs logic level inverse matching on the regular signal output by Schmitt trigger 2261, so that the final output control level logic is fully adapted to the conduction and cutoff control requirements of the third NMOS transistor 2271, ensuring that the impedance switching logic accurately corresponds to the turn-off control timing of the power device. On the other hand, it can enhance the signal driving capability, improve the charging and discharging speed of the capacitive load of the MOS transistor inside the resistor array sub-unit 227, ensure that the gate impedance switching action is fast and timely, and eliminate the signal transmission lag problem.

[0047] The drive control unit 22 includes a resistor array subunit 227, which is connected to the signal processing subunit 226. The resistor array subunit 227 receives logic control signals after shaping, noise reduction, and drive enhancement, and performs adaptive switching of the gate drive impedance of the power devices. The resistor array subunit 227 includes a signal terminal, a third NMOS transistor 2271, a first resistor 2272, and a second resistor 2273. The signal terminal is connected to the gate of the third NMOS transistor 2271, the source of the third NMOS transistor 2271 is connected in series with the second resistor 2273, and the first resistor 2272 and the second resistor 2273 are connected in parallel. The resistance value of the first resistor 2272 is greater than the resistance value of the second resistor 2273. The signal input terminal of the resistor array subunit 227 is electrically connected to the output terminal of the inverter 2262 in the signal processing subunit 226.

[0048] Specifically, the signal terminal is directly connected to the gate of the third NMOS transistor 2271 to receive logic control signals to manage the on / off state of the third NMOS transistor 2271. The source of the third NMOS transistor 2271 is connected in series with the second resistor 2273. The first resistor 2272 and the second resistor 2273 form a parallel topology, and the resistance of the first resistor 2272 is greater than that of the second resistor 2273. When the third NMOS transistor 2271 is turned on, the first resistor 2272 and the second resistor 2273 are connected in parallel to the gate drive circuit. The overall equivalent resistance is small, forming a low-impedance path, which can quickly extract the gate charge of the power device, shorten the switching overlap time, and effectively reduce the turn-off loss. When the third NMOS transistor 2271 is turned off, the branch of the second resistor 2273 is disconnected, and the circuit only retains the large-value first resistor 2272, forming a high-impedance path, slowing down the gate charge extraction speed, smoothing the collector current decay curve of the power device, and suppressing the voltage overshoot problem caused by parasitic inductance from the root.

[0049] The drive control unit 22 converts the front-end analog state signal into discrete digital control instructions. The logic architecture of the drive control unit 22 avoids the defects of analog resistor-capacitor (RC) charge-discharge timers in traditional control chips that are susceptible to process deviation (PVT) and temperature drift. It uses the time difference based on the intrinsic propagation delay of transistors to synthesize control pulses.

[0050] Drive control unit 22 set pulse synthesis path: The VDET signal output by the high-speed comparator enters the first edge pulse generator, which internally divides the signal into two paths: one is a straight path without additional components, and the other is a delayed path containing an inverter cascade structure. In the specific transistor-level layout wiring, the pull-up resistor at the input of the first inverter group is stably connected to the power supply VDD node to provide initial bias. Then, the internal inverters are directly cascaded to the first NOR gate. The signals of the pass-through path and the delay path are finally input to the unified first NOR gate. Under the steady-state condition where the input level remains constant, the logic states of the two inputs of the first NOR gate are opposite, and its output remains at a logic low level. When the VDET signal output by the comparator subunit 222 generates a falling edge transition due to the voltage slope decay, the pass-through signal instantly jumps to a logic low level. The signal in the delay path is limited by the physical delay of the charging and discharging of the parasitic capacitance inside the inverter chain and the transit time of the carriers, and remains at the original level for a short time. Within this nanosecond-level transmission delay window, the two inputs of the first NOR gate simultaneously present a logic low level, and then synthesize and output an extremely narrow positive set pulse (S_PULSE) according to its truth table.

[0051] The reset pulse synthesis path of the drive control unit 22: The system is equipped with a second edge pulse generator with a symmetrical topology on the command input side, and its input is coupled to the system's global enable command signal (VIN). When the system passes the turn-off dead zone and the main controller issues the PWM turn-on command for the next switching cycle (represented by the falling edge of the VIN signal), the pulse generator extracts the command edge characteristics and generates the corresponding positive reset pulse (R_PULSE).

[0052] The RS latch subunit's closed-loop execution and holding mechanism: The system's state control is accomplished by an RS latch composed of dual NOR gates with cross-coupled pins. This latch employs an asymmetrical transistor width-to-length ratio design to optimize the charging and discharging response speed of parasitic capacitances. Since the two pre-amplified pulse generators convert long-duration analog signals into discrete narrow pulses, illegal logic states where the latch inputs simultaneously reach high levels are effectively avoided. When the S_PULSE pulse is input to the set terminal of the RS latch, the internal positive feedback mechanism is triggered, the output control signal (EN) flips to a logic low level (0V), and the latch enters a closed-loop self-holding state. This physical deadlock mechanism effectively shields the complex conducted and radiated electromagnetic interference in the motor drive environment; the latch is only released from deadlock and cleared to its initial logic high level output when the R_PULSE pulse of the next cycle is input to the reset terminal of the RS latch.

[0053] Secondly, see Figure 8 This invention discloses a negative voltage turn-off control method for power switching devices, comprising, Step S1: Upon receiving the shutdown command, the first NMOS transistor and the second PMOS transistor are blocked, the first PMOS transistor and the second NMOS transistor are turned on, the emitter of the power switching device is clamped to the positive power supply, the gate is pulled down to the reference ground, the RS latch maintains the initial reset state, outputs a high level value to the resistor array sub-unit, the third NMOS transistor is turned on, the gate of the power switching device enters a low impedance state, and begins to exit the saturation region; Step S2: The collector voltage of the power switching device rises rapidly. The detection sub-unit acquires the collector voltage change rate signal in real time. Before the collector voltage rises rapidly to the DC bus high voltage value, the collector voltage change rate is higher than the reference threshold. The comparator sub-unit outputs a high level, and the gate of the power switching device remains in a low impedance state. Step S3: The collector voltage of the power switching device rises to the DC bus high voltage value, the collector voltage change rate signal decays rapidly, the collector voltage change rate gradually approaches 0, the collector voltage change rate is less than or equal to the reference threshold, the comparator sub-unit outputs a falling edge, the power switching device completes de-protection, the third NMOS transistor is turned off, and the gate of the power switching device switches from low impedance to high impedance in a step transition. Step S4: The gate of the power switching device remains in a high impedance state, and the RS latch sub-unit enters a logic self-locking state, waiting for the turn-on command of the next cycle to turn on the power switching device.

[0054] Specifically, in step S1, when the system receives a shutdown command (high level), the four-transistor full-bridge architecture inside the drive module performs topology reconfiguration, blocking the conduction path of the first NMOS transistor and the second PMOS transistor, while simultaneously turning on the first PMOS transistor and the second NMOS transistor. After the topology switch, the emitter of the power switching device to be controlled is clamped to the positive polarity power supply potential, and the gate is pulled down to the reference ground potential. Relying on the single-supply full-bridge structure, a gate-emitter negative voltage bias is naturally formed, constructing a reliable negative voltage shutdown environment, and suppressing the device's erroneous turn-on caused by high-frequency dV / dt interference from the root. At this time, the RS latch subunit maintains the initial reset state and outputs a stable high-level control signal. This signal is then stably input to the resistor array subunit after being shaped and denoised by a Schmitt trigger, matched by inverter logic, and enhanced by drive in the signal processing subunit. A high-level signal turns on the third NMOS transistor, causing the first and second resistors to form a parallel conduction structure. This significantly reduces the gate drive circuit impedance of the power switching device, allowing the gate charge to be discharged quickly. This enables the power switching device to quickly exit the saturation conduction region and start the turn-off process, effectively shortening the switching overlap time and reducing turn-off losses.

[0055] Specifically, in step S2, after the power switching device exits the saturation region, the collector voltage begins to rise rapidly. The detection subunit inside the drive control unit acquires the collector voltage signal in real time through the first connection terminal, completes high-voltage isolation and differential conversion, and continuously outputs a real-time collector voltage change rate signal. During the stage before the collector voltage rises to the DC bus high voltage value, the voltage change rate is relatively fast, and the amplitude of the detection signal output by the detection subunit is always greater than the reference threshold provided by the bandgap reference source. The comparator subunit continuously outputs a high-level signal. This signal is processed step-by-step by the edge pulse generator, RS latch, and signal processing subunit, continuously maintaining the third NMOS transistor in the on state, and the gate of the power switching device always maintains a low-impedance discharge state. This stage utilizes a low-impedance loop to quickly extract the remaining charge from the gate, maximizing the device turn-off speed and continuously reducing switching losses. Simultaneously, the gate is kept negatively biased throughout the process to resist electromagnetic interference during the switching process and prevent the device from being falsely turned on.

[0056] Specifically, in step S3, when the collector voltage of the power switching device continues to rise to the DC bus high voltage value, the device completely desaturates, and the collector voltage change rate signal decays rapidly and gradually approaches zero. At this time, the amplitude of the voltage change rate detection signal is less than or equal to the preset reference threshold, the output level of the comparator subunit jumps, and a characteristic falling edge is generated. The second edge pulse generator subunit accurately captures this falling edge signal, generates a nanosecond-level narrow pulse, and triggers the RS latch subunit to set and flip. After the latch output level state switch, the output signal is filtered by a Schmitt trigger to remove switching noise and normalize the waveform, and then logic adaptation and drive enhancement are completed by an inverter. Finally, a low-level control signal is output to act on the resistor array subunit. The low-level signal reliably turns off the third NMOS transistor, disconnects the parallel branch of the second resistor, and the gate drive circuit retains only the first resistor with a larger resistance value, realizing a step switching of the gate impedance from low impedance to high impedance. By increasing the gate circuit impedance in time at the desaturation critical point, the carrier extraction rate is slowed down, and the collector current is prevented from dropping rapidly. This effectively suppresses the high voltage overshoot caused by the parasitic inductance of the line, solving the technical problem that traditional turn-off schemes cannot balance loss and overshoot.

[0057] Specifically, in step S4, after the gate switches to a high-impedance state, the RS latch subunit enters a logic self-locking state, unaffected by operating condition fluctuations, power supply noise, and temperature drift. It continuously and stably outputs control signals, ensuring the power switching device maintains a high-impedance operating state at the end of the turn-off period, smoothly completing current tail decay, completely avoiding voltage oscillations and secondary overshoot problems, and ensuring a smooth and safe turn-off process. Simultaneously, the system remains on standby, monitoring the turn-on command for the next cycle in real time. Upon arrival of the turn-on command, the first edge pulse generator subunit generates a reset pulse, releasing the RS latch self-locking state, re-turning the third NMOS transistor, restoring the gate to its low-impedance initial state, and resetting the full-bridge circuit to the turn-on topology, completing the entire process of a single adaptive negative voltage turn-off and achieving periodic stable switching control.

[0058] It is understandable that by reconstructing the full-bridge architecture topology to achieve negative voltage turn-off, and combining it with segmented gate impedance switching control, a balance between turn-off loss and voltage overshoot can be optimized while ensuring highly reliable negative voltage turn-off and effectively suppressing false turn-on due to voltage change rate. The entire control process does not rely on additional negative voltage generation devices and complex peripheral circuits. The negative voltage establishment and impedance switching response are rapid and the logic is stable, further reducing integration complexity. While simplifying system implementation, it significantly improves the safety and reliability of the power switching device turn-off process.

[0059] After step S4, the following steps are included: Upon receiving the power-on command, the first NMOS transistor and the second PMOS transistor are turned on, the first PMOS transistor and the second NMOS transistor are blocked, and the power switching device is turned on.

[0060] It is understandable that when the system is in steady-state forward conduction, the internal logic drivers work together to turn on the diagonal transistor combination of the first NMOS and the second PMOS, while simultaneously blocking the first PMOS and the second NMOS. At this time, current flows out from the power supply VCC, passes through the channel of the first NMOS, the external turn-on current-limiting resistor connected in series, and is injected into the gate metal layer of the power switching device. After filling the gate oxide dielectric capacitance, it flows out through the emitter of the power switching device and finally flows back to GND through the channel of the second PMOS. Under this steady state, a stable +VCC electric field (such as +5V) is established between the gate and emitter, maintaining the strong inversion conduction layer of the power switching device.

[0061] The detailed process of the negative pressure shutdown control method is as follows: When the system receives a shutdown command and starts the drive module, the RS latch remains in its initial reset state (EN signal is logic high). This high level drives the third NMOS transistor into the linear conduction region, causing the first and second resistors to be in parallel conduction on the physical link. Since the resistance of the second resistor is extremely small, according to the principle of parallel current division, the overall equivalent impedance of the array is extremely low. This low impedance channel accelerates the extraction rate of minority carriers inside the gate of the power switching device, allowing the collector voltage VCE of the power switching device to rise at a higher slope. The rapid voltage rise significantly shortens the integral of the voltage and current overlap time during the shutdown process, thereby reducing the crossover loss in the initial stage of switching to an extremely low level. As the collector voltage of the power switching device rises to the DC bus high voltage level, the expansion of the internal drift region depletion layer is limited, and the voltage rise slope (dVCE / dt) decays rapidly. The pre-mounted probe subunit and pulse generator generate a set pulse accordingly. The RS latch responds to the set pulse and flips its state (EN signal jumps to logic low level). This signal drives the third NMOS transistor to turn off rapidly within nanoseconds. The turn-off of the third NMOS transistor physically cuts off the low-impedance branch, so that the discharge path of the power switching device gate can only rely on the first resistor branch with a larger resistance value. The system equivalent impedance experiences a step increase of more than ten times. This impedance step moment corresponds precisely to the tail stage when the collector current ICE of the power switching device is about to begin to decay sharply. The entry of the high-impedance network effectively increases the RC time constant of the discharge circuit, limiting the continued rapid loss of gate charge, thereby smoothing the decay curve of the tail current. The controlled current drop rate directly breaks down the condition for the reverse induced electromotive force generated by the parasitic inductance of the line from a physical perspective, thereby effectively reducing the peak amplitude of transient voltage overshoot.

[0062] Furthermore, the aforementioned high impedance and overshoot suppression states are stably maintained by the deadlock mechanism of the RS latch, covering the entire decay period of the collector current and the system's turn-off dead zone sleep time, until the main controller issues the turn-on command for the next switching cycle. The reset pulse triggers the RS latch to clear, the third NMOS transistor resumes conduction, and the system returns to the low impedance standby state, preparing for the transient scheduling of the next working cycle.

[0063] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0064] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0066] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0067] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0068] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0069] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0070] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A negative voltage turn-off circuit for a power switching device, characterized in that, It includes a drive module and a control module. The control module is connected to the drive module, and the drive module is used to drive the power switching device. The driving module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a power supply, a reference ground, a first connection terminal, a second connection terminal, and a third connection terminal. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are arranged in a diagonally interlocked configuration to form a four-transistor full-bridge driving architecture. The power supply is connected to the first PMOS transistor and the first NMOS transistor, and the reference ground is connected to the second PMOS transistor and the second NMOS transistor. The first connection terminal is connected to the collector of the power switching device, the second connection terminal is connected to the gate of the power switching device, and the third connection terminal is connected to the second NMOS transistor. The control module includes a bandgap reference source unit and a drive control unit, which are connected together.

2. The circuit according to claim 1, characterized in that, The bandgap reference source unit outputs multiple reference threshold power supplies, which serve as reference thresholds for power supply comparison in each drive control unit.

3. The circuit according to claim 1, characterized in that, The drive control unit includes a probe subunit and a comparator subunit. The probe subunit is connected to the comparator subunit and the probe subunit is connected to the first connection terminal.

4. The circuit according to claim 1, characterized in that, The drive control unit includes a first edge pulse generator subunit, a second edge pulse generator subunit, and an RS latch subunit. The first edge pulse generator subunit is connected to the reset terminal of the RS latch subunit, and the second edge pulse generator subunit is connected to the set terminal of the RS latch subunit.

5. The circuit according to claim 1, characterized in that, The first edge pulse generator subunit includes a first signal input terminal, a first inverter group, and a first NOR gate. The first signal input terminal is connected to the input terminal of the first inverter group. The output terminal of the first inverter group and the first signal input terminal are respectively connected to the two input terminals of the first NOR gate. The output terminal of the first NOR gate is connected to the RS latch subunit.

6. The circuit according to claim 1, characterized in that, The second edge pulse generator subunit includes a second inverter group and a second NOR gate. The input terminal of the second inverter group is connected to the first connection terminal. The output terminal of the second inverter group and the second signal input terminal are respectively connected to the two input terminals of the second NOR gate. The output terminal of the second NOR gate is connected to the RS latch subunit.

7. The circuit according to claim 1, characterized in that, The drive control unit includes a signal processing subunit, which is connected to the RS latch subunit.

8. The circuit according to claim 1, characterized in that, The drive control unit includes a resistor array subunit, which is connected to the signal processing subunit; The resistor array sub-unit includes a signal terminal, a third NMOS transistor, a first resistor, and a second resistor. The signal terminal is connected to the gate of the third NMOS transistor, the source of the third NMOS transistor is connected in series with the second resistor, the first resistor is connected in parallel with the second resistor, and the resistance value of the first resistor is greater than the resistance value of the second resistor.

9. A negative voltage turn-off control method for power switching devices, applicable to the negative voltage turn-off circuit for power switching devices as described in any one of claims 1-8, characterized in that, include, Upon receiving a shutdown command, the first NMOS transistor and the second PMOS transistor are blocked, and the first PMOS transistor and the second NMOS transistor are turned on. The emitter of the power switching device is clamped to the positive power supply, and the gate is pulled down to the reference ground. The RS latch subunit of the drive control unit maintains the initial reset state and outputs a high level value to the resistor array subunit of the drive control unit. The third NMOS transistor of the drive control unit is turned on, and the gate of the power switching device enters a low impedance state and begins to exit the saturation region. When the collector voltage of the power switching device rises rapidly, the detection subunit of the drive control unit acquires the collector voltage change rate signal in real time. Before the collector voltage rises rapidly to the DC bus high voltage value, the collector voltage change rate is higher than the reference threshold. The comparator subunit of the drive control unit outputs a high level, and the gate of the power switching device remains in a low impedance state. When the collector voltage of the power switching device rises to the high voltage value of the DC bus, the collector voltage change rate signal decays rapidly, the collector voltage change rate gradually approaches 0, the collector voltage change rate is less than or equal to the reference threshold, the comparator subunit of the drive control unit outputs a falling edge, the power switching device completes de-protection, the third NMOS transistor of the drive control unit is turned off, and the gate of the power switching device switches from low impedance to high impedance in a step transition. The gate of the power switching device remains in a high impedance state, driving the RS latch subunit of the control unit to enter a logic self-locking state, waiting for the turn-on command of the next cycle to turn on the power switching device.

10. The method according to claim 9, characterized in that, The following steps are then included: Upon receiving the power-on command, the first NMOS transistor and the second PMOS transistor are turned on, the first PMOS transistor and the second NMOS transistor are blocked, and the power switching device is turned on.

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