A high-precision adc on-chip auto-calibration method and system for robot control chip

Abstract

The application discloses a high-precision ADC on-chip automatic calibration method and system for a robot control chip, relates to the technical field of robots, and has the technical scheme as follows: in the background gap of normal work of the ADC, a known excitation is generated by using an internal reference source, and through full-digital and closed-loop feedback modes such as statistical analysis and correlation detection, various errors are estimated and compensated in real time and adaptively, so that the calibration process does not interrupt normal data conversion, and temperature and process changes can be tracked quickly and accurately, the problems in the prior art, such as slow calibration convergence, low precision, large resource occupation, incapability of adapting to temperature drift and long-term operation, and background calibration interference with normal sampling, are solved, and high-precision, fast-converging, low-overhead, highly-adaptable on-chip automatic calibration is realized.

Description

Technical Field

[0001] This invention relates to the field of robotics, and more specifically, to a high-precision on-chip automatic calibration method and system for robot control chips. Background Technology

[0002] In the field of robot control, high-precision real-time control is a core requirement. Robot control chips, as central processing units, are widely used in key scenarios such as joint servo actuators, mobile chassis drives, robotic arm end effector control, sensor information fusion, and system power management. Typical high-performance robot control chips integrate multiple core IPs, including a RISC-V processor core, high-resolution PWM / timers, high-speed analog-to-digital converters (ADCs), direct memory access controllers (DDMAs), on-chip memory, and a system clock management unit. Among these, the ADC is a crucial bridge connecting the analog physical world and the digital control system, responsible for converting analog signals from actuator current, power bus voltage, temperature, and various force / position sensor outputs into digital quantities for real-time decision-making by the control algorithm. The conversion accuracy of the ADC directly determines the control accuracy of the current loop, velocity loop, and position loop, as well as the accuracy of system status monitoring and protection. For example, offset errors in actuator current sampling can lead to torque estimation deviations, affecting trajectory tracking; gain errors in power supply voltage measurement can affect battery state estimation and energy management; and nonlinearity of the ADC can lead to misjudgments in sensor fusion and fault diagnosis. Therefore, achieving high-precision and high-stability ADC conversion is the cornerstone for improving the overall performance, reliability, and safety of robots.

[0003] However, as semiconductor processes advance to the nanoscale, achieving high-precision ADCs on chips faces unprecedented challenges. First, process deviations are becoming increasingly prominent. At the nanoscale, manufacturing parameters of transistors, capacitors, and other devices can deviate by ±30%, significantly increasing the inherent offset, gain, and nonlinear errors of the ADC, severely impacting factory accuracy. Second, industrial robot applications require chips to operate stably over a wide temperature range of -40°C to 125°C, but device characteristics drift with temperature, potentially increasing the static error of the ADC by 2 to 3 times, and causing calibration effectiveness to deteriorate over time and with environmental changes. To address these challenges, the industry has developed various calibration techniques, but all have significant limitations. Traditional foreground calibration techniques require pausing the normal ADC conversion process and injecting a test signal for calibration, which is unsuitable for the continuous, real-time sampling requirements of robot systems. While common background calibration techniques can be performed while the ADC is operating, they typically suffer from slow convergence speeds, long calibration cycles, and require large amounts of sampling data and hardware resources, making them difficult to integrate into robot control chips that are extremely sensitive to area and power consumption. Furthermore, calibration with fixed parameters cannot adapt to temperature changes and drift caused by long-term aging, and the calibration effect will gradually decline.

[0004] Therefore, researching and designing a high-precision on-chip automatic calibration method and system for robot control chips that can overcome the above-mentioned defects is an urgent problem to be solved. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a high-precision on-chip automatic calibration method and system for robot control chips. During the background interval of normal ADC operation, a known stimulus is generated using an internal reference source. Through statistical analysis and related detection, and other fully digital, closed-loop feedback methods, various errors are estimated and compensated in real time and adaptively. This ensures that the calibration process does not interrupt normal data conversion and can quickly and accurately track temperature and process changes, achieving high-precision, fast-convergence, low-overhead, and highly adaptable on-chip automatic calibration.

[0006] The above-mentioned technical objective of the present invention is achieved through the following technical solution: In a first aspect, a high-precision on-chip automatic calibration method for ADCs used in robot control chips is provided, comprising the following steps: After calibration is triggered, statistical distribution analysis is performed on the ADC sampling data of multiple calibration reference points provided by the internal reference source, and the size of the calculation window is adaptively adjusted according to the analysis results to generate an initial error vector containing offset, gain and nonlinearity information. Using the initial error vector, static offset compensation, gain compensation, and nonlinear interpolation compensation based on lookup table are sequentially performed on the real-time converted code stream of the ADC. After compensation is completed, a known pseudo-random sequence is injected into the ADC calibration path. Correlation detection is performed on the ADC output after forward and reverse injection to obtain the corresponding error estimation components. The two are then fused to generate a refined error vector. Based on the temperature value and its rate of change monitored by the on-chip temperature sensor, and combined with the update status of the error vector, the system dynamically decides whether to continue, pause, or terminate the calibration iteration, and controls the update and switching of the calibration coefficients. After the decision requires updating the coefficients, the updated calibration coefficients are safely synchronized from the calibration processing clock domain to the ADC sampling clock domain through a cross-clock domain synchronous handshake mechanism, and then applied to the static offset compensation, gain compensation and nonlinear interpolation compensation in an atomic manner.

[0007] Furthermore, the adaptive adjustment of the calculation window size based on the analysis results includes: Calculate the kurtosis and skewness of the ADC sampled data within the current window; When the kurtosis is greater than the first threshold and the absolute value of the skewness is less than the second threshold, the data distribution is determined to be concentrated, and the window size is reduced accordingly. When the kurtosis is less than the first threshold or the absolute value of the skewness is greater than the third threshold, it is determined that the data distribution is scattered or skewed, and a decision is made to expand the window size.

[0008] Furthermore, the generation of the initial error vector containing offset, gain, and nonlinear information includes: The offset error vector is obtained by subtracting the average value of the reference ground level from the ideal zero code. The difference between the average sampling values ​​of the high reference level and the low reference level is calculated as the actual code difference. The ratio of the actual code difference to the difference of the ideal code value is calculated to obtain the gain error vector associated with the current temperature. Multiple segmented reference level sample values ​​are acquired, and residuals are formed after removing the effects of offset and gain. Piecewise linear fitting is performed on the residuals to obtain a nonlinear error vector.

[0009] Furthermore, the step of performing correlation detection on the ADC outputs after forward and reverse injection respectively, obtaining the corresponding error estimation components, and fusing the two to generate a refined error vector includes: A pseudo-random sequence with positive polarity is injected into the ADC front end, and the ADC output code is accumulated by sliding window correlation to obtain the positive correlation value; Inject a pseudo-random sequence of opposite polarity into the ADC front end, and perform sliding window correlation accumulation on the ADC output code to obtain the inverse correlation value; Based on the current temperature, gain estimate confidence level, and residual variance, weights are assigned to the positive correlation value and the negative correlation value, and weighted fusion is performed to generate the calibration update value; The current error vector is iteratively calculated using the calibration update amount to generate a refined error vector.

[0010] Furthermore, the dynamic decision-making regarding the continuation, pause, or termination of the calibration iteration based on the temperature value and its rate of change monitored by the on-chip temperature sensor, combined with the update status of the error vector, includes: When the detected temperature change rate exceeds the first preset threshold, the system enters a state to freeze the currently active calibration coefficients and prohibit updates. When the rate of temperature change is lower than the first preset threshold and the temperature tends to stabilize, it is determined whether the change in the error vector during a preset number of consecutive iterations is less than the second preset threshold. If the change is less than the second preset threshold, the calibration is determined to have converged and the iteration is terminated.

[0011] Furthermore, the updated calibration coefficients are securely synchronized from the calibration processing clock domain to the ADC sampling clock domain via a cross-clock domain synchronization handshake mechanism, and applied atomically to the static offset compensation, gain compensation, and nonlinear interpolation compensation, including: Write the updated and verified calibration coefficients into the shaded buffer located in the calibration processing clock domain; Synchronization from the calibration processing clock domain to the ADC sampling clock domain is achieved through asynchronous FIFO and request-response handshake protocol; In a safe time slot determined by the on-chip timer or system clock management unit that does not affect the normal sampling of the ADC, the coefficients in the shadow buffer are atomically switched to the active buffer of the ADC sampling clock domain.

[0012] Furthermore, the execution of this method is performed by the RISC-V core within the chip for strategy configuration and status monitoring, and is triggered in non-critical control time slots by the on-chip PWM / timer module, using the DMA controller to transfer calibration coefficients and sampling data.

[0013] Furthermore, in each calibration iteration, this method employs a multi-stage pipeline structure to decouple the updating and application of calibration coefficients, wherein: The update of the offset error vector is independent of the update of the gain error vector, and both are performed in parallel or sequentially with the update of the nonlinear error vector. The updated error vectors are then synchronized and combined for application in the multi-level error compensation.

[0014] Secondly, a high-precision on-chip automatic calibration system for robot control chips is provided, integrated within the robot control chip, including: The dynamic window self-converging calibration engine is configured to perform statistical distribution analysis on ADC sampled data from multiple calibration reference points provided by an internal reference source, and adaptively adjust the size of the calculation window according to the analysis results to generate an initial error vector containing offset, gain, and nonlinearity information. A multi-level error vector quantization compensation unit is configured to use the initial error vector to sequentially perform static offset compensation, gain compensation, and lookup table-based nonlinear interpolation compensation on the real-time converted code stream of the ADC. A pseudo-random injection bidirectional approximation calibrator is configured to inject a known pseudo-random sequence into the ADC calibration path after the compensation is completed, obtain the forward and reverse error estimation components through relevant detection, and fuse the two to generate a refined error vector. The temperature adaptive iteration termination determination module is configured to dynamically decide whether to continue, pause, or terminate the calibration iteration based on the temperature value and its rate of change monitored by the on-chip temperature sensor, combined with the update status of the error vector, and control the update and switching of the calibration coefficients. The dual-time-domain asynchronous latch synchronization module is configured to, after a decision requires updating the coefficients, securely synchronize the updated calibration coefficients from the calibration processing clock domain to the ADC sampling clock domain through a cross-clock domain synchronization handshake mechanism, and apply them to the multi-level error vector quantization compensation unit in an atomic manner.

[0015] Furthermore, the robot control chip is a system-on-a-chip based on a RISC-V core; and the system is located in the internal ADC conversion link of the chip, and works in conjunction with the on-chip PWM / timer module, DMA controller, internal reference source or calibration DAC, on-chip SRAM or lookup table memory, temperature sensor, system clock management unit and RISC-V core.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention provides a high-precision on-chip automatic calibration method for robot control chips using an ADC. During the background interval of normal ADC operation, a known stimulus is generated using an internal reference source. Through statistical analysis and related detection, and other fully digital, closed-loop feedback methods, various errors are estimated and compensated in real time and adaptively. This ensures that the calibration process does not interrupt normal data conversion and can quickly and accurately track temperature and process changes. It solves the problems of slow calibration convergence, low accuracy, high resource consumption, inability to adapt to temperature drift and long-term operation, and background calibration interference with normal sampling in the prior art. It achieves high-precision, fast convergence, low overhead, and high adaptability on-chip automatic calibration.

[0017] 2. This invention adaptively adjusts the calculation window by introducing statistical distribution analysis based on kurtosis and skewness, and precisely decouples the calculation of three types of error vectors—offset, gain, and nonlinearity—within the window. Kurtosis and skewness sensitively reflect the concentration and symmetry of the sampled data, thereby intelligently judging the reliability of the current estimate. The dynamic adjustment of the window achieves a balance between fast convergence and high-precision estimation. At the same time, the independent and quantified calculation of the three types of errors provides accurate input for subsequent hierarchical and pipelined compensation, enabling the system to quickly generate accurate initial error estimates with the shortest sampling time and the least amount of computation. This improves the calibration startup speed and initial accuracy, effectively solving the problems of slow convergence and inaccurate estimation caused by the use of fixed windows or single error models in traditional calibration methods.

[0018] 3. This invention employs pseudo-random sequence bidirectional injection and correlation detection techniques to refine errors, and combines a multi-stage pipeline structure to decouple coefficient updates and applications. By injecting weak pseudo-random perturbations with known statistical characteristics and utilizing their correlation with the ADC output residuals, the interference of normal input signals and noise on error estimation can be greatly suppressed, extracting high signal-to-noise ratio error information by measuring noise with noise. Simultaneously, the update paths for different types of error vectors are designed as independent modules that can be parallelized or pipelined, significantly improving hardware utilization and processing throughput. This invention improves the robustness and accuracy of error estimation while ensuring system efficiency, thus solving the problems of inaccurate error estimation under strong background signals, calibration resource conflicts, and poor system real-time performance.

[0019] 4. This invention integrates temperature-adaptive iterative termination judgment logic and a dual-time-domain asynchronous latch synchronization mechanism, and deeply collaborates with on-chip modules such as the RISC-V core, PWM / timer, and DMA. By real-time monitoring of the temperature change rate to freeze or allow coefficient updates, it avoids applying unstable coefficients during periods of rapid temperature change. Through asynchronous FIFO, handshake protocol, and atomic switching mechanism, it ensures absolute safety and disturbance-free operation of coefficients during cross-clock domain transmission and updates. By utilizing PWM non-critical time slots to trigger calibration and DMA to automatically transfer data, it achieves perfect decoupling of calibration tasks and main control tasks in terms of time and resources. This invention enables the calibration system to intelligently adapt to the operating environment across the entire temperature range, reducing the risk of system crashes due to metastable or semi-updated coefficients, and minimizing CPU usage on the main controller. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart from Embodiment 1 of the present invention; Figure 2 This is a flowchart of the dynamic window self-convergence calibration in Embodiment 1 of the present invention; Figure 3 This is a logic diagram of multi-level error vector quantization compensation in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the pseudo-random injection bidirectional approximation calibration in Embodiment 1 of the present invention; Figure 5 This is a logic diagram of the temperature adaptive iteration termination determination in Embodiment 1 of the present invention; Figure 6 This is a timing diagram of the dual-time-domain asynchronous latch synchronization mechanism in Embodiment 1 of the present invention; Figure 7 This is a system architecture diagram in Embodiment 2 of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this invention are only for explaining this invention and are not intended to limit this invention.

[0022] Example 1: A high-precision on-chip automatic calibration method for robot control chips, such as... Figure 1 As shown, it includes the following steps: S1: After triggering calibration, perform statistical distribution analysis on the ADC sampling data of multiple calibration reference points provided by the internal reference source, and adaptively adjust the size of the calculation window according to the analysis results to generate an initial error vector containing offset, gain and nonlinearity information. S2: Using the initial error vector, static offset compensation, gain compensation, and nonlinear interpolation compensation based on lookup table are sequentially performed on the real-time converted code stream of the ADC. S3: After compensation is completed, a known pseudo-random sequence is injected into the ADC calibration path. Correlation detection is performed on the ADC output after forward injection and reverse injection respectively to obtain the corresponding error estimation components. The two are then fused to generate a refined error vector. S4: Based on the temperature value and its rate of change monitored by the on-chip temperature sensor, combined with the update status of the error vector, dynamically decide whether to continue, pause or terminate the calibration iteration, and control the update and switching of the calibration coefficients. S5: After the decision requires updating the coefficients, the updated calibration coefficients are safely synchronized from the calibration processing clock domain to the ADC sampling clock domain through a cross-clock domain synchronous handshake mechanism, and then applied to static offset compensation, gain compensation and nonlinear interpolation compensation in an atomic manner.

[0023] In step S1, as Figure 2 As shown, the on-chip automatic calibration system is triggered when preset conditions are met. The triggering mechanism is designed to coordinate with the execution timing of robot control tasks to ensure that critical real-time control loops are not affected. The calibration triggering conditions include three modes, selectable according to system configuration. The first is a timed trigger based on a fixed period, such as executing every 100 milliseconds. The second is a trigger based on environmental changes, i.e., it starts when the rate of temperature change detected by the on-chip temperature sensor exceeds a set threshold. The third is directly controlled by the control logic, i.e., using non-critical control task time slots generated by the on-chip PWM module or general-purpose timer module as the calibration window. This triggering condition is configured by the RISC-V core and written to the control register of the calibration state machine.

[0024] After the calibration process is triggered, the calibration state machine takes over the internal analog signal path. Under the control of the state machine, the analog multiplexer inside the chip sequentially connects a series of precise internal reference signals to the analog input of the ADC. These internal reference signals are generated by the integrated reference voltage source and calibration DAC within the chip, requiring no external excitation. A typical reference point sequence includes: a ground level for measuring offset error; a low reference level for defining the starting point of gain calculation; a high reference level for defining the ending point of gain calculation; and multiple segmented reference levels generated by the calibration DAC to cover the entire input range of the ADC to accurately map its nonlinear characteristics. In this embodiment, the number of segmented reference points is preferably 16 to achieve a balance between characterization accuracy and hardware overhead.

[0025] For each selected reference level, the ADC continuously samples under its normal sampling clock. The acquired raw digital code is sent to a buffer managed by the DMA controller. The system presets an initial statistical window size, such as 1024 sampling points, as the basis for the initial error estimation. This larger window helps to obtain stable statistical characteristics in the initial stage, laying the foundation for subsequent dynamic adjustments.

[0026] After acquiring the sampling data window of the current reference point, the dynamic window self-converging calibration engine is activated and begins to execute the core adaptive algorithm. This algorithm first performs in-depth statistical distribution analysis on the ADC sampling data within the window, calculating four key statistics: mean, variance, kurtosis, and skewness.

[0027] The mean reflects the central location of the sampled data. Variance measures the dispersion of the data. Kurtosis quantifies the steepness of the data distribution; a value greater than 3 indicates a sharper distribution than a normal distribution, with the data more concentrated around the mean; a value less than 3 indicates a flatter distribution. Skewness measures the asymmetry of the distribution; an absolute value of 0 indicates perfect symmetry, a value greater than 0 indicates a tail to the right, and a value less than 0 indicates a tail to the left.

[0028] The calibration engine uses these statistical characteristics to dynamically and intelligently adjust the size of the sampling window used to calculate the next error vector. The decision logic is as follows: Window shrinkage condition: When analysis shows that the kurtosis of the data within the current window is greater than 3 and the absolute value of the skewness is less than 0.5, the algorithm determines that the data distribution is highly concentrated and nearly symmetrical. This means that the estimation within the current window is relatively accurate and stable, with minimal impact from noise and outliers. In this case, the system decides to shrink the size of the computation window. After the window shrinks, the number of sample points used for the next estimation decreases, thus enabling a faster response to changes in error trends and significantly accelerating the overall convergence speed of the calibration process. The window size transitions smoothly according to a preset sequence (e.g., shrinking from 1024 points to 512 points, 256 points, etc.).

[0029] Window expansion condition: Conversely, when the kurtosis of the data is less than 3, or the absolute value of the skewness is greater than 1, the algorithm determines that the data distribution is relatively scattered or has obvious asymmetry. This may be caused by large measurement noise, transient interference, or the estimation itself not yet being stable. To improve the accuracy and robustness of the estimation and suppress the influence of bad data, the system decides to expand the size of the calculation window. Expanding the window means using more historical data for averaging, which can effectively smooth random fluctuations and improve the accuracy of error estimation.

[0030] Through this real-time, data quality-feedback-based window adjustment mechanism, the system achieves a dynamic balance between the often contradictory goals of rapid convergence and high-accuracy estimation. The window size is automatically and smoothly transitioned from an initial large window to a final small window, completing the self-convergence process.

[0031] After determining the current optimal window, the system uses the statistics (mainly the mean) calculated within that window to decouple and calculate three independent vectors that constitute the total ADC error: the offset error vector, the gain error vector, and the nonlinearity error vector. These calculations strictly follow a three-level error model.

[0032] Offset error refers to the deviation of the actual transfer characteristic curve of the ADC at the zero point. To measure offset error, the system processes the sampled data from the reference ground level. Let the average sampling window value of the reference ground level be... Ideally, the ADC output code corresponding to zero input is Offset error vector The difference between the two is obtained after quantization: ; in, This represents the fixed-point quantization and limiting function, ensuring the result remains within the dynamic range of the digital compensation circuit. The calculated... This value will be directly used for the first-level compensation of subsequent data paths, i.e., subtracted from the source code.

[0033] Gain error describes the deviation between the actual slope of the ADC's transfer curve and the ideal slope, and this deviation varies significantly with temperature. Calculating gain error requires two different reference points: a low reference point and a high reference point. and high reference point Let their sampling window mean values ​​be respectively and The corresponding ideal output codes are respectively and Gain error vector The ratio of the actual code difference to the ideal code difference is determined and stored in the lookup table according to the current temperature index T: ;in, It is a coefficient close to 1. During compensation, after subtracting the offset from the original code, this coefficient is multiplied to correct the gain error.

[0034] Nonlinear errors, especially integral nonlinear errors, are inherent to ADCs and cannot be eliminated by simple offset and gain adjustments. Their calculation is based on multiple segmented reference points. Let the average sampling window value of the k-th segmented reference point be... Its ideal output code is First, using the already obtained... and right Pre-compensation is performed to obtain residuals containing only nonlinear errors. : This calculation removes the output deviation caused by offset and gain errors at that point, making... It purely reflects the nonlinear deviation at that point.

[0035] Then, the system performs piecewise linear fitting on the residual sequences calculated for all segmented reference points. Typically, the ADC input range is divided into N segments (e.g., 16 segments), and within each segment, a straight line is used to fit the residuals corresponding to the segment's boundary points. This fitting allows the construction of a nonlinear error lookup table. ,in The error compensation value is determined by the high-order bits of the ADC output code. For any output code falling within the segment, its nonlinear error compensation value can be obtained by looking up a table and linear interpolation.

[0036] Finally, the calculated and quantized offset error vector Temperature-related gain error vector and nonlinear error vector These factors combine to form a complete initial error vector. This vector is temporarily stored in a register or a dedicated shadow buffer within the calibration engine as the output of this calibration iteration, ready to be processed by subsequent pseudo-random injection refinement steps, or determined by temperature adaptive logic to determine whether it can be used to update the active compensation coefficients.

[0037] In step S2, as Figure 3 As shown, the initial error vector generated in step S1, after verification, is prepared for application to the normal data path of the ADC. When the ADC completes one sampling and quantization of the analog input signal, its output raw digital code is denoted as... The data will immediately enter a dedicated digital compensation pipeline. This pipeline is the data path of the multi-level error vector quantization compensation unit, and its design goal is to sequentially and uninterruptedly perform static offset compensation, gain compensation, and lookup table-based nonlinear interpolation compensation on the real-time converted code stream of the ADC.

[0038] Raw ADC code First, we enter the first-level compensation module, namely the static offset compensation stage. This module's function is to eliminate the fixed DC offset introduced by factors such as the ADC's internal circuit offset voltage and comparator threshold deviation. The compensation operation is very straightforward: from the original code... In the middle, subtract the offset error vector calculated in step S1. The error vector This is a quantized value representing the average deviation between the actual output code and the ideal zero code of the ADC when input at zero point (or reference ground). After this compensation step, the output code... The systematic DC bias has been corrected. Its operational relationship can be expressed by the following formula: .

[0039] Intermediate code after offset correction The system then proceeds to the second-level compensation module, the gain compensation stage. This module corrects the ADC's transfer gain error, which causes a deviation between the actual conversion curve's slope and the ideal slope. This deviation drifts with changes in the chip junction temperature. Gain compensation is not a simple addition or subtraction operation, but involves a linear transformation of multiplication and addition (or equivalent scaling and biasing). The compensation operation utilizes the gain error vector calculated in step S1, which is associated with the current temperature. Specifically, the system reads the current temperature index T from the on-chip temperature sensor and retrieves the corresponding gain compensation coefficient from a lookup table storing the gain error vector based on this index. and a possible residual bias term Then, for the intermediate code Apply the following transformation: ; in, It is an intermediate digital code after the second-stage gain compensation. At this point, the amplitude ratio (gain) of the output code has been corrected for temperature adaptation.

[0040] Finally, the bitstream after gain compensation. The third and most complex compensation stage is nonlinear interpolation compensation. The goal of this stage is to correct the integral nonlinearity error of the ADC. This error manifests as a deviation from an ideal straight line in the actual transmission curve of the ADC, even after the user has eliminated offset and gain errors; this deviation is related to the input signal amplitude. The core of this module is a distributed lookup table that stores the nonlinear error vector calculated in step S1. This vector divides the entire input range of the ADC into multiple consecutive segments (e.g., 16 segments), with each segment index k corresponding to a stored error value.

[0041] The compensation process consists of two steps: indexing and interpolation. First, based on the current input code... The higher-order bits determine the segment index k in which it resides. Simultaneously, based on... For the lower digits within this segment, a precise decimal position parameter is calculated. Then, the nonlinear error values ​​corresponding to the current segment index k and the next segment index k+1 are obtained through a table lookup operation. and Finally, a linear interpolation is performed between the two stored error values ​​to calculate the result corresponding to the current precise input position. The final nonlinear error compensation value. This compensation value is added to (or subtracted from, depending on the error definition)... The final high-precision output code after calibration is obtained. The operational relationships can be summarized as follows: ; in, It is the output code after the second-stage gain compensation; Represents a linear interpolation function, which is based on The value, in and An interpolation result is calculated between them. This represents the final high-precision calibration digital code after all three levels of compensation. Its accuracy is significantly higher than the original code D_raw, and it can be directly supplied to the RISC-V kernel or control algorithm.

[0042] It should be noted that the compensation coefficient applied to the above three-stage production line... The coefficients are not fixed. They are continuously calculated and updated in the background by the calibration engine. To ensure that coefficient updates do not affect ongoing normal data conversions, the system employs a double-buffering mechanism. Newly calculated coefficient sets are first written to a storage area called the shadow buffer. Only when the new coefficient set passes verification and the temperature-adaptive iterative termination decision logic allows for updates, will the new coefficients in the shadow buffer be instantly switched to the active buffer via an atomic operation at a safe timing boundary determined by the system clock management unit (such as the gap between two ADC sampling conversions). Afterward, all new ADC sampling data entering the compensation pipeline will be immediately compensated using the updated, more accurate coefficients, thus achieving real-time, seamless, and non-disruptive online upgrades of the calibration process.

[0043] In step S3, as Figure 4 As shown, after real-time compensation based on the initial error vector is completed in step S2, a more refined calibration stage, namely pseudo-random injection bidirectional approximation calibration, is entered. The goal of this step is to refine the initially compensated error vector to further improve calibration accuracy and suppress estimation biases introduced by the input signal itself, environmental noise, or the inherent nonlinearity of the ADC. This step does not require an external excitation source, nor does it require a long interruption of the ADC's normal sampling. Instead, during the normal operation interval of the ADC, a known, statistically controllable small perturbation signal is injected into the calibration path through the chip's internal resources, and the pure error information is extracted with high precision from the complex output signal using relevant detection techniques.

[0044] The calibration and refinement process begins with the generation of a pseudo-random sequence. An integrated linear feedback shift register module is enabled, configured to generate a maximum-length sequence with excellent properties, namely the M-sequence. The generated initial sequence consists of 0s and 1s. To facilitate subsequent correlation operations, this sequence is mapped to a bipolar form, i.e. The sequence length can be configured according to accuracy and speed requirements, for example, using a period of 15 bits or longer to ensure good statistical properties.

[0045] The generated bipolar sequence The sequence cannot be injected directly into the ADC at full amplitude, as this would severely interfere with normal signal sampling. Therefore, the sequence must pass through an amplitude shaping unit before injection. This unit scales the sequence amplitude to a tiny value much smaller than the least significant bit of the ADC. Specifically, the injection amplitude... The value is set to a preset ratio of the target LSB, such as LSB / 4. This keeps the impact of the injected pseudo-random perturbation signal on the normal conversion result within an acceptable range, while still allowing for effective detection by the subsequent high-sensitivity correlator. Finally, the shaped injected signal is represented as... .

[0046] The pseudo-random injection employs a bidirectional approximation strategy, which involves superimposing the same pseudo-random template onto the ADC input path with both positive and negative polarities. This is achieved by controlling the internal reference source, the calibration DAC, and the analog multiplexing switch.

[0047] First, a positive injection is performed. The calibration state machine controls the analog switch, superimposing a positive pseudo-random perturbation onto a selected internal reference level; that is, the injected signal is... The ADC continuously samples the injected synthesized signal and outputs digital codes compensated for by the current activity error vector. These output codes are compared with a known ideal reference code, and the differences form a positive residual sequence. The residuals include the response caused by the injected signal, incompletely compensated errors, and noise.

[0048] Subsequently, under the same calibration conditions, reverse injection was performed. At this point, the polarity of the injected signal was reversed, becoming... The ADC is resampled and, after the same compensation, the output code is obtained. The difference between the output code and the ideal value is calculated to obtain the inverse residual sequence. .

[0049] After obtaining the forward and inverse residual sequences, correlation detection techniques are used to extract the error components that are in phase with the pseudo-randomly injected sequence. This is because the normal input signal, noise, and the known pseudo-random sequence... Statistically uncorrelated, but the response caused by injection path and ADC miscalibration error is related to... The correlation is strong, therefore the correlation operation can effectively suppress the uncorrelated components and highlight the error information.

[0050] The forward and reverse correlators within the system perform the same operation. Taking the forward channel as an example, the correlator operates on the forward residual sequence... With known pseudo-random templates Perform cumulative calculations related to the sliding window. The specific formula is: ; Where N represents the length of the sliding window used for relevant accumulation, and its size can be dynamically adjusted according to the convergence phase. This represents the calculated positive correlation value, the magnitude and sign of which directly reflect the correlation strength between the system residual error and the pseudo-random injected signal under positive injection conditions, i.e., the positive error estimation component.

[0051] Similarly, the inverse correlator affects the inverse residual sequence. With pseudo-random sequences By performing correlation summation, the inverse correlation value is obtained. : .

[0052] Two error estimation components, one forward and one backward, are obtained. and Subsequently, instead of simply averaging, the system employs an adaptive weighted fusion strategy to further improve the robustness and accuracy of the estimation. The weighted fusion module calculates the fusion based on multiple state parameters of the current system. and Dynamically allocate fusion weights and These state parameters include the current temperature T read from the on-chip temperature sensor, the confidence level of the current gain error estimate, and the variance of the residual sequence.

[0053] The logic behind weight allocation aims to trust the more reliable estimated components. For example, if the gain estimate is stable at the current temperature, or the residual variance is smaller under a certain polarity injection, the correlation value corresponding to that polarity may be assigned a higher weight. The weights satisfy the normalization condition, i.e. .

[0054] Then, the two relevant values ​​are weighted and fused using the assigned weights to calculate the calibration update amount for this iteration. : .

[0055] The amount of calibration updates obtained This is used to update the current error vector. This update process is an iterative operation. Let the currently stored error vector be... An iteration step size is determined based on factors such as the current convergence stage and window confidence. Then, using the calibration update amount The old vector is corrected to generate a refined new error vector. : ;in, The iteration step size is a positive number less than 1. A larger value can be chosen in the early stages of convergence for rapid approximation, while a smaller value is chosen in the later stages to stabilize accuracy. This new vector will be temporarily stored in the shadow buffer, awaiting the decision of the temperature adaptive iteration termination logic in step S4 to determine whether to switch it as an active coefficient for subsequent real-time compensation. Through this closed-loop iterative refinement, the system can continuously optimize the calibration coefficients to approximate the true error, thereby achieving high-precision on-chip self-calibration.

[0056] In step S4, as Figure 5As shown, the operating environment temperature of robot control chips varies drastically. From low-temperature startup to full-load operation, the junction temperature can drift significantly within the industrial range of -40°C to 125°C. The error characteristics of the ADC, especially the gain error, change significantly with temperature. If the dynamic temperature changes are ignored during calibration, and coefficients calculated based on unstable temperature conditions are applied to real-time compensation during periods of rapid temperature change, additional errors will be introduced, potentially even leading to system performance degradation. Therefore, this invention introduces a dedicated state machine logic, namely, a temperature-adaptive iterative termination decision logic. Its core function is to jointly decide whether the calibration iteration should continue, be temporarily paused, or permanently terminated based on real-time monitored temperature and its changing trend, combined with the convergence state of the calibration process itself.

[0057] The input to this decision logic mainly comes from two sources. The first key input is an on-chip temperature sensor. This sensor outputs digitized temperature values ​​at fixed intervals. For example, the update cycle is 1 millisecond, and the accuracy can reach ±1°C. The decision logic continuously reads these temperature values. The second input is a signal from inside the calibration engine, mainly including the update status of the error vector generated by steps S1 and S3, specifically reflected in the amount of change in the error vector. residual variance And the count value of the calibration iteration.

[0058] The decision logic first processes the temperature data, calculating the dynamic rate of temperature change. This is achieved by comparing the temperature values ​​of two adjacent sampling periods. Let the current sampling time be n, and the read temperature value be... The temperature value at the previous sampling time was The time interval between the two is Then the rate of temperature change : .

[0059] Calculated temperature change rate The temperature change rate will be compared to a preset threshold, called the temperature change rate threshold. For example, the threshold can be set to 0.5°C / millisecond. When the absolute value of the detected temperature change rate exceeds this threshold, the logic determines that a temperature abrupt change is currently occurring.

[0060] When the judgment logic determines that the current period is one of sudden temperature changes, no matter how accurate the new error vector calculated by the background calibration engine may seem, it is not allowed to take effect immediately. This is because the temperature is still changing rapidly, and the coefficients calculated based on the current temperature may become outdated in a very short time.

[0061] Therefore, the logic controls the state machine to enter either a hold or freeze state. In this state, two key actions are performed. First, switching any new calibration coefficients temporarily stored in the shadow buffer to the active buffer is strictly prohibited. This means that the ADC's real-time compensation path will continue to use the previous set of reliable calibration coefficients verified when the temperature is relatively stable. Second, the decision logic can send a pause signal to the calibration engine, temporarily halting time-consuming pseudo-random injection and related detection refinement iterations to save power until the temperature stabilizes again. This strategy effectively prevents unstable coefficients from contaminating the data path, ensuring the system's output stability during periods of drastic environmental changes.

[0062] When the rate of temperature change If the absolute value of the temperature is lower than the preset threshold and remains low for a continuous period of time, the decision logic considers the temperature to have stabilized. At this point, the system enters the fine calibration and convergence determination phase.

[0063] At this stage, the decision logic shifts its focus to the convergence of the calibration process itself. It continuously monitors the calibration updates generated in step S3. The decision logic checks whether the change in the error vector generated in each of the preset number of consecutive calibration iterations (e.g., 4 consecutive iterations) is less than a set small threshold. This threshold is called the convergence decision threshold, which can be set to 0.01 LSB for example.

[0064] Meanwhile, as an auxiliary criterion, the decision logic also monitors the residual variance. The trend of change. If the residual variance no longer decreases during the iteration process, or even begins to increase, it may mean that the calibration has overfitted or encountered other problems.

[0065] The decision logic makes the final decision on calibration convergence when the following joint conditions are met: the temperature is stable, the change in the error vector for a consecutive preset number of iterations is less than the convergence decision threshold, and the residual variance does not show an upward trend.

[0066] Once convergence is determined, the temperature adaptive iterative termination logic will execute a termination action. First, it allows the error vector, after the final refinement and verification, to atomically switch from the shadow buffer to the active buffer, completing the final update of the coefficients. Second, it sets the calibration state machine to an idle or completed state and updates the corresponding state registers, marking the successful completion of this calibration task. Afterward, the system can enter a low-power monitoring state, continuously monitored only by the temperature sensor, until a new round of calibration is initiated due to temperature changes or periodic triggering.

[0067] In addition to normal pause and termination paths, the decision logic also includes an exception handling state. For example, when the number of calibration iterations exceeds a safety limit, or the residual variance continues to increase abnormally, or the reference point sampling value goes out of bounds, the decision logic will force entry into an exception handling state regardless of the temperature status. In this state, the logic will disable coefficient updates, record specific error codes, the temperature value T at the time of the exception, and the iteration count in the status register, and can be configured to issue an interrupt request to the RISC-V core for advanced error handling and recovery by software. This ensures the robustness of the system under extreme or unexpected conditions.

[0068] Through the joint judgment and intelligent control of the above-mentioned multi-condition and multi-state, the temperature adaptive iterative termination judgment logic makes the calibration system no longer a simple open-loop execution, but a closed-loop intelligent system that can sense the environment, evaluate itself, and make optimal decisions, thereby maintaining high accuracy and high reliability in the full temperature range and various dynamic operating conditions.

[0069] In step S5, as Figure 6 As shown, after the temperature adaptive iteration termination decision logic in step S4, if it is determined that the calibration coefficients need to be updated (i.e., the newly generated, verified, refined error vector is better than the current active coefficients), and the ambient temperature allows for the update, then the system will initiate this synchronization step. The calculation of calibration coefficients is typically performed in a separate calibration processing clock domain, which is not from the ADC sampling clock. The coefficients are ultimately applied to the ADC's digital compensation data path, which operates in the ADC's sampling clock domain. These two clock domains are asynchronous, posing a potential metastability risk. Furthermore, it is essential to ensure that the ongoing data conversion of the ADC is not interrupted or contaminated when updating the coefficients, i.e., to achieve background, disturbance-free coefficient switching.

[0070] The first step in the synchronization process is to safely store the updated coefficients within the calibration processing clock domain. After the decision logic generates an update permission signal, the calibration engine calculates and finally determines the complete set of calibration coefficients, including the offset error vector. Gain error vector and nonlinear error vector The coefficients are first written to a specific storage area called the shadow buffer. Before writing, these coefficients are typically checked for integrity, such as cyclic redundancy check or parity check, to ensure that no bit errors occur during storage or transmission. The shadow buffer is a temporary storage area specifically designed to receive new coefficients, and it is physically isolated from the active coefficient buffer currently being read by the ADC compensation data path. At this time, the coefficients in the active buffer remain unchanged, and the ADC's real-time conversion and compensation are completely unaffected, continuing to operate stably using the old coefficients.

[0071] After the coefficients are safely stored in the shadow buffer of the calibration processing clock domain, a cross-clock domain synchronization process is initiated to reliably transfer update requests and coefficient data from the calibration processing clock domain to the ADC sampling clock domain. This invention employs a combination of classic asynchronous design methods.

[0072] First, for coefficient data transmitted in batches, an asynchronous FIFO is used as an isolation buffer. The calibration processing clock domain is used as the write clock to write the verified coefficients into the asynchronous FIFO; the ADC sampling clock domain is used as the read clock to read the coefficients from the FIFO when ready. The pointer comparison logic of the asynchronous FIFO is Gray code encoded to safely handle address comparisons under two asynchronous clocks, fundamentally avoiding metastability caused by simultaneous reading and writing to the same address.

[0073] Secondly, a request-response handshake protocol is used for control signal synchronization. After confirming that the coefficients are ready, the calibration processing clock domain generates a coefficient update request signal `req`. This `req` signal undergoes synchronization processing through two or more stages of synchronizers within the ADC sampling clock domain, transforming it into a stable, glitch-free synchronization request signal within the ADC sampling clock domain. The state machine in the ADC sampling clock domain detects a stable state. Then, it will determine whether it is in a safe state at its clock tick, for example, if there is no critical sampling or compensation calculation in progress. If it is safe, an acknowledgment signal (ack) will be generated. This ack signal is also processed by the synchronizer in the calibration processing clock domain and sent back to the state machine on the calibration processing side. Through this back-and-forth handshake, the two clock domains reach a reliable consensus that the coefficients are ready and the receiver is ready.

[0074] Upon receiving a valid ACK signal from the ADC sampling clock domain, the system enters the switching preparation state. However, the switching operation is not executed immediately; it must wait for an absolutely safe time slot determined by the on-chip timer or system clock management unit. This safe time slot refers to a specific time window within the ADC sampling clock domain that will not interfere with normal data conversion. For example, in motor drive applications controlled by a PWM module, the safe time slot can be selected at the dead time of the PWM wave or a non-critical sampling moment of a specific phase; in continuous sampling systems, it can be the brief interval between the start of two ADC conversions. The purpose of determining this safe time slot is to ensure that at the instant of coefficient switching, no ADC sample is passing through the compensation pipeline, thereby avoiding the situation where the first half of the same sampled data is compensated using the old coefficients and the second half using the new coefficients, leading to serious errors in the output data.

[0075] When the predetermined safety time slot arrives, the control logic within the ADC sampling clock domain executes an atomic operation. An atomic operation is one that is logically indivisible, its execution is uninterrupted, and its effect is instantaneously visible to the entire system. In this embodiment, the atomic operation involves instantaneously swapping the memory mapping address of the shadow buffer with the memory mapping address of the active buffer, or switching them within a single clock cycle via a multiplexer control signal. After this operation, the next read request from the ADC compensation data path to the coefficient storage area will automatically point to the original shadow buffer, which has now been loaded with the new coefficients. The original active buffer is then released and can be used to receive the new coefficients generated in the next calibration iteration.

[0076] After the atomic switching operation is completed, the dual-time-domain asynchronous latch synchronization mechanism immediately reports the completion of the coefficient update to the system's state machine. Simultaneously, the request signal `req` and the acknowledgment signal `ack` used for handshaking are reset, the asynchronous FIFO pointer is cleared or reset, and the entire synchronization mechanism returns to an idle state, awaiting the triggering of the next coefficient update decision. At this point, from the perspective of the ADC sampling clock domain, the coefficient update has been completed instantaneously. All subsequent newly sampled data will be immediately compensated using more accurate new calibration coefficients, and the entire switching process does not cause any disturbance or interruption to the continuous output data stream of the ADC, achieving the design goal of background update and seamless switching. Through this rigorous asynchronous synchronization, handshake confirmation, safety time slot determination, and atomic switching process, the metastability risk of cross-clock domain data exchange is eliminated, ensuring the absolute reliability of calibration coefficient updates and the overall stability of the system.

[0077] In some optional examples, the on-chip automatic calibration method of the present invention does not operate in isolation; its execution depth depends on the close collaboration of various functional modules within the robot control chip. The RISC-V core within the chip acts as the main controller, responsible for high-level strategy configuration and global status monitoring of the entire calibration system, rather than directly intervening in the high-speed, real-time data processing pipeline. The RISC-V core implements strategy configuration by reading and writing a set of configuration registers. These configurations include: setting the calibration trigger mode to be periodic, temperature-triggered, or event-triggered; defining threshold parameters for various algorithms, such as the thresholds for kurtosis and skewness in dynamic window self-convergence calibration, the temperature change rate threshold and convergence threshold in temperature adaptive iterative termination determination; and specifying the specific reference level sequence to be generated by the internal reference source and calibration DAC. During calibration execution, the RISC-V core reads the status register through polling or interrupts to monitor the current status of the calibration engine, such as idle, running, convergence complete, temperature freeze, or abnormal alarm, thereby achieving macro-level management and abnormal response of the calibration process. This hardware-software decoupling design allows complex control strategies and parameter adjustments to be flexibly defined by software, while high-real-time signal processing, error calculation, and compensation are automatically completed by dedicated hardware, balancing system flexibility and processing efficiency.

[0078] In some optional examples, to ensure the calibration process does not affect the robot's core control tasks at all, the timing of the calibration method's triggering and execution is carefully designed. The trigger signal is not generated in real-time by the RISC-V core software, but is automatically generated by an on-chip integrated PWM module or high-precision timer module during non-critical control time slots. In robot control systems, such as joint servo motor control, the PWM module generates pulse signals to drive power transistors. These pulse signals have dead times or specific non-switching moments within their cycles, periods where the sampling accuracy of analog quantities is low or not allowed. The on-chip timer module can be programmed to generate a calibration trigger pulse within these non-critical time slots identified by the PWM module or determined by the control timing. This calibration trigger pulse is directly sent to the calibration state machine, initiating or resuming the background calibration process. In this way, the calibration activity is strictly limited to execution within the idle or safe time window of the control task, achieving true parallel and interference-free operation with the main control loop.

[0079] In some optional examples, the calibration process involves the movement of a large amount of data, including reading raw data from the ADC sampling result buffer for statistical analysis and related detection, and writing the calculated new calibration coefficients into the shadow buffer. If all this data movement is done by the RISC-V core via load / store instructions, it will severely consume CPU resources and affect the real-time performance of the main control task. Therefore, this invention fully utilizes the on-chip DMA controller to achieve efficient and low-overhead automatic data movement. The RISC-V core only configures the DMA controller once during the initialization phase, setting the source address, destination address, data block length, and transfer mode. Afterward, when the calibration engine needs a new batch of sampling data, or when a new set of calibration coefficients is calculated, it only needs to send a transfer request to the DMA controller. The DMA controller will then automatically initiate data transfer on the system bus, moving the data directly from the source memory to the destination memory, without the RISC-V core's involvement. This approach frees the CPU from the heavy data copying work, greatly reducing the impact of the calibration process on the system's main control software performance and ensuring the overall real-time performance of the robot control system.

[0080] In some optional examples, the update process of the calibration coefficients in each calibration iteration is not a simple atomic operation, but rather a decoupled process using a multi-stage pipeline structure to improve hardware utilization and system throughput. Specifically, the updates of the offset error vector, the gain error vector, and the nonlinear error vector are treated as relatively independent data processing pipelines. They can be executed in parallel or sequentially depending on data dependencies and resource consumption. For example, the path for calculating the offset error vector based on the reference ground level and the path for calculating the gain error vector based on high and low reference levels can be updated simultaneously because they use different input data. While the calculation of the nonlinear error vector depends on the initial estimates of the offset and gain, its piecewise fitting and interpolation table generation process can also be organized as a pipeline.

[0081] In some optional examples, after being generated by their respective independent update pipelines, the various error vectors are not immediately and dispersedly applied to the compensation data path. A unified synchronization point is established. The updated offset error vector, gain error vector, and nonlinearity error vector are first temporarily stored in their respective intermediate buffers. Subsequently, through the dual-time-domain asynchronous latch synchronization mechanism described in step S5, these new coefficients, which may be generated at different times from different update pipelines, are safely synchronized from the calibration processing clock domain to the ADC sampling clock domain as a complete and consistent set of coefficients. During a safe time slot in the ADC sampling clock domain, this complete new set of coefficients is switched to the active compensation path via atomic operations. This mode of independent updating, unified synchronization, and combined application, on the one hand, improves the utilization efficiency of computing units through pipelined processes, and on the other hand, ensures through the final combination and atomic switching that at any given time, the offset, gain, and nonlinear coefficients used by the ADC compensation path are versions from the same calibration iteration that match each other. This avoids compensation errors introduced by coefficient version mismatches and ensures the overall consistency and final accuracy of multi-level error compensation.

[0082] Example 2: A high-precision on-chip automatic calibration system for robot control chips, integrated within the robot control chip. This system implements the high-precision on-chip automatic calibration method for robot control chips described in Example 1, such as... Figure 7 As shown, it includes a dynamic window self-converging calibration engine, a multi-level error vector quantization compensation unit, a pseudo-random injection bidirectional approximation calibrator, a temperature adaptive iterative termination determination module, and a dual time-domain asynchronous latch synchronization module.

[0083] The system includes a dynamic window self-converging calibration engine, configured to perform statistical distribution analysis on ADC sampling data from multiple calibration reference points provided by an internal reference source, and adaptively adjust the size of the calculation window based on the analysis results to generate an initial error vector containing offset, gain, and nonlinearity information; a multi-level error vector quantization compensation unit, configured to use the initial error vector to sequentially perform static offset compensation, gain compensation, and lookup table-based nonlinear interpolation compensation on the real-time converted code stream of the ADC; and a pseudo-random injection bidirectional approximation calibrator, configured to inject a known pseudo-random sequence into the ADC calibration path after compensation, and perform relevant detections to... The system acquires and fuses the forward and reverse error estimation components to generate a refined error vector. A temperature-adaptive iteration termination decision module is configured to dynamically decide whether to continue, pause, or terminate the calibration iteration based on the temperature value and its rate of change monitored by the on-chip temperature sensor, combined with the update status of the error vector, and to control the updating and switching of calibration coefficients. A dual-time-domain asynchronous latch synchronization module is configured to, after deciding that coefficients need to be updated, securely synchronize the updated calibration coefficients from the calibration processing clock domain to the ADC sampling clock domain through a cross-clock domain synchronous handshake mechanism, and apply them atomically to the multi-level error vector quantization compensation unit.

[0084] In some optional examples, the robot control chip is a system-on-a-chip based on a RISC-V core; and the system is located in the chip’s internal ADC conversion link and works in conjunction with the on-chip PWM / timer module, DMA controller, internal reference source or calibration DAC, on-chip SRAM or lookup table memory, temperature sensor, system clock management unit and RISC-V core.

[0085] Working principle: During the background interval of normal ADC operation, this invention uses an internal reference source to generate known excitation. Through statistical analysis and related detection, and other fully digital, closed-loop feedback methods, it estimates and compensates for various errors in real time and adaptively. This ensures that the calibration process does not interrupt normal data conversion and can quickly and accurately track temperature and process changes. It solves the problems of slow calibration convergence, low accuracy, large resource consumption, inability to adapt to temperature drift and long-term operation, and background calibration interference with normal sampling in the prior art. It achieves high-precision, fast convergence, low overhead, and high adaptability on-chip automatic calibration.

[0086] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0087] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0088] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0089] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0090] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-precision on-chip automatic calibration method for robot control chips, characterized in that, Includes the following steps: After calibration is triggered, statistical distribution analysis is performed on the ADC sampling data of multiple calibration reference points provided by the internal reference source, and the size of the calculation window is adaptively adjusted according to the analysis results to generate an initial error vector containing offset, gain and nonlinearity information. Using the initial error vector, static offset compensation, gain compensation, and nonlinear interpolation compensation based on lookup table are sequentially performed on the real-time converted code stream of the ADC. After compensation is completed, a known pseudo-random sequence is injected into the ADC calibration path. Correlation detection is performed on the ADC output after forward and reverse injection to obtain the corresponding error estimation components. The two are then fused to generate a refined error vector. Based on the temperature value and its rate of change monitored by the on-chip temperature sensor, and combined with the update status of the error vector, the system dynamically decides whether to continue, pause, or terminate the calibration iteration, and controls the update and switching of the calibration coefficients. After the decision requires updating the coefficients, the updated calibration coefficients are safely synchronized from the calibration processing clock domain to the ADC sampling clock domain through a cross-clock domain synchronous handshake mechanism, and then applied to the static offset compensation, gain compensation and nonlinear interpolation compensation in an atomic manner.

2. The high-precision on-chip automatic calibration method for robot control chips according to claim 1, characterized in that, The adaptive adjustment of the calculation window size based on the analysis results includes: Calculate the kurtosis and skewness of the ADC sampled data within the current window; When the kurtosis is greater than the first threshold and the absolute value of the skewness is less than the second threshold, the data distribution is determined to be concentrated, and the window size is reduced accordingly. When the kurtosis is less than the first threshold or the absolute value of the skewness is greater than the third threshold, it is determined that the data distribution is scattered or skewed, and a decision is made to expand the window size.

3. The high-precision on-chip automatic calibration method for robot control chips according to claim 1, characterized in that, The generation of the initial error vector, which includes offset, gain, and nonlinearity information, includes: The offset error vector is obtained by subtracting the average value of the reference ground level from the ideal zero code. The difference between the average sampling values ​​of the high reference level and the low reference level is calculated as the actual code difference. The ratio of the actual code difference to the difference of the ideal code value is calculated to obtain the gain error vector associated with the current temperature. Multiple segmented reference level sample values ​​are acquired, and residuals are formed after removing the effects of offset and gain. Piecewise linear fitting is performed on the residuals to obtain a nonlinear error vector.

4. The high-precision on-chip automatic calibration method for robot control chips according to claim 1, characterized in that, The process of performing correlation detection on the ADC outputs after forward and reverse injection respectively, obtaining the corresponding error estimation components, and fusing the two to generate a refined error vector includes: A pseudo-random sequence with positive polarity is injected into the ADC front end, and the ADC output code is accumulated by sliding window correlation to obtain the positive correlation value; Inject a pseudo-random sequence of opposite polarity into the ADC front end, and perform sliding window correlation accumulation on the ADC output code to obtain the inverse correlation value; Based on the current temperature, gain estimate confidence level, and residual variance, weights are assigned to the positive correlation value and the negative correlation value, and weighted fusion is performed to generate the calibration update value; The current error vector is iteratively calculated using the calibration update amount to generate a refined error vector.

5. The high-precision on-chip automatic calibration method for robot control chips according to claim 1, characterized in that, The dynamic decision-making process for continuing, pausing, or terminating the calibration iteration, based on the temperature value and its rate of change monitored by the on-chip temperature sensor and the update status of the error vector, includes: When the detected temperature change rate exceeds the first preset threshold, the system enters a state to freeze the currently active calibration coefficients and prohibit updates. When the rate of temperature change is lower than the first preset threshold and the temperature tends to stabilize, it is determined whether the change in the error vector during a preset number of consecutive iterations is less than the second preset threshold. If the change is less than the second preset threshold, the calibration is determined to have converged and the iteration is terminated.

6. The high-precision on-chip automatic calibration method for robot control chips according to claim 1, characterized in that, The updated calibration coefficients are securely synchronized from the calibration processing clock domain to the ADC sampling clock domain via a cross-clock domain synchronization handshake mechanism, and then applied atomically to the static offset compensation, gain compensation, and nonlinear interpolation compensation, including: Write the updated and verified calibration coefficients into the shaded buffer located in the calibration processing clock domain; Synchronization from the calibration processing clock domain to the ADC sampling clock domain is achieved through asynchronous FIFO and request-response handshake protocol; In a safe time slot determined by the on-chip timer or system clock management unit that does not affect the normal sampling of the ADC, the coefficients in the shadow buffer are atomically switched to the active buffer of the ADC sampling clock domain.

7. The high-precision on-chip automatic calibration method for robot control chips according to claim 1, characterized in that, The method is executed by the RISC-V core on the chip for strategy configuration and status monitoring, and is triggered by the on-chip PWM / timer module in non-critical control time slots, using the DMA controller to transfer calibration coefficients and sampling data.

8. The high-precision on-chip automatic calibration method for robot control chips according to claim 1, characterized in that, In each calibration iteration, this method employs a multi-stage pipeline structure to decouple the updating and application of calibration coefficients, wherein: The update of the offset error vector is independent of the update of the gain error vector, and both are performed in parallel or sequentially with the update of the nonlinear error vector. The updated error vectors are then synchronized and combined for application in the multi-level error compensation.

9. A high-precision on-chip automatic calibration system for robot control chips, characterized in that, Integrated into the robot control chip, including: The dynamic window self-converging calibration engine is configured to perform statistical distribution analysis on ADC sampled data from multiple calibration reference points provided by an internal reference source, and adaptively adjust the size of the calculation window according to the analysis results to generate an initial error vector containing offset, gain, and nonlinearity information. A multi-level error vector quantization compensation unit is configured to use the initial error vector to sequentially perform static offset compensation, gain compensation, and lookup table-based nonlinear interpolation compensation on the real-time converted code stream of the ADC. A pseudo-random injection bidirectional approximation calibrator is configured to inject a known pseudo-random sequence into the ADC calibration path after the compensation is completed, obtain the forward and reverse error estimation components through relevant detection, and fuse the two to generate a refined error vector. The temperature adaptive iteration termination determination module is configured to dynamically decide whether to continue, pause, or terminate the calibration iteration based on the temperature value and its rate of change monitored by the on-chip temperature sensor, combined with the update status of the error vector, and control the update and switching of the calibration coefficients. The dual-time-domain asynchronous latch synchronization module is configured to, after a decision requires updating the coefficients, securely synchronize the updated calibration coefficients from the calibration processing clock domain to the ADC sampling clock domain through a cross-clock domain synchronization handshake mechanism, and apply them to the multi-level error vector quantization compensation unit in an atomic manner.

10. A high-precision on-chip automatic calibration system for robot control chips according to claim 9, characterized in that, The robot control chip is a system-on-a-chip based on a RISC-V core; and the system is located in the internal ADC conversion link of the chip, and works in conjunction with the on-chip PWM / timer module, DMA controller, internal reference source or calibration DAC, on-chip SRAM or lookup table memory, temperature sensor, system clock management unit and RISC-V core.

Images