Eight-channel successive approximation analog-to-digital converter system, integrated circuit, and electronic device

Abstract

The application relates to an eight-channel successive approximation analog-to-digital converter system, an integrated circuit and an electronic device, wherein the eight-channel successive approximation analog-to-digital converter system comprises a time-interleaved clock distribution module and eight successive approximation analog-to-digital converters; wherein: the time-interleaved clock distribution module is used for generating eight first clock signals with different phases, which are used for controlling the corresponding successive approximation analog-to-digital converters to perform analog-to-digital conversion; the successive approximation analog-to-digital converter comprises four digital-to-analog converters, four comparators and two clock selectors; the clock selector is used for generating a second clock signal according to the digital level signals output by the two comparators in the current conversion period; and the second clock signal is used for activating the operation of the comparators in the next conversion period. The eight successive approximation analog-to-digital converters can be cooperatively operated through the time-interleaved clock distribution module, and the comparators can be cooperatively operated through the clock selector, so that the sampling rate of the successive approximation analog-to-digital converter is improved.

Description

Technical Field

[0001] This application relates to the field of analog and mixed-signal integrated circuit technology, and in particular to an eight-channel successive approximation analog-to-digital converter system, integrated circuits, and electronic devices. Background Technology

[0002] With the rapid development of high-speed communication, radar detection, aerospace and industrial automation, increasingly stringent requirements have been placed on the sampling rate, conversion accuracy, power consumption and chip area of ​​analog-to-digital converters. Successive approximation analog-to-digital converters have become the mainstream choice for medium and high-speed signal acquisition scenarios due to their advantages of simple structure, low power consumption, small area and moderate accuracy.

[0003] However, single-channel successive approximation analog-to-digital converters (ADCs) are inherently limited by their bit-by-bit comparison operating principle, resulting in a significant physical bottleneck in sampling rate. This makes it difficult to meet the ultra-high-speed sampling requirements of 10 GS / s and to adapt to the high-frequency signal acquisition needs of high-end electronic systems. Therefore, related technologies suffer from the problem of low sampling rates in successive approximation ADCs.

[0004] There is currently no effective solution to the problem of low sampling rate in successive approximation analog-to-digital converters in related technologies. Summary of the Invention

[0005] This embodiment provides an eight-channel successive approximation analog-to-digital converter system, integrated circuit, and electronic device to solve the problem of low sampling rate in successive approximation analog-to-digital converters in related technologies.

[0006] In the first aspect, this embodiment provides an eight-channel successive approximation analog-to-digital converter system, including a time-interleaved clock distribution module and eight successive approximation analog-to-digital converters; the input terminals of the successive approximation analog-to-digital converters are connected to the output terminals of the time-interleaved clock distribution module; wherein:

[0007] The time-interleaving clock distribution module is used to generate eight first clock signals with different phases. The first clock signals are used to control the corresponding successive approximation analog-to-digital converters to perform analog-to-digital conversion.

[0008] The successive approximation analog-to-digital converter (ADC) includes four digital-to-analog converters (DACs), four comparators, and two clock selectors. The four DACs are connected one-to-one with the four comparators, and the input of each clock selector is connected to the outputs of the two comparators. The DACs generate corresponding analog voltages according to digital instructions. The comparators compare the analog input voltage to be converted with the analog voltage output by the DACs and output a digital level signal. The clock selectors generate a second clock signal based on the digital level signals output by the two comparators in the current conversion cycle. The second clock signal activates the comparators for the next conversion cycle.

[0009] In some embodiments, the time-interleaved clock distribution module employs two horizontal transmission lines for transmitting a differential global clock signal and a differential input analog signal, respectively, with the differential global clock signal and the differential input analog signal transmitted in the same direction.

[0010] In some embodiments, the time-interleaved clock distribution module further includes eight ring counters; the output of the ring counters is connected to the input of the successive approximation analog-to-digital converter; the ring counters are used to generate the corresponding first clock signal based on the differential global clock signal.

[0011] In some embodiments, two of the four digital-to-analog converters are configured to generate, within the current conversion cycle, two candidate analog voltages corresponding to the next conversion cycle according to the digital instructions.

[0012] In some embodiments, the comparator is also used to output a digital pulse signal; the digital pulse signal is used to control the comparator to perform a reset operation in the next conversion cycle.

[0013] In some embodiments, the digital-to-analog converter is a parallel plate structure composed of a first metal, a second metal, and a third metal.

[0014] In some embodiments, a programmable capacitor is connected to an internal node of the comparator; the programmable capacitor is used to finely compensate for the comparator's offset.

[0015] Secondly, this embodiment provides an integrated circuit including the eight-channel successive approximation analog-to-digital converter system described in the first aspect.

[0016] Thirdly, this embodiment provides a chip including the eight-channel successive approximation analog-to-digital converter system described in the first aspect.

[0017] Fourthly, this embodiment provides an electronic device including the integrated circuit described in the second aspect, and / or the chip described in the third aspect.

[0018] Compared with related technologies, the eight-channel successive approximation analog-to-digital converter (ADC) system provided in this application includes a time-interleaved clock distribution module and eight successive approximation ADCs. The input terminals of the successive approximation ADCs are connected to the output terminals of the time-interleaved clock distribution module. The time-interleaved clock distribution module generates eight first clock signals with different phases, which control the corresponding successive approximation ADCs to perform analog-to-digital conversion. Each successive approximation ADC includes four digital-to-analog converters (DACs), four comparators, and two clock selectors. The four DACs are connected one-to-one with the four comparators, and the input terminal of each clock selector is connected to the output terminals of the two comparators. The DACs generate corresponding analog voltages according to digital instructions. The comparators compare the analog input voltage to be converted with the analog voltage output by the DACs and output digital level signals. The clock selectors generate second clock signals based on the digital level signals output by the two comparators in the current conversion cycle. The second clock signals activate the comparators for the next conversion cycle. It can enable eight successive approximation analog-to-digital converters to work together through a time-interleaved clock distribution module, and enable four comparators to work together through a clock selector, thereby improving the sampling rate of the successive approximation analog-to-digital converters.

[0019] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0021] Figure 1 This is a schematic diagram of the eight-channel successive approximation analog-to-digital converter system of this embodiment;

[0022] Figure 2 This is an internal structural diagram of the successive approximation analog-to-digital converter in this embodiment;

[0023] Figure 3 This is an internal structural diagram of the clock selector in this embodiment;

[0024] Figure 4 This is a structural diagram of the initialization implementation of a successive approximation analog-to-digital converter in this embodiment;

[0025] Figure 5This is a diagram of the internal structure of the ring counter in this embodiment;

[0026] Figure 6 This is a structural diagram of an asynchronous handshake logic implementation in this embodiment;

[0027] Figure 7 This is the equivalent RC network of the digital-to-analog converter in this embodiment;

[0028] Figure 8 This is an internal structure diagram of the comparator in this embodiment;

[0029] Figure 9 This is the chip layout of the eight-channel successive approximation analog-to-digital converter system in this embodiment;

[0030] Figure 10 This is the chip layout of the successive approximation analog-to-digital converter in this embodiment. Detailed Implementation

[0031] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0032] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0033] This embodiment provides an eight-channel successive approximation analog-to-digital converter system. Figure 1This is a schematic diagram of the eight-channel successive approximation analog-to-digital converter system of this embodiment, as shown below. Figure 1 As shown, the system includes a time-interleaved clock distribution module 101 and eight successive approximation analog-to-digital converters 102; the input terminals of the successive approximation analog-to-digital converters 102 are connected to the output terminals of the time-interleaved clock distribution module 101; wherein:

[0034] The time-interleaved clock distribution module 101 is used to generate eight first clock signals with different phases. The first clock signals are used to control the corresponding successive approximation analog-to-digital converter 102 to perform analog-to-digital conversion.

[0035] Specifically, the time-interleaved clock distribution module 101 employs two horizontal transmission lines, one for transmitting the differential global clock signal and the other for transmitting the differential input analog signal. The differential global clock signal and the differential input analog signal are transmitted in the same direction. The time-interleaved clock distribution module 101 also includes eight ring counters; the output of each ring counter is connected to the input of the successive approximation analog-to-digital converter 102. These ring counters are used to generate corresponding first clock signals based on the differential global clock signal. The eight first clock signals are sequentially delayed by 12.5 picoseconds, controlling the corresponding successive approximation analog-to-digital converters 102 to perform analog-to-digital conversion at corresponding times, thereby achieving a total sampling rate of 10 billion samples per second for the eight-channel successive approximation analog-to-digital converter system.

[0036] Figure 2 This is an internal structural diagram of the successive approximation analog-to-digital converter in this embodiment, as shown below. Figure 2 As shown, the successive approximation analog-to-digital converter 102 includes four digital-to-analog converters 201, four comparators 202, and two clock selectors 203. The four digital-to-analog converters 201 are connected one-to-one with the four comparators 202, and the input terminal of each clock selector 203 is connected to the output terminals of the two comparators 202. The digital-to-analog converters 201 are used to generate corresponding analog voltages according to digital instructions. The comparators 202 are used to compare the analog input voltage to be converted with the analog voltage output by the digital-to-analog converters 201 and output digital level signals. The clock selectors 203 are used to generate a second clock signal based on the digital level signals output by the two comparators 202 in the current conversion cycle. The second clock signal is used to activate the comparators 202 in the next conversion cycle.

[0037] Specifically, the successive approximation analog-to-digital converter 102 includes four digital-to-analog converters 201, four comparators 202, and two clock selectors 203. The four digital-to-analog converters 201 are connected one-to-one with the four comparators 202, and the input of each clock selector 203 is connected to the outputs of two comparators 202. The digital-to-analog converters 201 are used to generate corresponding analog voltages according to digital instructions. Two of the four digital-to-analog converters 201 are used to generate two candidate analog voltages corresponding to the next conversion cycle according to digital instructions within the current conversion cycle. The comparators 202 are used to compare the analog input voltage to be converted with the analog voltage output by the digital-to-analog converters 201 and output a digital level signal. The comparators 202 are also used to output a digital pulse signal, which is used to control the comparators 202 to perform a reset operation in the next conversion cycle. The clock selectors 203 are used to generate a second clock signal based on the digital level signals output by the two comparators 202 in the current conversion cycle. This second clock signal is used to activate the comparators 202 in the next conversion cycle.

[0038] Figure 3 This is an internal structural diagram of the clock selector in this embodiment, as shown below. Figure 3 As shown, when the clock signal , Activate the comparators separately , When working, the comparator The analog input voltage to be converted With candidate voltage Perform amplitude comparison and output. and comparator The analog input voltage to be converted With candidate voltage Perform amplitude comparison and output. and ;when For 1, When the value is 0, the clock signal passes through clock selector 203. A high level activates the comparator. Work.

[0039] Figure 4 This is a structural diagram of the initialization implementation of a successive approximation analog-to-digital converter in this embodiment, as shown below. Figure 4 As shown, during the sampling phase, the control signal R is high. At this time, the latch sets the Start signal high, and simultaneously, the internal node P of the clock selector is high, and the clock signal... When the signal is low, all comparators are in a reset state. After the sampling phase ends, the control signal R changes from high to low, while the Start signal remains high. At this time, the Start signal forces node P inside the clock selector low. This node P, after passing through an inverter, generates the comparator. clock signal Activate comparator The first bit-by-bit voltage comparison is initiated, completing the initialization of the successive approximation analog-to-digital converter. This is done on the clock signal. When the first rising edge arrives, the latch detects the trigger event and resets the Start signal to low. Afterward, the Start signal loses control over node P, and the successive approximation analog-to-digital converter enters normal operating mode.

[0040] In this embodiment, the eight-channel successive approximation analog-to-digital converter (ADC) system includes a time-interleaved clock distribution module 101 and eight successive approximation ADCs 102. The input terminals of the successive approximation ADCs 102 are connected to the output terminals of the time-interleaved clock distribution module 101. The time-interleaved clock distribution module 101 generates eight first clock signals with different phases, which control the corresponding successive approximation ADCs 102 to perform analog-to-digital conversion. Each successive approximation ADC 102 includes four digital-to-analog converters 201, four comparators 202, and two clock selectors 201. 03; Four digital-to-analog converters 201 are connected one-to-one with four comparators 202. The input of each clock selector 203 is connected to the output of two comparators 202. The digital-to-analog converters 201 are used to generate corresponding analog voltages according to digital instructions. The comparators 202 are used to compare the analog input voltage to be converted with the analog voltage output by the digital-to-analog converters 201 and output digital level signals. The clock selector 203 is used to generate a second clock signal based on the digital level signals output by the two comparators 202 in the current conversion cycle. The second clock signal is used to activate the comparators 202 in the next conversion cycle. It can enable the eight successive approximation analog-to-digital converters 102 to work together through the time-interleaved clock distribution module 101, and enable the four comparators 202 to work together through the clock selector 203, thereby improving the sampling rate of the successive approximation analog-to-digital converters.

[0041] In some embodiments, the time-interleaved clock distribution module 101 employs two horizontal transmission lines for transmitting a differential global clock signal and a differential input analog signal, respectively, which are transmitted in the same direction.

[0042] Specifically, the time-interleaved clock distribution module 101 employs two horizontal transmission lines, one for transmitting the differential global clock signal and the other for transmitting the differential input analog signal. The differential global clock signal and the differential input analog signal are transmitted in the same direction, ensuring that the transmission path lengths of both signals to the eight successive approximation analog-to-digital converters 102 are completely identical. Therefore, the transmission delay of the differential global clock signal and the differential input analog signal reaching each successive approximation analog-to-digital converter 102 is the same.

[0043] This embodiment avoids timing shifts caused by delay differences, thereby improving the sampling accuracy of the eight-channel successive approximation analog-to-digital converter system.

[0044] In some embodiments, the time-interleaved clock distribution module 101 further includes eight ring counters, the outputs of which are connected to the inputs of the corresponding successive approximation analog-to-digital converters 102. Figure 5 This is an internal structural diagram of the ring counter in this embodiment, as shown below. Figure 5 As shown, this ring counter is used based on the differential global clock signal. Generate the corresponding first clock signal.

[0045] Specifically, such as Figure 5 As shown, this ring counter is controlled by a synchronous latch. Eight latches ( ~ It consists of an inverter and two AND gate logic units. This ring counter is used to operate based on a differential global clock signal. Generate eight different phases of the first clock signal ( ~ The inverter input is connected to a differential global clock signal. The output terminal generates an inverted clock CK; synchronous latch. Data terminal access global synchronization signal The clock input and the clock inputs of the eight latches are all connected to the inverted clock CK; the input of an AND gate is connected to the clock signal of the latch with the odd number of positions. , , , The other AND gate's input is connected to the clock signal of a latch with an even-numbered sequence number. , , , This global synchronization signal It is caused by an external synchronization signal This generates a ring counter that ensures all eight channels enter the same initial state simultaneously, providing a reliable timing reference for the eight-channel successive approximation analog-to-digital converter system. The latch is implemented using clock-controlled complementary metal-oxide-semiconductor (CMOS) logic, with each transistor having a layout size of only 25μm × 6μm. When a 5GHz differential global clock signal is input, the eight latches generate eight clock signals with different phases and a 25% duty cycle. These eight clock signals with different phases and a 25% duty cycle are then converted into eight first clock signals with different phases and a 12.5% ​​duty cycle through two AND gates. In other words, the ring counter generates eight first clock signals with different phases and a 12.5% ​​duty cycle.

[0046] Through this embodiment, a corresponding first clock signal can be generated based on the differential global clock signal, enabling eight successive approximation analog-to-digital converters to work together.

[0047] In some embodiments, two of the four digital-to-analog converters 201 are used to generate two candidate analog voltages corresponding to the next conversion cycle according to digital instructions within the current conversion cycle.

[0048] Specifically, the successive approximation register, based on the determinism of the binary search algorithm, pre-calculates the two possible results of the current conversion cycle, namely the voltage value of the next conversion cycle corresponding to the most significant bit being "1" or "0". Two of the four digital-to-analog converters 201 are used to generate two candidate analog voltages corresponding to the next conversion cycle within the current conversion cycle according to the digital instructions of the successive approximation register. The establishment process of the analog voltage output by the digital-to-analog converter 201 does not require waiting for the pointer register to complete its state update. After the comparator 202 completes the voltage comparison, it generates a trigger pulse signal. One of these trigger pulse signals is directly input to the control terminal of the digital-to-analog converter 201, controlling the digital-to-analog converter 201 to start establishing the candidate analog voltage corresponding to the next conversion cycle. This path bypasses the pointer register and has no storage delay. The other path is simultaneously input to the clock terminal of the pointer register to update its state. This method makes the loop time of the analog circuit in the successive approximation analog-to-digital converter 102 less than the loop time of the digital circuit, satisfying timing safety conditions and eliminating race conditions common in asynchronous systems.

[0049] For example, a digital-to-analog converter operating in the current conversion cycle The output voltage is V REF / 2, the successive approximation register, based on the deterministic nature of the binary search algorithm, pre-calculates the two possible results for the current conversion cycle: the voltage value for the next conversion cycle corresponding to the most significant bit being "1" or "0" is 3V. REF / 4、V REF / 4. Digital-to-Analog Converter and Based on the digital instructions of the successive approximation register, two candidate analog voltages of 3V corresponding to the next conversion cycle are generated respectively. REF / 4、V REF / 4.

[0050] This embodiment eliminates the limitation of the digital-to-analog converter output voltage settling time on the conversion speed, thereby improving the conversion rate of the successive approximation analog-to-digital converter.

[0051] In some embodiments, comparator 202 is also used to output a digital pulse signal, which is used to control comparator 202 to perform a reset operation in the next conversion cycle.

[0052] Specifically, when comparator 202 completes the comparison between the input voltage to be converted and the corresponding output voltage of digital-to-analog converter 201, and outputs the comparison result, comparator 202 outputs a digital pulse signal. This digital pulse signal is directly transmitted to the reset control terminal of comparator 202 in the next adjacent conversion cycle via asynchronous handshake logic. This asynchronous handshake logic also considers whether the output voltage of digital-to-analog converter 201 in the next conversion cycle is stable, ensuring that a reset is only allowed if the output voltage of digital-to-analog converter 201 in the next conversion cycle is stable.

[0053] For example, Figure 6 This is a structural diagram of an asynchronous handshake logic implementation in this embodiment, as shown below. Figure 6 As shown, within the current conversion cycle, the logic circuit uses a binary search algorithm to direct the input to the digital-to-analog converter. Send digital commands, digital-to-analog converter Generate corresponding candidate voltages At this point, only the comparator The work involves converting the analog input voltage to be converted. With candidate voltage Perform amplitude comparison; when the comparator Decision level , After stabilization, the OR gate is triggered to generate a high level. Signal; in the comparator Output decision level Simultaneously, a reset pulse signal is generated through an AND gate, which directly acts on the comparator to be operated in the next conversion cycle. The reset control terminal.

[0054] This embodiment eliminates the conversion gap between the previous and next bit conversions, thereby improving the conversion rate of the successive approximation analog-to-digital converter.

[0055] In some embodiments, the digital-to-analog converter 201 is a parallel plate structure composed of a first metal, a second metal, and a third metal.

[0056] Specifically, the digital-to-analog converter 201 is a parallel plate structure with a size of 1μm × 1μm and a unit capacitance of 0.43fF, composed of a first metal, a second metal, and a third metal. This parallel plate structure minimizes the edge capacitance with the surrounding geometry. This parallel plate structure is beneficial for suppressing kT / C noise. To minimize the area of ​​the digital-to-analog converter 201, the switches of the digital-to-analog converter 201 can be placed below each capacitor, thus ensuring that the switching resistance of each unit capacitor is consistent with the resistance of the reference source. Figure 7 This is the equivalent RC network of the digital-to-analog converter in this embodiment, such as... Figure 7 As shown, the transfer function of the equivalent RC network is expressed as:

[0057] ;

[0058] in This represents the parasitic capacitance of the digital-to-analog converter to ground, where R is the unit switching resistance, C is the unit capacitance, k is the conversion period, and N is the number of bits converted by the digital-to-analog converter. Let be the time constant, expressed as:

[0059] ;

[0060] For example, each 6-bit binary digital-to-analog converter (DAC) employs 64 unit modules in a fully symmetrical structure, minimizing deterministic mismatch. The total area occupied by all DACs is only 8.7% of the total area of ​​a successive approximation DAC. The DAC has an input capacitance of 32.3 fF and a layout size of 8 μm × 24 μm. The total input capacitance of this successive approximation DAC is 130 fF, with 85% coming from the capacitor-based DAC and 15% from the top-plate wiring, comparator gate capacitance, and drain-source capacitance of the sampling switch.

[0061] This embodiment can suppress the kT / C noise of the digital-to-analog converter and improve the conversion accuracy of the successive approximation analog-to-digital converter.

[0062] In some embodiments, a programmable capacitor is connected to an internal node of comparator 202, which is used to finely compensate for the offset of comparator 202.

[0063] Specifically, Figure 8 This is an internal structure diagram of the comparator in this embodiment, as shown below. Figure 8 As shown, , , , For the capacitor used as offset correction, by setting and The width is adjusted so that the input equivalent offset reaches a correctable maximum value. This minimizes the comparator's input capacitance, thereby reducing the comparator's impact on the gain error of the capacitor-to-analog converter and reducing... The system generates kickback noise. Offset compensation employs both fine and coarse compensation methods. Fine compensation is achieved by connecting a programmable capacitor to the internal node of the comparator. This method provides a calibration range of 9mV in 1.5mV steps. While a wider range is better, it significantly reduces circuit speed and increases power consumption. The system also introduces a coarse compensation mechanism, utilizing the unused unit capacitor in the digital-to-analog converter. The bottom plate of this unit capacitor is... and Switching between these modes produces a ±0.5 LSB step. This method not only avoids additional power loss but also significantly reduces the design complexity of the comparator.

[0064] This embodiment can compensate for comparator misalignment and improve the conversion accuracy of successive approximation analog-to-digital converters.

[0065] This embodiment also provides an integrated circuit, which includes any of the above-described embodiments of an eight-channel successive approximation analog-to-digital converter system.

[0066] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated in this embodiment.

[0067] This embodiment also provides a chip, which includes any of the above-described eight-channel successive approximation analog-to-digital converter systems.

[0068] Specifically, Figure 9 This is the chip layout of the eight-channel successive approximation analog-to-digital converter system in this embodiment, such as... Figure 9 As shown, the core layout area of ​​the chip for this eight-channel successive approximation analog-to-digital converter system is 940μm × 150μm, and eight successive approximation analog-to-digital converters (CH1 to CH8) are arranged in this area. Figure 10This is the chip layout of the successive approximation analog-to-digital converter (ADC) in this embodiment. A multiplexer (MUX) is integrated at the center of the bottom of the ADC array to output the digital conversion results of the eight ADCs. A reference voltage decoupling capacitor array (VREF DECAPS) with dimensions of 154μm × 447μm is also configured to stabilize the reference voltage level, absorb current spikes caused by ADC switching, and suppress power supply noise and switching noise interference to the analog circuit. The overall compact and symmetrical layout design achieves high integration while effectively ensuring the sampling accuracy and sampling rate of the eight-channel ADC system.

[0069] This embodiment also provides an electronic device, which includes the above-described embodiment of the integrated circuit and / or the above-described embodiment of the chip.

[0070] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated in this embodiment.

[0071] It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. All other embodiments derived by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0072] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0073] Obviously, the accompanying drawings are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar situations based on these drawings without any creative effort. Furthermore, it is understood that although the work done in this development process may be complex and lengthy, for those skilled in the art, certain design, manufacturing, or production modifications made based on the technical content disclosed in this application are merely conventional technical means and should not be considered as insufficient disclosure of this application.

[0074] The term "embodiment" in this application refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply that it is mutually exclusive with or independent of other embodiments. It will be clearly or implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0075] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. An eight-channel successive approximation analog-to-digital converter system, characterized in that, It includes a time-interleaved clock distribution module and eight successive approximation analog-to-digital converters (ADCs); the input terminals of the successive approximation ADCs are connected to the output terminals of the time-interleaved clock distribution module; wherein: The time-interleaving clock distribution module is used to generate eight first clock signals with different phases. The first clock signals are used to control the corresponding successive approximation analog-to-digital converters to perform analog-to-digital conversion. The successive approximation analog-to-digital converter (ADC) includes four digital-to-analog converters (DACs), four comparators, and two clock selectors. The four DACs are connected one-to-one with the four comparators, and the input of each clock selector is connected to the outputs of the two comparators. The DACs generate corresponding analog voltages according to digital instructions. The comparators compare the analog input voltage to be converted with the analog voltage output by the DACs and output a digital level signal. The clock selectors generate a second clock signal based on the digital level signals output by the two comparators in the current conversion cycle. The second clock signal activates the comparators for the next conversion cycle.

2. The eight-channel successive approximation analog-to-digital converter system according to claim 1, characterized in that, The time-interleaved clock distribution module uses two horizontal transmission lines to transmit the differential global clock signal and the differential input analog signal, respectively. The differential global clock signal and the differential input analog signal are transmitted in the same direction.

3. The eight-channel successive approximation analog-to-digital converter system according to claim 2, characterized in that, The time-interleaved clock distribution module further includes eight ring counters; the output of the ring counters is connected to the input of the successive approximation analog-to-digital converter; the ring counters are used to generate the corresponding first clock signal based on the differential global clock signal.

4. The eight-channel successive approximation analog-to-digital converter system according to claim 1, characterized in that, Two of the four digital-to-analog converters are used to generate, within the current conversion cycle, two candidate analog voltages corresponding to the next conversion cycle according to the digital instructions.

5. The eight-channel successive approximation analog-to-digital converter system according to claim 1, characterized in that, The comparator is also used to output a digital pulse signal; the digital pulse signal is used to control the comparator to perform a reset operation in the next conversion cycle.

6. The eight-channel successive approximation analog-to-digital converter system according to claim 1, characterized in that, The digital-to-analog converter is a parallel plate structure composed of a first metal, a second metal, and a third metal.

7. The eight-channel successive approximation analog-to-digital converter system according to claim 1, characterized in that, A programmable capacitor is connected to an internal node of the comparator; the programmable capacitor is used to finely compensate for the offset of the comparator.

8. An integrated circuit, characterized in that, The system includes the eight-channel successive approximation analog-to-digital converter system as described in any one of claims 1 to 7.

9. A chip, characterized in that, The system includes the eight-channel successive approximation analog-to-digital converter system as described in any one of claims 1 to 7.

10. An electronic device, characterized in that, Includes the integrated circuit of claim 8, and / or the chip of claim 9.

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