A self-interference cancellation system and method based on a multi-tap delay switch matrix

Abstract

This invention discloses a self-interference cancellation system and method based on a multi-tap delay switch matrix, comprising a transmitting device, a receiving device, a reference extraction module, a multi-tap power divider, a multi-channel tap cancellation circuit, a multi-tap combiner, a coupler, an injection coupler, and a digital processing unit. The output of the transmitting device is electrically connected to the input of the reference extraction module. The output of the reference extraction module is connected to multiple parallel tap cancellation circuits through the multi-tap power divider. By employing discrete delay, two-channel orthogonal independent attenuation, dual-channel reverse selection, and orthogonal synthesis in a single tap cancellation circuit, it is suitable for discrete fitting of multipath self-interference on the same platform. The self-interference cancellation system and method based on a multi-tap delay switch matrix provided by this invention are more conducive to distributed configuration and closed-loop optimization in the case of multi-tap parallel operation.

Description

Technical Field

[0001] This invention relates to the field of communication system technology, and in particular to a self-interference cancellation system and method based on a multi-tap delay switch matrix. Background Technology

[0002] In co-platform transceiver systems, full-duplex communication systems, and systems with high-power transmission accompanied by weak signal reception, the transmitted signal can couple into the input path of the receiving device through various pathways, such as insufficient antenna isolation, feeder leakage, coupling of platform structural components, scattering by the housing, and reflection from the external environment, thus creating co-platform self-interference. This self-interference is usually much stronger than the useful received signal and can easily lead to receiver front-end compression, decreased dynamic range of low-noise amplifiers, saturation of analog-to-digital converters, and reduced receiver sensitivity.

[0003] Actual self-interference on the same platform is not composed of a single path, but is usually formed by the superposition of a direct leakage path and multiple reflection and scattering paths. Different paths correspond to different propagation delays, amplitudes, and phases, and therefore can be regarded as self-interference channels with obvious multipath characteristics. If only fixed isolation, fixed attenuation, or single-tap compensation methods are used, it is usually difficult to fully fit the complex multipath self-interference.

[0004] In existing analog domain self-interference cancellation schemes, common single-tap structures typically employ a "delay + phase shift + attenuation" approach to construct the cancellation component. While this type of structure can compensate for a certain time delay component to some extent, it generally suffers from the following shortcomings in scenarios with significant multipath propagation, parallel multi-tap operation, and dynamic parameter updates:

[0005] 1. The ability to discretize and model multipath self-interference channels is limited, which is not conducive to stable fitting of multiple components with different time delays.

[0006] 2: Phase shifters and attenuators are prone to problems such as amplitude-phase coupling, nonlinearity, and insufficient consistency in engineering implementation;

[0007] 3. When optimizing multiple taps together, the parameter search dimension is high and the mutual influence is obvious, which is not conducive to efficient control of the digital processing unit.

[0008] 4. Under wide bandwidth conditions, relying solely on phase shifters to perform phase compensation functions is difficult in terms of parameter calibration and stability.

[0009] Therefore, a tap cancellation structure and system scheme that is more suitable for multi-path self-interference fitting and more conducive to digital closed-loop control and engineering implementation is needed. Summary of the Invention

[0010] To address the aforementioned issues, a self-interference cancellation system and method based on a multi-tap delay switch matrix are provided, aiming to solve the problems existing in the prior art.

[0011] The specific technical solution is as follows:

[0012] A self-interference cancellation system based on a multi-tap delay switching matrix includes a transmitting device, a receiving device, a reference extraction module, a multi-tap power divider, a multi-channel tap cancellation circuit, a multi-tap combiner, a coupler, an injection coupler, and a digital processing unit. The output of the transmitting device is electrically connected to the input of the reference extraction module. The output of the reference extraction module is connected to the parallel multi-channel tap cancellation circuit through the multi-tap power divider. The outputs of the parallel multi-channel tap cancellation circuit are sequentially connected to the receiving device through the multi-tap combiner, the coupler, and the injection coupler. The tap cancellation circuit generates a fitted component with a specific discrete delay and a signed weight from the reference signal output by the transmitting device. Multiple fitted components are superimposed in the multi-tap combiner to form a total cancellation signal. The total cancellation signal is input to the receiving device after passing through the coupler and the injection coupler to cancel self-interference on the same platform in the analog domain.

[0013] The aforementioned self-interference cancellation system based on a multi-tap delay switch matrix also has the following characteristics: the tap cancellation circuit includes a first switch chip, a first delay line group, a second switch chip, a first quadrature power divider, a first digitally controlled attenuator, a second digitally controlled attenuator, a first polarity selection unit, a second polarity selection unit, and a first quadrature combiner. The first switch chip is used to receive the reference signal output by the multi-tap power divider. The output terminal of the first switch chip is electrically connected to the second switch chip through the first delay line group. The output terminal of the second switch chip is electrically connected to the input terminal of the first quadrature power divider. One output terminal of the first quadrature power divider is electrically connected to one input terminal of the first quadrature combiner after passing through the first digitally controlled attenuator and the first polarity selection unit in sequence. The other output terminal of the first quadrature power divider is electrically connected to the other input terminal of the first quadrature combiner after passing through the second digitally controlled attenuator and the second polarity selection unit in sequence. The output terminal of the first quadrature combiner is electrically connected to one input terminal of the multi-tap combiner.

[0014] The aforementioned self-interference cancellation system based on a multi-tap delay switch matrix also has the following characteristics: the first delay line group includes a 0ns delay line, a 2ns delay line, a 4ns delay line, an 8ns delay line, and a delay line with a preset delay value of Nns. Multiple delay lines are connected in parallel to form the first delay line group. The first switch chip and the second switch chip are respectively located at the input and output ends of the first delay line group, and are used to select one of the multiple discrete delay lines so that the reference signal input to that branch obtains the corresponding discrete time delay.

[0015] The self-interference cancellation system based on a multi-tap delay switch matrix described above also has the following features: the first polarity selection unit includes a third switch chip, a first inverter, and a fourth switch chip; the input terminal of the third switch chip is electrically connected to the output terminal of the first numerically controlled attenuator; one output terminal of the third switch chip is electrically connected to one input terminal of the fourth switch chip; the other output terminal of the third switch chip is electrically connected to the other input terminal of the fourth switch chip through the first inverter; and the output terminal of the fourth switch chip is electrically connected to one input terminal of the first quadrature combiner.

[0016] The aforementioned self-interference cancellation system based on a multi-tap delay switch matrix also has the following characteristics: the second polarity selection unit includes a fifth switch chip, a second inverter, and a sixth switch chip. The input terminal of the fifth switch chip is electrically connected to the output terminal of the second digitally controlled attenuator. One output terminal of the fifth switch chip is electrically connected to one input terminal of the sixth switch chip. The other output terminal of the fifth switch chip is electrically connected to the other input terminal of the sixth switch chip through the second inverter. The output terminal of the sixth switch chip is electrically connected to the other input terminal of the first quadrature combiner.

[0017] The self-interference cancellation system based on the multi-tap delay switch matrix described above also has the following feature: it further includes a digital processing unit, which is used to control the delay line selection state, digitally controlled attenuator attenuation value, and polarity selection state of each tap cancellation circuit, and to update the above states and values ​​according to the total cancellation signal sampling information output by the coupler and the residual self-interference information in the input path of the receiving device.

[0018] The self-interference cancellation system based on the multi-tap delay switch matrix described above also has the following feature: the digital processing unit is also connected to the detection node on the input side of the receiving device or in the receiving link, and the connection to the detection node is used to obtain residual self-interference information.

[0019] The self-interference cancellation method based on a multi-tap delay switching matrix, applied to the above system, includes the following steps:

[0020] S1. The reference extraction module extracts a reference signal from the transmission signal output by the transmitting device;

[0021] S2, The multi-tap power divider distributes the reference signal to at least two parallel tap cancellation circuits;

[0022] S3. In each of the tap cancellation circuits, a delay line is selected in the delay line group by the first switch chip and the second switch chip, so that the reference signal of that channel obtains the corresponding discrete time delay.

[0023] S4. The time-delayed reference signal is sent to the quadrature power divider to obtain two mutually orthogonal components.

[0024] S5. Use two digitally controlled attenuators to independently adjust the amplitude of the two orthogonal components;

[0025] S6. Use two polarity selection units to perform pass-through selection or phase-reversal selection on the two orthogonal components respectively to form two signed orthogonal components.

[0026] S7. The two signed orthogonal components are combined into a single tap cancellation signal by an orthogonal combiner, and the tap cancellation signals are combined into a total cancellation signal by a multi-tap combiner.

[0027] S8. The total cancellation signal is injected into the input path of the receiving device via a coupler and an injection coupler to cancel out self-interference on the same platform.

[0028] In summary, the beneficial effects of this scheme are:

[0029] The self-interference cancellation system and method based on a multi-tap delay switch matrix provided by this invention employs a structure of discrete delay, two-path orthogonal independent attenuation, dual-path reverse selection, and orthogonal synthesis in a single tap cancellation circuit, making it suitable for discrete fitting of multipath self-interference on the same platform. The self-interference cancellation system and method based on a multi-tap delay switch matrix provided by this invention are more conducive to distributed configuration and closed-loop optimization in multi-tap parallel scenarios. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the self-interference cancellation system based on a multi-tap delay switch matrix according to the present invention;

[0031] Figure 2 This is a schematic diagram of the tap cancellation circuit of the self-interference cancellation system based on a multi-tap delay switch matrix according to the present invention. Detailed Implementation

[0032] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0033] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0034] The present invention will be further described below with reference to specific embodiments, but these are not intended to limit the scope of the invention.

[0035] Figure 1 This is a schematic diagram of the self-interference cancellation system based on a multi-tap delay switch matrix according to the present invention. Figure 2 This is a schematic diagram of the tap cancellation circuit of the self-interference cancellation system based on a multi-tap delay switch matrix according to the present invention, as shown below. Figure 1 and Figure 2 As shown, the self-interference cancellation system and method based on a multi-tap delay switch matrix provided in this embodiment includes a transmitting device, a receiving device, a reference extraction module, a multi-tap power divider, a multi-channel tap cancellation circuit, a multi-tap combiner, a coupler, an injection coupler, and a digital processing unit. The output terminal of the transmitting device is electrically connected to the input terminal of the reference extraction module. The output terminal of the reference extraction module is connected to the parallel multi-channel tap cancellation circuit through the multi-tap power divider. The output terminals of the parallel multi-channel tap cancellation circuit are sequentially connected to the receiving device through the multi-tap combiner, the coupler, and the injection coupler. The tap cancellation circuit is used to generate a fitting component with a specific discrete delay and a signed weight for the reference signal output by the transmitting device. Multiple fitting components are superimposed in the multi-tap combiner to form a total cancellation signal. The total cancellation signal is input to the receiving device after passing through the coupler and the injection coupler to cancel self-interference on the same platform in the analog domain.

[0036] In the above embodiments, the tap cancellation circuit includes a first switching chip, a first delay line group, a second switching chip, a first quadrature power divider, a first digitally controlled attenuator, a second digitally controlled attenuator, a first polarity selection unit, a second polarity selection unit, and a first quadrature combiner. The first switching chip is used to receive the reference signal output by the multi-tap power divider. The output terminal of the first switching chip is electrically connected to the second switching chip through the first delay line group. The output terminal of the second switching chip is electrically connected to the input terminal of the first quadrature power divider. One output terminal of the first quadrature power divider is electrically connected to one input terminal of the first quadrature combiner after passing through the first digitally controlled attenuator and the first polarity selection unit in sequence. The other output terminal of the first quadrature power divider is electrically connected to the other input terminal of the first quadrature combiner after passing through the second digitally controlled attenuator and the second polarity selection unit in sequence. The output terminal of the first quadrature combiner is electrically connected to one input terminal of the multi-tap combiner.

[0037] In the above embodiments, the first delay line group includes a 0ns delay line, a 2ns delay line, a 4ns delay line, an 8ns delay line, and a delay line with a preset delay value of Nns. Multiple delay lines are connected in parallel to form the first delay line group. The first switch chip and the second switch chip are respectively disposed at the input end and the output end of the first delay line group, and are used to select one of the multiple discrete delay lines so that the reference signal input to the branch obtains the corresponding discrete time delay.

[0038] In the above embodiments, the first polarity selection unit includes a third switching chip, a first inverter, and a fourth switching chip. The input terminal of the third switching chip is electrically connected to the output terminal of the first numerically controlled attenuator. One output terminal of the third switching chip is electrically connected to one input terminal of the fourth switching chip. The other output terminal of the third switching chip is electrically connected to the other input terminal of the fourth switching chip through the first inverter. The output terminal of the fourth switching chip is electrically connected to one input terminal of the first quadrature combiner.

[0039] In the above embodiment, the second polarity selection unit includes a fifth switching chip, a second inverter, and a sixth switching chip. The input terminal of the fifth switching chip is electrically connected to the output terminal of the second digitally controlled attenuator. One output terminal of the fifth switching chip is electrically connected to one input terminal of the sixth switching chip. The other output terminal of the fifth switching chip is electrically connected to the other input terminal of the sixth switching chip through the second inverter. The output terminal of the sixth switching chip is electrically connected to the other input terminal of the first quadrature combiner.

[0040] In the above embodiments, a digital processing unit is also included. The digital processing unit is used to control the delay line selection state, digitally controlled attenuator attenuation value and polarity selection state of each tap cancellation circuit, and to update the above states and values ​​according to the total cancellation signal sampling information output by the coupler and the residual self-interference information in the input path of the receiving device.

[0041] In the above embodiments, the digital processing unit is also connected to the input side of the receiving device or a detection node in the receiving link, and the connection to the detection node is used to obtain residual self-interference information.

[0042] The self-interference cancellation method based on a multi-tap delay switching matrix utilizes the above system to perform the following steps:

[0043] S1. The reference extraction module extracts a reference signal from the transmission signal output by the transmitting device;

[0044] S2, The multi-tap power divider distributes the reference signal to at least two parallel tap cancellation circuits;

[0045] S3. In each of the tap cancellation circuits, a delay line is selected in the delay line group by the first switch chip and the second switch chip, so that the reference signal of that channel obtains the corresponding discrete time delay.

[0046] S4. The time-delayed reference signal is sent to the quadrature power divider to obtain two mutually orthogonal components.

[0047] S5. Use two digitally controlled attenuators to independently adjust the amplitude of the two orthogonal components;

[0048] S6. Use two polarity selection units to perform pass-through selection or phase-reversal selection on the two orthogonal components respectively to form two signed orthogonal components.

[0049] S7. The two signed orthogonal components are combined into a single tap cancellation signal by an orthogonal combiner, and the tap cancellation signals are combined into a total cancellation signal by a multi-tap combiner.

[0050] S8. The total cancellation signal is injected into the input path of the receiving device via a coupler and an injection coupler to cancel out self-interference on the same platform.

[0051] Working principle: When the system is working, the transmitting device outputs a transmission signal. The reference extraction module extracts a coherent reference signal from the transmission signal and sends it to a multi-tap power divider. The multi-tap power divider distributes the reference signal with equal amplitude and phase to a multi-channel tap cancellation circuit. In the first tap cancellation circuit, the digital processing unit controls the first and second switching chips to select one delay line from the first delay line group 42, so that the reference signal obtains a specific discrete time delay (the reference amplitude and phase remain unchanged, but the transmission time is extended). The signal after time delay processing enters the first quadrature power divider and is decomposed into two mutually orthogonal components (the two orthogonal signals have the same amplitude and a phase difference of 90°). The digital processing unit controls the first and second digitally controlled attenuators respectively to independently adjust the amplitude of the two orthogonal components (the two orthogonal signals only have equal amplitude and a phase difference of 90°). The amplitude is changed without changing the phase, and the phase difference remains 90°. Simultaneously, the digital processing unit controls the first and second polarity selection units to select either direct output or inverted output for the two quadrature components (the amplitude of the two output quadrature signals remains unchanged, and the phase remains unchanged or is inverted by 180°). Finally, the two signed quadrature components are combined into a single tapped cancellation signal in the first quadrature combiner. The multi-tap cancellation signals output from the multi-tap cancellation circuit enter the multi-tap combiner and are then vector-superimposed to form a total cancellation signal. The total cancellation signal is sampled by a coupler (the sampled signal amplitude decreases, but the phase remains unchanged, and the signal characteristics remain unchanged), and then sent to an injection coupler. The injection coupler couples the total cancellation signal into the input path of the receiving device, allowing the total cancellation signal to be superimposed and canceled with the actual self-interference on the same platform at the receiving front end in the analog domain.

[0052] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made based on the content of this specification should be included within the protection scope of the present invention.

Claims

1. A self-interference cancellation system based on a multi-tap delay switching matrix, characterized in that, The system includes a transmitting device, a receiving device, a reference extraction module, a multi-tap power divider, a multi-channel tap cancellation circuit, a multi-tap combiner, a coupler, an injection coupler, and a digital processing unit. The output of the transmitting device is electrically connected to the input of the reference extraction module. The output of the reference extraction module is connected to the parallel multi-channel tap cancellation circuit through the multi-tap power divider. The outputs of the parallel multi-channel tap cancellation circuit are sequentially connected to the receiving device through the multi-tap combiner, the coupler, and the injection coupler. The tap cancellation circuit generates a fitted component with a specific discrete delay and a signed weight from the reference signal output by the transmitting device. Multiple fitted components are superimposed in the multi-tap combiner to form a total cancellation signal. The total cancellation signal is input to the receiving device after passing through the coupler and the injection coupler to cancel self-interference on the same platform in the analog domain.

2. The self-interference cancellation system and method based on a multi-tap delay switch matrix according to claim 1, characterized in that: The tap cancellation circuit includes a first switching chip, a first delay line group, a second switching chip, a first quadrature power divider, a first digitally controlled attenuator, a second digitally controlled attenuator, a first polarity selection unit, a second polarity selection unit, and a first quadrature combiner. The first switching chip is used to receive the reference signal output by the multi-tap power divider. The output terminal of the first switching chip is electrically connected to the second switching chip through the first delay line group. The output terminal of the second switching chip is electrically connected to the input terminal of the first quadrature power divider. One output terminal of the first quadrature power divider is electrically connected to one input terminal of the first quadrature combiner after passing through the first digitally controlled attenuator and the first polarity selection unit in sequence. The other output terminal of the first quadrature power divider is electrically connected to the other input terminal of the first quadrature combiner after passing through the second digitally controlled attenuator and the second polarity selection unit in sequence. The output terminal of the first quadrature combiner is electrically connected to one input terminal of the multi-tap combiner.

3. The self-interference cancellation system and method based on a multi-tap delay switch matrix according to claim 2, characterized in that: The first delay line group includes a 0ns delay line, a 2ns delay line, a 4ns delay line, an 8ns delay line, and a delay line with a preset delay value of Nns. Multiple delay lines are connected in parallel to form the first delay line group. The first switch chip and the second switch chip are respectively disposed at the input and output terminals of the first delay line group, and are used to select one of the multiple discrete delay lines so that the reference signal input to that branch obtains the corresponding discrete delay.

4. The self-interference cancellation system and method based on a multi-tap delay switching matrix according to claim 2, characterized in that: The first polarity selection unit includes a third switching chip, a first inverter, and a fourth switching chip. The input terminal of the third switching chip is electrically connected to the output terminal of the first numerically controlled attenuator. One output terminal of the third switching chip is electrically connected to one input terminal of the fourth switching chip. The other output terminal of the third switching chip is electrically connected to the other input terminal of the fourth switching chip through the first inverter. The output terminal of the fourth switching chip is electrically connected to one input terminal of the first quadrature combiner.

5. A self-interference cancellation system based on a multi-tap delay switch matrix according to claim 4, characterized in that: The second polarity selection unit includes a fifth switching chip, a second inverter, and a sixth switching chip. The input terminal of the fifth switching chip is electrically connected to the output terminal of the second digitally controlled attenuator. One output terminal of the fifth switching chip is electrically connected to one input terminal of the sixth switching chip. The other output terminal of the fifth switching chip is electrically connected to the other input terminal of the sixth switching chip through the second inverter. The output terminal of the sixth switching chip is electrically connected to the other input terminal of the first quadrature combiner.

6. The self-interference cancellation system and method based on a multi-tap delay switching matrix according to claim 1, characterized in that: It also includes a digital processing unit, which is used to control the delay line selection state, digitally controlled attenuator attenuation value and polarity selection state of each tap cancellation circuit, and update the above states and values ​​according to the total cancellation signal sampling information output by the coupler and the residual self-interference information in the input path of the receiving device.

7. A self-interference cancellation system and method based on a multi-tap delay switching matrix according to claim 6, characterized in that: The digital processing unit is also connected to the input side of the receiving device or a detection node in the receiving link, and the connection to the detection node is used to obtain residual self-interference information.

8. A self-interference cancellation method based on a multi-tap delay switching matrix, characterized in that: The system described in claim 5 is used to perform the following steps, including: S1. The reference extraction module extracts a reference signal from the transmission signal output by the transmitting device; S2, The multi-tap power divider distributes the reference signal to at least two parallel tap cancellation circuits; S3. In each of the tap cancellation circuits, a delay line is selected in the delay line group by the first switch chip and the second switch chip, so that the reference signal of that channel obtains the corresponding discrete time delay. S4. The time-delayed reference signal is sent to the quadrature power divider to obtain two mutually orthogonal components. S5. Use two digitally controlled attenuators to independently adjust the amplitude of the two orthogonal components; S6. Use two polarity selection units to perform pass-through selection or phase-reversal selection on the two orthogonal components respectively to form two signed orthogonal components. S7. The two signed orthogonal components are combined into a single tap cancellation signal by an orthogonal combiner, and the tap cancellation signals are combined into a total cancellation signal by a multi-tap combiner. S8. The total cancellation signal is injected into the input path of the receiving device via a coupler and an injection coupler to cancel out self-interference on the same platform.

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