Asynchronous preloading frequency hopping method, system and device under limited hardware resources
By pre-generating a frequency hopping configuration set and utilizing the interrupt-driven advance preloading mechanism, the problem of high-speed frequency hopping with a large number of frequency points under limited hardware resources is solved, achieving microsecond-level precision and continuity of frequency hopping timing, which is suitable for resource-constrained embedded systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 湖南智领通信科技有限公司
- Filing Date
- 2026-05-09
- Publication Date
- 2026-08-04
AI Technical Summary
With limited hardware resources, existing technologies struggle to achieve high-speed frequency hopping with a large number of frequency points. Furthermore, the accuracy of software timers is affected by operating system scheduling and system load, leading to inaccurate frequency hopping timing, which can easily cause interrupts or missed frequency hopping timing.
By pre-generating a set of frequency hopping configurations and storing them in memory, and utilizing the pre-loading mechanism of interrupt-driven architecture, combined with the mapping relationship between hardware configuration units and frequency hopping configurations, the target configuration is loaded asynchronously. This avoids time-consuming SPI operations from being executed in the interrupt context, ensuring the continuity and accuracy of frequency hopping timing.
It achieves high-speed frequency hopping that supports a large number of frequency points under limited hardware resources, avoids interruption blocking, ensures microsecond-level accuracy and continuity of frequency hopping timing, improves the reliability and concealment of communication links, and is suitable for resource-constrained embedded real-time systems.
Smart Images
Figure CN122512950A_ABST
Abstract
Description
Technical Field
[0001] Frequency hopping communication is an important anti-environmental disturbance technology in the field of wireless communication. By rapidly hopping the carrier frequency between multiple frequency points, it can effectively avoid narrowband blocking and tracking-type environmental disturbances, and is therefore widely used in secure communication scenarios. Frequency hopping speed is a key indicator of the performance of a frequency hopping system; the higher the hopping speed, the stronger the system's ability to resist tracking-type environmental disturbances, but at the same time, it places higher demands on frequency switching latency and system real-time performance. Currently, the AD9361 RF agile transceiver is widely used in software-defined radio and frequency hopping communication devices due to its wide bandwidth (70MHz to 6GHz) and programmability. This chip provides a function called FastLock, which allows users to pre-store up to eight frequency profiles in hardware registers and achieve nanosecond-level frequency switching through fast recall instructions. When the number of operating frequency points required by the frequency hopping system does not exceed eight, the system can directly write the configurations of these eight frequency points into the hardware registers, achieving high-speed frequency hopping through fast recall, which is relatively simple to implement in engineering.
[0002] However, in practical frequency hopping communication, more frequency points are often required to improve signal concealment and environmental adaptability. When the number of required frequency points exceeds the eight FastLockProfiles supported by the AD9361 hardware, the system must dynamically update the Profile data in the hardware registers via the Serial Peripheral Interface (SPI) bus. SPI bus operations typically take tens of microseconds or even longer and involve kernel sleep waiting. In high-speed frequency hopping scenarios, directly calling the SPI write function in the interrupt handler can lead to system blocking or a severe deterioration in real-time performance, or even missing the next frequency hopping timing due to incomplete SPI operations, causing frequency hopping errors. To address this issue, some existing solutions use software timers to trigger frequency hopping and Profile updates, but the accuracy of software timers is greatly affected by operating system scheduling and system load, making it difficult to meet the stringent requirements of microsecond-level frequency hopping timing. Other solutions utilize FPGA hardware to generate precise frequency hopping timing, but these solutions are usually only applicable to a fixed and limited list of frequency points and cannot flexibly expand the number of frequency points. Summary of the Invention
[0003] Based on this, it is necessary to provide an asynchronous preloading frequency hopping method, system, and device under limited hardware resources that can achieve high-speed frequency hopping with a large number of frequency points, high-precision timing, and no interruption or blocking under limited hardware resources, in order to address the above-mentioned technical problems.
[0004] An asynchronous preloading frequency hopping method under limited hardware resources, the method comprising: Pre-generate a set of frequency hopping configurations and store them in memory; The initial configuration in the frequency hopping configuration set is loaded into the hardware configuration unit of the RF chip, and the mapping relationship between the hardware configuration unit and the frequency hopping configuration is established and initialized. Enable hardware frequency hopping timing and interrupt triggering mechanism; When the frequency hopping time slot interrupt is triggered, the current frequency hopping status is read, the current hardware configuration unit is determined, and the target frequency hopping configuration to be used after a predetermined number of hops is calculated based on the current frequency hopping status. Based on the mapping relationship, determine whether the current hardware configuration unit matches the target frequency hopping configuration; If there is a mismatch, an asynchronous loading process is triggered to load the target frequency hopping configuration into the current hardware configuration unit and update the mapping relationship.
[0005] On the other hand, an asynchronous preload frequency hopping system with limited hardware resources is also provided, including a processing system, programmable logic, and an RF chip, wherein the processing system includes: A configuration pre-generation module is used to pre-generate a set of frequency hopping configurations and store them in memory; An initialization module is used to load the initial configuration from the frequency hopping configuration set into the hardware configuration unit of the RF chip, and to establish and initialize the mapping relationship between the hardware configuration unit and the frequency hopping configuration. The programmable logic includes: a timing control module, used to initiate hardware frequency hopping timing and generate an interrupt signal at the end of each frequency hopping time slot; The processing system further includes an interrupt handling module, which is used to respond to the interrupt signal, read the current frequency hopping state, determine the current hardware configuration unit, and calculate the target frequency hopping configuration to be used after a predetermined number of hops based on the current frequency hopping state. The matching and judgment module is used to determine whether the current hardware configuration unit matches the target frequency hopping configuration based on the mapping relationship; An asynchronous loading module is used to trigger an asynchronous loading process when there is a mismatch, load the target frequency hopping configuration into the current hardware configuration unit and update the mapping relationship.
[0006] On another front, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the asynchronous preload frequency hopping method under limited hardware resources described above.
[0007] Compared with existing technologies, the asynchronous preloading frequency hopping method, system, and device provided by this invention under limited hardware resources have the following beneficial effects: 1. By pre-generating the entire frequency hopping configuration set and utilizing the interrupt-driven advance preloading mechanism, a limited number of hardware configuration units can support a much larger number of frequency hopping points, breaking through hardware resource limitations and enabling high-speed frequency hopping for a large number of frequency points.
[0008] 2. When a mismatch occurs, an asynchronous loading process is triggered, which removes the time-consuming configuration writing operation from the interrupt context and allows the asynchronous loading process to execute it in the process context. This avoids system blocking or real-time performance degradation caused by directly calling the SPI write function in the interrupt handler function, and ensures the continuity of frequency hopping timing and microsecond-level accuracy.
[0009] 3. Because it can support high-speed frequency hopping of a large number of frequency points, the complexity and randomness of the frequency hopping pattern are significantly enhanced, thereby effectively avoiding narrowband blocking and tracking environmental disturbances, and improving the reliability and concealment of the communication link.
[0010] 4. Interrupt handling only performs lightweight read, calculation, and matching operations, without involving time-consuming I / O operations; the asynchronous loading process is executed when the system is idle, with low CPU utilization, making it particularly suitable for resource-constrained embedded real-time systems.
[0011] 5. It is not dependent on a specific RF chip model or a specific asynchronous loading implementation method, and can be flexibly applied to various RF agile transceivers with limited hardware configuration units, with good portability and commercial value. Attached Figure Description
[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention, and those skilled in the art can obtain other related drawings based on these drawings without creative effort.
[0013] Figure 1 This is a flowchart illustrating an asynchronous preloading frequency hopping method under limited hardware resources in one embodiment. Figure 2 This is a timing diagram of hardware configuration unit updates in one embodiment; Figure 3 This is a block diagram of an asynchronous preload frequency hopping system under limited hardware resources in one embodiment; Figure 4 This is an internal structural diagram of a computer device in one embodiment.
[0014] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0016] It is understood that the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.
[0017] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0018] Example 1 like Figure 1 As shown, an asynchronous preloading frequency hopping method under limited hardware resources is provided, including the following steps: Step 201: Pre-generate a set of frequency hopping configurations and store them in memory.
[0019] Step 202: Load the initial configuration from the frequency hopping configuration set into the hardware configuration unit of the RF chip, and establish and initialize the mapping relationship between the hardware configuration unit and the frequency hopping configuration.
[0020] Step 203: Start the hardware frequency hopping timing and interrupt triggering mechanism.
[0021] Step 204: When the frequency hopping time slot interrupt is triggered, read the current frequency hopping status, determine the current hardware configuration unit, and calculate the target frequency hopping configuration to be used after a predetermined number of hops based on the current frequency hopping status.
[0022] Step 205: Determine whether the current hardware configuration unit matches the target frequency hopping configuration based on the mapping relationship.
[0023] Step 206: If there is no match, an asynchronous loading process is triggered to load the target frequency hopping configuration into the current hardware configuration unit and update the mapping relationship.
[0024] In the aforementioned asynchronous preloading frequency hopping method under limited hardware resources, by pre-generating configuration data for all frequency points, and utilizing only a limited number of hardware configuration units provided by the RF chip, combined with hardware interrupt-driven advance preloading and asynchronous writing of process context, the limitation of hardware resources on the number of frequency hopping points is overcome, enabling the system to support any number of frequency hopping points. At the same time, the impact of SPI operation on interrupt real-time performance is avoided, ensuring the precise execution of microsecond-level frequency hopping timing.
[0025] In the specific implementation of step 201, the configuration pre-generation module receives the frequency hopping parameters input by the user. The frequency hopping parameters include the start frequency, end frequency, and step frequency. The configuration pre-generation module generates a complete frequency hopping configuration set based on the above frequency hopping parameters. The frequency hopping configuration set contains FastLock configuration data corresponding to all frequency hopping operating frequencies. FastLock configuration data refers to a complete set of frequency configuration data that conforms to the format of the RF chip hardware register, including the frequency divider coefficients of the frequency synthesizer, filter tuning parameters, etc.
[0026] Preferably, the RF chip uses the AD9361 RF agile transceiver. The configuration pre-generation module calls the corresponding API interface of AD9361 to calculate the FastLock configuration data for each frequency hopping operating frequency point one by one. All FastLock configuration data are stored in the memory space of the processing system in the order of frequency point index, forming a frequency hopping configuration set that can be directly called, without the need to temporarily calculate configuration data during frequency hopping operation.
[0027] This step generates and stores all frequency hopping configuration data in advance, avoiding the real-time configuration calculation overhead during the frequency hopping operation phase, providing stable data support for high-speed frequency hopping, and adapting to the generation requirements of any number of frequency hopping points.
[0028] In the specific implementation of step 202, the hardware configuration unit is a hardware register (FastLock Profile) inside the RF chip used to store FastLock configuration data. The number of hardware configuration units is a fixed finite value M. Preferably, M is 8, corresponding to the 8 hardware FastLock configuration registers built into the AD9361 chip. The initialization module extracts the initial configurations corresponding to the first M consecutive frequency points in the frequency hopping configuration set, and loads each set of initial configurations into the corresponding hardware configuration unit of the RF chip one by one through the serial peripheral interface. The slot number of the hardware configuration unit corresponds one-to-one with the frequency point index of the initial configuration. The initialization module establishes a mapping relationship between the hardware configuration units and the frequency hopping configurations. The mapping relationship is stored in the form of an array hw_profile_map of length M. The subscript of the array hw_profile_map corresponds to the slot number of the hardware configuration unit, and the array element value corresponds to the frequency point index currently loaded by the hardware configuration unit. Preferably, the subscript of the array hw_profile_map is in the range of 0 to 7. During initialization, each element value of the mapping array is assigned the corresponding subscript value to complete the initialization of the mapping relationship.
[0029] This step lays the foundation for the cyclic reuse of hardware configuration units by loading the initial configuration and initializing the mapping relationship, ensuring that the hardware configuration units can be directly called to achieve fast frequency switching during the frequency hopping startup phase.
[0030] In the specific implementation of step 203, before starting the hardware frequency hopping timing and interrupt triggering mechanism, the processing system sends a clear instruction to the programmable logic to clear the frequency hopping sequence number counter hop_count inside the programmable logic, ensuring that the frequency hopping sequence number starts counting from the initial value of 0. Preferably, the processing system and the programmable logic are integrated into a Zynq programmable on-chip system, and the frequency hopping sequence number counter hop_count is integrated into the programmable logic part of the Zynq. The processing system configures the timing control module in the programmable logic to automatically increment the count value of the frequency hopping sequence number counter hop_count at the end of each frequency hopping time slot, and synchronously generates a frequency hopping time slot end interrupt signal, which is transmitted to the interrupt handling module (FPGA interrupt controller) of the processing system. The processing system enables the frequency hopping timing control function and interrupt triggering function of the programmable logic, starts the complete frequency hopping transmission process, and the frequency hopping timing is generated by the programmable logic hardware, ensuring microsecond-level timing accuracy.
[0031] This step eliminates the timing control method of software timers by starting the hardware timing and interrupt triggering mechanism, thereby eliminating the impact of system scheduling and load on frequency hopping accuracy and achieving microsecond-level precise frequency hopping.
[0032] In the specific implementation of step 204, after the frequency hopping time slot interrupt is triggered, the interrupt handling module immediately responds to the interrupt signal and reads the current count value of the frequency hopping sequence counter in the programmable logic. This count value is the core parameter of the current frequency hopping state. The number of hardware configuration units is M, and the future predetermined number is set to a value equal to M. Preferably, M is 8, and the future predetermined number is 8 frequency hopping cycles. The interrupt handling module calculates the remainder when the current value of the frequency hopping sequence counter is divided by M, and uses this remainder as the slot number hw_slot of the current hardware configuration unit. The formula for calculating the slot number hw_slot is: hw_slot = hop_count % M. The current hardware configuration unit corresponding to the slot number hw_slot is being or will be used to transmit the carrier of the current frequency hopping cycle.
[0033] Meanwhile, to achieve high-speed frequency hopping supporting a large number of frequency points under limited hardware resources, this step does not load the frequency point for the next frequency hopping cycle in each interrupt, but instead loads the frequency point to be used in the Mth future frequency hopping cycle. Specifically, the interrupt handler calculates the sum of the current value of the frequency hopping sequence counter and M, and takes the modulo of this sum with the total number of frequency points in the frequency hopping configuration set to obtain the target frequency point index future_idx. The calculation formula for the target frequency point index future_idx is: future_idx = (hop_count + M) % total_freq_count, where total_freq_count is the total number of frequency points in the frequency hopping configuration set. Preferably, the total number of frequency points N in the frequency hopping configuration set is 81. Based on the target frequency point index future_idx, the corresponding target frequency hopping configuration is retrieved from the frequency hopping configuration set in memory to complete the calculation of the target frequency hopping configuration after a predetermined number of hops.
[0034] This step provides a loading time window of up to M-1 hopping cycles for each hardware configuration unit by predicting the frequency index after the future M hops, effectively alleviating the time pressure of SPI write operations.
[0035] In the specific implementation of step 205, the matching judgment module calls the initialized mapping relationship array, using the slot number hw_slot of the current hardware configuration unit as the array index, queries the mapping relationship array hw_profile_map, and obtains the current loaded frequency point index current_idx of the current hardware configuration unit. Preferably, the length of the mapping relationship array is 8, and the array subscripts 0 to 7 correspond to the 8 hardware configuration unit slot numbers hw_slot respectively. The matching judgment module compares the current loaded frequency point index current_idx with the target frequency point index future_idx obtained in step 204. If the two index values are equal, it is determined that the current hardware configuration unit matches the target frequency hopping configuration, and no loading operation is required; if the two index values are not equal, it is determined that the current hardware configuration unit does not match the target frequency hopping configuration, and an asynchronous loading process needs to be triggered.
[0036] This step avoids repeatedly loading configuration data by quickly querying and comparing mapping relationships, reducing the number of operations on serial peripheral interfaces and lowering system resource consumption.
[0037] In the specific implementation of step 206, after determining a mismatch, the interrupt handling module generates a loading task based on the storage address of the target frequency hopping configuration and the slot number hw_slot of the current hardware configuration unit. The loading task includes the target frequency hopping configuration call information and the current hardware configuration unit location information. The interrupt handling module submits the loading task to the work queue submodule. During this process, the interrupt handling module only performs lightweight calculations and task submission operations, and does not perform serial peripheral interface write operations. The work queue submodule retrieves the loading task in the kernel's process context. Preferably, the serial peripheral interface uses the SPI interface. The ad9361_tx_fastlock_load function is called through the SPI interface to write the FastLock configuration data of the target frequency hopping configuration to the corresponding hardware configuration unit register.
[0038] After loading is complete, the asynchronous loading module updates the mapping array, modifying the array element value corresponding to the current hardware configuration unit slot number hw_slot to the target frequency index. After successful loading, hw_profile_map[hw_slot] = future_idx is updated.
[0039] In the asynchronous loading process, a loading task suspension flag is maintained for each hardware configuration unit. Before triggering the asynchronous loading process, the loading task suspension flag corresponding to the current hardware configuration unit is checked. If the loading task suspension flag is already set, the asynchronous loading process is not triggered again. When the asynchronous loading process starts, the loading task suspension flag corresponding to the current hardware configuration unit is set. After the asynchronous loading process completes the configuration writing and updates the mapping relationship, the loading task suspension flag corresponding to the current hardware configuration unit is cleared. If the SPI interface write operation fails, the system records the error information of this loading failure and reports the error information to the upper-layer application of the processing system, and / or reschedules the asynchronous loading process to try to load the target frequency hopping configuration into the current hardware configuration unit again. When loading fails, the current hardware configuration unit retains its original configuration data to ensure that frequency hopping communication is not interrupted. Preferably, the system counts the number of loading failures in real time and provides a system query interface for easy debugging and optimization.
[0040] This step transfers time-consuming SPI interface operations to the process context through an asynchronous loading process, avoiding interrupt context blocking. At the same time, it ensures continuous and stable frequency hopping through an exception handling mechanism, enabling high-speed frequency hopping of a large number of frequency points under limited hardware resources.
[0041] It should be understood that, although this embodiment Figure 1 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0042] Example 2 Based on the asynchronous preloading frequency hopping method with limited hardware resources in Embodiment 1, this embodiment discloses an asynchronous preloading frequency hopping system with limited hardware resources, such as... Figure 3 As shown, the asynchronous preload frequency hopping system under limited hardware resources includes: a processing system (PS), programmable logic (PL), and an RF chip. The processing system includes: A configuration pre-generation module is used to pre-generate a set of frequency hopping configurations and store them in memory.
[0043] An initialization module is used to load the initial configuration from the frequency hopping configuration set into the hardware configuration unit of the RF chip, and to establish and initialize the mapping relationship between the hardware configuration unit and the frequency hopping configuration. The programmable logic includes: a timing control module, used to initiate hardware frequency hopping timing and generate an interrupt signal at the end of each frequency hopping time slot; The processing system further includes an interrupt handling module, which is used to respond to the interrupt signal, read the current frequency hopping state, determine the current hardware configuration unit, and calculate the target frequency hopping configuration to be used after a predetermined number of hops based on the current frequency hopping state. The matching and judgment module is used to determine whether the current hardware configuration unit matches the target frequency hopping configuration based on the mapping relationship; An asynchronous loading module is used to trigger an asynchronous loading process when there is a mismatch, load the target frequency hopping configuration into the current hardware configuration unit and update the mapping relationship.
[0044] In this embodiment, the specific working process and working principle of each module in the processing system, programmable logic, and radio frequency chip are the same as those in Embodiment 1, so they will not be described again in this embodiment. Each unit module can be implemented entirely or partially through software, hardware, or a combination thereof. Each unit module can be embedded in the processor of the computer device in hardware form or independent of it, or it can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above unit modules.
[0045] Example 3 like Figure 4The diagram illustrates a computer device disclosed in this embodiment, including a transmitter, a receiver, a memory, and a processor. The transmitter is used to send instructions and data, the receiver is used to receive instructions and data, the memory is used to store computer execution instructions, and the processor is used to execute the computer execution instructions stored in the memory to implement the method in Embodiment 1 above.
[0046] It is important to note that the aforementioned memory can be either standalone or integrated with the processor. When the memory is set up independently, the terminal device also includes a bus for connecting the memory and the processor.
[0047] Example 4 This embodiment discloses a computer-readable storage medium storing computer-executable instructions. When a processor executes the computer-executable instructions, it implements the method in Embodiment 1 above.
[0048] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0049] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0050] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.
Claims
1. An asynchronous preloading frequency hopping method under limited hardware resources, characterized in that, The method includes: Pre-generate a set of frequency hopping configurations and store them in memory; The initial configuration in the frequency hopping configuration set is loaded into the hardware configuration unit of the RF chip, and the mapping relationship between the hardware configuration unit and the frequency hopping configuration is established and initialized. Enable hardware frequency hopping timing and interrupt triggering mechanism; When the frequency hopping time slot interrupt is triggered, the current frequency hopping status is read, the current hardware configuration unit is determined, and the target frequency hopping configuration to be used after a predetermined number of hops is calculated based on the current frequency hopping status. Based on the mapping relationship, determine whether the current hardware configuration unit matches the target frequency hopping configuration; If there is a mismatch, an asynchronous loading process is triggered to load the target frequency hopping configuration into the current hardware configuration unit and update the mapping relationship.
2. The asynchronous preloading frequency hopping method under limited hardware resources according to claim 1, characterized in that, Before enabling the hardware frequency hopping timing and interrupt triggering mechanism, the following also applies: The processing system clears the frequency hopping sequence counter inside the programmable logic and configures the programmable logic to automatically increment the frequency hopping sequence counter and generate an interrupt signal at the end of each frequency hopping time slot.
3. The asynchronous preloading frequency hopping method under limited hardware resources according to claim 1, characterized in that, Read the current frequency hopping status, determine the current hardware configuration unit, and calculate the target frequency hopping configuration to be used after a predetermined number of hops based on the current frequency hopping status, including: Let the number of the hardware configuration units be M, and the future predetermined number be equal to M; The frequency hopping state includes a frequency hopping sequence number counter maintained by programmable logic, which increments by a count value at the end of each frequency hopping time slot. Read the current value of the frequency hopping number counter, calculate the remainder when the current value is divided by M, and use the remainder as the slot number of the current hardware configuration unit; Read the current value of the frequency hopping number counter, calculate the sum of the current value and M, take the modulo of the sum with the total number of frequency points in the frequency hopping configuration set to obtain the target frequency point index, and retrieve the corresponding target frequency hopping configuration from the memory according to the target frequency point index.
4. The asynchronous preloading frequency hopping method under limited hardware resources according to claim 3, characterized in that, Determining whether the current hardware configuration unit matches the target frequency hopping configuration based on the mapping relationship includes: The mapping relationship is set as an array of length M, where each element of the array is used to record the frequency index currently loaded by the hardware configuration unit of the corresponding slot number; Using the slot number of the current hardware configuration unit as an index, query the array of the mapping relationship to obtain the index of the current loading frequency point; The current loaded frequency index is compared with the target frequency index. If they are equal, it is determined to be a match; otherwise, it is determined to be a mismatch.
5. The asynchronous preloading frequency hopping method under limited hardware resources according to any one of claims 1 to 4, characterized in that, Triggering the asynchronous loading process includes: The interrupt handling submodule of the processing system generates a loading task based on the target frequency hopping configuration and the current hardware configuration unit. The loading task includes the storage address of the target frequency hopping configuration and the slot number of the current hardware configuration unit. The interrupt handling submodule submits the loading task to the work queue submodule; The work queue submodule retrieves the loading task from the kernel's process context, writes the target frequency hopping configuration into the current hardware configuration unit through the serial peripheral interface, and updates the mapping relationship after successful writing.
6. The asynchronous preloading frequency hopping method under limited hardware resources according to claim 5, characterized in that, During the asynchronous loading process, the interrupt handling submodule of the processing system only performs the following operations: Read the current value of the frequency hopping sequence counter, calculate the current hardware configuration unit slot number, calculate the target frequency index, query the mapping relationship to determine whether it matches, and generate and submit the loading task when loading is required; The interrupt handling submodule does not perform the operation of writing frequency configuration data through the serial peripheral interface.
7. The asynchronous preloading frequency hopping method under limited hardware resources according to claim 6, characterized in that, In the asynchronous loading process, if writing the target frequency hopping configuration via the serial peripheral interface fails, the following operations are performed: Record the error message of this failure and report it to the upper-layer application of the processing system; and / or The asynchronous loading process is rescheduled, and the target frequency hopping configuration is re-loaded into the current hardware configuration unit.
8. The asynchronous preloading frequency hopping method under limited hardware resources according to any one of claims 1 to 4, characterized in that, The method further includes: Maintain a loading task suspension flag for each hardware configuration unit; Before triggering the asynchronous loading process, check the loading task suspension flag corresponding to the current hardware configuration unit. If the loading task suspension flag is already set, the asynchronous loading process will not be triggered again. When the asynchronous loading process begins, the loading task suspension flag corresponding to the current hardware configuration unit is set; After the asynchronous loading process completes the configuration writing and updates the mapping relationship, the loading task suspension flag corresponding to the current hardware configuration unit is cleared.
9. An asynchronous preload frequency hopping system with limited hardware resources, comprising a processing system, programmable logic, and a radio frequency chip, characterized in that, The processing system includes: A configuration pre-generation module is used to pre-generate a set of frequency hopping configurations and store them in memory; An initialization module is used to load the initial configuration from the frequency hopping configuration set into the hardware configuration unit of the RF chip, and to establish and initialize the mapping relationship between the hardware configuration unit and the frequency hopping configuration. The programmable logic includes: a timing control module, used to initiate hardware frequency hopping timing and generate an interrupt signal at the end of each frequency hopping time slot; The processing system further includes an interrupt handling module, which is used to respond to the interrupt signal, read the current frequency hopping state, determine the current hardware configuration unit, and calculate the target frequency hopping configuration to be used after a predetermined number of hops based on the current frequency hopping state. The matching and judgment module is used to determine whether the current hardware configuration unit matches the target frequency hopping configuration based on the mapping relationship; An asynchronous loading module is used to trigger an asynchronous loading process when there is a mismatch, load the target frequency hopping configuration into the current hardware configuration unit and update the mapping relationship.
10. A computer device, comprising a memory and a processor, characterized in that, The memory stores a computer program, and when the processor executes the computer program, it implements the steps of the asynchronous preload frequency hopping method under limited hardware resources as described in any one of claims 1 to 8.