Low power optical communication apparatus, method and computing node

Abstract

This application provides a low-power optical communication device, method, and computing node. The device includes: a motherboard and a front panel separately mounted on the motherboard; a graphics processing unit (GPU) chip and a pluggable optical module interface are mounted on the motherboard, and an optical module cage is mounted on the front panel; the GPU chip integrates a digital signal processing unit for processing service data and outputting signal-compensated electrical signals; the pluggable optical module interface is connected to a linearly driven pluggable optical module and is directly electrically connected to the GPU chip via electrical connection lines on the motherboard to transmit electrical signals; the optical module cage is connected to the optical interface of the linearly driven pluggable optical module via optical fiber, for distributing the optical signal generated after photoelectric conversion to other node devices, and / or receiving optical signals returned by other node devices and transmitting them to the linearly driven pluggable optical module via optical fiber. This application reduces the power consumption and cost of the optical module and the entire optical communication system by optimizing the device structure and functional allocation.

Description

Technical Field

[0001] This application relates to the field of optical communication, and in particular to a low-power optical communication device, method and computing node. Background Technology

[0002] With the rapid development of emerging technologies such as cloud computing, artificial intelligence training, and big data analytics, data centers, as the core of information infrastructure, are experiencing a dramatic expansion in their data processing and transmission demands. Against this backdrop, the bandwidth requirements for single nodes are growing exponentially, and high-density rack deployment is gradually becoming the mainstream trend. To meet these demands, high-speed interaction of massive amounts of data is required between computing nodes in data centers. Optical modules, as key components for achieving high-speed optical communication, play a crucial role in signal conversion and transmission bridging between computing nodes and transmission links; their performance directly determines the efficiency and quality of data communication.

[0003] Currently, in short-distance interconnect scenarios within data centers, there are two technical options: traditional copper cabling and fiber optic transmission. Traditional copper cabling transmits electrical signals directly through copper wires, resulting in lower transmission costs. However, due to inherent resistance in copper cables, transmission speed and distance are significantly limited, especially in high-density rack deployments where extensive copper cabling leads to space congestion and further impacts signal quality. Fiber optic transmission, on the other hand, is primarily based on optical fibers and modules. It offers high transmission speeds, no conductor loss, and immunity to electromagnetic interference. In high-density rack deployments, it saves space and meets the demands of large-scale data transmission. During data transmission, the electrical signal output from the computing node enters the digital signal processor of the optical module, where it undergoes specific processing and is converted into a specific optical signal. This signal is then transmitted through the fiber optic cable to other nodes. At the receiving end, the optical signals returned from other nodes are converted back into electrical signals by the optical module, then processed by the internal digital signal processor, and the result is sent back to the computing node, completing the entire data transmission process.

[0004] However, existing optical communication methods suffer from high power consumption and high cost in pursuit of high-speed transmission, both in terms of optical modules and the entire optical communication system. Summary of the Invention

[0005] The low-power optical communication device, method, and computing node provided in this application are intended to solve the problems of high power consumption and high cost of optical modules and the entire optical communication system when pursuing high-speed transmission in existing optical communication methods.

[0006] In a first aspect, embodiments of this application provide a low-power optical communication device, including a motherboard and a front panel separately disposed from the motherboard; the motherboard is equipped with a graphics processor chip and a pluggable optical module interface, and the front panel is equipped with an optical module cage;

[0007] A graphics processing unit chip integrates a digital signal processing unit to process business data and output electrical signals after signal compensation processing.

[0008] A pluggable optical module interface is used to plug in a linearly driven pluggable optical module, and is directly electrically connected to the graphics processor chip through electrical connection lines laid on the motherboard to transmit electrical signals to the linearly driven pluggable optical module.

[0009] The optical module cage is connected to the optical interface of the linearly driven pluggable optical module via optical fiber. It is used to distribute the optical signal generated by the linearly driven pluggable optical module after photoelectric conversion of electrical signals to other node devices, and / or to receive the optical signals returned by other node devices and transmit them to the linearly driven pluggable optical module via optical fiber.

[0010] In one possible implementation, the digital signal processing unit is further configured to perform signal recovery processing on the electrical signals received from the linearly driven pluggable optical module.

[0011] In one possible implementation, the digital signal processing unit includes an equalization circuit and a clock recovery circuit; the signal compensation processing includes pre-emphasis processing, and the signal recovery processing includes clock data recovery processing.

[0012] In one possible implementation, the electrical connection line is a copper line laid out based on near-encapsulated copper cable, used to realize the electrical connection between the graphics processor chip and the pluggable optical module interface within a preset distance.

[0013] In one possible implementation, the pluggable optical module interface is located on the edge area of ​​the motherboard near the front panel; the motherboard is equipped with an upper reinforcing plate and a lower reinforcing plate, which together form a receiving cavity, and the graphics processor chip is fixed inside the receiving cavity.

[0014] In one possible implementation, the optical module cage is equipped with a fiber optic adapter interface for cascading with optical module cages of other node devices via optical fiber to achieve optical communication with other node devices.

[0015] In one possible implementation, there are multiple pluggable optical module interfaces on the motherboard, and each pluggable optical module interface is electrically connected to the graphics processor chip through an independent electrical connection line to realize multi-channel parallel optical communication.

[0016] Secondly, embodiments of this application provide a low-power optical communication method, applicable to the first aspect and / or various possible low-power optical communication devices described above. The method includes: acquiring a first electrical signal generated after a graphics processor chip processes service data; transmitting the first electrical signal to a linearly driven pluggable optical module plugged into a pluggable optical module interface via an electrical connection line; performing photoelectric conversion processing on the first electrical signal based on the linearly driven pluggable optical module to obtain a first optical signal; transmitting the first optical signal to an optical module cage via an optical fiber, and distributing it to other node devices via the optical module cage.

[0017] In one possible implementation, the method further includes: acquiring a second optical signal received by the optical module cage and transmitted through an optical fiber to a linearly driven pluggable optical module; performing photoelectric conversion processing on the second optical signal through the linearly driven pluggable optical module to obtain a second electrical signal; transmitting the second electrical signal to a graphics processor chip through an electrical connection line; and performing signal recovery processing on the second electrical signal based on the digital signal processing unit integrated inside the graphics processor chip to obtain target service data.

[0018] Thirdly, embodiments of this application provide a computing node, including a chassis, and low-power optical communication devices as described in the first aspect above and / or various possible low-power optical communication devices disposed within the chassis.

[0019] The low-power optical communication device, method, and computing node provided in this application embodiment, by mounting a graphics processor chip with an integrated digital signal processing unit on the motherboard and directly electrically connecting the pluggable optical module interface to the graphics processor chip, and cooperating with the optical module cage and fiber optic transmission path mounted on the front panel separately from the motherboard, allows the graphics processor chip to process service data and output signal-compensated electrical signals for direct transmission to the linearly driven pluggable optical module. This reduces the functional complexity and power consumption of the optical module itself, and avoids signal interference and energy loss in complex connections. Simultaneously, leveraging the low power consumption and simple structure of the linearly driven pluggable optical module, along with a reasonable device layout, reduces the cost of the optical module and the overall power consumption, alleviates the heat dissipation pressure under high-density deployment, and makes the cabling within the rack more organized, facilitating module replacement and fault location, and reducing maintenance costs. Furthermore, the direct connection ensures signal transmission quality, and the overall design is adaptable to high-density rack deployment scenarios, thus meeting the needs of large-scale data transmission. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] Figure 1 Schematic diagram of the low-power optical communication device provided in this application Figure 1 ;

[0022] Figure 2 Schematic diagram of the low-power optical communication device provided in this application Figure 2 ;

[0023] Figure 3 A schematic diagram of the motherboard structure in the low-power optical communication device provided in this application;

[0024] Figure 4 Flowchart of the low-power optical communication method provided in this application Figure 1 ;

[0025] Figure 5 Flowchart of the low-power optical communication method provided in this application Figure 2 .

[0026] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0028] It should be understood that the terms “comprising” and “having” and any variations thereof used in this application are intended to cover but not exclude inclusion. For example, a product or device that includes a series of components is not necessarily limited to those components that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0029] As used in this application, the term "module" means any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0030] The following explanations are provided for some of the terms used in the embodiments of this application, so that those skilled in the art can understand them:

[0031] NPC (Near-Port Copper): Near-port copper cable technology brings the optical module directly close to the GPU (Graphics Processing Unit) chip, shortening the copper cable length and reducing signal loss and latency.

[0032] LPO (Linear-drive Pluggable Optics): Linear-drive pluggable optical modules are a type of optical module packaging technology that uses linear direct drive technology and eliminates the need for a DSP (Digital Signal Processor) chip.

[0033] CAGE (Optical Cage): A fiber optic cage used for centralized management of fiber optic connections, enabling the distribution and aggregation of multiple optical signals.

[0034] High-speed optical interconnect technology is widely used in data exchange scenarios between data center servers, artificial intelligence training platforms, edge computing devices, and other high-performance computing nodes. It is particularly suitable for system environments where continuous high-bandwidth, low-latency communication between nodes is required. In such scenarios, computing nodes are equipped with high-performance computing devices to complete various tasks, and multiple nodes need to exchange various data through high-speed links. To meet the requirements of high-density rack deployment, nodes use optical modules to convert electrical signals to optical signals, and then establish communication links with other node devices through optical fibers.

[0035] In existing technologies, high-speed optical communication for computing nodes typically employs a combination of computing chips, motherboard electrical connections, pluggable optical modules, and external fiber optic links. In this approach, the power consumption of the optical module itself increases significantly due to the integrated digital signal processor. When multiple ports are deployed simultaneously, this results in a cumulative increase in overall power consumption and heat dissipation pressure, particularly in high-density servers and training clusters, where module heat further strains the system's thermal budget. Simultaneously, the transmission of high-speed electrical signals between the computing chip and the optical module usually requires a long electrical connection path, which is susceptible to interference, increasing the compensation workload of the internal processor and further enhancing power consumption and complexity. Furthermore, in traditional architectures, optical modules are typically distributed around the motherboard or interface area, resulting in uncentralized external cabling. This leads to congested cabling within the rack, crisscrossing wires, and inconvenient maintenance, impacting port density, network cleanliness, heat dissipation channels, and the efficiency of module replacement and fault location. These problems are even more pronounced in edge devices or compact servers.

[0036] Therefore, while existing technologies can achieve basic optical interconnects and improve transmission rates, the implementation process is hampered by several factors. Firstly, the integration of digital signal processors into optical modules significantly increases power consumption, leading to increased overall power consumption and heat dissipation pressure. Secondly, long electrical connection paths introduce interference, further increasing power consumption and complexity. Thirdly, traditional distributed layouts present numerous wiring and maintenance challenges, resulting in overall high power consumption. All these power-related issues ultimately translate into high costs, making it difficult to meet the demands of practical applications for efficient and low-cost optical interconnects.

[0037] To address the aforementioned issues, this application provides a low-power optical communication device, method, and computing node. The device employs a separate motherboard and front panel architecture. A graphics processing unit (GPU) chip and a pluggable optical module interface are mounted on the motherboard, while an optical module cage is installed on the front panel. This allows the internal electrical signal processing path and the external optical signal distribution path to operate collaboratively. The GPU chip integrates a digital signal processing unit, which outputs a signal-compensated electrical signal during service data processing. This signal is directly transmitted via the motherboard's electrical connection lines to the pluggable linearly driven pluggable optical module. After photoelectric conversion, the optical signal is transmitted via optical fiber to the optical module cage on the front panel for distribution to other nodes or reception of return signals. This device leverages the powerful data processing capabilities of the GPU chip, integrating a digital signal processing unit to offload the optical module's functions, reducing its power consumption and complexity. The simple structure and drive of the linearly driven pluggable optical module allow for lower energy consumption and reduced optical module usage costs while maintaining photoelectric conversion functionality. Furthermore, the pluggable optical module interface, directly connected to the motherboard, reduces signal loss and interference during transmission, further lowering the overall power consumption of the optical communication system.

[0038] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0039] Figure 1 Schematic diagram of the low-power optical communication device provided in this application Figure 1 ,like Figure 1As shown, the low-power optical communication device may include a motherboard and a front panel separately mounted on the motherboard; the motherboard is equipped with a graphics processor chip and a pluggable optical module interface, and the front panel is equipped with an optical module cage; the graphics processor chip integrates a digital signal processing unit for processing service data and outputting signal-compensated electrical signals; the pluggable optical module interface is used to plug in linearly driven pluggable optical modules, and is directly electrically connected to the graphics processor chip through electrical connection lines laid on the motherboard to transmit electrical signals to the linearly driven pluggable optical modules; the optical module cage is connected to the optical interface of the linearly driven pluggable optical modules through optical fibers, and is used to distribute the optical signals generated by the photoelectric conversion of electrical signals by the linearly driven pluggable optical modules to other node devices, and / or receive the optical signals returned by other node devices and transmit them to the linearly driven pluggable optical modules through optical fibers.

[0040] In this embodiment, the motherboard can refer to the basic carrier board used to carry the graphics processor chip, pluggable optical module interface and its electrical connection lines. It is used to form the main path for high-speed electrical signal transmission inside the device and to provide a stable installation and wiring platform for subsequent optical interconnects. In one possible embodiment, the motherboard can be a multilayer rigid printed circuit board, made of FR-4 (Flame Retardant 4) low-loss resin board or high-frequency copper-clad board, such as PCBA (Printed Circuit Board Assembly). It can also be a high-frequency composite dielectric board or a metal-based composite board to adapt to different heat dissipation and electrical performance requirements. Its shape can be a rectangular board, a stepped board or a partially open board, which is convenient for matching with the internal structure of the chassis.

[0041] Furthermore, in one possible implementation, the motherboard can be an open accelerator module (OAM) board designed in accordance with open standards, or a module board including an OAM board; wherein, the graphics processor chip is mounted on the motherboard, and the pluggable optical module interface is also located on the motherboard. Using NPC technology, the motherboard can be directly connected to the linearly driven pluggable optical module (i.e., LPO) through electrical connection lines (i.e., lines based on NPC technology), forming an architecture of OAM direct output NPC and LPO.

[0042] The front panel refers to the interface support structure located at the front of the device, separate from the motherboard. It serves to centrally house the optical module cages and provides an interface for the extraction, insertion, and maintenance of external optical fibers. In one possible embodiment, the front panel can be a metal plate, composite reinforced plate, or engineering plastic panel. It can also be made of aluminum alloy, stainless steel, or shielded coated plate to enhance structural strength and electromagnetic shielding capabilities. Its form can be a flat plate, a plate with reinforcing ribs, or a plate with partially folded edges. The front panel and motherboard can be relatively fixed together via a chassis frame, connecting brackets, or guide pillars. The optical module cages are installed at pre-reserved openings in the front panel, ensuring the insertion and removal direction of the optical modules faces outwards from the chassis, facilitating maintenance and concentrating external cabling in the front-end area. In some examples, it should be noted that a separation distance of several millimeters to tens of millimeters can be maintained between the motherboard and the front panel to meet the requirements of optical module insertion, wiring harness connection, and chassis assembly, while minimizing the length of high-speed electrical connection lines to reduce insertion loss and crosstalk risks.

[0043] Furthermore, a graphics processing unit (GPU) chip can refer to a high-speed computing and signal processing module mounted on the motherboard, which integrates a digital signal processing unit (such as a DSP) and possesses superior parallel computing and data processing capabilities. For example, a GPU or GPU-related products can be used as the graphics processing unit chip. During device operation, it is used to equalize, compensate, restore, or preprocess the output data while performing business computing tasks, thereby forming an electrical signal suitable for subsequent linear drive pluggable optical modules to receive, ensuring the quality and accuracy of the signal in subsequent transmission and conversion processes. In some possible embodiments, the graphics processing unit chip can be packaged in a BGA (Ball Grid Array), LGA (Land Grid Array), or FC-BGA (Flip Chip Ball Grid Array) package carrier, or it can be in flip chip packaging, chip-level packaging, or multi-chip module packaging. Its size can be configured according to the computing power level and pin density, and a short-distance high-speed wiring area is usually reserved on the periphery to reduce transmission loss between the interface and the pluggable optical module. In addition, the graphics processor chip can be arranged in conjunction with the power supply, heat dissipation and high-speed signal lines on the motherboard, so that its output electrical signals can be delivered to the optical module interface in a shorter path, thereby reducing the degradation caused by traditional long-distance electrical connections.

[0044] A pluggable optical module interface refers to an electrical connection interface located on the motherboard for mounting linearly driven pluggable optical modules. It establishes a direct electrical path between the graphics processor chip and the linearly driven pluggable optical module, transmitting processed electrical signals to the optical module for subsequent photoelectric conversion. In some possible embodiments, this interface can be an onboard socket interface, an edge-connected interface, or a cage-type pluggable interface. It can also be configured as a high-speed differential connector, a backplane connector, or a customized optical module housing, depending on different standards. Its shape typically matches the optical module housing and electrical contact layout, and the port spacing can be configured according to the standard optical module dimensions. In one example, the pluggable optical module interface can be located near the front panel or guide opening on the motherboard, so that after the linearly driven pluggable optical module is plugged in, its optical interface can establish a stable connection with the optical module cage on the front panel side via optical fiber.

[0045] Furthermore, a linearly driven pluggable optical module (LPO) refers to a replaceable module plugged into a pluggable optical module interface, used for photoelectric conversion of received electrical signals and relying on linear drive to complete optical transmission and reception. In some possible embodiments, this optical module can adopt a small pluggable package, an eight-channel small pluggable package, or other high-speed pluggable packages, and can also adopt a metal shielded shell, a plastic shielded shell, or a composite thermally conductive shell. It should be noted that its internal components may include modulation drive circuitry, photoelectric conversion devices, and necessary linear amplification units, but a high-power digital signal processor is not necessarily required. Its shape typically forms a detachable fit with the interface slot, and its length, width, and height can be designed according to standardized chassis space to ensure pluggability reliability and unobstructed heat dissipation.

[0046] Electrical connection lines refer to high-speed transmission lines laid on the motherboard, used to directly transmit the signal-compensated electrical signals output by the graphics processor chip to the pluggable optical module interface, minimizing the electrical path between the chip and the module. In one example, the electrical connection line can be formed using differential microstrip lines, striplines, or impedance-controlled trace structures, or using low-loss copper foil, silver-plated conductors, or composite conductors; its line width, spacing, and dielectric thickness can be matched according to the target impedance to reduce reflections, crosstalk, and high-frequency attenuation. Furthermore, the electrical connection line can be arranged in short-path areas on the inner or outer layers of the motherboard, avoiding high-current power supply traces and high-noise devices as much as possible to improve high-speed signal integrity.

[0047] An optical module cage, such as a CAGE, refers to an optical interface support and protection structure mounted on the front panel. It houses and secures externally pluggable fiber optic connectors, while simultaneously distributing the optical signals converted by the linearly driven pluggable optical module to other node devices in an orderly manner, or receiving optical signals returned from other node devices and guiding them back to the linearly driven pluggable optical module. In one example, the optical module cage can be a metal cage, a shielded cage, or a coated alloy cage. It can also employ an aluminum alloy frame, a stainless steel frame, or a conductive coating reinforcement structure. Its opening size is adapted to the fiber optic connector or optical module port, typically set to a clearance fit or a slight interference fit to ensure accurate plugging positioning and improve vibration resistance. Furthermore, the optical module cage can also be equipped with guide slots, limiting steps, and elastic locking structures to achieve rapid positioning, stable locking, and convenient maintenance in high-density cabling environments.

[0048] Furthermore, optical fiber refers to the optical transmission medium connecting the optical interface of the linearly driven pluggable optical module to the optical module cage. It is used to carry optical signals between internal and external nodes after electro-optical conversion. In one possible embodiment, the optical fiber can be single-mode fiber, multi-mode fiber, or a branched fiber bundle. Different cladding materials, sheath materials, and connector end face forms can also be used to adapt to transmission distance and bandwidth requirements. Its end can be equipped with standard fiber optic connectors, customized adapters, or convergent adapters. It should be noted that the length of the optical fiber can be determined according to the spacing between the motherboard and the front panel and the internal wiring path of the chassis, so that it can complete reliable conversion while avoiding excessive bending radius or additional loss due to excessive length.

[0049] For example, in the construction of optical communication networks in large data centers, this low-power optical communication device can be widely used for high-speed data transmission between server nodes. The motherboard uses a high-performance PCBA, installed inside the server chassis, providing a stable operating environment for each component. The graphics processing unit (GPU) chip performs rapid computation and signal processing on the massive amounts of business data processed by the server. Its integrated digital signal processing unit performs compensation, equalization, and restoration on the output signal, ensuring that the output electrical signal has electrical characteristics more suitable for high-speed transmission before entering the subsequent link. Subsequently, the optimized electrical signal is output through the electrical connection lines on the motherboard to the linearly driven pluggable optical module plugged into the pluggable optical module interface. This optical module converts the electrical signal into an optical signal, which is transmitted through optical fiber to the optical module cage on the front panel. The optical module cage then accurately distributes the optical signal to other server nodes. Conversely, the optical signals returned by other server nodes are also converted into electrical signals through the optical module cage and the linearly driven pluggable optical module, and then sent back to the graphics processing unit chip of this server for further processing.

[0050] In this way, this embodiment can build a low-loss, low-latency optical communication path that is easy to deploy at high density within the limited space of the motherboard and front panel, making the device more suitable for scenarios with high requirements for high-speed interconnection and energy consumption control, such as data centers, artificial intelligence training platforms, and edge computing nodes.

[0051] The low-power optical communication device provided in this application embodiment reduces signal transmission loss and interference, lowers the power consumption and complexity of optical modules, and optimizes the device layout, improves space utilization and maintenance efficiency, thereby achieving low-power, low-cost, and high-efficiency optical communication through the powerful processing capabilities of the graphics processor chip and the simple and efficient conversion of the linear drive pluggable optical module.

[0052] Furthermore, in some embodiments, the digital signal processing unit is also used to perform signal recovery processing on the electrical signals received from the linearly driven pluggable optical module.

[0053] In this embodiment, in addition to signal compensation processing, the digital signal processing unit can also perform signal recovery processing on the electrical signals received from the linearly driven pluggable optical module. In other words, its function is to perform distortion correction, timing recovery, and data reconstruction on the received electrical signals in the backhaul link to improve the integrity and reliability of the received data.

[0054] Furthermore, the digital signal processing unit is located inside the graphics processor chip and works collaboratively with the graphics processor chip's business processing logic, the pluggable optical module interface, and the linearly driven pluggable optical module. In the receiving direction, after the linearly driven pluggable optical module completes photoelectric conversion, it transmits the electrical signal to the graphics processor chip through the pluggable optical module interface, where the digital signal processing unit performs recovery processing.

[0055] In some examples, the digital signal processing unit (DSP) can be composed of hardware logic circuits, programmable logic circuits, or application-specific integrated circuit (ASIC) units. Internally, it may contain fixed-function logic, microcode units, or configurable register arrays. Its implementation can be a silicon-based semiconductor chip, an SOI (Silicon-on-Insulator) chip, or an advanced packaged chip structure. Furthermore, the DSP can exist as an internal functional block, occupying a small portion of the graphics processor chip area, and its width should match the data channel width of the receiving path to meet throughput requirements. Its processing delay should ideally meet preset timing constraints with respect to the link clock cycle. During operation, the unit can perform recovery operations such as parsing, filtering, timing alignment, and error correction on the input electrical signal, outputting a target electrical signal or recovered data signal for subsequent calculations. In addition, in some examples, the DSP can also be composed of multiple parallel processing submodules to meet different signal recovery processing needs.

[0056] For example, during device operation, the linearly driven pluggable optical module sends the photoelectric converted electrical signal to the graphics processor chip on the motherboard through the pluggable optical module interface in the receiving direction. The digital signal processing unit inside the graphics processor chip then performs recovery processing on the electrical signal. The recovery processing may include correcting amplitude attenuation and waveform distortion, aligning the sampling clock and data edges, suppressing noise and jitter introduced during link transmission, and, if necessary, combining preset equalization parameters, bit error detection rules, or compensation coefficients obtained through training to complete data reconstruction, thereby restoring the original electrical signal at the receiving end to a stable data signal usable by business logic. Since this recovery processing is directly set inside the graphics processor chip and executed close to the receiving interface, the received electrical signal can complete distortion correction and timing adjustment before entering the subsequent calculation unit. Therefore, it can reduce the additional dependence on cables, interfaces, and external processing modules, shorten the signal dwell time in the board-level path, and reduce the accumulation of insertion loss and crosstalk caused by long-distance electrical connections. Meanwhile, linearly driven pluggable optical modules can maintain a relatively simplified body structure and do not need to undertake too many digital recovery functions, which is conducive to controlling module power consumption and heat generation. After the signal recovery is completed inside the graphics processor chip, the returned data can enter the business processing flow with higher integrity and more stable timing, thereby improving the communication reliability, reception tolerance and overall operation stability of high-speed optical interconnect links in high-density deployment environments.

[0057] The signal recovery processing function of the digital signal processing unit can repair the distortion and other problems caused by signal transmission and conversion, and improve the accuracy and stability of data transmission between nodes. This method reduces power consumption while ensuring the device's adaptability to complex signal environments in different application scenarios.

[0058] Based on the above embodiments, the digital signal processing unit includes an equalization circuit and a clock recovery circuit; the signal compensation processing includes pre-emphasis processing, and the signal recovery processing includes clock data recovery processing.

[0059] In some examples, the equalization circuit can operate in transmitter mode to implement pre-emphasis processing; in other examples, the equalization circuit can also operate in receiver mode to implement receiver equalization processing of the signal as part of the signal recovery process.

[0060] As a further example, the equalization circuit and clock recovery circuit in the digital signal processing unit are both integrated inside the graphics processor chip, corresponding to the signal processing functions on the transmitting and receiving sides, respectively. The equalization circuit is used to compensate for signal amplitude-frequency distortion and optimize the transmission waveform. It pre-emphasizes the signal to be transmitted before the graphics processor chip outputs an electrical signal to the pluggable optical module interface, enhancing the high-frequency components of the high-speed signal in the motherboard electrical connection lines, connectors, and interface contact points, thus offsetting waveform degradation caused by line attenuation and edge passivation. The clock recovery circuit is used to recover clock information from the received data and reconstruct the sampling reference. It performs clock data recovery processing on the return electrical signal from the linearly driven pluggable optical module in the receiving direction, extracting a stable clock reference from the input data stream and completing the sampling phase reconstruction, enabling subsequent processing to make decisions and recover data under correct timing.

[0061] The equalization circuit can be located on the transmit link side inside the graphics processor chip and electrically connected to the output port facing the linearly driven pluggable optical module. The clock recovery circuit can be located on the receive link side inside the graphics processor chip and electrically connected to the input port from the linearly driven pluggable optical module. The two can be implemented separately in the same digital signal processing unit, or they can be configured in multiple independent processing paths according to the number of channels.

[0062] In one possible example, the equalization circuit can be implemented as an analog equalization circuit, a digital equalization circuit, or a mixed-signal equalization circuit, and the clock recovery circuit can be implemented as a phase-locked loop (PLL), a delay-locked loop (DLL), or a phase interpolation recovery circuit. In other examples, the equalization circuit can consist of multiple programmable tap units, gain adjustment units, and output drive units, and the clock recovery circuit can consist of a phase detector unit, a loop filter unit, and an oscillation unit, in order to adapt to the requirements of optical communication systems under different rates and channel loss conditions.

[0063] Furthermore, it should be noted that the circuit size of the equalization circuit and clock recovery circuit can be configured according to the communication rate, the number of channels, and the target bit error rate. The amplitude increase of the pre-emphasis processing is usually matched with the insertion loss of the motherboard electrical connection lines. The locking range of the clock recovery circuit should cover the frequency offset, jitter, and phase drift range that may exist in the received signal. The relevant loop bandwidth and the target jitter tolerance should maintain a design constraint relationship to ensure stable operation in high-bandwidth links.

[0064] In one example, during the signal transmission phase, the equalization circuit inside the graphics processor chip first pre-emphasizes the data to be transmitted based on the attenuation characteristics of the link corresponding to the pluggable optical module interface on the motherboard. This ensures appropriate enhancement of the transmitted waveform during high-speed transitions, maintaining good eye diagram opening and edge integrity when transmitted to the linearly driven pluggable optical module via the electrical connection lines on the motherboard. Subsequently, the linearly driven pluggable optical module performs photoelectric conversion on the electrical signal and outputs it via the optical interface to the optical module cage on the front panel, from where it is transmitted to other node devices via optical fiber. During the signal reception phase, the optical signals returned by other node devices are received by the optical module cage on the front panel and then sent back to the linearly driven pluggable optical module via optical fiber, where they are converted into electrical signals. When the returned electrical signals are returned to the graphics processor chip via the electrical connection lines on the motherboard, the clock recovery circuit performs clock data recovery processing on the input data stream, reconstructing the sampling clock based on the data edge and phase relationship. The recovered clock reference is then used for synchronous sampling and subsequent decision-making of the received data.

[0065] Since the pre-emphasis processing on the transmitting side can compensate for high-frequency loss of the link, and the clock data recovery processing on the receiving side can reduce timing deviation and sampling uncertainty, it can improve the integrity of high-speed electrical signal transmission on the motherboard side and the accuracy of reception recovery. This is conducive to reducing the link bit error rate and improving the communication stability and adaptability of computing nodes in high-speed optical interconnect scenarios, avoiding the data quality degradation caused by canceling the signal processing function of the optical module due to reducing power consumption.

[0066] Furthermore, based on the above embodiments, the electrical connection line is a copper line laid out based on near-encapsulated copper cable, used to realize the electrical connection between the graphics processor chip and the pluggable optical module interface within a preset distance.

[0067] In this embodiment, the electrical connection line is a copper line formed by routing near-package copper cables, used to transmit high-speed electrical signals between the graphics processor chip and the pluggable optical module interface. The function of this line is to send the compensated electrical signal output by the graphics processor chip to the pluggable optical module interface via a shorter path, thereby shortening the signal propagation distance, reducing transmission loss, and improving high-frequency signal integrity. Furthermore, this copper line is routed on the motherboard and can be electrically connected to the high-speed output terminal of the graphics processor chip and the input terminal of the pluggable optical module interface, respectively. Its routing can be arranged near the edge of the graphics processor chip package, the interface pad area, or the edge area of ​​the motherboard to meet the short-distance interconnection requirements within a preset distance and reduce impedance discontinuities caused by cross-area routing.

[0068] In one possible embodiment, the copper trace can be a microstrip line structure, a stripline structure, or a differential pair trace structure. The conductor is preferably high-purity copper, silver-plated copper, or a low-resistivity copper alloy. The insulating medium can be polyimide, epoxy resin substrate, or low-loss copper-clad dielectric to adapt to different speeds and board layer design requirements. It should be noted that the linewidth, line spacing, and interlayer spacing of the copper trace can be set according to the target transmission rate and characteristic impedance. The coupling distance between differential pairs is usually kept constant to control impedance consistency. The total trace length is limited by a preset distance, which can be limited to meet the range of short-distance connections between the chip and the interface to avoid significant insertion loss, reflection, and crosstalk caused by excessively long paths. Furthermore, as part of the motherboard wiring, the copper trace can be formed during manufacturing through etching, lamination, interlayer via connections, or localized thickening of copper foil. Stable electrical connections are established at both ends of the trace with the graphics processor chip and the pluggable optical module interface through pads, solder points, or board-level connection structures.

[0069] For example, while processing business data, the graphics processing unit (GPU) chip outputs a high-speed electrical signal, compensated by the digital signal processing unit (DSP), via a copper line connected to it. Because this line uses a near-package copper cable routing method, the signal can be directly transmitted to the pluggable optical module interface within a preset distance. This allows the linearly driven pluggable optical module at the interface to receive the electrical signal and perform subsequent photoelectric conversion within a shorter electrical path. Since the trace length of the copper line is limited, and impedance can be controlled using differential pairs, microstrip lines, or striplines, the insertion loss, reflection, and crosstalk experienced by the electrical signal during transmission can be reduced accordingly, thus helping to maintain eye diagram quality and clock edge integrity. At the same time, the near-package copper cable routing method makes the electrical connection path between the GPU chip and the pluggable optical module interface more compact, helping to reduce the length of bypass wiring and ineffective wires on the motherboard, and reducing the additional power consumption and signal attenuation caused by long-distance electrical interconnections.

[0070] Based on the above analysis, it can be seen that by limiting the copper lines to short-distance high-speed interconnect paths within a preset distance, this solution can achieve higher quality electrical signal transmission within a limited motherboard space and provide better input conditions for the stable photoelectric conversion of subsequent optical modules. This reduces power consumption while improving the link stability, wiring compactness, and high-speed transmission adaptability of the entire device.

[0071] Furthermore, based on this embodiment, it can be seen that this low-power optical communication device can be widely used for high-speed data transmission between server nodes. In one implementation, the device is based on an architecture of OAM direct output NPC and LPO: the motherboard adopts an OAM board or a module board containing an OAM board, the graphics processor chip is mounted on the motherboard, and is directly connected to the pluggable optical module interface through near-packaged copper cables (corresponding to NPC) laid on the motherboard, and pluggable optical modules (corresponding to LPO) are linearly driven by the pluggable cables. This architecture allows the OAM board to directly output optical signals, eliminating the need for adapter driver chips, repeaters or additional boards required in traditional solutions, thereby constructing an optical communication path with extremely low power consumption, extremely low latency and easy high-density deployment in a limited space. This makes the device more suitable for scenarios with extremely high requirements for high-speed interconnection and energy consumption control, such as data centers, artificial intelligence training platforms, and edge computing nodes.

[0072] In some implementations, the pluggable optical module interface is located on the edge area of ​​the motherboard near the front panel; the motherboard is equipped with an upper reinforcing plate and a lower reinforcing plate, which together form a receiving cavity, and the graphics processor chip is fixed inside the receiving cavity.

[0073] In this embodiment, the pluggable optical module interface is located on the edge area of ​​the motherboard near the front panel. This allows the interface to form a shorter docking path with the optical module cage on the front panel, facilitating the insertion and replacement of the linearly driven pluggable optical module near the front of the chassis and reducing the length of the high-speed electrical connection lines inside the motherboard.

[0074] The upper and lower reinforcing plates that come with the motherboard can be located on opposite upper and lower sides or both sides of the motherboard. They are fixed to a local area of ​​the motherboard by screws, rivets, clips, or press-fitting. After the upper and lower reinforcing plates are combined to form a receiving cavity, the graphics processor chip is installed inside the receiving cavity and is fixed in place. This provides mechanical support and assembly constraints for the area where the chip is located, suppresses the bending deformation of the motherboard during the insertion and removal of optical modules or during operation, and reduces the risk of solder joint fatigue, chip misalignment, or decreased connection reliability caused by concentrated stress, thereby reducing costs.

[0075] Furthermore, the pluggable optical module interface can take the form of a rectangular socket, a high-density cage interface, or a board-edge gold finger interface to accommodate different specifications of linear drive pluggable optical modules. The distance between the pluggable optical module interface and the edge of the motherboard is typically matched to the front panel mounting position to ensure that the optical interface can smoothly mate with the fiber optic connection components after the optical module is inserted.

[0076] The upper and lower reinforcing plates can be metal plates, composite material plates, or high-strength insulating plates. Metal plates can be made of aluminum alloy, stainless steel, or nickel-plated steel; composite material plates can be made of glass fiber reinforced epoxy board, carbon fiber composite board, or sandwich reinforcement board; and insulating plates can be made of high-strength engineering plastics, laminates, or ceramic substrates. The cavity can be rectangular, frame-shaped, or partially open. Its inner wall can be designed with steps, limiting edges, or positioning grooves according to the package outline of the graphics processor chip to achieve positioning constraints on the chip edge and package shape. The graphics processor chip can be mounted in the cavity as a bare die, packaged chip, or die-chip assembly, and forms a stable fit with the motherboard and reinforcing plates through solder balls, thermally conductive adhesive, stud clamping structures, or support pads. The spacing between the upper and lower reinforcing plates should be adapted to the height of the graphics processor chip and its package, allowing sufficient space around the chip to meet assembly tolerances, heat dissipation clearances, and electrical safety clearances. The planar dimensions of the cavity can be slightly larger than the external dimensions of the graphics processor chip to achieve limiting installation without additional compression.

[0077] Because the graphics processor chip is confined and fixed inside the cavity, the structural rigidity near the chip is enhanced. This effectively reduces local deformation of the motherboard when external forces disturb the optical module during insertion and removal, thereby reducing stress concentration in electrical connection lines and the probability of loosening of signal connection points. Combined with the concentrated optical connection method on the front panel side, the transmission path of high-speed electrical signals from the chip to the optical module interface is more compact. Overall, this helps to reduce link loss, improve assembly stability, and enhance maintenance convenience in high-density rack environments, thereby reducing production and maintenance costs.

[0078] Based on the above embodiments, the optical module cage is equipped with a fiber optic adapter interface for cascading with optical module cages of other node devices via optical fiber to achieve optical communication with other node devices.

[0079] The fiber optic adapter interface can be a fiber optic docking port located on the optical module cage, used to enable the plug-in mating of the fiber optic connector and the cage. The function of this fiber optic adapter interface is to stably transmit the optical signal converted by the linearly driven pluggable optical module of this node to the optical module cage of other node devices via optical fiber. It also allows optical signals returned from other node devices to enter this node through the same path, forming a cascaded optical communication channel between nodes, thereby enabling multiple computing nodes to be continuously interconnected according to a predetermined topology.

[0080] In some examples, the fiber optic adapter interface can be located at the front end, side end, or exposed surface of the optical module cage for easy maintenance and operation, and aligned with the optical path channel inside the optical module cage. After the fiber optic plug is inserted, it can be directly axially positioned and coupled to the corresponding adapter structure. The interface can also be connected to the optical module cage of adjacent nodes via patch cords or pre-terminated optical fibers, so that the optical interfaces on the front panel side of each node form a unified cascaded link, which facilitates group cabling and centralized management within the cabinet.

[0081] In one possible embodiment, the fiber optic adapter interface can adopt various structural forms to adapt to single-core, dual-core, or multi-core fiber optic connection scenarios; its housing or base can be made of engineering plastics, metal insert composite materials, or all-metal shielding to take into account insertion and removal life, vibration resistance, and electromagnetic shielding capability; in another possible embodiment, the interface can also be set as a movable adapter, a flip-top adapter, or an integrated splitter interface to adapt to deployment requirements of different densities and different link organization methods.

[0082] It should be noted that in some examples, the external dimensions of the fiber optic adapter interface must match the reserved opening of the optical module cage, the center distance of its ports should correspond to the standard spacing of the optical connectors used, and the internal guide hole diameter, snap-fit ​​groove depth, and ferrule alignment length of the interface should meet the requirements of stable locking and low-loss coupling of the end face after the fiber is plugged in. When cascading connection is used, the fiber length can be determined according to the installation spacing of adjacent nodes inside the cabinet, and the necessary bending radius should be reserved to avoid increased optical loss.

[0083] In practical implementation, after the optical module cage on the front panel receives the output optical signal from the linearly driven pluggable optical module, the optical signal can be guided into the external optical fiber through the fiber optic adapter interface on the cage and further transmitted to the optical module cages of other node devices. In the reverse process, the optical signal returned by other node devices can also enter the optical module cage of this node along the same type of optical fiber, and then be transmitted to the linearly driven pluggable optical module to complete the subsequent transmit and receive conversion. Since the fiber optic adapter interface directly constitutes the cascading connection point between nodes, the optical paths on the front panel of multiple nodes can be organized together in a more centralized manner, thereby reducing the dispersion, crossing, and repeated detours of cables when connecting across nodes, reducing the complexity of internal cabinet wiring, and making the optical path connection relationship clearer. At the same time, the optical signal is transmitted in the form of optical fiber during the cascading process, which can avoid the additional power consumption and link loss caused by converting to electrical signals again between nodes. This allows the entire communication link to meet the needs of multi-node interconnection while having good transmission stability, installation convenience, and maintenance operability.

[0084] Based on the above analysis, it can be seen that by configuring fiber optic adapter interfaces on the optical module cage and enabling it to support cage cascading with other node devices, power consumption and cost can be effectively reduced without significantly increasing the complexity of internal electrical connections of the node, thereby realizing cross-node optical communication and providing a structural foundation for port organization and link expansion in high-density deployment scenarios.

[0085] Based on the above embodiments, in one possible implementation, there are multiple pluggable optical module interfaces on the motherboard, and each pluggable optical module interface is electrically connected to the graphics processor chip through an independent electrical connection line to realize multi-channel parallel optical communication.

[0086] Multiple pluggable optical module interfaces can refer to at least two interface units on the same motherboard for plugging in linearly driven pluggable optical modules. Their purpose is to enable the graphics processing unit (GPU) chip to simultaneously output service electrical signals to multiple optical modules through corresponding electrical connection lines, and to perform electro-optical conversion and optical signal transmission in parallel on multiple channels. In other words, a pluggable optical module interface can be understood as a board-level connection component for supporting optical module plugging and electrical connection. In its assembled state, it forms a detachable electrical connection with the linearly driven pluggable optical module and introduces high-speed electrical signals from the GPU chip into the corresponding optical module. Each interface is electrically connected to the GPU chip through an independent electrical connection line. These independent electrical connection lines are used to carry differential or single-ended signals from different channels, avoiding crosstalk and path coupling caused by multiple channels sharing a path, thus ensuring that each channel operates relatively independently.

[0087] In some examples, the multiple interfaces can be arranged on one edge of the motherboard near the front panel and can be arranged side by side along the edge of the motherboard so that their plug-in direction faces the optical module cage on the front panel side, so that after each optical module completes electrical connection in the board, it can then establish connection with the optical interface on the front panel side and the external optical network through optical fiber.

[0088] In one example, multiple pluggable optical module interfaces can be implemented using array-type sockets, parallel-arranged sockets, or partitioned interface groups. The interface housing can be a metal housing, a plastic housing, or a metal-clad plastic housing. Independent electrical connection lines can use short-pitch microstrip lines, differential copper wires, or flexible interconnects. The graphics processor chip can be a single-chip multi-channel structure or a multi-core collaborative structure. Furthermore, considering the signal synchronization requirements of multi-channel parallel communication, the length, impedance, and delay of each independent electrical connection line can be controlled according to channel matching principles to ensure that the propagation paths corresponding to different interfaces maintain consistent electrical characteristics or are consistent within a preset tolerance range. Additionally, the center-to-center spacing between interfaces can be set according to the optical module's external dimensions, heat dissipation gaps, and insertion / removal operation space to avoid mechanical interference between adjacent modules and reduce heat accumulation.

[0089] Furthermore, in some examples, multiple interfaces can be located on one edge of the motherboard near the front panel, maintaining a preset distance from the graphics processor chip. Independent electrical connection lines are led out from inside the motherboard or near the packaging area to each interface, forming a branched but independent connection relationship. During assembly, each interface corresponds to a linear drive pluggable optical module, and the optical interfaces of each optical module are then connected to the optical module cage on the front panel or an external network via optical fibers, thereby forming a multi-port parallel optical communication system.

[0090] The interface can be configured as a long strip, rectangle, or modular slot. Internally, it may include metal terminals, an insulating base, and a positioning guide structure. The metal terminals can be made of copper alloy, gold-plated copper alloy, or phosphor bronze. The insulating base can be made of polymer engineering plastic, liquid crystal polymer, or high-temperature nylon. Independent electrical connection lines can be routed as multi-layer board traces, near-package copper traces, or flexible board traces, and can be shielded or impedance controlled according to different channel speeds. The number of interfaces can be set to two, four, eight, or more, depending on the number of channels supported by the graphics processor chip. The width and height of a single interface should match the corresponding optical module housing size. The spacing between multiple interfaces should meet the requirements for plug-in / plug-out handle movement space and heat dissipation airflow. The equivalent electrical length of each independent electrical connection line is preferably controlled within a preset range to ensure timing consistency between multiple parallel links.

[0091] For example, while performing business calculations, the graphics processor chip outputs multiple electrical signals, compensated by the digital signal processing unit, to the independent electrical connection lines corresponding to multiple pluggable optical module interfaces on the motherboard. Each independent line sends the signals of different channels to the corresponding linear drive pluggable optical modules, which perform electro-optical conversion to form multiple optical signals. These signals are then transmitted via optical fiber to the optical module cage on the front panel and further distributed to external node devices. In the receiving direction, the multiple optical signals returned by the external node devices are converted into electrical signals by the corresponding optical modules and then returned to the graphics processor chip along their respective independent electrical connection lines, where the processor performs subsequent recovery processing.

[0092] Based on the above analysis, it can be seen that the multiple pluggable optical module interfaces, as board-side connection units on the motherboard, are mainly used to carry the plugging and signal conversion of different service links. Their function is to guide the multiple compensated electrical signals output by the graphics processor chip to the corresponding linearly driven pluggable optical modules, thereby forming multiple parallel optical communication links. This structure ensures that each communication path has an independent electrical connection line, achieving physical isolation at the channel level. This reduces the risks of high-frequency signal reflection, insertion loss, and crosstalk in board-level traces, and can adapt to high-density port expansion requirements.

[0093] Since each pluggable optical module interface has an independent path, multiple channels can work in parallel without occupying the same electrical channel. This allows for increased port density and total link bandwidth without significantly increasing the load on a single path. Simultaneously, it reduces crosstalk and path loss caused by shared lines, lowers power consumption, and makes the load distribution among modules more balanced. Furthermore, because each channel can be expanded independently as needed, the system does not require excessive stacking of single paths when increasing communication capacity. This helps reduce localized heat concentration and electrical compensation pressure, lowers costs, and improves stability and maintenance convenience in high-density deployment scenarios.

[0094] Based on the above embodiments, the low-power optical communication device provided in this application achieves low-power, low-latency, and high-density cabling capabilities for internal optical interconnects of computing nodes through the coordinated optimization of hardware architecture and software processing. Specifically, it adopts a split motherboard-front panel architecture, directly connecting the graphics processor chip and the optical module at close range (i.e., NPC technology), eliminating the built-in DSP of the optical module, and integrating the signal processing function into the graphics processor chip (i.e., LPO technology), and using the optical module cage to centrally distribute or receive optical signals. This device solves the problems of high power consumption, complex cabling, and large signal loss in traditional solutions through simplified hardware structure (reducing redundant DSP modules) and integrated software functions (graphics processor chip with built-in digital signal processing unit), achieving low-power, low-cost, and high-efficiency optical communication, while being compatible with existing optical module interface standards and improving system maintainability.

[0095] Based on the above embodiments, the following describes the low-power optical communication device in detail, taking a low-power optical communication device including a motherboard and a front panel that is separately set from the motherboard. Figure 2 Schematic diagram of the low-power optical communication device provided in this application Figure 2 ,like Figure 2 As shown, the device includes an upper motherboard assembly and a lower, independently arranged front panel assembly, with the two components spatially separated and isolated from each other.

[0096] Among them, combined Figure 1As shown in the corresponding embodiment, the upper motherboard integrates multiple graphics processor chips and corresponding pluggable optical module interfaces. Linear drive pluggable optical modules are plugged into each pluggable optical module interface. The graphics processor chips achieve close-range direct electrical communication with the corresponding pluggable optical modules through the near-packaged copper electrical connection lines arranged inside the motherboard. The graphics processor chip integrates a digital signal processing unit, which can complete the pre-emphasis compensation processing of electrical signals during the data transmission stage. The lower front panel is equipped with a row of optical module cages. The optical ports of each linear drive pluggable optical module extend forward across the split space through independent optical fiber cables and are connected to the optical module cages on the front panel side. The optical module cages integrate multiple optical fiber adapter interfaces, which can receive the optical signals output by the optical modules and split and distribute them to other external node devices in the rack. They can also aggregate the optical signals returned by other nodes and transmit them back to the linear drive pluggable optical modules via optical fibers. After the optical modules complete photoelectric conversion, the converted electrical signals are then transmitted back to the graphics processor chips along the internal electrical connection lines of the motherboard. The digital signal processing unit inside the chip completes the signal recovery processing on the receiving side.

[0097] Furthermore, in Figure 2 Based on the implementation examples, Figure 3 This is a schematic diagram of the motherboard structure in the low-power optical communication device provided in this application, as shown below. Figure 3 As shown, the motherboard is based on a PCBA (Printed Circuit Board Assembly) substrate. A GPU chip (graphics processing unit) and an optical module slot are mounted on the motherboard. The GPU chip is contained within a cavity formed by an upper and lower reinforcing plate. The upper and lower reinforcing plates are fastened to the PCBA board with fasteners. The double-layer reinforcing plate structure provides mechanical reinforcement and protection for the GPU chip. The optical module slot, the pluggable optical module interface described in the previous embodiment, is located on the side of the motherboard near the front end. The GPU chip is directly electrically connected to the adjacent optical module slot via a near-packaged copper electrical connection line located inside the PCBA board, minimizing the length of the electrical traces between them and reducing copper wire transmission loss. This structure improves the assembly stability of the GPU chip on the motherboard through the reinforcing plate structure and achieves close-range direct wiring between the GPU and the linearly driven pluggable optical module through the proximity of the optical module slot. Combined with the integrated digital signal processing unit within the GPU, signal compensation and recovery processing are achieved without the need for the optical module's built-in DSP chip, thus achieving low power consumption for the entire system.

[0098] Based on the above embodiments, in one example, after the electrical signal exits the GPU chip, it is directly connected to the port via copper wire for short-distance transmission between the chip and the pluggable optical module. The data processed by the GPU chip is transmitted to the optical module via lines on the PCBA. The optical module converts the electrical signal into an optical signal, which is then connected to the CAGE via optical fiber, enabling high-speed communication. This short-distance electrical signal transmission design, combined with LPO technology, reduces signal loss and latency during transmission, improving data transmission efficiency. Furthermore, the optical signal is connected to the CAGE via optical fiber. The CAGE then distributes the signal to other node devices in the rack, or receives optical signals from other node devices, converts them into electrical signals via the optical module, and transmits them back to the GPU chip, thus completing data interaction and the entire communication process.

[0099] The low-power optical communication device provided in this embodiment uses a compatible design scheme of NPC and LPO. Compared with traditional electrical signal transmission technology, this design adds optical signal transmission, adopts a pluggable optical module scheme, and removes the DSP chip in the optical module, integrating the relevant functions into the GPU chip on the motherboard. Furthermore, the optical module on the motherboard is directly connected to the optical module cage on the front panel via optical fiber, facilitating high-speed communication with other power-saving devices in the rack. This significantly reduces power consumption and cost, lowers transmission latency, and the pluggable packaging technology also makes the entire device easier to maintain.

[0100] Figure 4 Flowchart of the low-power optical communication method provided in this application Figure 1 ,like Figure 4 As shown, this method is applied to the low-power optical communication device described in the above embodiments, and the method may include:

[0101] S401, Obtain the first electrical signal generated after the graphics processor chip processes business data.

[0102] The graphics processing unit (GPU) chip is the core processing component used to process business data and generate the first and second electrical signals. It not only undertakes tasks such as model training, inference calculation, graphics rendering, and parallel data processing, but also integrates a digital signal processing unit in this embodiment. This allows it to directly generate the first electrical signal suitable for subsequent high-speed link transmission after the business data processing is completed. It should be noted that the first electrical signal can be understood as a high-speed transmission signal carrying the target business content. It is output by the GPU chip in the transmission direction and can also correspond and cooperate with the second electrical signal generated during transmission in the reception direction.

[0103] In practice, the graphics processing unit (GPU) chip can first read the service data to be exchanged from its local cache, high-bandwidth memory, or host-side transmission channel. The service data may include model parameter blocks, activation values, intermediate calculation results, image frame data, storage access requests, or data units required for collaborative processing by other nodes. After completing the corresponding calculations, the chip's internal computing core submits the data to be sent to the on-chip transmission channel. The digital signal processing unit in the transmission channel performs encoding mapping, clock domain shaping, amplitude shaping, pre-emphasis, or equalization parameter adaptation on the data according to the predetermined link rate, modulation format, and interface specifications to generate a first electrical signal that meets the input requirements of the external electrical connection link.

[0104] In one possible embodiment, the first electrical signal can be directly output by the graphics processor chip, that is, the service data is converted into a high-speed differential electrical signal after on-chip serial-to-parallel conversion and transmission buffer scheduling; in another possible embodiment, the graphics processor chip can also first combine the internal digital signal processing unit to perform compensation processing on the transmission code pattern corresponding to the service data, and then output the first electrical signal to enhance the signal integrity in the subsequent short-distance electrical transmission process.

[0105] In this embodiment, a transmission control logic can also be set between the graphics processor chip and the external interface. This transmission control logic is used to determine the transmission timing based on the link initialization result, module presence status, temperature status, and service scheduling priority. When it is detected that the pluggable optical module interface has completed module identification and the link is in an available state, the transmission control logic triggers the graphics processor chip to package the service data to be transmitted into several frames or several physical layer data blocks, and adds synchronization identifiers, frame boundary information, or error detection fields to each data block, so that the first electrical signal can be stably identified when it subsequently enters the linearly driven pluggable optical module.

[0106] Based on the above analysis, it can be seen that by adapting the first electrical signal and moving some of the digital signal processing functions traditionally undertaken by the optical module to the graphics processor chip, not only can the configuration requirements of the complex digital signal processor inside the optical module be reduced, but the transmitting signal can also meet the linear drive transmission conditions on the chip side, thereby reducing module power consumption and simplifying the module structure from a system structure perspective.

[0107] S402. The first electrical signal is transmitted to the linear drive pluggable optical module plugged into the pluggable optical module interface via an electrical connection line.

[0108] In a practical implementation, the first electrical signal output by the graphics processor chip passes through the package solder balls, carrier vias, or near-chip lead-out structures before entering the electrical connection line. This electrical connection line can be located on the motherboard or can be constructed from a combination of high-speed traces on the motherboard and near-package copper cables. Based on the device architecture of the above embodiments, the electrical connection line can be designed as a short-distance, high-speed link between the graphics processor chip and the pluggable optical module interface to minimize insertion loss, return loss, crosstalk, and jitter accumulation caused by transmission length.

[0109] In the actual operation of this step, after the first electrical signal is output from the graphics processor chip, it is transmitted to the pluggable optical module interface via the electrical connection line along a preset differential channel. The pluggable optical module interface provides electrical coupling to the plugged-in linear drive pluggable optical module, allowing the first electrical signal to enter the module's internal transmission front-end from the interface contacts. The module presence detection signal and management bus signal can also simultaneously confirm the type, rate level, temperature status, and power supply status of the linear drive pluggable optical module. When it is confirmed that the module is a compatible linear drive type and its operating parameters meet the transmission requirements, the interface allows the first electrical signal to enter the module's internal transmission drive path.

[0110] In some examples, if link attenuation exceeds the limit or module contact is detected, the internal control logic of the graphics processor chip can adjust the transmission amplitude, retrain the transmission parameters, or postpone the transmission to ensure the stability of the subsequent photoelectric conversion process.

[0111] This step shortens the electrical transmission path from the chip to the optical module in traditional solutions by using short-distance, low-loss electrical connections between the graphics processor chip and the linearly driven pluggable optical module, and forming a stable pluggable electrical connection through the pluggable optical module interface. This reduces signal attenuation and reflection issues caused by long-distance motherboard traces. Since the linearly driven pluggable optical module no longer undertakes a large number of complex digital compensation tasks, its power consumption is reduced, the system thermal load is simultaneously alleviated, and the interface organization under the separate motherboard and front panel architecture is clearer, thus providing a feasible internal interconnection foundation for high-density deployment scenarios.

[0112] S403. Based on a linearly driven pluggable optical module, the first electrical signal is processed by photoelectric conversion to obtain a first optical signal.

[0113] It should be noted that photoelectric conversion processing is the process of converting a first electrical signal into a first optical signal, or a second optical signal into a second electrical signal. In this step, it manifests as an electrical-to-optical conversion in the transmission direction. The linearly driven pluggable optical module, as the core conversion component in this step, receives the first electrical signal from the pluggable optical module interface and directly drives the light-emitting device or modulation device through its internal linear drive circuit to form a first optical signal carrying the same service information. The first optical signal is a high-speed optical communication signal propagating in optical fiber, which is more suitable for long-distance, low-loss transmission between nodes compared to electrical signals. Since this linearly driven pluggable optical module does not include a traditional complex DSP, the internal structure of the module can be concentrated on the transmit driver, receive front-end, clock coordination, bias control, monitoring circuit, and laser or other optical emitting devices, thereby reducing module-level digital processing power consumption.

[0114] In practice, after the first electrical signal enters the linearly driven pluggable optical module through the pluggable optical module interface, it can first pass through an input matching network, a common-mode adjustment circuit, or a limiting protection unit to achieve electrical adaptation with the internal transmit driver stage of the module. Subsequently, the transmit driver stage applies a corresponding drive current or modulation control quantity to the optical emitting device according to the amplitude change of the first electrical signal, so that the optical emitting device outputs a first optical signal corresponding to the first electrical signal.

[0115] In one possible embodiment, the linearly driven pluggable optical module can adopt a linearly driven structure without built-in digital signal processing functions, retaining only the analog or mixed signal transmission link, so that the compensated first electrical signal output by the graphics processor chip can directly participate in dimming; in another possible embodiment, the module can also be equipped with related units for monitoring signal status, such as a transmit power monitoring unit, a bias current monitoring unit, a temperature sensing unit, or a bit error trend monitoring unit. These units do not undertake complex DSP functions, but can help determine the conversion quality of the current first electrical signal to the first optical signal and feed back the status information to the main control side for parameter adjustment.

[0116] To ensure feasibility, the power supply for the linearly driven pluggable optical module in this step can be provided by the pluggable optical module interface. The power management circuit converts the input power into multiple voltage domains required for driving the laser, controlling and monitoring circuits, and managing the interface. Internally, the module can maintain the output stability of the first optical signal through an automatic power control mechanism. When ambient temperature, device aging, or power supply fluctuations cause a shift in transmission power, the monitoring unit detects the corresponding change and corrects the transmission bias to ensure stable transmission of the output first optical signal within the predetermined link budget.

[0117] Furthermore, if multi-channel concurrent transmission is required, the linearly driven pluggable optical module can contain multiple parallel transmission channels, each channel receiving the corresponding first electrical signal component and outputting the first optical signal on multiple channels or multiple parallel fiber cores.

[0118] This step establishes a collaborative mechanism between chip-side digital processing and module-side linear photoelectric conversion by primarily implementing complex signal compensation within the graphics processor chip, while focusing the linearly driven pluggable optical module on direct electro-optical conversion. This collaborative mechanism reduces the power consumption and heat generation introduced by the DSP within traditional pluggable optical modules, and also reduces the structural complexity caused by digital retiming and compensation processing within the module. This makes the module size, heat dissipation burden, and deployment difficulty more suitable for high-density server and training platform scenarios, thereby solving the problems of high power consumption, high heat density, and complex links in existing technologies.

[0119] S404. The first optical signal is transmitted to the optical module cage through the optical fiber and then distributed to other node devices through the optical module cage.

[0120] It should be noted that the optical fiber is the optical transmission medium used to transmit the first optical signal and the second optical signal received by the optical module cage and transmitted to the linearly driven pluggable optical module. It can be single-mode fiber, multimode fiber, parallel multi-core fiber, or other transmission media suitable for high-speed optical interconnection. The optical module cage is a structure used to receive the first optical signal and distribute it to other node devices, or to receive the second optical signal and transmit it back to the linearly driven pluggable optical module via optical fiber. In this scheme, it plays a role in centralizing, guiding, and distributing external optical connections. Other node devices are external nodes that receive the first optical signal distributed by the optical module cage and communicate with this device. They can be server nodes, accelerator card nodes, edge computing nodes, switching equipment interface-side nodes, or other computing devices.

[0121] In practical implementation, after the linearly driven pluggable optical module outputs its first optical signal, the signal is coupled into the corresponding optical fiber via the module's optical interface. This optical fiber extends along a pre-defined cabling channel within the unit to the front panel area and connects with the adapter connection structure in the optical module cage. Since the electrical path on the motherboard has been compressed to a shorter range, the longer signal transmission distance within the unit is handled by the optical fiber, thus avoiding the loss and crosstalk accumulation caused by long-distance cabling of high-speed electrical signals in a limited space. The optical module cage, located at the rear of the front panel, can centrally organize multiple optical fiber interfaces from different linearly driven pluggable optical modules, forming a regularized and maintainable port array externally. This allows maintenance personnel to complete optical link access, plugging, replacement, and labeling management at the front of the cabinet without needing complex cabling operations in the motherboard area.

[0122] Furthermore, after receiving the first optical signal, the optical module cage can guide the first optical signal to the corresponding external optical fiber link through the optical fiber adapter interface, ferrule connection structure or jumper management unit, and distribute it to other node devices.

[0123] In one possible embodiment, the optical module cage can correspond one-to-one with multiple external nodes, with each first optical signal being directly transmitted to the target node device via its corresponding port. In another possible embodiment, the optical module cage can also centrally manage multiple optical fiber paths, enabling the orderly distribution of multiple first optical signals according to port number, service category, or node topology, thereby supporting multi-path parallel optical communication. Upon receiving the first optical signal, other node devices can complete the corresponding photoelectric conversion and service processing at their receiving end. When backhaul is required, they generate a corresponding second optical signal, which is returned to the optical module cage of their own device via its local link. The signal is then transmitted back to the linearly driven pluggable optical module via optical fiber, converted into a second electrical signal, and sent back to the digital signal processing unit inside the graphics processor chip for signal recovery processing, ultimately restoring the target service data. The signal recovery processing involves restoring and correcting the second electrical signal, eliminating transmission errors, and restoring the target service data. This process is completed by the digital signal processing unit inside the graphics processor chip, thus forming a complete bidirectional communication closed loop.

[0124] This step centralizes the external optical signal distribution function in the optical module cage on the front panel, using optical fiber to complete medium-to-long-distance transmission and inter-node interconnection within the device, thus separating the electrical path from the optical path in spatial layout. This not only improves the wiring crossover, maintenance inconvenience, and heat dissipation obstruction problems caused by the traditional solution of optical modules being scattered around the motherboard, but also makes the front panel interface organization more centralized and orderly, improving port density and maintenance efficiency. At the same time, with optical fiber undertaking the main medium-to-long-distance transmission within the device, electrical link loss can be further reduced and overall transmission stability can be improved, thereby forming a high-speed optical communication path that balances low power consumption, low loss, low cost, and high reliability in high-density deployment scenarios such as data center servers, artificial intelligence training platforms, and edge computing devices.

[0125] In this embodiment, by moving some of the digital signal processing capabilities traditionally handled by the optical module to the graphics processor chip, and employing a structure that combines short-distance electrical connections on the motherboard side with centralized optical connections on the front panel side, high-speed service data in the transmission direction can reach the linearly driven pluggable optical module with a shorter electrical path, and then be converted into a first optical signal for external distribution. This reduces the module power consumption and thermal burden caused by the DSP inside the pluggable optical module, shortens the high-speed electrical transmission distance between the computing chip and the optical module, suppresses insertion loss, reflection, crosstalk, and noise accumulation, and improves the centralized wiring capability and maintenance convenience of the front panel ports. This approach can reduce the power consumption and cost of the computing node, achieve lower latency, and make the computing node easier to maintain.

[0126] Furthermore, based on Figure 4 Example, Figure 5 Flowchart of the low-power optical communication method provided in this application Figure 2 ,like Figure 5 As shown, the method may further include:

[0127] S501. Acquire the second optical signal received by the optical module cage and transmitted through the optical fiber to the linearly driven pluggable optical module.

[0128] S502. The second optical signal is photoelectrically converted by a linearly driven pluggable optical module to obtain a second electrical signal.

[0129] S503 transmits the second electrical signal to the graphics processor chip via an electrical connection line.

[0130] S504, based on the digital signal processing unit integrated within the graphics processor chip, performs signal recovery processing on the second electrical signal to obtain the target service data.

[0131] Understandably, the second optical signal is the return optical signal received by the optical module cage and transmitted via optical fiber to the linearly driven pluggable optical module, used to carry data returned by external nodes; the second electrical signal is the electrical domain signal output by the linearly driven pluggable optical module after photoelectric conversion of the second optical signal, used to continue transmission to the graphics processor chip. The target service data is the valid data content obtained after recovery and error correction, used by the graphics processor chip to continue executing subsequent calculation tasks.

[0132] In practical implementation, after the optical module cage receives the second optical signal returned by the external node device, it introduces the second optical signal into the linearly driven pluggable optical module plugged into the pluggable optical module interface via the connected optical fiber. The optical receiving device in this module can convert optical energy into corresponding current or voltage signals, and after linear amplification and shaping, form a second electrical signal, which is then sent to the graphics processor chip through the electrical connection lines on the motherboard. The electrical connection lines can use near-package copper cables or low dielectric constant copper cables to reduce transmission loss and crosstalk. In practical applications, other models can also be selected for this component, and this application embodiment does not limit this. The digital signal processing unit integrated inside the graphics processor chip can perform equalization, forward error correction decoding, clock data recovery, and phase correction on the second electrical signal to eliminate distortion introduced during long-distance electrical connection and photoelectric conversion, and output target service data for use by the chip's internal computing unit.

[0133] This method enables externally transmitted data to undergo photoelectric conversion first, followed by recovery processing by the chip's internal digital signal processing unit. This reduces the processing burden on the optical module and shortens the invalid transmission distance of high-speed electrical signals in the board-level path. Consequently, it reduces module power consumption, alleviates heat dissipation pressure, and improves signal integrity and service data recovery reliability of the backhaul link. It is suitable for low-power optical communication scenarios between high-density servers and high-computing-power nodes.

[0134] This application also provides a computing node, including a chassis and a low-power optical communication device disposed within the chassis in the various possible embodiments described above. In this embodiment, specific limitations regarding the computing node can be found in the limitations regarding the low-power optical communication device described above, and will not be repeated here.

[0135] By integrating low-power optical communication devices within the chassis, computing nodes can simultaneously perform high-speed computing and high-speed optical interconnection within a limited space. Because the device uses a separate motherboard and front panel, and the graphics processing unit on the motherboard directly outputs digitally processed electrical signals to linearly drive pluggable optical modules, the high-speed electrical connection path is shortened, reducing insertion loss, reflection, and crosstalk, thus improving link signal integrity. Furthermore, the optical modules do not require built-in high-power digital signal processors, which helps reduce the overall power consumption and heat dissipation pressure of the node, thereby increasing thermal design margin under high-density deployment conditions. At the same time, the optical module cage on the front panel allows for centralized organization of external fiber optic interfaces, optimizing cabling inside and outside the chassis, improving port integration, and enhancing maintenance convenience. This makes the computing node more suitable for the high-bandwidth, low-latency communication requirements of data centers, artificial intelligence training platforms, and other high-performance computing scenarios.

[0136] It should be noted that the various modules or components involved in a computing node can be implemented entirely or partially through software, hardware, or a combination thereof. These modules or components can be embedded in hardware within or independently of the processor in an electronic device, or stored in software within the memory of the electronic device, so that the processor can invoke and execute the operations corresponding to the computing node.

[0137] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. In the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0138] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A low-power optical communication device, characterized in that, Includes a motherboard and a front panel that is separate from the motherboard; the motherboard is equipped with a graphics processor chip and a pluggable optical module interface, and the front panel is equipped with an optical module cage; The graphics processor chip integrates a digital signal processing unit for processing business data and outputting electrical signals after signal compensation processing. The pluggable optical module interface is used to plug in a linearly driven pluggable optical module, and is directly electrically connected to the graphics processor chip through electrical connection lines laid on the motherboard, so as to transmit the electrical signal to the linearly driven pluggable optical module. The optical module cage is connected to the optical interface of the linearly driven pluggable optical module via an optical fiber. It is used to distribute the optical signal generated by the linearly driven pluggable optical module after photoelectric conversion of the electrical signal to other node devices, and / or to receive the optical signal returned by other node devices and transmit it to the linearly driven pluggable optical module via the optical fiber.

2. The low-power optical communication device according to claim 1, characterized in that, The digital signal processing unit is also used to perform signal recovery processing on the electrical signals received from the linearly driven pluggable optical module.

3. The low-power optical communication device according to claim 2, characterized in that, The digital signal processing unit includes an equalization circuit and a clock recovery circuit; the signal compensation processing includes pre-emphasis processing, and the signal recovery processing includes clock data recovery processing.

4. The low-power optical communication device according to claim 1, characterized in that, The electrical connection line is a copper line laid out based on near-encapsulated copper cable, used to realize the electrical connection between the graphics processor chip and the pluggable optical module interface within a preset distance.

5. The low-power optical communication device according to claim 1, characterized in that, The pluggable optical module interface is located on the edge area of ​​the motherboard near the front panel; the motherboard is equipped with an upper reinforcing plate and a lower reinforcing plate, which together form a receiving cavity, and the graphics processor chip is fixed inside the receiving cavity.

6. The low-power optical communication device according to claim 1, characterized in that, The optical module cage is equipped with an optical fiber adapter interface for cascading with optical module cages of other node devices via optical fiber to achieve optical communication with other node devices.

7. The low-power optical communication device according to any one of claims 1-6, characterized in that, The motherboard has multiple pluggable optical module interfaces, each of which is electrically connected to the graphics processor chip via an independent electrical connection line to achieve multi-channel parallel optical communication.

8. A low-power optical communication method, characterized in that, The method, applied to a low-power optical communication device as described in any one of claims 1 to 7, comprises: The first electrical signal generated after the graphics processor chip processes business data is acquired; The first electrical signal is transmitted to the linear drive pluggable optical module plugged into the pluggable optical module interface via an electrical connection line. Based on the linearly driven pluggable optical module, the first electrical signal is subjected to photoelectric conversion processing to obtain the first optical signal; The first optical signal is transmitted to the optical module cage via optical fiber, and then distributed to other node devices through the optical module cage.

9. The method according to claim 8, characterized in that, The method further includes: Acquire the second optical signal received by the optical module cage and transmitted through the optical fiber to the linearly driven pluggable optical module; The second optical signal is photoelectrically converted into a second electrical signal by the linearly driven pluggable optical module. The second electrical signal is transmitted to the graphics processor chip via the electrical connection line; Based on the digital signal processing unit integrated within the graphics processor chip, the second electrical signal is processed to recover the target service data.

10. A computing node, characterized in that, It includes a chassis, and a low-power optical communication device as described in any one of claims 1 to 7 disposed within the chassis.

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