Chip, flow control method and electronic device

Abstract

This disclosure provides a chip and a flow control method. The chip includes: multiple nodes interconnected via a multi-level bus; a flow control component disposed on a node port in the bus; the flow control component is configured to: acquire input signals passing through the node port within a first time period, and buffer the input signals if the transmission parameters of the input signals meet flow control conditions.

Description

Technical Field

[0001] This disclosure relates to the field of flow control, and more particularly to a chip, a flow control method, and an electronic device. Background Technology

[0002] As the core pathway for data interaction among nodes in a system, the rational allocation and efficient utilization of bus bandwidth directly determine the overall system performance. Bus link congestion can easily occur under conditions of concurrent transmission across multiple nodes, sudden surges in data volume, or uneven bandwidth demands among nodes.

[0003] In related technologies, when performing flow control on a bus, the method used is to segment data granularity and extend the data transmission interval under bus congestion conditions to alleviate bus congestion. However, this method has low sensitivity in adjusting bus bandwidth; downstream bus congestion can immediately spread to the upstream bus, resulting in the entire bus being blocked at a single point, affecting the normal transmission of other devices and consequently impacting device performance. Summary of the Invention

[0004] In view of this, the present disclosure provides a chip and a flow control method.

[0005] According to a first aspect of the present disclosure, a chip is provided, the chip comprising: Multiple nodes interconnected via a multi-level bus; A flow control component is located on a node port in the bus; The flow control component is configured to: acquire the input signal passing through the node port within a first time period, and buffer the input signal if the transmission parameters of the input signal meet the flow control conditions.

[0006] In some possible implementations, the node port includes any of the following: The node's output port; The node's input port.

[0007] In some possible implementations, the transmission parameters of the input signal satisfy flow control conditions, including at least one of the following: The bandwidth of the input signal reaches the bandwidth threshold; The priority of the input signal is lower than the preset priority.

[0008] In some possible implementations, the flow control component is configured to further output the input signal to the corresponding destination node if the transmission parameters of the input signal do not meet the flow control conditions.

[0009] In some possible implementations, the flow control component includes: a flow control module and a flow control storage module; The flow control module is configured as follows: Based on the transmission parameters of the input signal, a flow control result is obtained, which is used to characterize whether the transmission parameters meet the flow control conditions. The flow-controlled storage module is configured as follows: If the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is buffered. When the flow control result indicates that the transmission parameters do not meet the flow control conditions, an output signal is generated.

[0010] In some possible implementations, the flow-controlled storage module includes: a first multiplexer, a first demultiplexer, a first path, and a second path; The input signals include: read signals and write signals; The first demultiplexer is used to transmit the read signal in the input signal to the first path and the write signal in the input signal to the second path; The first multiplexer is used to determine, based on the flow control result, whether to output the read signal in the first path and the write signal in the second path.

[0011] In some possible implementations, the read signal in the input signal is a read request signal; the read request signal is a request from the requesting node in the chip to read data from the slave node; The write signal in the input signal is a write response signal; the write response signal is the response of the slave node in the chip to the write data request of the requesting node.

[0012] In some possible implementations, the flow-controlled storage module includes: a second multiplexer, a second demultiplexer, and a third path; the input signal is a read signal or a write signal; The second demultiplexer is used to receive the input signal; The second multiplexer is used to determine whether to output the input signal in the third path based on the flow control result.

[0013] According to a second aspect of the present disclosure, a flow control method is provided, the method being applied to the chip described in the first aspect above, the method comprising: Based on the flow control component set at the node port, the input signal passing through the node port within a first time period is acquired; the node port is the port of the node interconnected by a multi-level bus in the chip; If the transmission parameters of the input signal meet the flow control conditions, the input signal is buffered.

[0014] In some possible implementations, the transmission parameters of the input signal satisfy flow control conditions, including at least one of the following: The bandwidth of the input signal reaches the bandwidth threshold; The priority of the input signal is lower than the preset priority.

[0015] In some possible implementations, the method further includes: If the transmission parameters of the input signal do not meet the flow control conditions, the input signal will be output to the corresponding destination node.

[0016] In some possible implementations, the flow control component includes: a flow control module and a flow control storage module; The step of buffering the input signal when the transmission parameters of the input signal meet the flow control conditions includes: Based on the transmission parameters, the flow control module determines the flow control result of the input signal, and the flow control result is used to characterize whether the transmission parameters meet the flow control conditions. If the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is cached by the flow control storage module.

[0017] In some possible implementations, the flow-controlled storage module includes a first multiplexer, a first demultiplexer, a first path, and a second path; the input signals include read signals and write signals. When the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is buffered through the flow control storage module, including: In response to the flow control result indicating that the read signal in the input signal is buffered, the read signal in the input signal is transmitted to the first channel through the first demultiplexer, and the read signal in the input signal is buffered to the buffer queue in the first channel through the first multiplexer; In response to the flow control result indicating that the write signal in the input signal is buffered, the write signal in the input signal is transmitted to the second path through the first demultiplexer, and the write signal in the input signal is buffered to the buffer queue in the second path through the first multiplexer.

[0018] In some possible implementations, the read signal in the input signal is a read request signal; the read request signal is a request from the requesting node in the chip to read data from the slave node; The write signal in the input signal is a write response signal; the write response signal is the response of the slave node in the chip to the write data request of the requesting node.

[0019] In some possible implementations, the flow control storage module in the flow control component includes a second multiplexer, a second demultiplexer, and a third path; the input signal is a read signal or a write signal; When the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is buffered through the flow control storage module, including: In response to the flow control result indicating that the input signal is buffered, the input signal is transmitted to the third path through the second demultiplexer, and the input signal is buffered in the buffer queue of the third path through the second multiplexer.

[0020] This embodiment of the disclosure, through a flow control component installed on the node port of any node in the bus, can determine the transmission parameters of the input signal at that node port. If the transmission parameters meet the flow control conditions, the input signal is buffered to limit its flow, reducing transmission bandwidth and avoiding bus congestion. Furthermore, due to the flexibility of the flow control component's configuration, data transmission and access between congested nodes can be flexibly controlled, minimizing the impact on the performance of other nodes interconnected with the bus.

[0021] Another aspect of this disclosure is an electronic device including the aforementioned chip. Attached Figure Description

[0022] Figure 1 This is a schematic diagram illustrating a bus data transmission method according to an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram illustrating a bus data transmission method according to an exemplary embodiment of this disclosure; Figure 3 This is a schematic diagram illustrating a bus data transmission method according to an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram illustrating the placement of a flow control component according to an exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of a flow control component shown in an exemplary embodiment of the present disclosure; Figure 6 This is a schematic diagram illustrating the structure of a flow-controlled storage module according to an exemplary embodiment of the present disclosure; Figure 7 This is a schematic diagram illustrating a current-limited write signal according to an exemplary embodiment of this disclosure; Figure 8 This is a timing diagram illustrating a data writing method according to an exemplary embodiment of this disclosure; Figure 9 This is a schematic diagram illustrating the placement of a flow control component according to an exemplary embodiment of this disclosure; Figure 10This is a schematic diagram of the structure of a flow control component shown in an exemplary embodiment of the present disclosure; Figure 11 This is a schematic diagram illustrating the placement of a flow control component according to an exemplary embodiment of this disclosure; Figure 12 This is a flowchart illustrating a flow control method according to an exemplary embodiment of this disclosure; Figure 13 This is a schematic diagram of the structure of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0023] In bus interconnect scenarios for very large-scale chips, when multiple master devices concurrently access multiple slave devices via a bus, bus congestion may occur during the access process, affecting the overall performance of the chip. Bus congestion can be caused by various factors, such as the overall data bandwidth exceeding the device's receiving capacity; or by differences in bandwidth between interconnected buses, leading to congestion on the low-bandwidth bus when data is transmitted from the high-bandwidth bus to the low-bandwidth bus.

[0024] The following examples illustrate the situation of mainline congestion. For example... Figure 1 As shown, when the master device reads data from two slave devices through the two-level interconnected bus 1 and bus 2, the two slave devices concurrently send data to the master device. If the overall data bandwidth exceeds the receiving capacity of the master device interface, it will cause congestion on bus 1 and bus 2.

[0025] and Figure 2 The scenario depicts a master device configured on a high-bandwidth bus (bus 1) and a slave device configured on a low-bandwidth bus (bus 2). A data width conversion or clock domain conversion occurs between the two buses. If the master device writes data to the slave device at this time, the speed at which the master device writes data on bus 1 will be greater than the speed at which the data is consumed by the slave device via bus 2. This results in the input data rate on bus 1 exceeding the data consumption rate, ultimately leading to congestion on bus 1.

[0026] Figure 3 Another scenario that could lead to bus congestion involves a master device on a low-bandwidth bus (bus 1) and a slave device on a high-bandwidth bus (bus 2), with data width or clock domain conversion occurring between the two buses. If the master device reads data from the slave device, the slave device on the high-bandwidth bus (bus 2) can quickly prepare the data from its internal storage and place it on bus 2. However, the master device's data reading speed on the low-bandwidth bus (bus 1) is slower than its data writing speed on bus 2. This results in the data input speed on bus 2 exceeding the data consumption speed, leading to congestion on bus 2.

[0027] Therefore, to improve bus bandwidth utilization and avoid bus congestion, flow control can be implemented on the bus by adjusting the rates of bus input and output data to ensure smooth bus operation. In related technologies, when implementing flow control on the bus, it is typically necessary to segment the data to be transmitted at the master device's port and extend the data transmission interval after detecting bus congestion, in order to alleviate the bus congestion situation.

[0028] However, this method of flow control suffers from low sensitivity. Downstream bus congestion can immediately propagate to the upstream bus, causing the entire bus to be blocked at a single point, thus affecting data transmission to other devices. Furthermore, congestion on the bus path of a master device accessing a particular node does not necessarily mean congestion on the bus paths of that same master device accessing other nodes. Related technologies often default to applying the same processing to all data at the master device port, and directly restricting the master device's output requests at the master device port can significantly impact the master device's performance.

[0029] Based on this, this disclosure provides a chip that can be applied to electronic devices such as embedded devices, industrial control devices, radar devices, vehicle-mounted devices, Internet of Things devices, and mobile terminals.

[0030] In some possible implementations, the chip includes: Multiple nodes interconnected via a bus.

[0031] The flow control component is located on the node port of the bus.

[0032] The flow control component is configured to: acquire the input signal passing through the node port within a first time period, and buffer the input signal if the transmission parameters of the input signal meet the flow control conditions.

[0033] The bus can be a single-level bus or an interconnected multi-level bus. Multiple nodes are located on the bus, for example... Figure 1 The diagram shows multiple master devices located on bus 1 and multiple slave devices located on bus 2. In some embodiments, the nodes may also be nodes between interconnected multi-level buses, such as bus bridge nodes, clock domain conversion nodes, data bit width conversion nodes, router nodes, etc.

[0034] The flow control component can be installed on the node port of any node in the bus to monitor the transmission parameters of data transmitted through that node port, thereby determining whether to control the node's data transmission to prevent the node from transmitting data to the bus too quickly, which could lead to bus congestion. For example, the flow control component can be installed on... Figure 1The output port of the master device, as shown, controls the amount of data the master device outputs to the slave device, thus preventing downstream bus congestion. For example, the flow control component can be set on... Figure 1 As shown on the output port of the slave device, when the path between the master device and slave device 1 is congested, but the path between the master device and slave device 2 is not congested, data transmission between the master device and slave device 1 can be stopped by controlling the port of slave device 1. This does not affect access and data transmission between the master device and slave device 2, thus flexibly resolving the congestion problem between the master device and slave device 1 and reducing the performance impact on the master device and slave device 2. For example... Figure 4 As shown, the flow control component can be set on the nodes between buses, and control the data access between master device 1 and slave device 1 and slave device 2 respectively through the nodes between buses, so as to flexibly solve the congestion problem between the master device and each slave device, and reduce the impact on the performance of the master device and other slave devices.

[0035] The node ports mentioned can be input ports and / or output ports of a node, specifically configured according to flow control requirements. For example, flow control components can be set on the port of a node experiencing congestion. When the flow control component is set on an input port, it can control the node's input data; when it is set on an output port, it can control the node's output data. For example, when the flow control component is set on the output port of the requesting node, it can control the request signals sent by the requesting node to the slave node, stopping the requesting node from writing or reading data to the slave node, thereby reducing data transmission between the requesting node and the slave node and alleviating the pressure on the bus between them. As another example, when the flow control component is set on the input port of the slave node, it can cause the slave node to stop responding to the requesting node, thereby suspending or stopping data transmission between the requesting node and the slave node, alleviating the pressure on the bus between them.

[0036] In some possible implementations, the flow control component can acquire input signals passing through the node port within a first time period and buffer the input signals if the transmission parameters of the input signals meet the flow control conditions. The transmission parameters may include the transmission bandwidth and priority of the input signal, whereby the priority is assigned to the input signal by the node, meaning the input signal itself can carry priority information. The flow control conditions can be pre-set based on indicators such as the importance and transmission capacity of the node port; different nodes or different ports of the same node may have different flow control conditions.

[0037] The flow control component acquires the input signals passing through the node port within a first time period. Based on the data volume of the input signal and the duration of the first time period, it determines the already transmitted bandwidth of the input signal and then determines whether the signal can continue to be transmitted based on the already transmitted bandwidth. If the flow control component determines that the signal should no longer be transmitted based on the already transmitted bandwidth, it can buffer the input signal and then re-issue the buffered input signal when the already transmitted bandwidth no longer meets the flow control conditions.

[0038] It should be noted that if the transmission parameters of the input signal do not meet the flow control conditions, the input signal can be output to the corresponding destination node. For example, if the request signal of the requesting node does not meet the flow control conditions, the request signal can be output to the corresponding subordinate node, i.e., the destination node.

[0039] In some possible implementations, the transmission parameters of the input signal satisfy flow control conditions, including at least one of the following: the bandwidth of the input signal reaches a bandwidth threshold; the priority of the input signal is lower than a preset priority.

[0040] In one embodiment, once the bandwidth of the input signal reaches (is greater than or equal to) a preset bandwidth threshold, the flow control component determines that the transmission parameters of the input signal meet the flow control conditions and buffers the input signal. The bandwidth thresholds for different nodes or ports of the same node may be different, and these thresholds can be dynamically adjusted according to the service requirements of data transmission. If the bandwidth of the input signal does not reach (is less than) the bandwidth threshold, the flow control component determines that the transmission parameters of the input signal do not meet the flow control conditions and outputs the input signal to the corresponding destination node.

[0041] In one embodiment, after determining that the priority of the input signal is lower than the preset priority, the flow control component can determine that the transmission parameters of the input signal meet the flow control conditions and buffer the input signal. The preset priorities may be different for different nodes or different ports of the same node.

[0042] In one implementation, after the bandwidth of the input signal reaches a preset bandwidth threshold, it can be further determined whether the priority of the input signal is lower than a preset priority. If the bandwidth of the input signal reaches the bandwidth threshold and the priority of the input signal is lower than the preset priority, then it can be determined that the transmission parameters of the input signal meet the flow control conditions, and the input signal is buffered. If the bandwidth of the input signal reaches the bandwidth threshold, but the priority of the input signal is higher than (greater than or equal to) the preset priority, then it can be determined that the transmission parameters of the input signal do not meet the flow control conditions, and the input signal can be output to the bus.

[0043] In some possible implementations, the structure of the flow control component can be seen in [reference needed]. Figure 5The schematic diagram shows that the flow control components include: a flow control module 501 and a flow control storage module 502.

[0044] The flow control module 501 is configured to obtain a flow control result based on the transmission parameters of the input signal, wherein the flow control result is used to characterize whether the transmission parameters meet the flow control conditions.

[0045] The flow control module 501 can acquire the input signals passing through the node port within the first time period, determine the transmission parameters of the input signals, and judge whether the transmission parameters meet the flow control conditions, thereby obtaining the flow control result.

[0046] The flow control storage module 502 is configured to: buffer the input signal when the flow control result indicates that the transmission parameters meet the flow control conditions; and output the input signal when the flow control result indicates that the transmission parameters do not meet the flow control conditions.

[0047] The flow control storage module 502 can process the output signal accordingly based on the flow control result obtained from the flow control module 501. For example, if the flow control result indicates that the transmission parameters meet the flow control conditions, it means that the input signal can be controlled, and the flow control storage module 502 can pause the output of the signal and buffer the signal. If the flow control result indicates that the transmission parameters do not meet the flow control conditions, it means that the input signal can be output.

[0048] It should be noted that the construction of the flow-controlled storage module varies depending on the bus protocol used by the node ports. For example, when the bus protocol is AMBA CHI, this protocol has six data channels: Req (Request), Srsp (Snoop Response), Wdat (Write Data), Crsp (Completion Response), Rdat (Read Data), and Snp (Snoop). When a requesting node reads data from a slave node, the requesting node first sends a read request through the Req channel. After receiving the read request, the slave node locates the data and sends the read data through the Rdat channel. After receiving the data, the requesting node sends a completion response through the Crsp channel. When a requesting node writes data to a slave node, the requesting node first sends a write request through the Req channel. After receiving the write request, the slave node sends a write response through the Crsp channel. After receiving the write response, the requesting node transmits the write data through Wdat.

[0049] In other words, when reading and writing data via the CHI protocol, the request channel (Req) and response channel (Crsp) used for reading data are shared. Read / write requests are transmitted on the same channel, and read / write responses are transmitted on the same channel. Both the request and response channels simultaneously receive read and write signals. Therefore, in this case, two paths can be set up in the flow-controlled storage module 502 to separate the read and write signals for independent transmission, thus preventing write operations from blocking subsequent read operations, or vice versa.

[0050] In some embodiments, the structure of the flow-controlled storage module 502 can be found in [reference needed]. Figure 6 The schematic diagram is shown. The flow-controlled storage module includes: a first multiplexer 601, a first demultiplexer 602, a first path 603, and a second path 604; the input signals include: a read signal and a write signal.

[0051] The first demultiplexer 601 is used to transmit the read signal in the input signal to the first path 603 and the write signal in the input signal to the second path 604.

[0052] The first multiplexer 602 is used to determine, based on the flow control result, whether to output the read signal in the first path 603 and the write signal in the second path 604.

[0053] The first demultiplexer can be a DeMux, and the first multiplexer can be a Mux. The first demultiplexer receives the input signal and distinguishes between read and write signals. It then inputs the read signal into the FIFO (First-In-First-Out queue) in the first path, which then enters the first multiplexer. Conversely, it inputs the write signal into the FIFO (First-In-First-Out queue) in the second path, which then enters the first multiplexer. Upon receiving the flow control result, the first multiplexer determines whether to output the read signal in the first path 603 and the write signal in the second path 604. If no read signal is output, it buffers the read signal in FIFO1 of the first path; if no write signal is output, it buffers the write signal in FIFO2 of the first path.

[0054] For example Figure 7 As shown in the diagram, after DeMux separates the read and write signals in the input signal and limits the read signal, only the read signal can be buffered, while the write signal can be transmitted normally. This avoids the read operation blocking the subsequent write operation and improves the accuracy of the input signal control.

[0055] According to the CHI protocol data reading process described above, when reading data, the requesting node sends a read request first, and the slave node returns data based on the received read request. That is, the read request is immediately followed by the read data. If the amount of read data is too large, it may cause congestion on the downstream bus. Therefore, when it is necessary to limit the read signal of the node port, it can be achieved by limiting the read request. Specifically, the read signal in the input signal is the read request signal; the read request signal is the requesting node's request for read data from the slave node in the chip. In this case, the flow control component can be set on the request channel Req, so that read requests go through the FIFO1 path and write requests go through the FIFO2 path. FIFO1 is used to buffer backpressure read requests, and FIFO2 is used to buffer backpressure write requests generated by the Mux, thereby preventing congestion from propagating forward and preventing rate-limited read requests from blocking subsequent write requests that do not need to be rate-limited.

[0056] According to the CHI protocol's data writing process described above, when writing data, the requesting node first sends a write request, the slave node returns a write response, and the requesting node sends the write data after receiving the write response. That is, the write data occurs after the write response. However, if the amount of write data is too large, it may cause congestion on the downstream bus. Therefore, when it is necessary to limit the write signal of the node port, this can be achieved by limiting the write response. Specifically, the write signal in the input signal is the write response signal; the write response signal is the response of the slave node in the chip to the requesting node's write data request. In this case, the flow control component can be set on the response channel Crsp, with the write response going through the FIFO1 path and the read response going through the FIFO2 path. FIFO1 is used to buffer backpressured write responses, and FIFO2 is used to buffer backpressured read responses generated by the Mux, thereby preventing congestion from propagating forward and preventing the blocked write responses from blocking subsequent read responses that do not need to be rate-limited.

[0057] In some embodiments, the requesting node can also adjust the priority of the input signal based on a QoS (Quality of Service) mechanism, making the urgency of the requesting node's own business positively correlated with the priority. For example, the requesting node can increase the priority of the input signal according to the urgency of the business, ensuring that the input signal is successfully sent even in the event of bus congestion, thus guaranteeing the smooth operation of the requesting node's business. The responding node can also dynamically adjust the priority of the response signal according to the busyness of its own business. This allows the responding node to increase the priority of the response signal when it is idle, enabling the requesting node to transmit buffered input signals normally, reducing input signal latency, improving bandwidth utilization, and thus adjusting the priority of the input signal after bus congestion is relieved. This achieves adaptive adjustment of the input signal bandwidth and avoids wasting bus resources.

[0058] For example Figure 8The flowchart shown illustrates an interaction sequence for writing data in the CHI protocol. This embodiment of the disclosure uses a rate-limited write response to limit the write data, effectively improving the sensitivity of adjusting the write signal bandwidth. This is because the write request has already been sent to the slave node; after the rate limit is lifted, a write response can be sent directly, followed by the write data. Compared to a rate-limited write request, which requires sequential sending and receiving of the write request, write response, and write data after the rate limit is lifted, the rate-limited write response reduces the time required to send the write request, thus achieving higher sensitivity in bandwidth adjustment.

[0059] Based on this, when the bus protocol is AMBA CHI, the location of the flow control component can be as follows: Figure 9 As shown, this flow control component can be set on the request channel Req and the response channel Crsp to limit the rate of read requests in the request channel or the rate of write responses in the response channel.

[0060] The structure and settings of the flow control component will be explained below when using other bus protocols.

[0061] For example, when the bus protocol is AMBA AXI, the protocol has five data channels: AR (Address Read), R (Read Data), AW (Address Write), W (Write Data), and B (Write Response).

[0062] The following explanation uses the CPU as the requesting node and the memory as the slave node to illustrate the processes of CPU writing and reading data. When the CPU reads data from memory via the AMBA AXI protocol, its output port first sends a read address request through the AR channel. The memory receives the address through its receive port, prepares the data, and then returns the data to the CPU through the R channel. The CPU receives the data and completes the read operation. When the CPU writes data to memory via the AMBA AXI protocol, it sends a write address request through the AW channel and sends the data to be written through the W channel. The memory receives the address and data, returns a write completion response through the B channel, and the CPU receives the response and completes the write operation.

[0063] In other words, when reading and writing data via the AXI protocol, the AR and R channels used for reading data are separate from the AW and W channels used for writing data. Therefore, when the flow control component is set on any channel, the input signal in the flow control component can only be a read signal or a write signal; the flow control component does not need to split the input signal. Based on this, in some embodiments, the structural diagram of the flow control component can be as follows: Figure 10As shown, the flow control storage module in the flow control component may include: a second multiplexer, a second demultiplexer, and a third path.

[0064] The second demultiplexer receives the input signal and then transmits it to the second multiplexer via the FIFO in the third path. The second multiplexer determines whether to output the input signal based on the flow control result; if not, it buffers the input signal in the FIFO of the third path.

[0065] To achieve separate control of write request signals and read request signals, the flow control component can be configured as follows: Figure 11 As shown, they are set in the AR channel and AW channel respectively.

[0066] Corresponding to the aforementioned chip embodiments, this disclosure also provides embodiments of a flow control method applied to the chip.

[0067] Please see Figure 12 The flowchart shown illustrates that the flow control method includes: S1201, based on the flow control component set at the node port, acquires the input signal passing through the node port within the first time period.

[0068] The node port refers to the port of a node interconnected via a bus within the chip; the node port can be an output port and / or an input port of a node. The flow control component can acquire the input signals passing through the node port within a first time period and determine the transmission parameters of the input signals.

[0069] S1202, if the transmission parameters of the input signal meet the flow control conditions, the input signal is buffered.

[0070] The flow control module in the flow control component determines the flow control result of the input signal based on the transmission parameters of the input signal and preset flow control conditions. This flow control result is used to characterize whether the transmission parameters meet the flow control conditions. The transmission parameters of the input signal meeting the flow control conditions include at least one of the following: the bandwidth of the input signal reaches a bandwidth threshold; the priority of the input signal is lower than a preset priority.

[0071] If the transmission parameters of the input signal meet the flow control conditions, the flow control component can buffer the input signal and temporarily refrain from transmitting it to avoid bus congestion. If the transmission parameters of the input signal do not meet the flow control conditions, it means that transmitting the input signal will not cause bus congestion, and the input signal can then be output to the corresponding destination node.

[0072] In some possible implementations, the flow control component includes: a flow control module and a flow control storage module; The step of caching the input signal when the transmission parameters of the input signal meet the flow control conditions includes: determining the flow control result of the input signal through the flow control module based on the transmission parameters, wherein the flow control result is used to characterize whether the transmission parameters meet the flow control conditions; and caching the input signal through the flow control storage module when the flow control result indicates that the transmission parameters meet the flow control conditions.

[0073] The flow control module can determine whether the input signal meets the flow control conditions based on the transmission parameters of the input signal, thereby obtaining the flow control result. Then, the flow control storage module can determine whether to buffer the input signal based on the flow control result. If the flow control result indicates that the transmission parameters meet the flow control conditions, then the input signal can be buffered through the flow control storage module.

[0074] It should be noted that different bus protocols may transmit data in different ways. For example, some bus protocols transmit read and write requests and read and write responses on the same channel when transmitting data between nodes. Other bus protocols transmit read and write requests and read and write responses on two separate channels.

[0075] Therefore, in order to meet the transmission requirements of different bus protocols, the storage modules in the flow control components are also different.

[0076] In some embodiments, the bus protocol may be the AMBA CHI protocol, in which read and write requests are transmitted on the same channel, and read and write responses are transmitted on the same channel. Therefore, for this bus protocol, the flow-controlled storage module can be configured to include a first multiplexer, a first demultiplexer, a first path, and a second path; the input signals include read signals and write signals. When the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is buffered through the flow control storage module, including: In response to the flow control result indicating that the read signal in the input signal is buffered, the read signal in the input signal is transmitted to the first channel through the first demultiplexer, and the read signal in the input signal is buffered to the buffer queue in the first channel through the first multiplexer; In response to the flow control result indicating that the write signal in the input signal is buffered, the write signal in the input signal is transmitted to the second path through the first demultiplexer, and the write signal in the input signal is buffered to the buffer queue in the second path through the first multiplexer.

[0077] The first demultiplexer is used to transmit the read signal from the input signal to the first path and the write signal from the input signal to the second path. The first multiplexer is used to determine, based on the flow control result, whether to output the read signal in the first path and the write signal in the second path. If the flow control module determines that the read signal in the input signal meets the flow control conditions, then the flow control result indicates that the read signal in the input signal can be buffered. In this case, the first demultiplexer can transmit the read signal from the input signal to the first path and buffer the read signal in the input signal into the buffer queue (i.e., FIFO) in the first path. If the flow control module determines that the write signal in the input signal meets the flow control conditions, then the flow control result indicates that the write signal in the input signal can be buffered. In this case, the first demultiplexer can transmit the write signal from the input signal to the second path and buffer the write signal in the input signal into the buffer queue (i.e., FIFO) in the second path.

[0078] It should be noted that, in order to improve the sensitivity of controlling the transmission bandwidth of the input signal, the read signal can be controlled by controlling the read request signal, that is, the read signal in the input signal is a read request signal; the read request signal is the requesting node in the chip to read data from the slave node. Similarly, the write signal can be controlled by controlling the write request, that is, the write signal in the input signal is a write response signal; the write response signal is the slave node in the chip's response to the requesting node's write data request.

[0079] In some embodiments, the bus protocol may be the AMBA AXI protocol, in which read and write requests are transmitted on different channels, and read and write responses are also transmitted on different channels. Therefore, the flow-controlled storage module in the flow control component includes a second multiplexer, a second demultiplexer, and a third path; the input signal is a read signal or a write signal; When the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is buffered through the flow control storage module, including: In response to the flow control result indicating that the input signal is buffered, the input signal is transmitted to the third path through the second demultiplexer, and the input signal is buffered in the buffer queue of the third path through the second multiplexer.

[0080] Since the input signal can only be a read signal or a write signal, there is no need to split the input signal for reading or writing. The second demultiplexer can be a single-input single-output device, directly transmitting the input signal to the third path. Based on the flow control result, the second multiplexer can determine whether to transmit the input signal in the third path. If the flow control result indicates that the input signal should be buffered, the input signal is buffered in the buffer queue of the third path and is not transmitted temporarily.

[0081] Figure 13 The diagram shows a structural block diagram of an electronic device according to some embodiments of the present disclosure. The chip and the flow control method can be applied to electronic devices. The following describes the process in conjunction with... Figure 13 Some embodiments of the electronic device described herein will be explained.

[0082] Reference Figure 13 The electronic device 1300 may include one or more of the following components: processing component 1302, memory 1304, power supply component 1306, multimedia component 1308, audio component 1310, input / output (I / O) interface 1312, sensor component 1316, and communication component 1318.

[0083] Processing component 1302 typically controls the overall operation of electronic device 1300, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1302 may include one or more processors 1820 to execute instructions. Furthermore, processing component 1302 may include one or more modules to facilitate interaction between processing component 1302 and other components. For example, processing component 1302 may include a multimedia module to facilitate interaction between multimedia component 1308 and processing component 1302. As another example, processing component 1302 may read executable instructions from memory to implement relevant functions of the electronic device.

[0084] Memory 1304 is configured to store various types of data to support the operation of electronic device 1300. Examples of such data include instructions for any application or method operating on electronic device 1300, contact data, phonebook data, messages, pictures, videos, etc. Memory 1304 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0085] Power supply component 1306 provides power to various components of electronic device 1300. Power supply component 1306 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1300.

[0086] The multimedia component 1308 includes a display screen that provides an output interface between the electronic device 1300 and the user. In some embodiments, the multimedia component 1308 includes a front-facing camera and / or a rear-facing camera. When the electronic device 1300 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera can receive external multimedia data. Each front-facing camera and rear-facing camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0087] Audio component 1310 is configured to output and / or input audio signals. For example, audio component 1310 includes a microphone (MIC) configured to receive external audio signals when electronic device 1300 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1304 or transmitted via communication component 1318. In some embodiments, audio component 1310 also includes a speaker for outputting audio signals.

[0088] I / O interface 1312 provides an interface between processing component 1302 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0089] Sensor assembly 1316 includes one or more sensors for providing state assessments of various aspects of electronic device 1300. For example, sensor assembly 1316 may detect the on / off state of electronic device 1300, the relative positioning of components such as the display and keypad of electronic device 1300, changes in position of electronic device 1300 or a component of electronic device 1300, the presence or absence of user contact with electronic device 1300, the orientation or acceleration / deceleration of electronic device 1300, and temperature changes of electronic device 1300. Sensor assembly 1316 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1316 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1316 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0090] Communication component 1318 is configured to facilitate wired or wireless communication between electronic device 1300 and other devices. Electronic device 1300 can access wireless networks based on communication standards, such as Wi-Fi, 2G, 3G, 4G, 5G, or 6G, or combinations thereof. In one exemplary embodiment, communication component 1318 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1318 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0091] In an exemplary embodiment, the electronic device 1300 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

Claims

1. A chip, characterized in that, The chip includes: Multiple nodes interconnected via a bus; A flow control component is located on a node port in the bus; The flow control component is configured to: acquire the input signal passing through the node port within a first time period, and buffer the input signal if the transmission parameters of the input signal meet the flow control conditions.

2. The chip according to claim 1, characterized in that, The node port includes any one of the following: The node's output port; The node's input port.

3. The chip according to claim 1, characterized in that, The transmission parameters of the input signal satisfy flow control conditions, including at least one of the following: The bandwidth of the input signal reaches the bandwidth threshold; The priority of the input signal is lower than the preset priority.

4. The chip according to claim 1, characterized in that, The flow control component is configured to further output the input signal to the corresponding destination node when the transmission parameters of the input signal do not meet the flow control conditions.

5. The chip according to claim 1, characterized in that, The flow control component includes: a flow control module and a flow control storage module; The flow control module is configured as follows: Based on the transmission parameters of the input signal, a flow control result is obtained, which is used to characterize whether the transmission parameters meet the flow control conditions. The flow-controlled storage module is configured as follows: If the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is buffered. If the flow control result indicates that the transmission parameters do not meet the flow control conditions, the input signal is output.

6. The chip according to claim 5, characterized in that, The flow-controlled storage module includes: a first multiplexer, a first demultiplexer, a first path, and a second path; The input signals include: read signals and write signals; The first demultiplexer is used to transmit the read signal in the input signal to the first path and the write signal in the input signal to the second path; The first multiplexer is used to determine, based on the flow control result, whether to output the read signal in the first path and the write signal in the second path.

7. The chip according to claim 6, characterized in that, The read signal in the input signal is a read request signal; the read request signal is a request from the requesting node in the chip to read data from the slave node; The write signal in the input signal is a write response signal; the write response signal is the response of the slave node in the chip to the write data request of the requesting node.

8. The chip according to claim 5, characterized in that, The flow-controlled storage module includes: a second multiplexer, a second demultiplexer, and a third path; the input signal is a read signal or a write signal. The second demultiplexer is used to receive the input signal; The second multiplexer is used to determine whether to output the input signal in the third path based on the flow control result.

9. A flow control method, characterized in that, The method is applied to the chip according to any one of claims 1-8, and the method includes: Based on the flow control component set at the node port, the input signal passing through the node port within a first time period is acquired; the node port is the port of the node interconnected by the bus in the chip; If the transmission parameters of the input signal meet the flow control conditions, the input signal is buffered.

10. The method according to claim 9, characterized in that, The transmission parameters of the input signal satisfy flow control conditions, including at least one of the following: The bandwidth of the input signal reaches the bandwidth threshold; The priority of the input signal is lower than the preset priority.

11. The method according to claim 9, characterized in that, The method further includes: If the transmission parameters of the input signal do not meet the flow control conditions, the input signal will be output to the corresponding destination node.

12. The method according to claim 9, characterized in that, The flow control component includes: a flow control module and a flow control storage module; The step of buffering the input signal when the transmission parameters of the input signal meet the flow control conditions includes: Based on the transmission parameters, the flow control module determines the flow control result of the input signal, and the flow control result is used to characterize whether the transmission parameters meet the flow control conditions. If the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is cached by the flow control storage module.

13. The method according to claim 12, characterized in that, The flow-controlled storage module includes a first multiplexer, a first demultiplexer, a first path, and a second path; the input signals include read signals and write signals. When the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is buffered through the flow control storage module, including: In response to the flow control result indicating that the read signal in the input signal is buffered, the read signal in the input signal is transmitted to the first channel through the first demultiplexer, and the read signal in the input signal is buffered to the buffer queue in the first channel through the first multiplexer; In response to the flow control result indicating that the write signal in the input signal is buffered, the write signal in the input signal is transmitted to the second path through the first demultiplexer, and the write signal in the input signal is buffered to the buffer queue in the second path through the first multiplexer.

14. The method according to claim 13, characterized in that, The read signal in the input signal is a read request signal; the read request signal is a request from the requesting node in the chip to read data from the slave node; The write signal in the input signal is a write response signal; the write response signal is the response of the slave node in the chip to the write data request of the requesting node.

15. The method according to claim 12, characterized in that, The flow control storage module in the flow control component includes a second multiplexer, a second demultiplexer, and a third path; the input signal is a read signal or a write signal. When the flow control result indicates that the transmission parameters meet the flow control conditions, the input signal is buffered through the flow control storage module, including: In response to the flow control result indicating that the input signal is buffered, the input signal is transmitted to the third path through the second demultiplexer, and the input signal is buffered in the buffer queue of the third path through the second multiplexer.

16. An electronic device comprising the chip according to any one of claims 1-8.

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