Bulky and flexible cable

Abstract

The application relates to a daisy chain communication method, system, device and chip, wherein the method comprises the following steps: when receiving an instruction frame sent by an upstream chip, a downstream chip delays for a preset m bit period and forwards the instruction frame to a next-stage chip; the downstream chip transmits data back to the upstream chip according to the instruction frame, and stops after completing n-bit data; when detecting that the FIFO cache depth of the upstream chip is not greater than n bits, the upstream chip sends a handshake signal to the downstream chip; after receiving the handshake signal, the downstream chip continues to send n-bit data; each chip starts a counter in response to the signal jump of a valid phase Manchester code; in an invalid phase, if the signal jump is detected, it is determined that the current bit is the same as the previous bit, and the counter is cleared; otherwise, when the count value reaches a preset timeout threshold, it is determined that the current bit is opposite to the previous bit, and the counter is cleared. By adopting the application, the robustness, reliability and cost-effectiveness of daisy chain communication are improved.

Description

Technical Field

[0001] This invention relates to the field of daisy-chain communication technology, and in particular to a daisy-chain communication method, system, device and chip. Background Technology

[0002] In multi-chip cascaded applications such as battery management systems and sensor networks, a daisy-chain architecture is often used for serial communication, with data transmitted bidirectionally between chips in Manchester code. Manchester code integrates clock and data into the same signal stream, allowing the receiver to recover the clock from the signal edges without requiring a separate clock line. Therefore, it is widely used to reduce wiring complexity and system cost.

[0003] However, in practical applications, cascaded chips typically use their own independent internal clock sources, lacking a common clock source. Due to factors such as process variations, voltage fluctuations, and temperature changes, the clock frequencies of different chips inevitably deviate to some extent. In this situation, when the receiver decodes Manchester code based on its local clock, the timing error for each bit cycle accumulates bit by bit, causing the sampling points to gradually drift. When the accumulated error reaches half a bit cycle, decoding errors or data frame loss may occur. Furthermore, during uplink data transmission, the mismatch in transmission rates between chips can cause the receiver's FIFO buffer depth to drift, easily leading to overflow or empty reads, further affecting communication reliability.

[0004] Therefore, how to effectively suppress the accumulation of Manchester code decoding errors and prevent FIFO buffer anomalies in daisy chain communication of multiple chips without cascading of the same source clock, so as to improve the robustness and reliability of communication, is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] In view of this, it is necessary to provide a daisy-chain communication method, system, device and chip to solve the technical problems of low communication robustness and reliability of daisy chains in the prior art.

[0006] To address the aforementioned problems, in a first aspect, the present invention provides a daisy-chain communication method, wherein the daisy chain comprises multiple chips connected sequentially in an upstream-downstream order, and the chips transmit data bidirectionally in Manchester code form via differential signal lines, the method comprising: When the downstream chip receives the instruction frame sent by the upstream chip, it forwards the instruction frame to the next-level chip of the downstream chip after a preset delay of m bit periods, where m is a positive integer. The downstream chip sends data back to the upstream chip according to the instruction frame. It stops after completing every n bits of data. When the upstream chip detects that its own FIFO buffer depth is less than or equal to n bits, it sends a handshake signal to the downstream chip. After receiving the handshake signal, the downstream chip continues to send the next n bits of data, where n is a positive integer. Each chip divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase, and starts a counter in response to the Manchester code signal transition during the valid edge phase. During the invalid edge phase, if a Manchester code signal transition is detected, the current bit is determined to be the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches the preset timeout threshold, the current bit is determined to be opposite to the previous bit and the counter is cleared.

[0007] In one possible implementation, each chip divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase, including: The transition edge of the Manchester code signal at the middle of the bit period is determined as the effective edge phase; The time interval between two adjacent valid edge phases in the Manchester code signal is defined as the invalid edge phase.

[0008] In one possible implementation, the Manchester code signal has a bit value of 1 on the rising edge and a bit value of 0 on the falling edge during the effective edge phase. During the invalid edge phase, if a Manchester code signal transition is detected, the current bit is determined to be the same as the previous bit; if no Manchester code signal transition is detected, the current bit is determined to be different from the previous bit.

[0009] In one possible implementation, the time corresponding to the preset timeout threshold is located in the second half of the current bit period.

[0010] In one possible implementation, the time corresponding to the preset timeout threshold is located at 2 / 3 of the bit period at the start of the current bit period.

[0011] In one possible implementation, when the downstream chip sends back data, there is a delay of m bit cycles, and the FIFO buffer has a depth of n+m bits.

[0012] Secondly, the present invention also provides a daisy-chain communication system, comprising multiple chips cascaded together in a daisy-chain manner, each chip comprising: The transmitting module is used to send data to downstream or upstream chips. The receiving module is used to receive data from upstream or downstream chips; The FIFO caching module is used to cache received data; The control module, connected to the sending module, the receiving module, and the FIFO buffer module, is used to control the downstream chip to forward the instruction frame downstream after a preset delay of m bit periods when receiving the instruction frame sent by the upstream chip; control the downstream chip to send data back to the upstream chip, stopping after every n bits of data are completed, and controlling the downstream chip to continue sending the next n bits of data based on the handshake signal triggered by the upstream chip detecting its own FIFO buffer depth. The receiving module integrates a Manchester decoding unit, which divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase; in response to a Manchester code signal transition during the valid edge phase, a counter is started; during the invalid edge phase, if a Manchester code signal transition is detected, it is determined that the current bit is the same as the previous bit and the counter is cleared; otherwise, when the counter value reaches a preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared.

[0013] Thirdly, the present invention also provides a daisy-chain communication device, wherein the daisy chain includes multiple chips connected sequentially in an upstream and downstream order, and the chips transmit data bidirectionally in Manchester code form via differential signal lines. The device includes: The forwarding unit is used to forward the instruction frame to the next-level chip of the downstream chip after a preset delay of m bit periods when the downstream chip receives the instruction frame sent by the upstream chip, where m is a positive integer. The sending unit is used for the downstream chip to send data back to the upstream chip according to the instruction frame. It stops after completing every n bits of data. When the upstream chip detects that its own FIFO buffer depth is less than or equal to n bits, it sends a handshake signal to the downstream chip. After receiving the handshake signal, the downstream chip continues to send the next n bits of data, where n is a positive integer. The first communication unit is used for each chip to divide each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase, and to start a counter in response to the Manchester code signal transition in the valid edge phase. The second communication unit is used to determine that the current bit is the same as the previous bit and clear the counter if a Manchester code signal transition is detected during the invalid edge phase; otherwise, when the counter value reaches a preset timeout threshold, determine that the current bit is opposite to the previous bit and clear the counter.

[0014] Fourthly, the present invention also provides an upstream chip in a daisy chain, comprising: The first receiving module is used to receive data transmitted back from the downstream chip. The first receiving module integrates a first Manchester decoding unit. The first Manchester decoding unit is used to divide each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase. In response to the Manchester code signal transition in the valid edge phase, the counter is started. If a Manchester code signal transition is detected in the invalid edge phase, it is determined that the current bit is the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches a preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared. The caching module is used to cache the data transmitted back after being decoded by the first receiving module; The first sending module is used to send instruction frames to downstream chips and to send handshake signals to downstream chips. The first control module, connected to the FIFO buffer module and the first sending module, is used to detect the depth of the FIFO buffer module. When the depth is less than or equal to a preset n bits, the first sending module sends the handshake signal to the downstream chip, where n is a positive integer.

[0015] Fifthly, the present invention also provides a downstream chip of the daisy chain, comprising: The second receiving module is used to receive instruction frames and handshake signals from the upstream chip. The second receiving module integrates a second Manchester decoding unit. The second Manchester decoding unit is used to divide each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase. In response to the Manchester code signal transition in the valid edge phase, the counter is started. If a Manchester code signal transition is detected in the invalid edge phase, it is determined that the current bit is the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches the preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared. The second sending module is used to send data back to the upstream chip and to forward the instruction frame to the next-level chip. The second control module, connected to the second receiving module and the second sending module, is used to control the second sending module to forward the instruction frame to the next-level chip after a preset delay of m bit periods when the second receiving module receives the instruction frame, where m is a positive integer; the second control module is also used to control the second sending module to stop transmission after completing n bits of data return and wait for the handshake signal, and when the second receiving module receives the handshake signal, control the second sending module to continue sending the next n bits of data, where n is a positive integer.

[0016] The beneficial effects of this invention are: The daisy-chain communication method provided by this invention improves the transmission efficiency and reliability of downlink commands by delaying the transmission of command frames sent by the upstream chip by m bit periods. The downstream chip forwards the command frames to the next-level chip after receiving them from the upstream chip. The downstream chip transmits data back to the upstream chip according to the command frames, pausing after each n bits of data are transmitted. When the upstream chip detects that its FIFO buffer depth is less than or equal to n bits, it sends a handshake signal to the downstream chip. Upon receiving the handshake signal, the downstream chip continues to send the next n bits of data, thus improving the robustness of large-capacity data transmission. Each chip divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase. In response to the Manchester code signal transition during the valid edge phase, a counter is started. During the invalid edge phase, if a Manchester code signal transition is detected, it is determined that the current bit is the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches a preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared. This eliminates the phenomenon of bit-by-bit error accumulation in traditional schemes, reduces the material cost and power consumption of the chip, and improves the robustness, reliability and cost-effectiveness of daisy-chain communication. Attached Figure Description

[0017] Figure 1 A schematic flowchart of an embodiment of the daisy-chain communication method provided by the present invention; Figure 2 A state cycle diagram of the communication cycle provided by the present invention; Figure 3 Waveform diagram of the data return structure provided by this invention; Figure 4 Waveform diagram of Manchester code half-cycle sampling decoding and clock recovery mechanism provided by the present invention; Figure 5 This is a schematic diagram of the chip structure provided by the present invention; Figure 6 This is a schematic diagram of the daisy-chain communication device provided by the present invention; Figure 7 A schematic diagram of the upstream chip of the daisy chain provided by the present invention; Figure 8 This is a schematic diagram of the downstream chip structure of the daisy chain provided by the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] In the description of the embodiments of the present invention, unless otherwise stated, "a plurality of" means two or more.

[0020] The terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a technical feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] This invention provides a daisy-chain communication method, system, device, and chip, which are described below.

[0023] The daisy-chain communication method in this application embodiment can be implemented by the daisy-chain communication device or daisy-chain communication system provided in this application embodiment, or by different types of electronic devices such as server equipment, physical host, or user equipment (UE) that integrates the daisy-chain communication device. The daisy-chain communication device can be implemented in hardware or software. The UE can be a terminal device such as a smartphone, tablet computer, laptop computer, handheld computer, desktop computer, or personal digital assistant (PDA).

[0024] The daisy-chain communication method described in this application has clear application prospects in cost-sensitive fields such as BMS, industrial control, and sensor networks, which require multi-chip cascading. It reduces the requirements for chip clock speeds, helping to lower system costs; at the same time, it improves communication robustness, meeting reliability requirements in industrial environments and possessing significant industrial application value.

[0025] Figure 1 This is a schematic flowchart of an embodiment of the daisy-chain communication method provided by the present invention, as shown below. Figure 1 As shown, a daisy chain comprises multiple chips connected sequentially in an upstream and downstream order. These chips transmit data bidirectionally in Manchester code via differential signal lines. The daisy chain communication method includes: S101. When the downstream chip receives the instruction frame sent by the upstream chip, it forwards the instruction frame to the next-level chip of the downstream chip after a preset delay of m bit periods, where m is a positive integer.

[0026] In this embodiment's daisy-chain communication architecture, multiple chips are connected in series according to the signal transmission direction, forming a Level 1 chip, a Level 2 chip, ..., a Level N chip. Along the forward signal transmission direction, the end sending data is called the upstream, and the end receiving data is called the downstream. For any two adjacent chips, the chip closer to the main controller or the previous level is called the upstream chip, and the chip closer to the end or the next level is called the downstream chip. For example, the Level 1 chip is the upstream chip of the Level 2 chip, and the Level 2 chip is the downstream chip of the Level 1 chip. Simultaneously, the Level 2 chip is the upstream chip of the Level 3 chip, and so on. This upstream-downstream relationship is relative and depends on the current direction of signal transmission.

[0027] A daisy chain is constructed, in which multiple chips are connected sequentially in an upstream-downstream order to form a serial link. The chips transmit data bidirectionally in Manchester code via differential signal lines.

[0028] Differential signal lines, typically denoted as DIO_P and DIO_N, are used to transmit differential Manchester code. Manchester code is a synchronous clock encoding technique that divides each bit period into two equal-length half-cycles and forces a level transition in the middle of each bit period, thus embedding clock information into the data stream. The receiving end can use this transition to recover the clock without requiring a separate clock line.

[0029] Specifically, during the downlink command transmission phase, the upstream chip sends a command frame to the downstream chip. Upon receiving the command frame, the downstream chip does not forward it immediately. Instead, it delays for a preset m bit cycles before forwarding the same command frame to the next-level chip. Here, m is a positive integer, for example, 5. In this embodiment, the downstream chip delays forwarding the command frame sent by the upstream chip, passing it step by step in a pipeline manner, ensuring that each downstream chip in the chip chain receives the complete command frame sequentially. By setting a fixed forwarding delay, signal contention caused by differences in processing time within the chips can be effectively avoided, ensuring that command frames do not overlap or get lost in the long chain.

[0030] The downlink delayed forwarding mechanism in this embodiment allows each chip to perform necessary parsing or preparation operations while receiving the command frame, without waiting for the entire command frame to be transmitted. Simultaneously, fixed-delay forwarding avoids bit errors caused by signal reflection or timing misalignment in multi-stage cascading, ensuring that the command frame can reliably penetrate the entire daisy chain and preventing command interruptions. This improves the transmission efficiency of downlink commands and the reliability of downlink command transmission through the daisy chain.

[0031] S102. The downstream chip sends data back to the upstream chip according to the instruction frame. It stops after completing every n bits of data. When the upstream chip detects that its own FIFO buffer depth is less than or equal to n bits, it sends a handshake signal to the downstream chip. After receiving the handshake signal, the downstream chip continues to send the next n bits of data, where n is a positive integer.

[0032] The FIFO cache depth refers to the amount of data that has been stored but not yet read.

[0033] Specifically, during the uplink data transmission phase, the downstream chip transmits data back to the upstream chip according to the requirements of the received instruction frame, such as the collected voltage or temperature values. To avoid FIFO buffer overflow or emptying of the upstream chip due to mismatched transmit and receive rates, a flow control mechanism combining segmented transmission and handshake signals is adopted. Specifically, after the downstream chip completes the transmission of n bits of data, it actively stops transmission, where n is a positive integer, for example, 32. At the same time, the upstream chip continuously monitors the current depth of its own FIFO buffer (First In First Out buffer). When the upstream chip detects that the FIFO buffer depth is less than or equal to n bits, it means that the buffer still has enough space to receive the next segment of data, so it sends a handshake signal to the downstream chip. After receiving the handshake signal, the downstream chip resumes transmission and continues to send the next segment of n bits of data. The above process is repeated until all data has been transmitted back.

[0034] In one specific implementation, such as Figure 2 The diagram illustrates the state cycle of a communication cycle. The communication cycle state refers to the sequential timing stages that each chip in the daisy-chain system experiences during a complete data exchange. Three states are identified: Idle, Command, and Confirmation. The Idle state begins upon power-on or reset; when a command is needed, the state transitions to the Command state; after the command frame transmission is complete, the state automatically transitions to the Confirmation state for uplink data transmission; after the Confirmation state ends, the state returns to the Idle state, awaiting the next communication task.

[0035] During the command phase, the data length 'n' for segmented transmission can be set to 32 bits. This means that the downstream chip actively stops transmission after sending each 32-bit segment and waits for a handshake signal from the upstream chip. The upstream chip continuously monitors its FIFO buffer depth. When this depth is less than or equal to 32 bits, it sends a handshake signal to the downstream chip. Upon receiving the signal, the downstream chip continues sending the next 32-bit segment until all confirmed data converges at the upstream chip. During idle periods, each chip can enter a low-power standby mode, while maintaining basic clock synchronization through a specific idle waveform.

[0036] In another specific implementation, such as Figure 3 The diagram shows the waveform of the data return structure. In the diagram, chip_0 represents the master control chip or the upstream chip, and chip_1, chip_2, and chip_3 are the downstream chips in sequence. During the downlink command transmission phase, chip_0 broadcasts a command frame downstream, and each chip receives and forwards the command sequentially. During the uplink data return phase, chip_3 first sends its own confirmation data (confirmation3) upstream; after receiving confirmation3, chip_2 merges it with its own generated confirmation2 and forwards it upstream; chip_1 similarly forwards the received confirmation2, confirmation3, and its own generated confirmation1; finally, chip_0 obtains the confirmation data from all chips. When chip_3 sends confirmation3, it follows the... Figure 2 The segmentation rule in the chip involves pausing after sending every n bits to wait for the handshake signal from chip_2; chip_2 performs the same operation during the forwarding process.

[0037] Understandably, this embodiment improves the transmission reliability of uplink confirmation data in long chain cascading by segmented transmission and FIFO depth-based handshake feedback, avoiding FIFO overflow or read-empty problems caused by mismatch in transmit and receive rates, and ensuring that the confirmation data of each chip can be completely aggregated to the main control end.

[0038] This embodiment effectively solves the FIFO overflow or read-empty problem caused by clock frequency offset or processing speed differences between upstream and downstream chips by dividing the returned data into fixed-length data segments and introducing handshake feedback based on the remaining FIFO depth after each segment. The upstream chip always requests the next data segment when the buffer is sufficient, thus avoiding data overwriting or loss; the downstream chip does not send data blindly, ensuring the reliability and stability of the return process. Compared with the continuous transmission method without flow control, it improves the robustness of large-capacity data transmission.

[0039] S103. Each chip divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase, and starts a counter in response to the Manchester code signal transition during the valid edge phase.

[0040] S104. During the invalid edge phase, if a Manchester code signal transition is detected, it is determined that the current bit is the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches the preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared.

[0041] The effective edge phase refers to the transition edge of the Manchester code signal at the middle of the bit period, which is used to determine the value of the current bit; the invalid edge phase refers to the time period between two adjacent effective edges, and the transition situation during this period reflects the relationship between the bit values ​​before and after.

[0042] The preset timeout threshold refers to the maximum count value that the counter is allowed to reach when no Manchester code signal transition is detected within the invalid edge phase. Its specific value can be determined based on the system clock frequency and the Manchester code bit period.

[0043] Specifically, in terms of physical layer decoding, each chip performs a decoding method based on edge characteristics and counter calibration on the received Manchester code signal. Specifically, each chip divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase. When a chip detects a transition in the Manchester code signal during the valid edge phase, it starts a counter to measure the time elapsed since that valid edge, in order to determine whether the duration of the invalid edge phase has reached a preset timeout threshold. If a signal transition is detected within the invalid edge phase, the current bit is immediately determined to be the same as the previous bit, and the counter is reset to zero; if no signal transition is detected and the counter value reaches the preset timeout threshold, the current bit is determined to be the opposite of the previous bit, and the counter is reset to zero.

[0044] It should be understood that the aforementioned counter is reset to zero after each decision, whether through transition detection or timeout, thus recalibrating the timing start point for each bit cycle. Since the reset operation occurs within each bit cycle, any timing errors caused by clock frequency offset will not propagate to the next bit cycle, ensuring that the error window does not exceed half a bit cycle. Therefore, even if there is no shared clock between chips and a large frequency deviation exists, the decoding error rate can be effectively suppressed.

[0045] This embodiment eliminates the bit-by-bit error accumulation phenomenon in traditional schemes by dividing each bit period into valid and invalid edges and using the transition state of the invalid edge for real-time decision-making and counter clearing, thus improving the tolerance to clock frequency offset. This significantly reduces the clock accuracy requirements of daisy-chain communication systems, enabling error-free communication even when each chip uses low-cost, low-precision internal RC oscillators. Furthermore, this decoding method eliminates the need for phase-locked loops or complex preamble synchronization sequences, reducing chip material costs and power consumption. This enhances the robustness, reliability, and cost-effectiveness of daisy-chain communication.

[0046] For example, assuming the bit period of the Manchester code signal is T, the counter counts in units of the chip's local clock period. If the local clock frequency is 16 times the transmitting clock frequency, then ideally, half a bit period corresponds to a count value of 8, and a complete bit period corresponds to a count value of 16. When there is no transition within the invalid edge phase, it indicates that the two bit values ​​are different. In this case, the chip will determine the opposite value when the count value reaches a preset timeout threshold (e.g., 16, i.e., a complete bit period) and reset the counter to zero. This timeout threshold is located in the latter half of the current bit period.

[0047] In summary, the daisy-chain communication method provided by this invention improves the transmission efficiency of instruction frames in a multi-level chip chain by delaying the forwarding of instruction frames by a preset m bit cycles during the downlink instruction transmission phase. This ensures that downlink commands can reliably penetrate the entire daisy chain without interruption, while avoiding bit errors caused by signal reflection or timing misalignment. During the uplink data return phase, the downstream chip actively pauses and waits for a handshake signal from the upstream chip after completing every n bits of data. The upstream chip decides whether to send a handshake signal based on its own FIFO buffer depth. This segmented transmission and handshake flow control solve the FIFO depth drift problem caused by inconsistent transmit and receive rates in multi-chip cascading, ensuring that data return does not result in packet loss or overflow, and improving the stability and integrity of uplink transmission. During the decoding phase at the receiving end, each chip divides each bit cycle of the received Manchester code signal into a valid edge phase and an invalid edge phase. A counter is started in response to a valid edge transition, and during the invalid edge phase, the relationship between the current bit and the previous bit is determined based on whether the Manchester code signal transitions, with the counter being reset after each determination. This decoding mechanism ensures that the error window does not exceed half a bit cycle, eliminating the bit-by-bit accumulation phenomenon in traditional schemes, thereby significantly improving the tolerance to inter-chip clock frequency offset. It achieves low cost, high robustness, and high reliability in daisy-chain communication.

[0048] In some embodiments of the present invention, step S103 includes: determining the transition edge of the Manchester code signal at the middle position of the bit period as the effective edge phase; and determining the time period between two adjacent effective edge phases in the Manchester code signal as the invalid edge phase.

[0049] Specifically, the effective edge phase refers to the phase in which a transition occurs in the middle of the bit period of the Manchester code signal. This transition edge is an inherent feature of Manchester code and is used to distinguish the value of the current bit. The ineffective edge phase is the time interval between two adjacent effective edge phases. This time interval may or may not contain transitions at bit boundaries, depending on the difference between the values ​​of the two consecutive bits.

[0050] Understandably, this embodiment clearly divides each bit period in the data signal into a valid edge phase and an invalid edge phase, allowing subsequent decoding operations to utilize these two phases for different processing: the valid edge phase is used to determine the starting reference for the bit value, and the invalid edge phase is used to detect whether the bit value has changed. This phase division improves the timing consistency of the decoding process and the operability of the hardware implementation.

[0051] In some embodiments of the present invention, the rising edge of the Manchester code signal in the effective edge phase corresponds to a bit value of 1, and the falling edge corresponds to a bit value of 0; in the invalid edge phase, if a Manchester code signal transition is detected, it is determined that the current bit is the same as the previous bit; if no Manchester code signal transition is detected, it is determined that the current bit is different from the previous bit.

[0052] The effective edge phase refers to the forced transition edge that occurs in the middle of each bit period of the Manchester code signal. The direction of this transition edge determines the value of the current bit: a rising edge indicates that the current bit value is logic 1, and a falling edge indicates that the current bit value is logic 0.

[0053] Specifically, during the invalid edge phase, if the current bit value is the same as the previous bit value, the Manchester code signal will undergo an additional transition during this phase, located at the bit boundary; if the current bit value is different from the previous bit value, no transition will occur during the invalid edge phase, and the signal will remain at a constant level. Specifically, the rules for determining the valid edge phase are: a rising edge (0→1) at the middle of a bit indicates a bit value of 1, and a falling edge (1→0) indicates a bit value of 0; the rules for determining the invalid edge phase are: if the next bit value is the same as the current bit value, a Manchester code signal transition will occur during the invalid edge phase; if the next bit value is different from the current bit value, there will be no Manchester code signal transition during the invalid edge phase.

[0054] As an example, when two consecutive bit values ​​are both 1, the valid edge phase is represented by a rising edge. Subsequently, in the invalid edge phase (i.e., the bit boundary), the signal will jump from a high level to a low level, forming a falling edge. This falling edge can be used as the basis for determining whether the current bit is the same as the previous bit. When the two consecutive bit values ​​are 1 and 0, the middle of the first bit cycle is a rising edge, and the middle of the second bit cycle is a falling edge. During the invalid edge phase between the two valid edges, the signal remains at a high level without any transition. Based on this, it can be determined that the current bit is different from the previous bit.

[0055] Understandably, this embodiment decomposes the Manchester code signal into two stages: a valid edge and an invalid edge, and establishes clear correspondence rules between the transition direction and the bit value, and between the invalid edge transition and the bit value change. This allows the receiver to complete the decoding decision simply by the presence and direction of the signal transition, without relying on precise period counting or complex synchronization algorithms. This improves the frequency offset resistance and real-time performance of Manchester decoding, while reducing the requirements for the accuracy of the chip's internal oscillator.

[0056] In one specific implementation, such as Figure 4 The diagram shows the waveforms of the Manchester code half-cycle sampling decoding and clock recovery mechanism. The diagram clearly indicates the positional relationship between the valid and invalid edge phases, as well as the transition patterns of the invalid edge phase under different bit combinations. Specifically, two consecutive 1 data bits exhibit a falling edge transition in the invalid edge phase, while there is no transition when a 1 is followed by a 0. The `data` waveform represents the original Manchester code signal received by the chip, the `clk` waveform represents the locally recovered reference clock, and the counter waveform represents the change in the internal counter value. When receiving the `data` signal, each chip extracts the transition edge at the midpoint of each bit cycle as the valid edge; the continuous interval between two adjacent valid edges constitutes the invalid edge phase.

[0057] by Figure 4 Taking the data waveform as an example, the transitions at the bit cycle boundaries are uncertain, but there must be one transition in the middle of each bit cycle; this transition is defined as the valid edge phase. The complete interval between two valid edges is defined as the invalid edge phase. The clk signal is used to drive the counter, causing it to start timing at each valid edge transition and continuously accumulate during the invalid edge phase. The chip decomposes the Manchester code signal into two timing intervals with different functions, providing a clear time reference for subsequent bit decision and clock calibration.

[0058] In some embodiments of the present invention, the time corresponding to the preset timeout threshold is located in the second half of the current bit period.

[0059] In some embodiments of the present invention, the time corresponding to the preset timeout threshold is located at 2 / 3 of the bit period at the start time of the current bit period.

[0060] Specifically, since the valid edge of the Manchester code is located in the middle of the bit period, the invalid edge phase covers the period from after the valid edge to before the next valid edge. Furthermore, when the two bit values ​​are different, there is no transition in the invalid edge phase, and the duration is exactly half a bit period. Therefore, the timeout threshold is set in the second half of the period to ensure that a decision can be made at a reasonable time when there is no transition, while avoiding the misjudgment of noise as a valid edge due to premature decision.

[0061] Furthermore, the preset timeout threshold is specifically set to 2 / 3 of a bit cycle relative to the start time of the bit. For example, if the local clock frequency is 24 times the transmitting clock frequency, then one bit cycle corresponds to 24 local clock cycles, and half a bit cycle corresponds to 12 cycles. In this case, the timeout threshold can be set to 16 clock cycles, which is approximately 2 / 3 of a bit cycle. This value is easy to implement in engineering practice and can tolerate a certain range of clock frequency deviation. Even if there is a ±2% deviation between the upstream and downstream chip clocks, the timeout decision can still stably fall within the correct half-cycle window.

[0062] Understandably, this embodiment improves the accuracy of decision-making in the absence of transitions by limiting the timeout threshold to the latter half of the cycle, optimizing it to 2 / 3 of a bit cycle. This setting avoids misjudging noise before the valid edge as a transition due to an early threshold, and also avoids missing the valid edge of the next bit due to an late threshold, thus ensuring the robustness of Manchester decoding in frequency offset environments.

[0063] In some embodiments of the present invention, when the downstream chip transmits data back, there is a delay of m bit cycles, and the depth of the FIFO buffer is n+m bits.

[0064] Specifically, the downstream chip also delays data transmission by m bit cycles to maintain timing coordination across the entire link. Through this segmented flow control mechanism, even if there is a frequency offset between the clocks of the upstream and downstream chips, the FIFO depth can be dynamically adjusted to prevent overflow or empty reads, thus ensuring the integrity and reliability of the upstream data.

[0065] The start time of the uplink backhaul is shifted m bit cycles backward relative to the reception time of the downlink command. This symmetrical delay mechanism ensures that the data transmission and reception timing of each chip in the entire daisy chain remains coordinated.

[0066] By combining the m-bit periodic delay during downlink instruction forwarding, the pattern of FIFO buffer depth variation can be derived.

[0067] Continue with Figure 3Taking an example, the downstream chip pauses after transmitting n bits of data, and the upstream chip begins receiving and storing this data after a delay of m bit cycles. Since both upstream and downstream chips have the same m-bit cycle delay, and each transmitted data segment is n bits long, the upstream chip's FIFO buffer always maintains a stable amount of n+m bits of data. Here, m bits are used to compensate for the physical transmission and processing delays between chips, and n bits represent the currently received data segment. As long as n and m are positive integers, such as n=32 and m=5, the FIFO depth is dynamically maintained at approximately 37 bits.

[0068] It's important to note that the depth value n+m is not a fixed absolute value, but rather refers to the FIFO buffer depth fluctuating around n+m under stable operating conditions, but it will not fall below n bits nor grow indefinitely. Because the downstream chip must wait for a handshake signal after sending every n bits, while the upstream chip immediately sends a handshake signal when the FIFO depth drops to n bits, the lower limit of the depth is clamped at n bits. Simultaneously, because the upstream chip continuously reads data from the FIFO at the same rate, the upper limit of the depth will not exceed n+m bits.

[0069] Understandably, this embodiment achieves automatic balancing of FIFO buffer depth in multi-chip cascade scenarios by setting the same delay m-bit period and directly associating the data length n of segmented transmission with FIFO depth. This effectively prevents FIFO overflow or empty reading caused by clock frequency offset or processing speed differences, and improves the reliability and stability of uplink data backhaul.

[0070] Accordingly, embodiments of this application also provide a daisy-chain communication system, including multiple chips cascaded together in a daisy-chain manner, each chip including: The transmitting module is used to send data to downstream or upstream chips. The receiving module is used to receive data from upstream or downstream chips; The FIFO caching module is used to cache received data; The control module, connected to the sending module, the receiving module, and the FIFO buffer module, is used to control the downstream chip to forward the instruction frame downstream after a preset delay of m bit periods when receiving the instruction frame sent by the upstream chip; control the downstream chip to send data back to the upstream chip, stopping after every n bits of data are completed, and controlling the downstream chip to continue sending the next n bits of data based on the handshake signal triggered by the upstream chip detecting its own FIFO buffer depth. The receiving module integrates a Manchester decoding unit, which divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase; in response to a Manchester code signal transition during the valid edge phase, a counter is started; during the invalid edge phase, if a Manchester code signal transition is detected, it is determined that the current bit is the same as the previous bit and the counter is cleared; otherwise, when the counter value reaches a preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared.

[0071] Specifically, a daisy-chain communication system includes multiple chips cascaded together in a daisy-chain manner, such as... Figure 5 The diagram shows the structure of the chip. Each chip includes a transmitting module 501, a receiving module 502, a FIFO buffer module 503, a control module 504, and a Manchester decoding unit 505 integrated in the receiving module 502.

[0072] The transmitting module 501 is used to send data to downstream or upstream chips. When transmitting downlink commands, the transmitting module 501 forwards the command frame to the next-level chip in the form of Manchester code differential signal; when transmitting uplink data back, the transmitting module 501 sends the data collected by this chip or the data forwarded from downstream to upstream.

[0073] The receiving module 502 is used to receive Manchester code differential signals from upstream or downstream chips and convert them into digital signals for subsequent processing. The receiving module 502 integrates a Manchester decoding unit 505, which is responsible for extracting clock and data from the Manchester code signal.

[0074] The FIFO buffer module 503 is used to buffer data that has been decoded by the receiving module 502 but has not yet been read by the control module 504. FIFO stands for First-In-First-Out queue, and its depth represents the maximum number of bits of data that can be stored. For example, a FIFO with a depth of 64 bits can be configured.

[0075] The control module 504 is connected to the transmitting module 501, the receiving module 502, and the FIFO buffer module 503. This control module 504 is responsible for implementing the timing control and segmented handshake mechanism for data forwarding. Specifically, the control module 504 performs the following operations: In the downlink direction, when the receiving module 502 of this chip receives a command frame sent by the upstream chip, the control module 504 controls the transmitting module 501 to delay by a preset m bit periods before forwarding the same command frame to the downstream chip. In the uplink direction, the control module 504 controls the transmitting module 501 of this chip to actively stop transmission after completing the return of n bits of data; simultaneously, the control module 504 reads the status fed back by the upstream chip (which is the receiving end for the downstream chip) through the handshake signal line in real time. When it detects a handshake signal issued by the upstream chip when the remaining FIFO depth is less than or equal to n bits, it controls the transmitting module 501 to resume transmission and continue sending the next segment of n bits of data.

[0076] The Manchester decoding unit 505 is configured to perform the same Manchester decoding and counter clearing operations as in the aforementioned method embodiments. The specific operation of this unit has been described in detail in the above embodiments and will not be repeated here.

[0077] To better implement the daisy-chain communication method in this invention embodiment, based on the daisy-chain communication method, correspondingly, as follows: Figure 6 As shown, this embodiment of the invention also provides a daisy-chain communication device. The daisy chain includes multiple chips connected sequentially in an upstream and downstream order, with the chips transmitting data bidirectionally in Manchester code via differential signal lines. The device includes: The forwarding unit 601 is used to forward the instruction frame to the next-level chip of the downstream chip after a preset delay of m bit periods when the downstream chip receives the instruction frame sent by the upstream chip, where m is a positive integer. The sending unit 602 is used for the downstream chip to send data back to the upstream chip according to the instruction frame. The transmission stops after each n bits of data are completed. When the upstream chip detects that its own FIFO buffer depth is less than or equal to n bits, it sends a handshake signal to the downstream chip. After receiving the handshake signal, the downstream chip continues to send the next n bits of data, where n is a positive integer. The first communication unit 603 is used to divide each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase for each chip, and to start a counter in response to the Manchester code signal transition in the valid edge phase. The second communication unit 604 is used to determine that the current bit is the same as the previous bit and clear the counter if a Manchester code signal transition is detected during the invalid edge phase; otherwise, when the counter value reaches a preset timeout threshold, determine that the current bit is opposite to the previous bit and clear the counter.

[0078] The daisy-chain communication device 600 provided in the above embodiments can realize the technical solutions described in the above daisy-chain communication method embodiments. The specific implementation principles of each module or unit can be found in the corresponding content in the above daisy-chain communication method embodiments, and will not be repeated here.

[0079] Accordingly, embodiments of this application also provide an upstream chip for the daisy chain, such as... Figure 7 The diagram shown illustrates the structure of the upstream chip in a daisy chain. The upstream chip in a daisy chain includes: The first receiving module 701 is used to receive data transmitted back from the downstream chip. The first receiving module 701 integrates a first Manchester decoding unit 705. The first Manchester decoding unit 705 is used to divide each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase. In response to the Manchester code signal transition in the valid edge phase, a counter is started. If a Manchester code signal transition is detected in the invalid edge phase, it is determined that the current bit is the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches a preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared. Cache module 702 is used to cache the data transmitted back after being decoded by the first receiving module 701; The first sending module 703 is used to send instruction frames to downstream chips and to send handshake signals to downstream chips. The first control module 704 is connected to the FIFO buffer module 702 and the first sending module 703. It is used to detect the depth of the FIFO buffer module 702. When the depth is less than or equal to a preset n bits, the first sending module 703 sends the handshake signal to the downstream chip, where n is a positive integer.

[0080] Specifically, for the specific implementation of the upstream chip in the daisy chain of this embodiment, please refer to the relevant descriptions of uplink data backhaul and Manchester decoding in the aforementioned method embodiments, which will not be repeated here.

[0081] The beneficial effects that the upstream chip of the daisy chain in this embodiment can achieve are also described in the above description, and will not be repeated here.

[0082] Accordingly, embodiments of this application also provide a downstream chip of the daisy chain, such as... Figure 8The diagram shown illustrates the structure of a downstream chip in a daisy chain. The downstream chip includes: The second receiving module 801 is used to receive instruction frames and handshake signals from the upstream chip. The second receiving module 801 integrates a second Manchester decoding unit 804. The second Manchester decoding unit 804 is used to divide each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase. In response to the Manchester code signal transition in the valid edge phase, a counter is started. If a Manchester code signal transition is detected in the invalid edge phase, it is determined that the current bit is the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches a preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared. The second sending module 802 is used to send data back to the upstream chip and to forward the instruction frame to the next level chip. The second control module 803, connected to the second receiving module 801 and the second sending module 802, is used to control the second sending module 802 to forward the instruction frame to the next-level chip after a preset delay of m bit periods when the second receiving module 801 receives the instruction frame, where m is a positive integer; the second control module 803 is also used to control the second sending module 802 to stop transmission after completing n bits of data return and wait for the handshake signal, and when the second receiving module 801 receives the handshake signal, control the second sending module 802 to continue sending the next n bits of data, where n is a positive integer.

[0083] Specifically, for the specific implementation of the downstream chip in this embodiment of the daisy chain, please refer to the relevant descriptions of downlink delayed forwarding, uplink segmented backhaul, and Manchester decoding in the aforementioned method embodiments, which will not be repeated here.

[0084] The beneficial effects that the downstream chip of the daisy chain in this embodiment can achieve are also described in the above description, and will not be repeated here.

[0085] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware (such as a processor, controller, etc.), and the computer program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0086] The daisy-chain communication method, system, device, and chip provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A daisy-chain communication method, characterized in that, The daisy chain comprises multiple chips connected sequentially in an upstream-downstream order, with upstream and downstream chips connected in a downstream-upstream sequence. The chips transmit data bidirectionally in Manchester code via differential signal lines. The method includes: When the downstream chip receives the instruction frame sent by the upstream chip, it forwards the instruction frame to the next-level chip of the downstream chip after a preset delay of m bit periods, where m is a positive integer. The downstream chip sends data back to the upstream chip according to the instruction frame. It stops after completing every n bits of data. When the upstream chip detects that its own FIFO buffer depth is less than or equal to n bits, it sends a handshake signal to the downstream chip. After receiving the handshake signal, the downstream chip continues to send the next n bits of data, where n is a positive integer. Each chip divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase, and starts a counter in response to the Manchester code signal transition during the valid edge phase. During the invalid edge phase, if a Manchester code signal transition is detected, the current bit is determined to be the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches the preset timeout threshold, the current bit is determined to be opposite to the previous bit and the counter is cleared.

2. The daisy-chain communication method according to claim 1, characterized in that, Each chip divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase, including: The transition edge of the Manchester code signal at the middle of the bit period is determined as the effective edge phase; The time interval between two adjacent valid edge phases in the Manchester code signal is defined as the invalid edge phase.

3. The daisy-chain communication method according to claim 1, characterized in that, The Manchester code signal has a bit value of 1 for the rising edge and a bit value of 0 for the falling edge during the effective edge phase. During the invalid edge phase, if a Manchester code signal transition is detected, the current bit is determined to be the same as the previous bit; if no Manchester code signal transition is detected, the current bit is determined to be different from the previous bit.

4. The daisy-chain communication method according to claim 1, characterized in that, The time corresponding to the preset timeout threshold is located in the second half of the current bit period.

5. The daisy-chain communication method according to claim 4, characterized in that, The preset timeout threshold corresponds to a time that is 2 / 3 of the bit period at the start of the current bit period.

6. The daisy-chain communication method according to claim 1, characterized in that, When the downstream chip sends back data, there is a delay of m bit cycles, and the depth of the FIFO buffer is n+m bits.

7. An upstream chip in a daisy chain, characterized in that, include: The first receiving module is used to receive data transmitted back from the downstream chip. The first receiving module integrates a first Manchester decoding unit. The first Manchester decoding unit is used to divide each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase. In response to the Manchester code signal transition in the valid edge phase, the counter is started. If a Manchester code signal transition is detected in the invalid edge phase, it is determined that the current bit is the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches a preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared. The caching module is used to cache the data transmitted back after being decoded by the first receiving module; The first sending module is used to send instruction frames to downstream chips and to send handshake signals to downstream chips. The first control module, connected to the FIFO buffer module and the first sending module, is used to detect the depth of the FIFO buffer module. When the depth is less than or equal to a preset n bits, the first sending module sends the handshake signal to the downstream chip, where n is a positive integer.

8. A downstream chip in a daisy chain, characterized in that, include: The second receiving module is used to receive instruction frames and handshake signals from the upstream chip. The second receiving module integrates a second Manchester decoding unit. The second Manchester decoding unit is used to divide each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase. In response to the Manchester code signal transition in the valid edge phase, the counter is started. If a Manchester code signal transition is detected in the invalid edge phase, it is determined that the current bit is the same as the previous bit and the counter is cleared. Otherwise, when the counter value reaches the preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared. The second sending module is used to send data back to the upstream chip and to forward the instruction frame to the next-level chip. The second control module, connected to the second receiving module and the second sending module, is used to control the second sending module to forward the instruction frame to the next-level chip after a preset delay of m bit periods when the second receiving module receives the instruction frame, where m is a positive integer; the second control module is also used to control the second sending module to stop transmission after completing n bits of data return and wait for the handshake signal, and when the second receiving module receives the handshake signal, control the second sending module to continue sending the next n bits of data, where n is a positive integer.

9. A daisy-chain communication system, characterized in that, It includes multiple chips cascaded together in a daisy-chain manner, each chip comprising: The transmitting module is used to send data to downstream or upstream chips. The receiving module is used to receive data from upstream or downstream chips; The FIFO caching module is used to cache received data; The control module, connected to the sending module, the receiving module, and the FIFO buffer module, is used to control the downstream chip to forward the instruction frame downstream after a preset delay of m bit periods when receiving the instruction frame sent by the upstream chip; control the downstream chip to send data back to the upstream chip, stopping after every n bits of data are completed, and controlling the downstream chip to continue sending the next n bits of data based on the handshake signal triggered by the upstream chip detecting its own FIFO buffer depth. The receiving module integrates a Manchester decoding unit, which divides each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase; in response to a Manchester code signal transition during the valid edge phase, a counter is started; during the invalid edge phase, if a Manchester code signal transition is detected, it is determined that the current bit is the same as the previous bit and the counter is cleared; otherwise, when the counter value reaches a preset timeout threshold, it is determined that the current bit is opposite to the previous bit and the counter is cleared.

10. A daisy-chain communication device, characterized in that, The daisy chain comprises multiple chips connected sequentially in an upstream-downstream order, with upstream and downstream chips connected in a downstream-upstream sequence. The chips transmit data bidirectionally in Manchester code via differential signal lines. The device includes: The forwarding unit is used to forward the instruction frame to the next-level chip of the downstream chip after a preset delay of m bit periods when the downstream chip receives the instruction frame sent by the upstream chip, where m is a positive integer. The sending unit is used for the downstream chip to send data back to the upstream chip according to the instruction frame. It stops after completing every n bits of data. When the upstream chip detects that its own FIFO buffer depth is less than or equal to n bits, it sends a handshake signal to the downstream chip. After receiving the handshake signal, the downstream chip continues to send the next n bits of data, where n is a positive integer. The first communication unit is used for each chip to divide each bit period of the received Manchester code signal into a valid edge phase and an invalid edge phase, and to start a counter in response to the Manchester code signal transition in the valid edge phase. The second communication unit is used to determine that the current bit is the same as the previous bit and clear the counter if a Manchester code signal transition is detected during the invalid edge phase; otherwise, when the counter value reaches a preset timeout threshold, determine that the current bit is opposite to the previous bit and clear the counter.

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