Semiconductor memory device

Abstract

A semiconductor memory device can include a substrate, a plurality of semiconductor patterns extending in a first horizontal direction on the substrate, the plurality of semiconductor patterns spaced apart from each other in a vertical direction, a first contact connected to the plurality of semiconductor patterns, the first contact extending in the vertical direction through the plurality of semiconductor patterns, a bit line on the first contact in the vertical direction, the bit line extending in a second horizontal direction crossing the first horizontal direction, a word line surrounding the plurality of semiconductor patterns, the word line extending in the first horizontal direction, and a second contact spaced apart from the first contact in the first horizontal direction, the second contact extending in the vertical direction through the plurality of semiconductor patterns, wherein the second contact includes a metal, and the first contact includes a main layer including doped polysilicon.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2025-0013932, filed on February 4, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor memory device, and more specifically, to a three-dimensional (3D) semiconductor memory device. Background Technology

[0004] The demand for compact, multifunctional, and high-performance electronic products necessitates high-capacity semiconductor memory devices. To provide these high-capacity devices, increased integration density is required. Therefore, 3D semiconductor memory devices have been proposed, which increase memory capacity by stacking memory cells on a substrate in a vertical direction. Summary of the Invention

[0005] According to some embodiments of this disclosure, a 3D semiconductor memory device with increased integration density is provided.

[0006] According to one aspect of this disclosure, a semiconductor memory device may include: a substrate; a plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; a first contact connected to the plurality of semiconductor patterns and extending through the plurality of semiconductor patterns in a vertical direction; a bit line on the first contact in a vertical direction and extending in a second horizontal direction intersecting the first horizontal direction; a word line surrounding the plurality of semiconductor patterns and extending in the first horizontal direction; and a second contact spaced apart from the first contact in the first horizontal direction and extending through the plurality of semiconductor patterns in a vertical direction, wherein the second contact includes a metal, and the first contact includes a master layer comprising doped polysilicon.

[0007] According to one aspect of this disclosure, a semiconductor memory device may include: a substrate; a plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; a first contact connected to the plurality of semiconductor patterns and extending through the plurality of semiconductor patterns in a vertical direction; a bit line on the first contact in a vertical direction and extending in a second horizontal direction intersecting the first horizontal direction; a word line surrounding the plurality of semiconductor patterns and extending in the first horizontal direction; and a second contact spaced apart from the first contact in the first horizontal direction and extending through the plurality of semiconductor patterns in a vertical direction, wherein the first contact includes a first master layer, the second contact includes a second master layer, and each of the first master layer and the second master layer includes doped polysilicon.

[0008] According to one aspect of this disclosure, a semiconductor memory device may include: a substrate; a plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; a first contact connected to the plurality of semiconductor patterns and extending through the plurality of semiconductor patterns in a vertical direction; a bit line on the first contact in a vertical direction and extending in a second horizontal direction intersecting the first horizontal direction; a word line surrounding the plurality of semiconductor patterns and extending in the first horizontal direction; and a second contact spaced apart from the first contact in the first horizontal direction and extending through the plurality of semiconductor patterns in a vertical direction, wherein the first contact comprises a metal, and a junction of the first contact is formed by using a boron (B) vapor-phase doping process.

[0009] According to one aspect of this disclosure, a method of manufacturing a semiconductor memory device may include: forming a plurality of semiconductor patterns extending in a first horizontal direction on a substrate, the plurality of semiconductor patterns being spaced apart from each other in a vertical direction; forming a first contact connected to the plurality of semiconductor patterns and extending through the plurality of semiconductor patterns in the vertical direction; forming a bit line on the first contact in the vertical direction, the bit line extending in a second horizontal direction intersecting the first horizontal direction; forming a word line surrounding the plurality of semiconductor patterns and extending in the first horizontal direction; forming a second contact spaced apart from the first contact in the first horizontal direction and extending through the plurality of semiconductor patterns in the vertical direction, wherein the second contact comprises a metal, and the first contact comprises a master layer comprising doped polysilicon.

[0010] According to one aspect of this disclosure, the main layer includes a dopant, which includes boron (B).

[0011] According to one aspect of this disclosure, the second contact includes a junction formed during a vapor-phase doping process using boron (B).

[0012] According to one aspect of this disclosure, the first contact also includes a buffer layer surrounding the main layer in a first horizontal direction.

[0013] The aspects and effects of the embodiments of this disclosure are not limited to those mentioned above, and other aspects and effects of the embodiments of this disclosure will be clearly understood by those skilled in the art from the following description. Attached Figure Description

[0014] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 This is a schematic block diagram of a semiconductor memory device according to an embodiment;

[0016] Figure 2 yes Figure 1 Circuit diagram of the cell array region in the diagram;

[0017] Figures 3 to 11 This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device according to an embodiment;

[0018] Figure 12A , Figure 12B and Figure 12C This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device according to an embodiment;

[0019] Figure 13A , Figure 13B and Figure 13C This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device according to an embodiment;

[0020] Figure 14A , Figure 14B and Figure 14C This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device according to an embodiment;

[0021] Figure 15A , Figure 15B and Figure 15C This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device according to an embodiment;

[0022] Figure 16A and Figure 16B This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device according to an embodiment;

[0023] Figure 17A and Figure 17BThis is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device according to an embodiment;

[0024] Figure 18A and Figure 18B This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device according to an embodiment;

[0025] Figure 19A and Figure 19B This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device according to an embodiment;

[0026] Figure 20 This is a schematic diagram of a semiconductor memory device according to an embodiment; and

[0027] Figure 21 This is a schematic diagram of a semiconductor memory device according to an embodiment. Detailed Implementation

[0028] In the following description, non-limiting exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same elements, and redundant descriptions may be omitted.

[0029] Non-limiting exemplary embodiments will be shown in the accompanying drawings and described in detail in the written description. However, this disclosure is not limited to these exemplary embodiments, and it should be understood that all changes, equivalents, and substitutions without departing from the spirit and scope of this disclosure are included in the embodiments of this disclosure. In the description of the embodiments, certain detailed descriptions of the related art may be omitted where it is thought that certain detailed descriptions of the related art may unnecessarily obscure aspects of this disclosure.

[0030] It should be understood that when a component or layer is referred to as being "on," "connected to," or "coupled to" another component or layer, it can be directly on, connected to, or coupled to the other component or layer, or there may be intermediate components or layers. Conversely, when a component or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers.

[0031] Figure 1 This is a schematic block diagram of a semiconductor memory device according to an embodiment.

[0032] refer to Figure 1 The semiconductor memory device 100 may include a cell array region MCA and a peripheral circuit region PCA, wherein the peripheral circuit region PCA is located at a higher vertical level than the cell array region MCA.

[0033] In some embodiments, the cell array region (MCA) can be a dynamic random access memory (DRAM) device, and the peripheral circuit region (PCA) can be the core region or peripheral circuit region of the DRAM device. For example, the PCA may include peripheral circuit transistors that transmit signals and / or power to the memory cell array in the MCA. In embodiments, the peripheral circuit transistors may form various circuits, such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, and data input / output circuits.

[0034] Despite Figure 1 The diagram shows that the peripheral circuit region PCA is at a higher vertical level than the cell array region MCA (e.g., the peripheral circuit region PCA is arranged on top of the cell array region MCA), but the semiconductor memory device 100 can be inverted such that the cell array region MCA is at a higher vertical level than the peripheral circuit region PCA.

[0035] In some embodiments, the peripheral circuit region PCA and the cell array region MCA can be formed on separate wafers and then attached to each other using bonding pads. In some embodiments, after the peripheral circuit region PCA is formed on the peripheral circuit wafer, the cell array region MCA can be formed on the peripheral circuit region PCA.

[0036] Figure 2 yes Figure 1 The circuit diagram of the cell array region MCA in the diagram.

[0037] refer to Figure 2 The cell array region MCA may include multiple sub-cell arrays SCA. The sub-cell arrays SCA may be spaced apart from each other in a second horizontal direction (e.g., the Y direction).

[0038] Each subcell array (SCA) may include multiple bit lines (BL), multiple word lines (WL), and multiple memory cells (MC). Each memory cell (MC) may include a cell transistor (TR) and a cell capacitor (CAP) connected to the cell transistor (TR). Each memory cell (MC) may have a one transistor-one capacitor (1T1C) structure.

[0039] Word lines WL may extend in a second horizontal direction (e.g., the Y direction) and may be spaced apart from each other in a first horizontal direction (e.g., the X direction) and a vertical direction (e.g., the Z direction). Bit lines BL may extend in a vertical direction (e.g., the Z direction) and may be spaced apart from each other in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction). A unit transistor TR may be arranged between a word line WL and a bit line BL.

[0040] The gate of the unit transistor TR can be connected to the word line WL, and the source of the unit transistor TR can be connected to the bit line BL via the first contact DC. The unit transistor TR can be connected to the unit capacitor CAP via the second contact BC. The drain of the unit transistor TR can be connected to the first electrode of the unit capacitor CAP via the second contact BC, and the second electrode of the unit capacitor CAP can be connected to the plate electrode PP.

[0041] In a subcell array (SCA), multiple cell transistors (TRs) can be arranged to overlap each other in the vertical direction (e.g., the Z direction). In a subcell array (SCA), multiple cell capacitors (CAPs) can be arranged to overlap each other in the vertical direction (e.g., the Z direction). A cell transistor (TR) and a cell capacitor (CAP) can be arranged in a line at the same vertical level. Multiple memory cells (MCs) can be stacked in the vertical direction (e.g., the Z direction), each memory cell (MC) including one cell transistor (TR) and one cell capacitor (CAP). The storage capacity of the subcell array (SCA) can vary with the number of memory cells (MCs) stacked in the vertical direction (e.g., the Z direction) (e.g., the number of cell capacitors (CAP)).

[0042] In some embodiments, Figure 2 The first contact DC in the circuit diagram can be a direct contact 150 (see...) Figure 12C ), which is described below. In some embodiments, Figure 2 The second contact BC in the circuit diagram can be a buried contact BC (see Figure 12C ), which is described below.

[0043] Figures 3 to 11 It is shown Figure 1 A cross-sectional view of a portion of the manufacturing process of the cell array region MCA in the image.

[0044] refer to Figure 3 A mode stack MS can be formed by alternating and sequentially forming at least one (e.g., multiple) sacrificial mode layers 112 and at least one (e.g., multiple) semiconductor layers 114 on a substrate 110.

[0045] In some embodiments, substrate 110 may include Si, Ge, or SiGe. In some embodiments, substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0046] In this embodiment, the sacrificial mold layer 112 may include a material that is etch-selective relative to the material of the semiconductor layer 114. For example, the sacrificial mold layer 112 and the semiconductor layer 114 may each comprise a single-crystal layer of a group IV semiconductor, a group IV-IV compound semiconductor, or a group III-V compound semiconductor, and may comprise materials different from each other. For example, the sacrificial mold layer 112 may comprise SiGe, and the semiconductor layer 114 may comprise single-crystal silicon. The sacrificial mold layer 112 and the semiconductor layer 114 may each have a thickness of tens of nanometers (nm).

[0047] In this embodiment, the sacrificial mold layer 112 and the semiconductor layer 114 can be formed epitaxially. For example, epitaxy can include vapor-phase epitaxy (VPE), chemical vapor deposition (CVD) processes (such as ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or combinations thereof. During epitaxy, liquid or gaseous precursors can be used to form the sacrificial mold layer 112 and the semiconductor layer 114.

[0048] In an embodiment, such as Figure 3 As shown, the thickness of the semiconductor layer 114 in the vertical direction (e.g., the Z direction) can be less than the thickness of the sacrificial mold layer 112 in the vertical direction (e.g., the Z direction). In some embodiments, the thickness of the semiconductor layer 114 in the vertical direction (e.g., the Z direction) can be substantially the same as the thickness of the semiconductor pattern AP to be formed in subsequent processes.

[0049] refer to Figure 4 A mask pattern can be formed on a mold stack MS, and a portion of the mold stack MS can be removed by using the mask pattern as an etching mask, thereby forming a mold stack pattern MSP comprising a plurality of semiconductor layer patterns 114P and a plurality of sacrificial mold layer patterns 112P stacked alternately with the semiconductor layer patterns 114P. The semiconductor layer patterns 114P and the sacrificial mold layer patterns 112P can be positioned to overlap each other in a vertical direction (e.g., the Z direction) and can extend in a first horizontal direction (e.g., the X direction).

[0050] refer to Figure 5 The sacrificial mold layer pattern 112P can be removed, and a first gap filling insulation layer 122 can be formed in the space from which the sacrificial mold layer pattern 112P is removed by using an insulating material.

[0051] In an embodiment, the process of removing the sacrificial mold layer pattern 112P may include a wet etching process or a pull-back process. For example, the process of removing the sacrificial mold layer pattern 112P may include an etching process that uses etch selectivity between the sacrificial mold layer pattern 112P and the semiconductor layer pattern 114P. For example, in a wet etching process or a pull-back process, the etching rate of the semiconductor layer pattern 114P may be relatively low, and the etching rate of the sacrificial mold layer pattern 112P may be relatively high.

[0052] Subsequently, a first mask pattern M1 can be formed on the first gap-filling insulating layer 122. Each of the semiconductor layer patterns 114P may include at least one first portion P1 and a second portion P2. The first mask pattern M1 may be arranged to overlap perpendicularly with the second portion P2 of each of the semiconductor layer patterns 114P.

[0053] Subsequently, the portion of the first gap-filling insulating layer 122 not covered by the first mask pattern M1 can be removed, thereby exposing the first portion P1 of each of the semiconductor layer patterns 114P. The second portion P2 of each of the semiconductor layer patterns 114P can be covered by the first gap-filling insulating layer 122 and therefore not exposed. In embodiments, the process of removing a portion of the first gap-filling insulating layer 122 may include a lateral recess process or a pull-back process.

[0054] refer to Figure 6 A first insulating pad 132 and a pre-written word line P140 may be formed on the top and bottom surfaces of each of the semiconductor layer patterns 114P and on the sidewalls of the first portion P1. In some embodiments, the first insulating pad 132 and the pre-written word line P140 may also be formed on the top surface of the substrate 110. In embodiments, the first insulating pad 132 may be formed using at least one selected from silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the pre-written word line P140 may include at least one from Ti, TiN, TiAlC, TiAlN, TiSiN, MoSiN, WN, WSiN, Ta, TaSiN, TaN, LaN, and combinations thereof.

[0055] In some embodiments, a gate insulating layer may be disposed between the pre-word line P140 and the semiconductor layer pattern 114P. The gate insulating layer may include at least one of a ferroelectric material and a high-k dielectric material having a dielectric constant higher than that of silicon oxide. In some embodiments, the gate insulating layer may include at least one of hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PbZrTiO), strontium bismuth tantalate (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0056] refer to Figure 7 Word lines 140 can be formed by removing a portion of the pre-prepared word line P140. In some embodiments, a portion of the pre-prepared word line P140 can be removed by an etching process. When a portion of the pre-prepared word line P140 is removed, the end of a first portion P1 of each of the semiconductor layer patterns 114P can be exposed. In some embodiments, as a portion of the pre-prepared word line P140 is removed, a portion of a first insulating pad 132 covering the top surface of the substrate 110 can be exposed. Figure 7 As shown, the space between the first portions P1 of adjacent semiconductor layer patterns in the semiconductor layer pattern 114P on the top surface of the substrate 110 in the first horizontal direction (e.g., the X direction) can be referred to as the first space H1 and the second space H2.

[0057] refer to Figure 8 A second gap-filling insulating layer 134 may be formed to fill the space surrounded by word lines 140, having a C-shaped cross-section between two adjacent semiconductor layer patterns 114P in the vertical direction (e.g., the Z direction). A second insulating pad 136 may be formed to surround the end portion of the first portion P1 of each of the semiconductor layer patterns 114P and fill the side portions of the first space H1 and the second space H2. During the formation of the second gap-filling insulating layer 134 and the second insulating pad 136, the end portions of the word lines 140 may be removed. In some embodiments, the process of removing the end portions of the word lines 140 may include a lateral recessing process or a pull-back process.

[0058] In some embodiments, when word lines 140 surround portions of the top and bottom surfaces of semiconductor layer pattern 114P, semiconductor memory device 100 may be referred to as a gate-all-around device.

[0059] refer to Figure 9 A mask pattern can be formed on the first gap-filling insulating layer 122, and a second portion P2 of each of the semiconductor layer patterns 114P can be exposed by using the mask pattern as an etching mask to remove a portion of the first gap-filling insulating layer 122. In embodiments, the process of removing a portion of the first gap-filling insulating layer 122 may include a lateral recess process or a pull-back process.

[0060] refer to Figure 10 A third insulating pad 138 and a third gap-filling insulating layer 142 may be sequentially formed on the second portion P2 of each of the semiconductor layer patterns 114P. The third insulating pad 138 may be conformally formed on the sidewalls of the first insulating pad 132 and the exposed surface of the second portion P2 of each of the semiconductor layer patterns 114P, and the third gap-filling insulating layer 142 may be formed on the third insulating pad 138 to surround the second portion P2 of each of the semiconductor layer patterns 114P.

[0061] Subsequently, the third space H3 can be formed by etching the second portion P2 of the semiconductor layer pattern 114P disposed on the central portion of the substrate 110. As the portion of the second portion P2 of the semiconductor layer pattern 114P disposed on the central portion of the substrate 110 is removed, a portion of the top surface of the substrate 110 can be exposed.

[0062] Among the multiple semiconductor layer patterns 114P, the portion of the semiconductor layer pattern 114P remaining after the portion of the second part P2 of the semiconductor layer pattern 114P arranged on the central portion of the substrate 110 is removed can be referred to as the semiconductor pattern AP.

[0063] In some embodiments, the semiconductor pattern AP may include undoped or doped semiconductor materials. In some embodiments, the semiconductor pattern AP may include polycrystalline silicon. In some embodiments, the semiconductor pattern AP may include amorphous metal oxides, polycrystalline metal oxides, or a combination of amorphous metal oxides and polycrystalline metal oxides. For example, the semiconductor pattern AP may include at least one of In-Ga oxide (IGO), In-Zn oxide (IZO), and In-Ga-Zn oxide (IGZO). In some embodiments, the semiconductor pattern AP may include two-dimensional (2D) material semiconductors. For example, 2D material semiconductors may include MoS2, WSe2, graphene, carbon nanotubes, or combinations thereof.

[0064] refer to Figure 11 The insulating structure 144 can be formed at the bottom of each of the first space H1, the second space H2, and the third space H3. The insulating structure 144 can be formed by removing a portion of the substrate 110 and filling the space from which that portion of the substrate 110 has been removed with an insulating material. In an embodiment, the top surface of the insulating structure 144 can be coplanar with the top surface of the substrate 110. During the formation of the insulating structure 144, a portion of the first insulating pad 132 on the substrate 110 can be removed.

[0065] In an embodiment, the insulating structure 144 may be formed using at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0066] Figures 12A to 12C This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device 10 according to an embodiment.

[0067] refer to Figure 12A It can be achieved by forming conformal coverage Figure 11 The sidewall of the first space H1 in the obtained structure (see Figure 11 ) and the sidewalls of the second space H2 (see Figure 11 Each of the buffer layers 154 and forming a main layer 152 that fills the remaining space after the buffer layer 154 is formed (e.g., the remaining portion of the first space H1 and the second space H2) to form a direct contact 150.

[0068] In some embodiments, buffer layer 154 may comprise dopant-free polysilicon, and main layer 152 may comprise dopant-containing polysilicon. The dopant included in main layer 152 may be, for example, boron (B). In some embodiments, the thickness of buffer layer 154 may not be greater than the thickness of main layer 152, but embodiments are not limited thereto.

[0069] In some embodiments, the buffer layer 154 can help control the dopant concentration in the direct contact 150 (see [link]). Figure 12A and 12C ).

[0070] refer to Figure 12BThe third space H3 can be filled with a fourth gap-filling insulating layer 162. A first insulating layer 164, a second insulating layer 166, a bit line 160, and a third insulating layer 168 can be sequentially formed to cover the second gap-filling insulating layer 134, the third gap-filling insulating layer 142, the fourth gap-filling insulating layer 162, the word line 140, the first insulating pad 132, the second insulating pad 136, the third insulating pad 138, and the top surface of the direct contact 150. Specifically, after forming the first insulating layer 164 and the second insulating layer 166, a portion of each of the first insulating layer 164 and the second insulating layer 166 can be removed. The bit line 160, extending in a second horizontal direction (e.g., the Y direction), can be formed in the space from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed, on the direct contact 150. Subsequently, the third insulating layer 168 can be formed around the top surface of the bit line 160 and the top surface of the second insulating layer 166.

[0071] In an embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise oxides.

[0072] In an embodiment, bit line 160 may include doped semiconductor material, conductive metal nitride, metal, or metal semiconductor compound.

[0073] refer to Figure 12C This can remove the fill in the third space H3 (see Figure 12A The fourth gap-filling insulating layer 162 is abutted. In an embodiment, the fourth gap-filling insulating layer 162 can be removed by an etching process. As the fourth gap-filling insulating layer 162 is removed, the top surface of the insulating structure 144 beneath the fourth gap-filling insulating layer 162 can be exposed. During the removal of the fourth gap-filling insulating layer 162, portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can also be removed. Subsequently, a buried contact 170 can be formed in the space where the fourth gap-filling insulating layer 162 and the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed.

[0074] According to some embodiments, vapor phase doping can be performed as a pretreatment before forming the buried contact 170. In some embodiments, vapor phase doping can be performed using B (e.g., B₂H₆). Before forming the buried contact 170, B₂H₆ gas can be injected into a high-temperature environment, allowing B to diffuse from the surface of the semiconductor pattern AP as a dopant. The buried contact 170 can be formed by forming a buried contact junction using a vapor phase doping process, followed by filling the third space H₃ with a metallic material.

[0075] Through the above process, a semiconductor memory device 10 can be manufactured.

[0076] The semiconductor memory device 10 can increase integration density and simplify the process by using a semiconductor pattern AP as the channel layer of a P-channel MOS (PMOS) transistor, wherein the semiconductor pattern AP is vertically stacked to form an N-channel metal-oxide-semiconductor (NMOS) transistor on a substrate 110. Therefore, high-density PMOS transistors can be formed using the remaining space of the substrate 110.

[0077] Figures 13A to 13C This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device 10a according to an embodiment. (See reference) Figures 13A to 13C The semiconductor memory device 10a described and the reference Figures 3 to 12C The semiconductor memory devices 10 described are not mutually exclusive, and identical components are denoted by the same reference numerals. Redundant descriptions of similar components can be omitted below, and the description will primarily focus on semiconductor memory device 10a and... Figures 3 to 12C The differences between the semiconductor memory devices 10.

[0078] refer to Figure 13A ,exist Figure 11 In the resulting structure, the main layer 152 can be formed to completely fill each of the first space H1 and the second space H2. In an embodiment, the main layer 152 may include polysilicon containing a dopant. The dopant included in the main layer 152 may be, for example, B. In this embodiment, the main layer 152 may be a direct contact 150.

[0079] refer to Figure 13B The third space H3 can be filled with a fourth gap-filling insulating layer 162. A first insulating layer 164, a second insulating layer 166, a bit line 160, and a third insulating layer 168 can be sequentially formed to cover the second gap-filling insulating layer 134, the third gap-filling insulating layer 142, the fourth gap-filling insulating layer 162, the word line 140, the first insulating pad 132, the second insulating pad 136, the third insulating pad 138, and the top surface of the direct contact 150. Specifically, after forming the first insulating layer 164 and the second insulating layer 166, a portion of each of the first insulating layer 164 and the second insulating layer 166 can be removed. The bit line 160, extending in a second horizontal direction (e.g., the Y direction), can be formed in the space from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed, on the direct contact 150. Subsequently, the third insulating layer 168 can be formed around the top surface of the bit line 160 and the top surface of the second insulating layer 166.

[0080] In an embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise oxides.

[0081] In an embodiment, bit line 160 may include doped semiconductor material, conductive metal nitride, metal, or metal semiconductor compound.

[0082] refer to Figure 13C This can remove the fill in the third space H3 (see Figure 13A The fourth gap-filling insulating layer 162 is abutted. In an embodiment, the fourth gap-filling insulating layer 162 can be removed by an etching process. As the fourth gap-filling insulating layer 162 is removed, the top surface of the insulating structure 144 beneath the fourth gap-filling insulating layer 162 can be exposed. During the removal of the fourth gap-filling insulating layer 162, portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can also be removed. Subsequently, a buried contact 170 can be formed in the space where the fourth gap-filling insulating layer 162 and the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed.

[0083] According to some embodiments, vapor phase doping can be performed as a pretreatment before forming the buried contact 170. In some embodiments, vapor phase doping can be performed using B (e.g., B₂H₆). Before forming the buried contact 170, B₂H₆ gas can be injected into a high-temperature environment, allowing B to diffuse from the surface of the semiconductor pattern AP as a dopant. The buried contact 170 can be formed by forming a buried contact junction using a vapor phase doping process, followed by filling the third space H₃ with a metallic material.

[0084] Through the above process, semiconductor memory device 10a can be manufactured.

[0085] Semiconductor memory device 10a can be substantially the same as semiconductor memory device 10, except that the buffer layer 154 at each of the opposite sides of the main layer 152 is omitted (see [link]). Figure 12C Therefore, semiconductor memory device 10a can also increase integration density and simplify the process.

[0086] Figures 14A to 14C This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device 10b according to an embodiment. (See reference) Figures 14A to 14C The semiconductor memory device 10b described and the reference Figures 3 to 12C The semiconductor memory devices 10 described are not mutually exclusive, and identical components are denoted by the same reference numerals. Redundant descriptions of similar components can be omitted below, and the description will primarily focus on semiconductor memory device 10b and... Figures 3 to 12CThe differences between the semiconductor memory devices 10.

[0087] refer to Figure 14A The buffer layer 154 can be formed as a conformal cover. Figure 11 The sidewall of the first space H1 in the obtained structure (see Figure 11 ) and the sidewalls of the second space H2 (see Figure 11 Each of the layers, and the main layer 152 can be formed to fill part of the remaining space after the buffer layer 154 is formed.

[0088] In this embodiment, the main layer 152 may not fill the entire remaining space after the buffer layer 154 is formed. In other words, the main layer 152 may not completely fill the first space H1 and the second space H2. Figure 11 Each of the following (in the middle) makes the first gap G1 able to be retained as a gap.

[0089] In one embodiment, buffer layer 154 may comprise polysilicon without dopant, and main layer 152 may comprise polysilicon containing dopant. The dopant included in main layer 152 may be, for example, B.

[0090] refer to Figure 14B The third space H3 can be filled with a fourth gap-filling insulating layer 162. A first insulating layer 164, a second insulating layer 166, a bit line 160, and a third insulating layer 168 can be sequentially formed to cover the top surfaces of the second gap-filling insulating layer 134, the third gap-filling insulating layer 142, the fourth gap-filling insulating layer 162, the word line 140, the first insulating pad 132, the second insulating pad 136, the third insulating pad 138, the main layer 152, and the buffer layer 154. Furthermore, a metal layer 156 can be formed to fill the first gap G1 and be located below the bit line 160. Specifically, after forming the first insulating layer 164 and the second insulating layer 166, a portion of each of the first insulating layer 164 and the second insulating layer 166 can be removed. Subsequently, a filling layer (see...) can be formed to fill the first gap G1 (see...). Figure 14A The main layer 152, buffer layer 154, and metal layer 156 can be formed in a space from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed. Since the main layer 152, buffer layer 154, and metal layer 156 can be collectively referred to as direct contact 150, the bit line 160 can be formed on the direct contact 150. Subsequently, a third insulating layer 168 can be formed around the top surface of the bit line 160 and the top surface of the second insulating layer 166.

[0091] In an embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise oxides.

[0092] In an embodiment, bit line 160 may include doped semiconductor material, conductive metal nitride, metal, or metal semiconductor compound.

[0093] refer to Figure 14C This can remove the fill in the third space H3 (see Figure 14A The fourth gap-filling insulating layer 162 is abutted. In an embodiment, the fourth gap-filling insulating layer 162 can be removed by an etching process. As the fourth gap-filling insulating layer 162 is removed, the top surface of the insulating structure 144 beneath the fourth gap-filling insulating layer 162 can be exposed. During the removal of the fourth gap-filling insulating layer 162, portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can also be removed. Subsequently, a buried contact 170 can be formed in the space where the fourth gap-filling insulating layer 162 and the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed.

[0094] According to some embodiments, vapor phase doping can be performed as a pretreatment before forming the buried contact 170. In some embodiments, vapor phase doping can be performed using B (e.g., B₂H₆). Before forming the buried contact 170, B₂H₆ gas can be injected into a high-temperature environment, allowing B to diffuse from the surface of the semiconductor pattern AP as a dopant. The buried contact 170 can be formed by forming a buried contact junction using a vapor phase doping process, followed by filling the third space H₃ with a metallic material.

[0095] Through the above process, semiconductor memory device 10b can be manufactured.

[0096] refer to Figures 14A to 14C The described semiconductor memory device 10b can be compared with the reference. Figures 12A to 12C The semiconductor memory device 10 described is essentially the same, except that the direct contact 150 is fully formed by filling the space reserved by the main layer 152 that is not filled by the buffer layer 154 with a metal layer 156. Therefore, the semiconductor memory device 10b can also increase integration density and simplify the process.

[0097] Figures 15A to 15C This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device 10c according to an embodiment. (See reference) Figures 15A to 15C The semiconductor memory device 10c described and the reference Figures 3 to 12CThe semiconductor memory devices 10 described are not mutually exclusive, and identical components are denoted by the same reference numerals. Redundant descriptions of similar components can be omitted below, and the description will primarily focus on semiconductor memory device 10c and... Figures 3 to 12C The differences between the semiconductor memory devices 10.

[0098] refer to Figure 15A The main layer 152 can be formed as a filler Figure 11 The first space H1 in the obtained structure (see Figure 11 ) and the second space H2 (see Figure 11 Each of the first space H1 and the second space H2. In an embodiment, the main layer 152 may include polysilicon containing a dopant. The dopant included in the main layer 152 may be, for example, B. The main layer 152 may not completely fill each of the first space H1 and the second space H2, such that the second gap G2 may remain as a void.

[0099] refer to Figure 15B The third space H3 can be filled with a fourth gap-filling insulating layer 162. A first insulating layer 164, a second insulating layer 166, a bit line 160, and a third insulating layer 168 can be sequentially formed to cover the top surfaces of the second gap-filling insulating layer 134, the third gap-filling insulating layer 142, the fourth gap-filling insulating layer 162, the word line 140, the first insulating pad 132, the second insulating pad 136, the third insulating pad 138, and the main layer 152. Furthermore, a metal layer 156 filling the second gap G2 and located below the bit line 160 can be formed. Specifically, after forming the first insulating layer 164 and the second insulating layer 166, a portion of each of the first insulating layer 164 and the second insulating layer 166 can be removed. Subsequently, the filling of the second gap G2 (see...) can be formed. Figure 15A The main layer 152 and the metal layer 156, and the bit line 160 extending in the second horizontal direction (e.g., the Y direction), can be formed in the space from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed. Since the main layer 152 and the metal layer 156 can be collectively referred to as direct contact 150, the bit line 160 can be formed on the direct contact 150. Subsequently, a third insulating layer 168 can be formed surrounding the top surface of the bit line 160 and the top surface of the second insulating layer 166.

[0100] In an embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise oxides.

[0101] In an embodiment, bit line 160 may include doped semiconductor material, conductive metal nitride, metal, or metal semiconductor compound.

[0102] refer to Figure 15C This can remove the fill in the third space H3 (see Figure 15A The fourth gap-filling insulating layer 162 is abutted. In an embodiment, the fourth gap-filling insulating layer 162 can be removed by an etching process. As the fourth gap-filling insulating layer 162 is removed, the top surface of the insulating structure 144 beneath the fourth gap-filling insulating layer 162 can be exposed. During the removal of the fourth gap-filling insulating layer 162, portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can also be removed. Subsequently, a buried contact 170 can be formed in the space where the fourth gap-filling insulating layer 162 and the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed.

[0103] According to some embodiments, vapor phase doping can be performed as a pretreatment before forming the buried contact 170. In some embodiments, vapor phase doping can be performed using B (e.g., B₂H₆). Before forming the buried contact 170, B₂H₆ gas can be injected into a high-temperature environment, allowing B to diffuse from the surface of the semiconductor pattern AP as a dopant. The buried contact 170 can be formed by forming a buried contact junction using a vapor phase doping process, followed by filling the third space H₃ with a metallic material.

[0104] Through the above process, a semiconductor memory device 10c can be manufactured.

[0105] refer to Figures 15A to 15C The described semiconductor memory device 10c can be compared with the reference. Figures 12A to 12C The semiconductor memory device 10 described is essentially the same, except that the main layer 152 is formed directly without a buffer layer 154, and the direct contact 150 is fully formed by forming a metal layer 156 in the remaining space after the main layer 152 has not completely filled each of the first space H1 and the second space H2. Therefore, the semiconductor memory device 10c can also increase integration density and simplify the process.

[0106] Figure 16A and Figure 16B This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device 10d according to an embodiment. (See reference) Figure 16A and Figure 16B The semiconductor memory device 10d described and the reference Figures 3 to 12C The semiconductor memory devices 10 described are not mutually exclusive, and identical components are indicated by the same reference numerals. Redundant descriptions of similar components can be omitted below, and the description will primarily focus on semiconductor memory devices 10d and 10d. Figures 3 to 12C The differences between the semiconductor memory devices 10.

[0107] refer to Figure 16AIt can be achieved by forming conformal coverage Figure 11 The sidewall of the first space H1 in the obtained structure (see Figure 11 ) and the sidewalls of the second space H2 (see Figure 11 Each of the buffer layers 154 and forming a first main layer 152a to fill the remaining space after the buffer layer 154 is formed to form a direct contact 150. Third space H3 (see...) Figure 11 It can be filled with the second main layer 152b.

[0108] In some embodiments, the process of forming the buffer layer 154 and the first main layer 152a may be performed before the process of forming the second main layer 152b. In some embodiments, the process of forming the buffer layer 154 and the first main layer 152a may be performed after the process of forming the second main layer 152b. In some embodiments, the process of forming the first main layer 152a may be performed simultaneously with the process of forming the second main layer 152b.

[0109] In some embodiments, buffer layer 154 may comprise dopant-free polysilicon, and the first main layer 152a and the second main layer 152b may each comprise dopant-containing polysilicon. The dopant included in each of the first main layer 152a and the second main layer 152b may be, for example, B. In some embodiments, the first main layer 152a and the second main layer 152b may comprise substantially the same material as each other. In some embodiments, the thickness of buffer layer 154 may not be greater than the thickness of the first main layer 152a, but embodiments are not limited thereto.

[0110] refer to Figure 16BA first insulating layer 164, a second insulating layer 166, a bit line 160, and a third insulating layer 168 can be sequentially formed to cover the top surface of a second gap-filling insulating layer 134, a third gap-filling insulating layer 142, a word line 140, a first insulating pad 132, a second insulating pad 136, a third insulating pad 138, a second main layer 152b, and a direct contact 150. A conductive pattern 158 can be formed on the second main layer 152b by removing a portion of each of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168. Specifically, after forming the first insulating layer 164 and the second insulating layer 166, a portion of each of the first insulating layer 164 and the second insulating layer 166 can be removed. A bit line 160 extending in a second horizontal direction (e.g., the Y direction) can be formed in the space from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed, on the direct contact 150. Subsequently, the third insulating layer 168 can be formed around the top surface of the bit line 160 and the top surface of the second insulating layer 166. Then, a portion of each of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can be removed, exposing the top surface of the second main layer 152b, and the space from which the portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed can be filled with the conductive pattern 158. In this embodiment, the second main layer 152b and the conductive pattern 158 can be collectively referred to as buried contact 170.

[0111] In this embodiment, the direct contact 150 and the buried contact 170 may each include a doped polysilicon layer (i.e., a first main layer 152a and a second main layer 152b), and therefore, the vapor phase doping process performed before the formation of the buried contact 170 in the above embodiment can be omitted.

[0112] In one embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise an oxide. In another embodiment, the conductive pattern 158 may comprise a metal.

[0113] In an embodiment, bit line 160 may include doped semiconductor material, conductive metal nitride, metal, or metal semiconductor compound.

[0114] Through the above process, a semiconductor memory device 10d can be manufactured.

[0115] refer to Figure 16A and Figure 16B The described semiconductor memory device 10d can be compared with the reference. Figures 12A to 12CThe semiconductor memory device 10 described is essentially the same, except that a portion of the buried contact 170 includes doped polysilicon. Therefore, the semiconductor memory device 10d can also increase integration density and simplify the process. Because... Figure 16B The buried contact 170 of the semiconductor memory device 10d includes a second main layer 152b, which can be formed simultaneously or sequentially according to user settings, along with a first main layer 152a included in the direct contact 150.

[0116] Figure 17A and Figure 17B This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device 10e according to an embodiment. (See reference) Figure 17A and Figure 17B The semiconductor memory device 10e described is related to the reference. Figures 3 to 12C The semiconductor memory devices 10 described are not mutually exclusive, and identical components are denoted by the same reference numerals. Redundant descriptions of similar components can be omitted below, and the description will primarily focus on semiconductor memory devices 10e and... Figures 3 to 12C The differences between the semiconductor memory devices 10.

[0117] refer to Figure 17A ,exist Figure 11 In the resulting structure, the first main layer 152a can be formed to completely fill each of the first space H1 and the second space H2 (see Figure 11 ), and the second main layer 152b can be formed to fill the third space H3 (see Figure 11 In this embodiment, the first main layer 152a can be referred to as direct contact 150.

[0118] In some embodiments, the process of forming the first main layer 152a may be performed before the process of forming the second main layer 152b. In some embodiments, the process of forming the first main layer 152a may be performed after the process of forming the second main layer 152b. In some embodiments, the process of forming the first main layer 152a may be performed simultaneously with the process of forming the second main layer 152b.

[0119] In an embodiment, the first main layer 152a and the second main layer 152b may each comprise polycrystalline silicon containing dopants. The dopant included in each of the first main layer 152a and the second main layer 152b may be, for example, B. In some embodiments, the first main layer 152a and the second main layer 152b may comprise substantially the same material as each other.

[0120] refer to Figure 17BA first insulating layer 164, a second insulating layer 166, a bit line 160, and a third insulating layer 168 can be sequentially formed to cover the top surface of a second gap-filling insulating layer 134, a third gap-filling insulating layer 142, a word line 140, a first insulating pad 132, a second insulating pad 136, a third insulating pad 138, a second main layer 152b, and a direct contact 150. A conductive pattern 158 can be formed on the second main layer 152b by removing a portion of each of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168. Specifically, after forming the first insulating layer 164 and the second insulating layer 166, a portion of each of the first insulating layer 164 and the second insulating layer 166 can be removed. A bit line 160 extending in a second horizontal direction (e.g., the Y direction) can be formed in the space from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed, on the direct contact 150. Subsequently, the third insulating layer 168 can be formed around the top surface of the bit line 160 and the top surface of the second insulating layer 166. Then, a portion of each of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can be removed, exposing the top surface of the second main layer 152b, and the space from which the portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed can be filled with the conductive pattern 158. In this embodiment, the second main layer 152b and the conductive pattern 158 can be collectively referred to as buried contact 170.

[0121] In this embodiment, the direct contact 150 and the buried contact 170 may each include a doped polysilicon layer (i.e., a first main layer 152a and a second main layer 152b), and therefore, the vapor phase doping process performed before the formation of the buried contact 170 in the above embodiment can be omitted.

[0122] In one embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise an oxide. In another embodiment, the conductive pattern 158 may comprise a metal.

[0123] In an embodiment, bit line 160 may include doped semiconductor material, conductive metal nitride, metal, or metal semiconductor compound.

[0124] Through the above process, a semiconductor memory device 10e can be manufactured.

[0125] refer to Figure 17A and Figure 17B The described semiconductor memory device 10e can be compared with the reference. Figures 12A to 12CThe semiconductor memory device 10 described is essentially the same, except that the direct contact 150 does not include the buffer layer 154 (see [link]). Figure 12C Furthermore, a portion of the buried contact 170 includes, outside of the doped polysilicon. Therefore, the semiconductor memory device 10e can also increase integration density and simplify the process. Because... Figure 17B The buried contact 170 of the semiconductor memory device 10e includes a second main layer 152b, which can be formed simultaneously or sequentially according to user settings, along with a first main layer 152a included in the direct contact 150.

[0126] Figure 18A and Figure 18B This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device 10f according to an embodiment. (See reference) Figure 18A and Figure 18B The semiconductor memory device 10f described and the reference Figures 3 to 12C The semiconductor memory devices 10 described are not mutually exclusive, and identical components are denoted by the same reference numerals. Redundant descriptions of similar components can be omitted below, and the description will primarily focus on semiconductor memory devices 10f and... Figures 3 to 12C The differences between the semiconductor memory devices 10.

[0127] refer to Figure 18A The buffer layer 154 can be formed as a conformal cover. Figure 11 The sidewall of the first space H1 in the obtained structure (see Figure 11 ) and the sidewalls of the second space H2 (see Figure 11 The first main layer 152a can be formed to fill a portion of the space remaining after the formation of the buffer layer 154. The second main layer 152b can be formed to fill a portion of the third space H3 (see [link]). Figure 11 The first main layer 152a may not fill the entire remaining space in each of the first space H1 and the second space H2, and therefore may include the third gap G3. Similarly, the second main layer 152b may not fill the entire third space H3, and therefore may include the third gap G3.

[0128] In some embodiments, the process of forming the buffer layer 154 and the first main layer 152a may be performed before the process of forming the second main layer 152b. In some embodiments, the process of forming the buffer layer 154 and the first main layer 152a may be performed after the process of forming the second main layer 152b. In some embodiments, the process of forming the first main layer 152a may be performed simultaneously with the process of forming the second main layer 152b.

[0129] In an embodiment, buffer layer 154 may comprise dopant-free polysilicon, and the first main layer 152a and the second main layer 152b may each comprise dopant-containing polysilicon. The dopant included in each of the first main layer 152a and the second main layer 152b may be, for example, B. In some embodiments, the first main layer 152a and the second main layer 152b may comprise substantially the same material as each other.

[0130] refer to Figure 18B The first insulating layer 164, the second insulating layer 166, the bit line 160, and the third insulating layer 168 can be sequentially formed to cover the top surface of the second gap-filling insulating layer 134, the third gap-filling insulating layer 142, the bit line 140, the first insulating pad 132, the second insulating pad 136, the third insulating pad 138, the first main layer 152a, the second main layer 152b, and the buffer layer 154. Furthermore, a third gap G3 (in the first main layer 152a) can be formed to fill the first main layer 152a. Figure 18A (in the middle) and located below bit line 160, a first metal layer 156a, and can form a third gap G3 to fill the second main layer 152b (in Figure 18A The second metal layer 156b (in the middle) is formed. Specifically, after forming the second metal layer 156b that fills the third gap G3 of the second main layer 152b, a first insulating layer 164 and a second insulating layer 166 can be formed, and a portion of each of the first insulating layer 164 and the second insulating layer 166 can be removed. Subsequently, the third gap G3 (in the middle) can be formed. Figure 18A The first metal layer 156a (in the middle) and the bit line 160 extending in the second horizontal direction (e.g., the Y direction) can be formed in the space from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed. In this embodiment, the first main layer 152a, the buffer layer 154, and the first metal layer 156a can be collectively referred to as the direct contact 150, and therefore, the bit line 160 can be formed on the direct contact 150. Thereafter, the third insulating layer 168 can be formed around the top surface of the bit line 160 and the top surface of the second insulating layer 166. Thereafter, a portion of each of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can be removed, exposing the top surfaces of the second main layer 152b and the second metal layer 156b, and a conductive pattern 158 can be formed to fill the space from which portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed. In this embodiment, the second main layer 152b, the second metal layer 156b, and the metal pattern 158 can be collectively referred to as the buried contact 170.

[0131] In this embodiment, the direct contact 150 and the buried contact 170 may each include a doped polysilicon layer (i.e., a first main layer 152a and a second main layer 152b), and therefore, the vapor phase doping process performed before the formation of the buried contact 170 in the above embodiment can be omitted.

[0132] In one embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise an oxide. In another embodiment, the first metal layer 156a and the second metal layer 156b may comprise substantially the same material, and the conductive pattern 158 may comprise a metal.

[0133] In an embodiment, bit line 160 may include doped semiconductor material, conductive metal nitride, metal, or metal semiconductor compound.

[0134] Through the above process, a semiconductor memory device 10f can be manufactured.

[0135] refer to Figure 18A and Figure 18B The described semiconductor memory device 10f can be compared with the reference. Figures 12A to 12C The semiconductor memory device 10 is substantially the same as described, except that the direct contact 150 is fully formed by forming a first metal layer 156a in the remaining space because the first master layer 152a does not completely fill the space surrounded by the buffer layer 154, and the buried contact 170 includes a second master layer 152b containing polysilicon. Therefore, the semiconductor memory device 10f can also increase integration density and simplify the process.

[0136] Figure 19A and Figure 19B This is a schematic diagram illustrating a portion of a method for manufacturing a semiconductor memory device 10g according to an embodiment. (See reference) Figure 19A and Figure 19B The semiconductor memory device 10g described and the reference Figures 3 to 12C The semiconductor memory devices 10 described are not mutually exclusive, and identical components are indicated by the same reference numerals. Redundant descriptions of similar components can be omitted below, and the description will primarily focus on semiconductor memory devices 10g and... Figures 3 to 12C The differences between the semiconductor memory devices 10.

[0137] refer to Figure 19A ,exist Figure 11 In the resulting structure, the first main layer 152a can be formed in the first space H1 (see...). Figure 11 ) and the second space H2 (see Figure 11 In each of the three spaces, and the second main layer 152b can be formed in the third space H3 (see...). Figure 11In an embodiment, the first main layer 152a and the second main layer 152b may each comprise polycrystalline silicon containing a dopant. In some embodiments, the first main layer 152a and the second main layer 152b may comprise substantially the same material as each other. The dopant included in each of the first main layer 152a and the second main layer 152b may be, for example, B. Each of the first main layer 152a and the second main layer 152b may not completely fill one of the first space H1, the second space H2, and the third space H3, such that the fourth gap G4 may remain as a void.

[0138] In this embodiment, the first main layer 152a and the second main layer 152b can be formed simultaneously. The first main layer 152a can be formed first, or the second main layer 152b can be formed first.

[0139] refer to Figure 19B The first metal layer 156a can be formed to completely fill the fourth gap G4 defined by the first main layer 152a, and the second metal layer 156b can be formed to completely fill the fourth gap G4 defined by the second main layer 152b. The first insulating layer 164, the second insulating layer 166, the bit line 160, and the third insulating layer 168 can be sequentially formed to cover the top surfaces of the second gap-filling insulating layer 134, the third gap-filling insulating layer 142, the word line 140, the first insulating pad 132, the second insulating pad 136, the third insulating pad 138, the first main layer 152a, the second main layer 152b, the first metal layer 156a, and the second metal layer 156b. Specifically, the first insulating layer 164 and the second insulating layer 166 can be formed, and a portion of each of the first insulating layer 164 and the second insulating layer 166 can be removed. Bit lines 160 extending in a second horizontal direction (e.g., the Y direction) can be formed in spaces from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed. In this embodiment, the first main layer 152a and the first metal layer 156a can be collectively referred to as direct contact 150, and therefore, bit lines 160 can be formed on direct contact 150. A third insulating layer 168 can be formed around the top surface of bit lines 160 and the top surface of the second insulating layer 166. A portion of each of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can be removed, exposing the top surfaces of the second main layer 152b and the second metal layer 156b, and conductive patterns 158 can be formed to fill the spaces from which portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed. In this embodiment, the second main layer 152b, the second conductive layer 156b, and the conductive patterns 158 can be collectively referred to as buried contact 170.

[0140] In this embodiment, the direct contact 150 and the buried contact 170 may each include a doped polysilicon layer (i.e., a first main layer 152a and a second main layer 152b), and therefore, the vapor phase doping process performed before the formation of the buried contact 170 in the above embodiment can be omitted.

[0141] In an embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise oxides.

[0142] In one embodiment, bit line 160 may include a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound. In another embodiment, conductive pattern 158 may include a metal, and the first metal layer 156a and the second metal layer 156b may include substantially the same material as each other.

[0143] refer to Figure 19A and Figure 19B The described semiconductor memory device 10g can be compared with the reference. Figures 12A to 12C The semiconductor memory device 10 described is substantially the same, except that the direct contact 150 does not include a buffer layer and because the first main layer 152a does not completely fill each of the first space H1 and the second space H2 (see [link]). Figure 11 In the remaining space, a first metal layer 156a is formed to completely form the direct contact 150, and the buried contact 170 includes a second main layer 152b containing polysilicon and a second metal layer 156b surrounded by the second main layer 152b, and therefore has a structure similar to that of the direct contact 150 and is formed by a process similar to that of the direct contact 150. Therefore, the semiconductor memory device 10g can also increase integration density and simplify the process.

[0144] Figure 20 and Figure 21 These are schematic diagrams of semiconductor memory devices 10h and 10i according to embodiments. Figure 20 and Figure 21 Semiconductor memory devices 10h and 10i with reference Figures 3 to 12C The semiconductor memory devices 10 described are not mutually exclusive, and identical elements are denoted by the same reference numerals. Redundant descriptions of similar elements may be omitted below, and the description will primarily focus on each of the semiconductor memory devices 10h and 10i. Figures 3 to 12C The differences between the semiconductor memory devices 10.

[0145] refer to Figure 20 First space H1 and second space H2 (see Figure 11Each of the spaces in the third space H3 can be completely filled with metal layer 156. In other words, in this embodiment, the direct contact 150 can be metal layer 156. (See also: Third space H3) Figure 11 It can be completely filled with a metal layer 156.

[0146] In an embodiment, a first insulating layer 164, a second insulating layer 166, a bit line 160, and a third insulating layer 168 may be sequentially formed to cover a second gap-filling insulating layer 134, a third gap-filling insulating layer 142, a word line 140, a first insulating pad 132, a second insulating pad 136, a third insulating pad 138, a metal layer 156, and the top surface of the direct contact 150. Specifically, after the first insulating layer 164 and the second insulating layer 166 are formed, a portion of each of the first insulating layer 164 and the second insulating layer 166 may be removed. The bit line 160, extending in a second horizontal direction (e.g., the Y direction), may be formed in the space from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed, on the direct contact 150. Subsequently, the third insulating layer 168 may be formed around the top surface of the bit line 160 and the top surface of the second insulating layer 166. Subsequently, a portion of each of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can be removed to expose the top surface of the second metal layer 156b, and a conductive pattern 158 can be formed in the space where portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed, thereby obtaining a buried contact 170 including the metal layer and the conductive pattern 158.

[0147] According to some embodiments, vapor phase doping can be performed as a pretreatment before forming the buried contact 170. In some embodiments, vapor phase doping can be performed using B (e.g., B₂H₆). Before forming the buried contact 170, B₂H₆ gas can be injected into a high-temperature environment, allowing B to diffuse from the surface of the semiconductor pattern AP as a dopant. The buried contact 170 can be formed by forming a buried contact junction using a vapor phase doping process, followed by filling the third space H₃ with a metallic material.

[0148] In some embodiments, similar to buried contact 170, the diffusion of dopant can be initiated by using a vapor-phase doping process prior to the formation of direct contact 150.

[0149] In an embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise oxides.

[0150] In one embodiment, bit line 160 may include a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound. In another embodiment, conductive pattern 158 may include a metal, and the first metal layer 156a and the second metal layer 156b may include substantially the same material as each other.

[0151] refer to Figure 20 The described semiconductor memory device 10h can be compared with the reference. Figures 12A to 12C The semiconductor memory device 10 described is essentially the same, except that both the direct contact 150 and the buried contact 170 are made of metallic material. Therefore, the semiconductor memory device 10h can also increase integration density and simplify the process.

[0152] refer to Figure 21 First space H1 and second space H2 (see Figure 11 Each of the spaces in the third space H3 can be completely filled with metal layer 156. In other words, in this embodiment, the direct contact 150 can be metal layer 156. (See also: Third space H3) Figure 11 The main layer 152 may be completely filled. In some embodiments, the main layer 152 may include doped polysilicon. In some embodiments, the dopant included in the main layer 152 may include B.

[0153] According to some embodiments, vapor-phase doping can be performed as a pretreatment before forming the direct contact 150. In some embodiments, vapor-phase doping can be performed using B (e.g., B₂H₆). Before forming the direct contact 150, B₂H₆ gas can be injected into a high-temperature environment, allowing B to diffuse as a dopant from the surface of the semiconductor pattern AP. The direct contact 150 can be formed by forming a junction using a vapor-phase doping process, followed by filling each of the first space H1 and the second space H2 with a metallic material.

[0154] In an embodiment, a first insulating layer 164, a second insulating layer 166, a bit line 160, and a third insulating layer 168 may be sequentially formed to cover the top surface of a second gap-filling insulating layer 134, a third gap-filling insulating layer 142, a word line 140, a first insulating pad 132, a second insulating pad 136, a third insulating pad 138, a main layer 152, and a direct contact 150. Specifically, after the first insulating layer 164 and the second insulating layer 166 are formed, a portion of each of the first insulating layer 164 and the second insulating layer 166 may be removed. The bit line 160, extending in a second horizontal direction (e.g., the Y direction), may be formed in the space from which portions of the first insulating layer 164 and the second insulating layer 166 have been removed, on the direct contact 150. Subsequently, the third insulating layer 168 may be formed around the top surface of the bit line 160 and the top surface of the second insulating layer 166. Subsequently, a portion of each of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 can be removed to expose the top surface of the main layer 152, and a conductive pattern 158 can be formed in the space where portions of the first insulating layer 164, the second insulating layer 166, and the third insulating layer 168 have been removed, thereby obtaining a buried contact 170 including the main layer 152 and the conductive pattern 158.

[0155] In an embodiment, the first insulating layer 164 and the third insulating layer 168 may comprise nitride-based materials, and the second insulating layer 166 may comprise oxides.

[0156] In one embodiment, bit line 160 may include a doped semiconductor material, a conductive metal nitride, a metal, or a metal semiconductor compound. In another embodiment, conductive pattern 158 may include a metal.

[0157] refer to Figure 21 The described semiconductor memory device 10i can be compared with the reference Figures 12A to 12C The semiconductor memory device 10 described is essentially the same, except that a portion of the buried contact 170 is composed of a main layer 152 comprising polysilicon. Therefore, the semiconductor memory device 10i can also increase integration density and simplify the process.

[0158] While non-limiting exemplary embodiments of the present disclosure have been described above with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor memory device, comprising: Substrate; A plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; A first contact is connected to the plurality of semiconductor patterns and extends through the plurality of semiconductor patterns in the vertical direction; Bit line, the bit line on the first contact in the vertical direction, the bit line extending in a second horizontal direction intersecting the first horizontal direction; Word lines, the word lines surrounding the plurality of semiconductor patterns, the word lines extending in the first horizontal direction; as well as A second contact, spaced apart from the first contact in the first horizontal direction, extends through the plurality of semiconductor patterns in the vertical direction. The second contact comprises a metal, and the first contact comprises a main layer comprising doped polycrystalline silicon.

2. The semiconductor memory device of claim 1, wherein the main layer comprises a dopant, the dopant comprising boron (B).

3. The semiconductor memory device according to claim 1, wherein, The second contact comprises a junction formed during a vapor-phase doping process using boron (B).

4. The semiconductor memory device according to claim 1, wherein, The first contact also includes a buffer layer surrounding the main layer in the first horizontal direction.

5. The semiconductor memory device according to claim 4, wherein, The buffer layer comprises polycrystalline silicon without dopants.

6. The semiconductor memory device according to claim 4, wherein, The thickness of the buffer layer is less than the thickness of the main layer.

7. The semiconductor memory device according to claim 1, wherein, The first contact also includes a metal layer surrounded by the main layer in the first horizontal direction.

8. The semiconductor memory device according to claim 7, wherein, The first contact also includes a buffer layer surrounding the main layer in the first horizontal direction.

9. The semiconductor memory device according to claim 8, wherein, The buffer layer comprises polycrystalline silicon without dopants.

10. The semiconductor memory device of claim 1, further comprising at least one insulating structure beneath each of the first contact and the second contact.

11. A semiconductor memory device, comprising: Substrate; A plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; A first contact is connected to the plurality of semiconductor patterns and extends through the plurality of semiconductor patterns in the vertical direction; Bit line, the bit line on the first contact in the vertical direction, the bit line extending in a second horizontal direction intersecting the first horizontal direction; Word lines, the word lines surrounding the plurality of semiconductor patterns, the word lines extending in the first horizontal direction; as well as A second contact, spaced apart from the first contact in the first horizontal direction, extends through the plurality of semiconductor patterns in the vertical direction. The first contact includes a first main layer, the second contact includes a second main layer, and each of the first main layer and the second main layer includes doped polysilicon.

12. The semiconductor memory device according to claim 11, wherein, Each of the first master layer and the second master layer includes a dopant, said dopant including boron (B).

13. The semiconductor memory device according to claim 11, wherein, The first contact further includes a buffer layer surrounding the first master layer in the first horizontal direction, and the buffer layer comprises polycrystalline silicon without dopants.

14. The semiconductor memory device according to claim 11, wherein, The first contact also includes a first metal layer that is surrounded by the first main layer in the first horizontal direction.

15. The semiconductor memory device according to claim 14, wherein, The first contact also includes a buffer layer surrounding the first main layer in the first horizontal direction.

16. The semiconductor memory device according to claim 11, wherein, The second contact also includes a second metal layer that is surrounded by the second main layer in the first horizontal direction.

17. A semiconductor memory device, comprising: Substrate; A plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; A first contact is connected to the plurality of semiconductor patterns and extends through the plurality of semiconductor patterns in the vertical direction; Bit line, the bit line on the first contact in the vertical direction, the bit line extending in a second horizontal direction intersecting the first horizontal direction; Word lines, the word lines surrounding the plurality of semiconductor patterns, the word lines extending in the first horizontal direction; as well as A second contact, spaced apart from the first contact in the first horizontal direction, extends through the plurality of semiconductor patterns in the vertical direction. The first contact comprises a metal, and the junction of the first contact is formed by using a boron (B) vapor-phase doping process.

18. The semiconductor memory device according to claim 17, wherein, The second contact includes a metal.

19. The semiconductor memory device according to claim 17, wherein, The second contact comprises doped polycrystalline silicon.

20. The semiconductor memory device according to claim 19, wherein, The second contact includes a dopant, which includes B.

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