A field effect transistor having a shaped contact layer and a method of manufacture

Abstract

The application relates to a field effect transistor with a special contact layer and a preparation method, and belongs to the field of semiconductor power devices, which comprises a semiconductor substrate, a drift layer, a first semiconductor epitaxial layer, a groove etched in the first semiconductor epitaxial layer, and a second semiconductor epitaxial layer and a semiconductor filling layer filled in the groove in sequence. A first contact hole forms ohmic contact with the semiconductor filling layer and is isolated from a second metallization layer through an interlayer dielectric; a second contact hole simultaneously contacts the second semiconductor epitaxial layer, the sidewall of the semiconductor contact layer and the bottom of the first semiconductor epitaxial layer, and is provided with a composite metal layer which is electrically connected with the second metallization layer to form a source metal area. The second contact hole of the application simultaneously contacts the second semiconductor epitaxial layer, the sidewall of the semiconductor contact layer and the bottom of the first semiconductor epitaxial layer, which can effectively inhibit the parasitic BJT conduction and the body region suspension effect, and improve the switching reliability and the anti-latch-up capability of the device.

Description

Technical Field

[0001] This invention relates to a field-effect transistor with an irregularly shaped contact layer and its fabrication method, and more particularly to a vertical trench gate field-effect transistor with an irregularly shaped contact layer, belonging to the field of semiconductor power device technology. Background Technology

[0002] Vertical channel SiC JFETs, due to their vertical current path and gate oxide-free structure, significantly outperform traditional planar devices in terms of on-resistance, switching speed, high-temperature tolerance, and reliability. However, existing vertical SiC JFETs still face the following technical challenges in manufacturing and application:

[0003] (i) High source ohmic contact resistance. In traditional devices, the source region often uses the same 4H-SiC material as the substrate. Due to the large bandgap of 4H-SiC (approximately 3.3 eV), the ohmic contact resistivity formed after annealing with Ni-based metals is high, which limits further optimization of the device's on-resistance.

[0004] (ii) Parasitic BJT conduction risk. In vertical JFET devices, the gate region, source region, and drift layer naturally form a parasitic NPN bipolar transistor (BJT). When the gate region is in a floating state or when a lateral voltage drop occurs under high current, the parasitic BJT is prone to unexpected conduction, triggering a latch-up effect, causing device runaway or even burnout.

[0005] (iii) The source region formation process is complex. In traditional devices, the source region is usually formed by high-temperature ion implantation, which requires high-dose implantation and high-temperature activation annealing (about 1700°C), making the process complex and the thermal budget high.

[0006] In addition, recent studies have attempted to use 3C-SiC as a contact layer in silicon carbide Schottky diodes (such as Chinese patent CN117174763A) to reduce contact resistance. However, in vertical channel JFETs, there is still no publicly available technical solution on how to use 3C-SiC to simultaneously solve the source contact resistance and parasitic BJT suppression problems. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a field-effect transistor with an irregular contact layer and its fabrication method. By using 3C-SiC material, the contact resistance of the source region is reduced, and ion implantation is not required, simplifying the process. Furthermore, by using the ohmic contact at the bottom of the second contact hole to pull the first semiconductor epitaxial layer and the source metal region to the same potential, parasitic BJT conduction and body region levitation effects are effectively suppressed, thereby improving the switching reliability and latch-up resistance of the device.

[0008] The present invention adopts the following technical solution:

[0009] A field-effect transistor with an irregular contact layer includes a first metallization layer at the bottom. The upper part of the first metallization layer includes, from bottom to top, a semiconductor substrate, a drift layer and a first semiconductor epitaxial layer. A trench is provided in the first semiconductor epitaxial layer. The bottom of the trench extends below the interface between the first semiconductor epitaxial layer and the drift layer, so that a second semiconductor epitaxial layer filled at the bottom of the trench is in direct contact with the drift layer.

[0010] The trench is sequentially filled with a second semiconductor epitaxial layer and a semiconductor filling layer. A semiconductor irregular contact layer is disposed above the second semiconductor epitaxial layer at a position corresponding to the first semiconductor epitaxial layer. An interlayer dielectric is deposited above the semiconductor irregular contact layer, and a first contact hole is formed between adjacent interlayer dielectrics. A second contact hole is etched between adjacent first contact holes, and the second contact hole extends through the interlayer dielectric, the semiconductor irregular contact layer, and the second semiconductor epitaxial layer to the top of the first semiconductor epitaxial layer.

[0011] A composite metal layer is deposited in the first contact hole to form the gate metal, and a composite metal layer is deposited in the second contact hole to form a metal contact plug. A second metallization layer is deposited on top of the device. The gate metal forms an ohmic contact with the semiconductor fill layer and is isolated from the second metallization layer by an interlayer dielectric. The metal contact plug simultaneously contacts the sidewalls of the second semiconductor epitaxial layer and the semiconductor irregular contact layer, as well as the bottom of the first semiconductor epitaxial layer, effectively suppressing parasitic BJT conduction and bulk region levitation effects, improving the switching reliability and latch-up resistance of the device. The metal contact plug is electrically connected to the second metallization layer to form the source metal region. The interlayer dielectric naturally isolates the gate metal and the source metal region in the vertical direction.

[0012] Preferably, the semiconductor substrate, drift layer, first semiconductor epitaxial layer, semiconductor filling layer and second semiconductor epitaxial layer are made of cubic SiC, preferably 4H-SiC.

[0013] Preferably, the semiconductor irregular contact layer is made of nitrogen-doped 3C-SiC, with a thickness in the range of 60 nm to 200 nm and a doping concentration of not less than 1 × 10⁻⁶. 19 cm -3 .

[0014] Preferably, the composite metal layer is a Ti / W composite filler, with the Ti layer below contacting the ohmic Ni layer, and the W layer above the Ti layer, formed using a lift-off process. A gate metal is formed in the first contact hole, and a metal contact plug is formed in the second contact hole. The Ni layer thickness is 10~100nm, and the composite metal layer thickness is 120nm~2μm. The first semiconductor epitaxial layer at the bottom of the second contact hole is electrically shorted to the source metal region via the metal contact plug to clamp the potential of the first semiconductor epitaxial layer and suppress the conduction of parasitic transistors.

[0015] Preferably, the trench is a trench with rounded corners, which is obtained by a dry plasma etching process.

[0016] Preferably, the drift layer and the second semiconductor epitaxial layer are of a first conductivity type, and the first semiconductor epitaxial layer and the semiconductor filling layer are of a second conductivity type; the first conductivity type is N-type or P-type; and the second conductivity type is the opposite of the first conductivity type.

[0017] Preferably, the doping concentration of the drift layer of the first conductivity type is in the range of 1×10⁻⁶. 15 ~ 1×10 16 cm -3 The thickness ranges from 5μm to 30μm;

[0018] The doping concentration of the second semiconductor epitaxial layer of the first conductivity type is lower than or the same as that of the drift layer, and the thickness ranges from 0.5 μm to 5 μm.

[0019] Preferably, the first semiconductor epitaxial layer and the semiconductor filling layer of the second conductivity type have a consistent doping concentration, ranging from 1 × 10⁻⁶. 16  cm -3 Up to 1×10 17 cm -3 .

[0020] Preferably, the first metallization layer and the second metallization layer are one or more combinations of the following materials: Ti, Ni, Ag, Au, Al, Cu.

[0021] A method for fabricating a field-effect transistor with an irregular contact layer, comprising the following steps:

[0022] (1) Growing a drift layer and a first semiconductor epitaxial layer on a semiconductor substrate;

[0023] (2) A trench is formed by etching the first semiconductor epitaxial layer through the first mask, and the bottom of the trench extends below the interface between the first semiconductor epitaxial layer and the drift layer;

[0024] (3) A second semiconductor epitaxial layer is grown inside and outside the trench, and a semiconductor filling layer is grown on the second semiconductor epitaxial layer;

[0025] (4) Perform chemical mechanical polishing to planarize the semiconductor filling layer;

[0026] (5) Deposit an N-type heavily doped 3C-SiC semiconductor irregular contact layer on the top of the planarized device, and then use a second mask to selectively etch the semiconductor irregular contact layer;

[0027] (6) Deposit interlayer dielectric, and form a first contact hole by etching through a third mask, the bottom of the first contact hole extending to the top of the semiconductor filling layer;

[0028] (7) A second contact hole is formed by etching through a fourth mask. The second contact hole is located between adjacent first contact holes and extends through the interlayer dielectric, semiconductor profile contact layer, and second semiconductor epitaxial layer to the top of the first semiconductor epitaxial layer.

[0029] (8) Sputtering a Ni layer and annealing to form an ohmic contact in the first contact hole and the second contact hole. The ohmic contact is obtained by sputtering and annealing the Ni layer. The thickness of the Ni layer is 10~100nm.

[0030] (9) A Ti / W composite metal layer is deposited using a lift-off process through the fifth mask, specifically: a gate metal is formed in the first contact hole, and a metal contact plug is formed in the second contact hole;

[0031] (10) Deposit interlayer medium again; then etch the interlayer medium through the sixth mask to form an opening and expose the metal contact plug above the second contact hole;

[0032] (11) A metal layer is deposited on the top of the device surface, and a metal pattern is defined through the seventh mask to perform top metallization and form a second metallization layer;

[0033] (12) Perform metallization on the bottom to form the first metallization layer.

[0034] For any details not covered in this invention, please refer to the prior art.

[0035] The beneficial effects of this invention are as follows:

[0036] 1. Reduced source contact resistance: The material of the semiconductor irregular contact layer is 3C-SiC. 3C-SiC has a narrower bandgap (about 2.4 eV) than 4H-SiC, and can form a lower ohmic contact resistivity after annealing with the subsequently deposited Ni layer.

[0037] 2. Suppressing parasitic BJTs: The metal contact plug in the second contact hole of the present invention simultaneously contacts the first semiconductor epitaxial layer and the second metallization layer, pulling them to the same potential, effectively clamping the body region potential, suppressing the conduction of parasitic NPN transistors, improving the device's anti-latch-up capability and switching reliability, without increasing the number of process steps.

[0038] 3. Simplified Process Steps: This invention uses chemical vapor deposition (CVD) of N-type heavily doped 3C-SiC semiconductor heterogeneous contact layers to replace traditional high-temperature N⁺ implantation, avoiding implantation damage and high-temperature activation annealing, thus reducing thermal budget and process complexity. Furthermore, the source metal contact plug and gate metal are formed simultaneously through a single W / Ti lift-off process, eliminating the need for separate deposition, simplifying the process flow and reducing manufacturing costs. The second metallization layer only contacts the metal in the second contact hole, and is isolated from the gate metal in the first contact hole by an interlayer dielectric, eliminating the need for additional masks or alignment steps.

[0039] 4. Enhanced surge current withstand capability: The ohmic contact at the bottom of the second contact hole in this invention ensures that the first semiconductor epitaxial layer of the second conductivity type is at the same potential as the source metal region, guaranteeing that the surge current is uniformly distributed throughout the active region and avoiding current concentration and hot spot formation caused by local potential rise. Furthermore, the low-resistance ohmic contact formed by the 3C-SiC semiconductor irregular contact layer and the Ni layer significantly reduces Joule heating at the contact point during surges. Therefore, the device of this invention has a higher surge current withstand capability for the same chip area. Attached Figure Description

[0040] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.

[0041] Figure 1 This is a schematic cross-sectional view of the field-effect transistor with an irregular contact layer according to the present invention;

[0042] Figure 2 This is a schematic cross-sectional view of the semiconductor after the semiconductor substrate, drift layer and first semiconductor epitaxial layer are formed in the preparation method of this embodiment of the invention;

[0043] Figure 3 A schematic diagram of the cross-section after trench etching;

[0044] Figure 4 A schematic cross-sectional view of the trench after the second semiconductor epitaxial layer and semiconductor filling layer have been filled.

[0045] Figure 5 This is a schematic diagram of the cross-section after flattening.

[0046] Figure 6 This is a schematic diagram of a cross-section after the semiconductor contact layer has been deposited.

[0047] Figure 7 This is a schematic diagram of the cross-section after selective etching of the semiconductor contact layer;

[0048] Figure 8 A schematic diagram of the cross-section after depositing the interlayer medium and etching to form the first contact hole;

[0049] Figure 9 This is a schematic diagram of the cross-section after etching to form the second contact hole;

[0050] Figure 10 A schematic diagram of the cross-section after sputtering and annealing to form an ohmic contact in the first and second contact holes;

[0051] Figure 11 A schematic cross-sectional view of the first and second contact holes after the composite metal layer is filled by the lift-off process;

[0052] Figure 12 This is a schematic diagram of the cross-section after the interlayer medium layer has been deposited again;

[0053] In the figure, 1-first metallization layer, 2-semiconductor substrate, 3-drift layer, 4-first semiconductor epitaxial layer, 5-second metallization layer, 6-ohmic contact, 7-interlayer dielectric, 8-metal contact plug, 9-gate metal, 10-semiconductor irregular contact layer, 11-second semiconductor epitaxial layer, 12-first contact hole, 13-second contact hole, 14-source metal region, 15-trench, 16-composite metal layer, 17-semiconductor filling layer. Detailed Implementation

[0054] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. However, this is not the only description; all aspects not described in detail herein are based on conventional techniques in the art.

[0055] Example 1

[0056] A field-effect transistor with an irregularly shaped contact layer, such as Figures 1 to 12 As shown, the first metallization layer 1 at the bottom is included. The upper part of the first metallization layer 1 includes, from bottom to top, a semiconductor substrate 2, a drift layer 3 and a first semiconductor epitaxial layer 4. A trench 15 is provided in the first semiconductor epitaxial layer 4. The bottom of the trench 15 extends below the interface between the first semiconductor epitaxial layer 4 and the drift layer 3, so that the second semiconductor epitaxial layer 11 filled at the bottom of the trench 15 is in direct contact with the drift layer 3.

[0057] The trench 15 is sequentially filled with a second semiconductor epitaxial layer 11 and a semiconductor filling layer 17. A semiconductor irregular contact layer 10 is disposed above the second semiconductor epitaxial layer 11 at a position corresponding to the first semiconductor epitaxial layer 4. An interlayer dielectric 7 is deposited above the semiconductor irregular contact layer 10, and a first contact hole 12 is formed between adjacent interlayer dielectrics 7. A second contact hole 13 is etched between adjacent first contact holes 12. The second contact hole 13 extends through the interlayer dielectric 7, the semiconductor irregular contact layer 10, and the second semiconductor epitaxial layer 11 to the top of the first semiconductor epitaxial layer 4.

[0058] A composite metal layer 16 is deposited in the first contact hole 12 to form the gate metal 9, and a composite metal layer 16 is deposited in the second contact hole 13 to form the metal contact plug 8. A second metallization layer 5 is deposited on the top of the device. The gate metal 9 and the semiconductor filling layer 17 form an ohmic contact 6 and are isolated from the second metallization layer 5 by the interlayer dielectric 7. The metal contact plug 8 simultaneously contacts the sidewalls of the second semiconductor epitaxial layer 11 and the semiconductor irregular contact layer 10 and the bottom of the first semiconductor epitaxial layer 4, and is electrically connected to the second metallization layer 5 to form the source metal region 14. The interlayer dielectric 7 naturally isolates the gate metal 9 and the source metal region 14 in the vertical direction.

[0059] Example 2

[0060] A field-effect transistor with an irregular contact layer, as described in Example 1, except that the semiconductor substrate 2, drift layer 3, first semiconductor epitaxial layer 4, semiconductor filling layer 17 and second semiconductor epitaxial layer 11 are made of 4H-SiC.

[0061] Semiconductor substrate 2 is made of N-type 4H-SiC material, doped with phosphorus at a concentration of 1×10⁻⁶. 14 cm -3 ~ 1×10 16 cm -3 ;

[0062] Drift layer 3 also employs phosphorus doping, with a doping concentration of 1×10⁻⁶. 15 cm -3 ~ 1×10 16 cm -3 The thickness is 5~30μm.

[0063] The doping concentration of the first semiconductor epitaxial layer 4 is the same as that of the drift layer 3, and the thickness ranges from 0.5 μm to 5 μm.

[0064] The doping concentrations of the first semiconductor epitaxial layer 4 and the semiconductor filling layer 17 are the same, both ranging from 1×10⁻⁶. 16 cm -3 Up to 1×1017 cm -3 .

[0065] Example 3

[0066] A field-effect transistor with an irregular contact layer, as described in Example 2, differs in that the semiconductor irregular contact layer 10 is made of nitrogen-doped 3C-SiC, with a thickness ranging from 60 nm to 200 nm and a doping concentration of not less than 1 × 10⁻⁶. 19 cm -3 .

[0067] Example 4

[0068] A field-effect transistor with an irregularly shaped contact layer, as described in Embodiment 3, differs in that the composite metal layer 16 is filled with a Ti / W composite. The Ti layer is located below and contacts the Ni layer with ohmic contact, while the W layer is located above the Ti layer. It is formed using a lift-off process. A gate metal is formed in the first contact hole, and a metal contact plug is formed in the second contact hole. In this embodiment, the Ni layer thickness is 50 nm, and the composite metal layer 16 thickness is 200 nm. The first semiconductor epitaxial layer 4 at the bottom of the second contact hole 13 is electrically shorted to the source metal region 14 through the metal contact plug 8 to clamp the potential of the first semiconductor epitaxial layer and suppress the conduction of parasitic transistors.

[0069] Example 5

[0070] A field-effect transistor with an irregular contact layer, as described in Example 4, except that the trench 15 is a trench with rounded corners to reduce electric field concentration. The trench with rounded corners is obtained by a dry plasma etching process.

[0071] Example 6

[0072] A field-effect transistor with an irregular contact layer, as described in Embodiment 5, except that the drift layer 3 and the second semiconductor epitaxial layer 11 are of the first conductivity type, and the first semiconductor epitaxial layer 4 and the semiconductor filling layer 17 are of the second conductivity type; in this embodiment, the first conductivity type is N-type; and the second conductivity type is P-type.

[0073] Example 7

[0074] A field-effect transistor with an irregular contact layer, as described in Example 6, except that the first metallization layer 1 and the second metallization layer 5 are both Ti.

[0075] Example 8

[0076] A method for fabricating a field-effect transistor with an irregularly shaped contact layer includes the following steps:

[0077] (1) such as Figure 2A drift layer 3 and a first semiconductor epitaxial layer 4 are grown on a semiconductor substrate 2.

[0078] (2) such as Figure 3 A trench 15 is formed by etching the first semiconductor epitaxial layer 4 through the first mask, and the bottom of the trench 15 extends below the interface between the first semiconductor epitaxial layer 4 and the drift layer 3.

[0079] (3) such as Figure 4 A second semiconductor epitaxial layer 11 is grown inside and outside the trench 15, and a semiconductor filling layer 17 is grown on the second semiconductor epitaxial layer 11.

[0080] (4) such as Figure 5 The semiconductor filling layer 17 is planarized by chemical mechanical polishing;

[0081] (5) such as Figure 6 , Figure 7 An N-type heavily doped 3C-SiC semiconductor irregular contact layer 10 is deposited on the top of the planarized device, and then the semiconductor irregular contact layer 10 is selectively etched using a second mask.

[0082] (6) For example Figure 8 The interlayer dielectric 7 is deposited, and the first contact hole 12 is formed by etching through the third mask. The bottom of the first contact hole 12 extends to the top of the semiconductor filling layer 17.

[0083] (7) For example Figure 9 The second contact hole 13 is formed by etching through the fourth mask. The second contact hole 13 is located between the adjacent first contact holes 12, and the second contact hole 13 extends through the interlayer dielectric 7, the semiconductor irregular contact layer 10, and the second semiconductor epitaxial layer 11 to the top of the first semiconductor epitaxial layer 4. The first contact hole 12 is used to lead out the gate, and the second contact hole 13 is used to lead out the source.

[0084] (8) such as Figure 10 A Ni layer is sputtered and annealed to form an ohmic contact 6 in the first contact hole 12 and the second contact hole 13. The ohmic contact 6 is obtained by sputtering and annealing the Ni layer. After high-temperature annealing, it forms a Ni2Si compound with the semiconductor irregular contact layer 10 to achieve a low-resistance ohmic contact.

[0085] (9) For example Figure 11 Through the fifth mask, a Ti / W composite metal layer is deposited using a lift-off process, specifically: a gate metal 9 is formed in the first contact hole 12, and a metal contact plug 8 is formed in the second contact hole 13;

[0086] (10) such as Figure 12Then, the interlayer medium 7 is deposited again; then, through the sixth mask, the interlayer medium 7 is etched to form an opening, exposing the metal contact plug 8 above the second contact hole 13;

[0087] (11) A metal layer is deposited on the top of the device surface, and a metal pattern is defined through the seventh mask to perform top metallization and form a second metallization layer 5;

[0088] (12) Metallize the bottom to form a first metallization layer 1. The first metallization layer 1 serves as the drain and forms an ohmic contact with the semiconductor substrate 2.

[0089] In this embodiment, the first mask is used for trench etching; the second mask is used for selective etching of the semiconductor irregular contact layer 10; the third mask is used for etching to form the first contact hole 12; the fourth mask is used for etching to form the second contact hole 13; the fifth mask is used for lift-off filling of the Ti / W composite metal layer; the sixth mask is used for etching after the second deposition of the interlayer dielectric; and the seventh mask is used for top source / gate metallization to form the first metallization layer 1 and the second metallization layer 5.

[0090] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A field-effect transistor with an irregularly shaped contact layer, characterized in that, The first metallization layer includes a bottom first metallization layer, and the upper part of the first metallization layer includes, from bottom to top, a semiconductor substrate, a drift layer and a first semiconductor epitaxial layer. A trench is provided in the first semiconductor epitaxial layer, and the bottom of the trench extends below the interface between the first semiconductor epitaxial layer and the drift layer. The trench is sequentially filled with a second semiconductor epitaxial layer and a semiconductor filling layer. A semiconductor irregular contact layer is disposed above the second semiconductor epitaxial layer at a position corresponding to the first semiconductor epitaxial layer. An interlayer dielectric is deposited above the semiconductor irregular contact layer, and a first contact hole is formed between adjacent interlayer dielectrics. A second contact hole is etched between adjacent first contact holes, and the second contact hole extends through the interlayer dielectric, the semiconductor irregular contact layer, and the second semiconductor epitaxial layer to the top of the first semiconductor epitaxial layer. A composite metal layer is deposited in the first contact hole to form a gate metal, and a composite metal layer is deposited in the second contact hole to form a metal contact plug; a second metallization layer is deposited on the top of the device, the gate metal and the semiconductor fill layer form an ohmic contact and are isolated from the second metallization layer by an interlayer dielectric; the metal contact plug simultaneously contacts the sidewalls of the second semiconductor epitaxial layer and the semiconductor irregular contact layer and the top of the first semiconductor epitaxial layer, and is electrically connected to the second metallization layer to form a source metal region; The semiconductor irregular contact layer is made of nitrogen-doped 3C-SiC, with a thickness ranging from 60 nm to 200 nm and a doping concentration of not less than 1 × 10⁻⁶. 19 cm -3 ; The drift layer and the second semiconductor epitaxial layer are of the first conductivity type, and the first semiconductor epitaxial layer and the semiconductor filling layer are of the second conductivity type; the first conductivity type is N-type or P-type; the second conductivity type is the opposite of the first conductivity type. The semiconductor substrate, drift layer, first semiconductor epitaxial layer, semiconductor filling layer, and second semiconductor epitaxial layer are all made of 4H-SiC.

2. The field-effect transistor with an irregularly shaped contact layer according to claim 1, characterized in that, The composite metal layer is filled with Ti / W composite material, with the Ti layer located below and in contact with the Ni layer in ohmic contact, and the W layer located above the Ti layer; the thickness of the Ni layer is 10~100nm, and the thickness of the composite metal layer is 120nm~2μm.

3. The field-effect transistor with an irregularly shaped contact layer according to claim 2, characterized in that, The trench is a rounded-corner trench, which is obtained by a dry plasma etching process.

4. The field-effect transistor with an irregularly shaped contact layer according to claim 3, characterized in that, The doping concentration range of the drift layer of the first conductivity type is 1×10⁻⁶. 15 ~ 1×10 16 cm -3 The thickness ranges from 5μm to 30μm; The doping concentration of the second semiconductor epitaxial layer of the first conductivity type is lower than or the same as that of the drift layer, and the thickness ranges from 0.5 μm to 5 μm.

5. The field-effect transistor with an irregularly shaped contact layer according to claim 4, characterized in that, The first semiconductor epitaxial layer and the semiconductor filling layer of the second conductivity type have a consistent doping concentration, ranging from 1 × 10⁻⁶. 16  cm -3 Up to 1×10 17 cm -3 .

6. The field-effect transistor with an irregularly shaped contact layer according to claim 5, characterized in that, The first metallization layer and the second metallization layer are one or more combinations of the following materials: Ti, Ni, Ag, Au, Al, Cu.

7. A method for fabricating a field-effect transistor with an irregular contact layer as described in claim 6, characterized in that, Includes the following steps: (1) Growing a drift layer and a first semiconductor epitaxial layer on a semiconductor substrate; (2) A trench is formed by etching the first semiconductor epitaxial layer through the first mask, and the bottom of the trench extends below the interface between the first semiconductor epitaxial layer and the drift layer; (3) A second semiconductor epitaxial layer is grown inside and outside the trench, and a semiconductor filling layer is grown on the second semiconductor epitaxial layer; (4) Perform chemical mechanical polishing to planarize the semiconductor filling layer; (5) Deposit a semiconductor irregular contact layer on top of the planarized device, and then use a second mask to selectively etch the semiconductor irregular contact layer; (6) Deposit interlayer dielectric, and form a first contact hole by etching through a third mask, the bottom of the first contact hole extending to the top of the semiconductor filling layer; (7) A second contact hole is formed by etching through a fourth mask. The second contact hole is located between adjacent first contact holes and extends through the interlayer dielectric, semiconductor profile contact layer, and second semiconductor epitaxial layer to the top of the first semiconductor epitaxial layer. (8) Sputtering Ni layer and annealing to form ohmic contacts in the first and second contact holes; (9) A Ti / W composite metal layer is deposited using a lift-off process through the fifth mask, specifically: a gate metal is formed in the first contact hole, and a metal contact plug is formed in the second contact hole; (10) Deposit interlayer medium again; then etch the interlayer medium through the sixth mask to form an opening and expose the metal contact plug above the second contact hole; (11) A metal layer is deposited on the top of the device surface, and a metal pattern is defined through the seventh mask to perform top metallization and form a second metallization layer; (12) Perform metallization on the bottom to form the first metallization layer.

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