Method of manufacturing a semiconductor device

Abstract

This application provides a method for fabricating a semiconductor device, belonging to the field of semiconductor technology. The fabrication method includes: providing a substrate having a first region and a second region; a first gate structure, a first photoblocking layer, and a sidewall layer disposed on the first region; the first photoblocking layer covering the top wall of the first gate structure, and the sidewall layer covering the sidewalls of the first gate structure; forming a second photoblocking layer and a hard mask layer, the second photoblocking layer and the hard mask layer sequentially conformally covering the surface of the second region and exposing the first gate structure and the substrate surface of the first region; irradiating the substrate with ultraviolet light along the longitudinal direction to perform a wet oxidative etching process on the substrate on both sides of the first gate structure to form an initial trench; and continuing to wet etch the substrate along the initial trench to transform the initial trench into a sigma trench. This application can reduce or avoid damage to the top of the gate structure when forming trenches in the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating a semiconductor device. Background Technology

[0002] Source-drain embedded germanium-silicon (SiGe) technology is widely used below 90nm to improve PMOS speed. In the SiGe process, the AA region of the PMOS transistor needs to be opened by dry etching, and then the Sigma trench is formed by chemical etching with alkaline etchant (TMAH, tetramethylammonium hydroxide). Then, the germanium-silicon structure is grown in the trench by epitaxy.

[0003] However, due to the limited etching selectivity of dry etching, the dry etching process can also damage the mask layer (usually silicon oxide) on top of the gate of the PMOS transistor, resulting in a height difference between the PMOS transistor and the surrounding structure (such as NMOS transistor), which has an adverse effect on subsequent processes. Summary of the Invention

[0004] In view of this, this application aims to provide a method for fabricating a semiconductor device to reduce or avoid damage to the top of the gate structure when forming trenches in a substrate.

[0005] This application provides a method for fabricating a semiconductor device, comprising: A substrate is provided, the substrate having a first region and a second region, the first region having a first gate structure, a first light blocking layer and a sidewall layer, the first light blocking layer covering the top wall of the first gate structure, and the sidewall layer covering the sidewall of the first gate structure. A second light-blocking layer and a hard mask layer are formed, wherein the second light-blocking layer and the hard mask layer sequentially cover the surface of the second region in a conformal manner, and expose the first gate structure and the substrate surface of the first region; The substrate is irradiated with ultraviolet light along the longitudinal direction to perform a wet oxidative etching process on the substrates on both sides of the first gate structure to form an initial trench. The substrate is further wet-etched along the initial trench to transform the initial trench into a sigma trench.

[0006] In some embodiments, the wet oxidative etching process etches the substrate and the first photoblocking layer in a ratio greater than or equal to 10:1.

[0007] In some embodiments, under the irradiation of the ultraviolet light, the ratio of the rate of longitudinal etching of the substrate to the rate of transverse etching of the substrate in the wet oxidative etching process is greater than or equal to 5:1.

[0008] In some embodiments, the absorption rate of the first light-blocking layer and / or the second light-blocking layer for the ultraviolet light is greater than 95%.

[0009] In some embodiments, the first light-blocking layer comprises a carbon layer and / or a metal oxide layer; and / or, the second light-blocking layer comprises a carbon layer and / or a metal oxide layer.

[0010] In some embodiments, the substrate is made of silicon, and the etching solution of the wet oxidative etching process includes a mixed solution of hydrofluoric acid and an oxidant.

[0011] In some embodiments, the oxidant includes at least one of ozone and nitric acid.

[0012] In some embodiments, the etching solution of the wet oxidative etching process includes hydrofluoric acid and ozone, wherein, The content of the hydrofluoric acid is 100ppm to 100,000ppm, and the content of the ozone is 1ppm to 50ppm.

[0013] In some embodiments, the second region has a second gate structure, the first light-blocking layer also covers the top wall of the second gate structure, the sidewall layer also covers the sidewall of the second gate structure, and the second light-blocking layer conformally covers the substrate of the second region, the sidewall layer and the surface of the first light-blocking layer.

[0014] In some embodiments, the second light-blocking layer also covers the top wall of the sidewall layer within the first region.

[0015] In summary, the unexpected effects of this application are: the wet oxidative etching process is used to etch the substrate to form the initial trench of the sigma trench, thereby avoiding damage to the top of the first gate structure during dry etching; at the same time, during the wet oxidative etching process, ultraviolet light is irradiated onto the substrate along the longitudinal direction, thereby giving the wet oxidative etching process an anisotropic (directional) characteristic, enabling the initial trench to be generated by etching the substrate along the longitudinal direction; furthermore, the surface of the second region is covered by a second light-blocking layer, which can absorb ultraviolet light and prevent ultraviolet light from being reflected / refracted to other directions (different from the longitudinal direction) and incident into the first region, affecting the etching direction of the wet oxidative etching process; in addition, replacing the mask layer at the top of the first gate structure with the first light-blocking layer can increase the etching selectivity with the substrate on the one hand, and absorb ultraviolet light on the other hand, further preventing ultraviolet light from being reflected / refracted to other directions. Attached Figure Description

[0016] Figure 1 A schematic diagram showing the formation of a gate structure and a first sidewall layer on the NMOS and PMOS regions of a first substrate.

[0017] Figure 2 This is a schematic diagram of forming a second mask layer on the NMOS region of the first substrate.

[0018] Figure 3 A schematic diagram of performing dry etching to form a first initial trench in a first substrate of a PMOS region.

[0019] Figure 4 A schematic diagram of performing wet etching to make the first initial trench become the first sigma trench.

[0020] Figure 5 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.

[0021] Figure 6 This is a schematic diagram of a substrate having a first gate structure, a sidewall layer, and a first light-blocking layer, provided in an embodiment of this application.

[0022] Figure 7 This is a schematic diagram showing the sequential formation of a second light-blocking layer and a hard mask layer covering the substrate surface, according to an embodiment of this application.

[0023] Figure 8 This is a schematic diagram illustrating the patterning of a second light-blocking layer and a hard mask layer to expose the surface of a first region, according to an embodiment of this application.

[0024] Figure 9 This is a schematic diagram of forming an initial trench by performing a wet oxidative etching process according to an embodiment of this application.

[0025] Figure 10 This is a schematic diagram of forming sigma trenches by performing a second wet etching process according to an embodiment of this application.

[0026] exist Figures 1 to 4 In the middle: a1-PMOS region; a2-NMOS region; 10-first substrate; 11-first isolation structure; 20-gate structure; 21-first sidewall layer; 23-first mask layer; 25-second mask layer; 27-first initial trench; 29-first sigma trench.

[0027] exist Figures 6 to 10 In the diagram: A1 - First region; A2 - Second region; 100 - Substrate; 101 - Isolation structure; 103 - Oxide layer; 201 - Sidewall layer; 203 - First photoblocking layer; 210 - First gate structure; 220 - Second gate structure; 205 - Second photoblocking layer; 207 - Hard mask layer; X - First direction; Y - Second direction; 300 - Initial trench; S1 - First interface; S2 - Second interface; S3 - Third interface; 310 - Sigma trench. Detailed Implementation

[0028] Figure 1 This is a schematic diagram showing the formation of a gate structure 20 and a first sidewall layer 21 on the NMOS region a1 and PMOS region a2 of the first substrate 10. Figure 1 As shown, the first substrate 10 includes an NMOS region a2 and a PMOS region a1 defined by a first isolation structure 11. Gate structures 20 are provided on both the NMOS region a2 and the PMOS region a1. The top wall of the gate structure 20 is covered by a first mask layer 23 retained after the patterning process; the mask layer is made of, for example, silicon oxide. The sidewalls of the gate structure 20 and the first mask layer 23 are covered by sidewall layers 21. At this time, the overall height of the gate structures 20 in the PMOS region a1 and the NMOS region a2 is basically flush, meaning the thickness of the first mask layer 23 on the top wall of the gate structure 20 is basically the same.

[0029] Figure 2 This is a schematic diagram showing the formation of a second mask layer 25 on the NMOS region a2 of the first substrate 10. (See diagram below.) Figure 2 As shown, a patterned second mask layer 25 is formed to cover the surface of the NMOS region a2 and expose the surface of the PMOS region a1.

[0030] Figure 3 A schematic diagram illustrating the process of performing dry etching to form a first initial trench 27 in the first substrate 10 of the PMOS region a1. (See diagram) Figure 3 As shown, using the patterned second mask layer 25, a dry etching process is performed to form a first initial trench 27 in the PMOS region a1. At this time, the first mask layer 23 (made of silicon oxide) on the top wall of the gate structure 20 of the PMOS region a1 is also etched away to remove at least part of its thickness, so that the overall height of the gate structure 20 of the PMOS region a1 is lower than that of the gate structure 20 of the NMOS region a2.

[0031] Figure 4 A schematic diagram illustrating the process of performing wet etching to transform the first initial trench 27 into the first sigma trench 29. (See diagram) Figure 4 As shown, the first initial trench 27 is etched using an alkaline liquid to form the first sigma trench 29.

[0032] Depend on Figures 1 to 4 As can be seen, after the first sigma trench 29 is formed in PMOS region a1, the overall height of the gate structure 20 in PMOS region a1 is significantly reduced compared to the gate structure 20 in NMOS region a2. This height difference will adversely affect subsequent processes. The reason for this is that the aforementioned height difference is due to... Figure 3 This is caused by the low etching selectivity of the first substrate 10 relative to the first mask layer 23 in the dry etching process of the step.

[0033] Therefore, this application provides a method for fabricating a semiconductor device, the method comprising: providing a substrate having a first region and a second region, wherein a first gate structure, a first photoblocking layer and a sidewall layer are disposed on the first region, the first photoblocking layer covering the top wall of the first gate structure and the sidewall layer covering the sidewall of the first gate structure; forming a second photoblocking layer and a hard mask layer, the second photoblocking layer and the hard mask layer sequentially conformally covering the surface of the second region and exposing the first gate structure and the substrate surface of the first region; irradiating the substrate with ultraviolet light along the longitudinal direction and performing a wet oxidative etching process on the substrate on both sides of the first gate structure to form an initial trench; and continuing to wet etch the substrate along the initial trench to transform the initial trench into a sigma trench. The initial trenches for forming sigma trenches are formed by etching the substrate using a wet oxidation etching process, thereby avoiding damage to the top of the first gate structure during dry etching. Simultaneously, during the wet oxidation etching process, ultraviolet light is irradiated onto the substrate along the longitudinal direction, giving the wet oxidation etching process an anisotropic (directional) characteristic, enabling the initial trenches to be formed by etching the substrate along the longitudinal direction. Furthermore, the surface of the second region is covered by a second light-blocking layer, which absorbs ultraviolet light, preventing it from being reflected / refracted to other directions (different from the longitudinal direction) and incident into the first region, thus affecting the etching direction of the wet oxidation etching process. Additionally, replacing the mask layer at the top of the first gate structure with the first light-blocking layer increases the etching selectivity with the substrate and further absorbs ultraviolet light, preventing it from being reflected / refracted to other directions.

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 5 As shown, a method for fabricating a semiconductor device according to an embodiment of this application includes: S100: Provides a substrate having a first region and a second region. The first region has a first gate structure, a first light blocking layer and a sidewall layer. The first light blocking layer covers the top wall of the first gate structure and the sidewall layer covers the sidewall of the first gate structure. S200: A second photoblocking layer and a hard mask layer are formed, wherein the second photoblocking layer and the hard mask layer sequentially cover the surface of the second region in a conformal manner, and expose the first gate structure and the substrate surface of the first region; S300: Irradiate the substrate with ultraviolet light along the longitudinal direction and perform a wet oxidative etching process on the substrate on both sides of the first gate structure to form the initial trench; S400: Continue wet etching of the substrate along the initial trench to transform the initial trench into a sigma trench.

[0036] Figures 6-10 This is a schematic diagram of the structure corresponding to the respective steps of the method for fabricating a semiconductor device according to an embodiment of this application. Next, we will combine... Figures 6-10 The method for fabricating the semiconductor device provided in the embodiments of this application will be described in detail.

[0037] First, such as Figure 6 As shown, in step S100, a substrate 100 is provided, which has a first region A1 and a second region A2. The first region A1 has a first gate structure 210, a first light-blocking layer 203, and a sidewall layer 201. The first light-blocking layer 203 covers the top wall of the first gate structure 210, and the sidewall layer 201 covers the sidewalls of the first gate structure 210 and the first light-blocking layer 203. The second region A2 has a second gate structure 220, a first light-blocking layer 203, and a sidewall layer 201. The first light-blocking layer 203 covers the top wall of the second gate structure 220, and the sidewall layer 201 covers the sidewalls of the second gate structure 220 and the first light-blocking layer 203.

[0038] In some embodiments, the substrate 100 may be a silicon-based substrate, such as a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, etc., which will not be described in detail here.

[0039] In some embodiments, the first region A1 may be a PMOS region, and a sigma trench needs to be formed in the substrate 100 of this region for epitaxial growth of germanium-silicon as a P-type source / drain structure. The second region A2 includes an NMOS region and other regions. In other embodiments, the first region A1 may be an NMOS region, and the trench to be formed in the substrate 100 of this region may be different from the sigma trench, for example, a rectangular or quasi-rectangular trench, for epitaxial growth of silicon carbide as an N-type source / drain structure.

[0040] In this embodiment, as Figure 6 As shown, the first region A1 is the PMOS region, and for ease of illustration, only the NMOS region is shown in the second region A2. The substrate 100 of the first region A1 has a first active region (…). Figure 6 (Not shown in the image), the first gate structure 210 is located on the first active region, and the first active regions on both sides of the first gate structure 210 are used to form source and drain structures; the substrate 100 of the second region A2 has a second active region ( Figure 6(Not shown in the image), the second gate structure 220 is located on the second active region, and the second active regions on both sides of the second gate structure 220 are used to form source and drain region structures. The substrate 100 also has an isolation structure 101 surrounding the corresponding active regions to define the aforementioned first and second active regions. A thin oxide layer 103 covers the first and second active regions, and the first gate structure 210 and the second gate structure 220 are located on this oxide layer 103. The first gate structure 210 and the second gate structure 220 can be the final gate structure or a pseudo-gate structure that is replaced in a subsequent process.

[0041] Please continue to refer to Figure 6 A first light-blocking layer 203 covers the top walls of the first gate structure 210 and the second gate structure 220, and a sidewall layer 201 covers the sidewalls of the first gate structure 210 and the second gate structure 220. The first light-blocking layer 203 can be a single-layer structure or a multi-layer composite structure, and its absorption rate of ultraviolet light (e.g., wavelengths of 200 nm to 400 nm) can be greater than 95%. In other words, replacing the mask layer on top of the first gate structure 210 and the second gate structure 220 with the first light-blocking layer 203 can increase the etching selectivity with respect to the substrate 100, preventing damage to the first light-blocking layer 203 during subsequent etching of the substrate 100. Furthermore, it can absorb ultraviolet light, preventing it from being reflected / refracted to other directions (other than the longitudinal direction), which will be explained below.

[0042] In one example, the first light-blocking layer 203 may include a carbon layer or other carbon structure layer, such as an amorphous carbon layer, a diamond-like carbon layer, or a spin-coated carbon layer. In another example, the first light-blocking layer 203 may include a metal oxide layer that satisfies the above characteristics, such as zinc oxide, titanium oxide, or tungsten oxide. Furthermore, in addition to strong absorption of ultraviolet light, the first light-blocking layer 203 can also absorb visible light.

[0043] In some embodiments, the steps of forming the first gate structure 210, the second gate structure 220, the first light blocking layer 203, and the sidewall layer 201 may include: sequentially stacking a gate material layer and a first light blocking layer 203 on a substrate 100; then, patterning the gate material layer and the first light blocking layer 203; using the remaining gate material layer on the first region A1 as the first gate structure 210 and the remaining gate material layer on the second region A2 as the second gate structure 220; and combining the first gate structure 210 and the second gate structure 220. A first light-blocking layer 203 is retained on the top wall of 220. Next, a sidewall material layer is formed to conformally cover the surfaces of the first region A1 and the second region A2, the sidewalls of the first gate structure 210 and the second gate structure 220, and the top wall of the first light-blocking layer 203. An etching process is then performed to remove the sidewall material layer from the surfaces of the first region A1 and the second region A2 and the top wall of the first light-blocking layer 203. The remaining sidewall material layer covers the sidewalls of the first gate structure 210 and the second gate structure 220, forming the sidewall layer 201. Alternatively, other film layers may be provided between the gate material layer and the first light-blocking layer 203, or the remaining sidewall material layer may cover the surface of the first light-blocking layer 203.

[0044] from Figure 6 As can be seen, the tops of the first gate structure 210 and the second gate structure 220 are flush or substantially flush, that is, the surfaces of the first light blocking layer 203 on the first gate structure 210 and the first light blocking layer 203 on the second gate structure 220 are flush or substantially flush.

[0045] Next, as Figures 7-8 As shown, step S200 is performed to form a second light blocking layer 205 and a hard mask layer 207. The second light blocking layer 205 and the hard mask layer 207 sequentially cover the surface of the second region A2 and expose the surface of the first gate structure 210 and the first region A1.

[0046] Specifically, such as Figure 7 As shown, a second light-blocking layer 205 and a hard mask layer 207 are sequentially formed. The second light-blocking layer 205 conformally covers the surfaces of the first region A1 and the second region A2, the sidewalls of the sidewall layer 201, and the top wall of the first light-blocking layer 203. The hard mask layer 207 conformally covers the surface of the second light-blocking layer 205. The absorption rate of ultraviolet light by the second light-blocking layer 205 can be greater than 95%, and the hard mask layer 207 can be a silicon nitride layer or a composite film layer composed of stacked silicon nitride and silicon oxide layers.

[0047] In some examples, the material of the second light-blocking layer 205 may be the same as or different from that of the first light-blocking layer 203, and the second light-blocking layer 205 may also include a carbon layer and / or a metal oxide layer.

[0048] like Figure 8 As shown, the second light blocking layer 205 and the hard mask layer 207 are patterned. The second light blocking layer 205 and the hard mask layer 207 in the first region A1 are removed, exposing the sidewall layer 201 located on the sidewall of the first gate structure 210, the first light blocking layer 203 located on the top wall of the first gate structure 210, and the surface of the substrate 100 (the surface of the first active region) located on both sides of the first gate structure 210. Meanwhile, the hard mask layer 207 and the second light blocking layer 205 in the second region A2 are completely preserved.

[0049] Specifically, the step of patterning the second photoblock layer 205 and the hard mask layer 207 may include: forming a patterned photoresist layer on a substrate, the patterned photoresist layer covering the surface of the second region A2 and having an opening to expose the surface of the first region A1; then, using the patterned photoresist layer, performing an etching process to remove the second photoblock layer 205 and the hard mask layer 207 of the first region A1, retaining the second photoblock layer 205 and the hard mask layer 207 of the second region A2, and then removing the patterned photoresist layer. The photomask used to form the patterned photoresist layer can be reused with other photomasks exposing the first region A1.

[0050] In some embodiments, an anisotropic etching process can be used to etch the second light-blocking layer 205 and the hard mask layer 207 in the first region A1, so that the etched portion of the second light-blocking layer 205 covers the surface of the sidewall layer 201 in the first region A1, thereby preventing ultraviolet light from being reflected / refracted to other directions (other than the longitudinal direction). It should be noted that since most of the ultraviolet light incident in the first region A1 will be incident in the second region A2 even if it is reflected / refracted by the first gate structure 210, the second light-blocking layer 205 is most importantly used to cover the surface of the second region A2. Therefore, the second light-blocking layer 205 in the first region A1 can be omitted.

[0051] Next, as Figure 9 As shown, in step S300, ultraviolet light is irradiated onto the substrate 100 along the longitudinal direction (X direction) to perform a wet oxidative etching process on the substrate 100 on both sides of the first gate structure 210 to form the initial trench 300.

[0052] In the wet oxidation etching process, an etching solution with a large etching selectivity ratio to the substrate 100 and the first photoblocking layer 203 can be selected, so that the etching selectivity ratio between the substrate 100 and the first photoblocking layer 203 is greater than or equal to 10:1 (i.e., a large etching selectivity ratio). This ensures that when the initial trench 300 is formed on the substrate 100 (first active region) on both sides of the first gate structure 210, the first photoblocking layer 203 on the top wall of the first gate structure 210 will not be damaged (or the consumption of the first photoblocking layer 203 will be within the range allowed by the process). After the wet oxidation etching process is performed, the first photoblocking layer 203 on the top wall of the first gate structure 210 and the first photoblocking layer 203 on the top wall of the second gate structure 220 are basically flush and no height difference will be generated.

[0053] Understandably, dry etching processes are relatively easy to achieve etching with a clear directionality, i.e., anisotropic etching. However, etching with a clear directionality has relatively poor selectivity during etching, and it is easy to etch the first photoblocking layer 203 on the top wall of the first gate structure 210, resulting in a significant height difference between the first photoblocking layer 203 on the top wall of the first gate structure 210 and the first photoblocking layer 203 on the top wall of the second gate structure 220 after etching. In contrast, although wet etching processes are relatively easy to achieve high etching selectivity, the etching in the substrate 100 by wet etching is usually isotropic or substantially isotropic (poor etching directionality). When etching the substrate 100 using conventional wet etching processes, the substrate 100 is etched simultaneously along the lateral and longitudinal directions, making it difficult for the initial trench 300 to extend only along the longitudinal direction, and it may also extend along the lateral direction.

[0054] Therefore, in this application, an etching solution that can be catalyzed by ultraviolet light during wet etching of the substrate 100 is selected to achieve directionality during wet etching of the substrate 100. Specifically, during the wet oxidation etching process on the substrate 100, ultraviolet light is irradiated onto the substrate 100 along the longitudinal direction. Since the wet oxidation etching process involves simultaneously oxidizing and etching the resulting oxide, the rate and direction of the oxidation reaction play a decisive role in the etching rate and direction of the wet oxidation etching process, thereby determining the direction and morphology of the initial trench 300. Under the catalysis of ultraviolet light, the oxidation reaction rate along the longitudinal direction is significantly higher than that along the transverse direction (Y direction). That is, the oxidation reaction rate (fast reaction) of the irradiated interface of the substrate 100 (such as the first interface S1 in the figure) is significantly higher than that of the non-irradiated interface (such as the second interface S2 and the third interface S3). As a result, the oxidation reaction along the transverse direction of the substrate 100 is suppressed, and the oxidation reaction proceeds rapidly along the longitudinal direction of the substrate 100. When performing the wet oxidation etching process, the substrate 100 is oxidized along the longitudinal direction, and then the oxide is removed by etching. This makes the initial trench 300 extend longitudinally and has good directionality. It is equivalent to the wet oxidation etching process being able to anisotropically etch the substrate 100 downward under the catalysis of ultraviolet light.

[0055] Furthermore, since the second light-blocking layer 205 covers the entire second region A2, ultraviolet light incident on the second region A2 will be absorbed by the second light-blocking layer 205 and will not be reflected / refracted to the first region A1, thereby causing a change in the direction of the catalytic oxidation reaction, which in turn causes a change in the morphology of the initial trench 300. Meanwhile, the top wall of the first gate structure 210 in the first region A1 is protected by the first light-blocking layer 203, and the sidewalls are protected by the sidewall layer 201, so it will not be damaged in the wet oxidative etching process.

[0056] Furthermore, under ultraviolet light irradiation, the ratio of the longitudinal etching rate to the lateral etching rate of the substrate 100 in the wet oxidation etching process is greater than or equal to 5:1, to form an initial trench 300 that extends substantially longitudinally. On the other hand, in the wet oxidation etching process, ultraviolet light irradiation of the substrate 100 can also significantly increase the etching rate of the substrate 100, which is also beneficial for the directional etching of the substrate 100 by the wet oxidation etching process.

[0057] In some embodiments, the substrate 100 may be a silicon substrate, and the etching solution in the wet oxidative etching process may be a mixed solution of hydrofluoric acid and an oxidant. The oxidant may be selected from at least one of ozone (O3) and nitric acid (HNO3). The etching process of the substrate 100 by this etching solution is roughly an oxidation-etching cycle, that is, the oxidant oxidizes the silicon on the surface of the substrate 100, and the hydrofluoric acid then etches away the products (e.g., silicon oxide) after the silicon oxidation. Under conditions without ultraviolet irradiation, the etching of silicon by the mixed solution of hydrofluoric acid and oxidant is isotropic, and the etching rate of the etching solution is limited by the rate of silicon oxidation. However, in this application, under directional ultraviolet irradiation, photon energy is absorbed by oxidant molecules on the silicon surface or in the solution, generating highly active substances (such as strongly oxidizing groups and free radicals). These active substances greatly accelerate the oxidation process of silicon in the ultraviolet-irradiated area of ​​the substrate 100 surface, rapidly converting it into silicon oxide. Since the generated silicon oxide can be rapidly etched away by hydrofluoric acid in the mixed solution, the ultraviolet-irradiated silicon on the substrate 100 surface continues to be exposed, thereby enabling the oxidation-etching cycle to continue at high speed along the longitudinal direction. This results in relatively steep sidewalls of the initial trench 300, extending mainly along the direction of ultraviolet irradiation. In other words, the longitudinal cross-sectional shape (longitudinal section shape) of the initial trench 300 is a rectangular shape extending longitudinally, providing an ideal initial contour for subsequent etching steps.

[0058] In a specific example, the hydrofluoric acid content (mass fraction) in the mixed solution can be from 100 ppm to 100,000 ppm to obtain a stable and efficient directional etching effect. It should be noted that if the hydrofluoric acid concentration is too low, the generated silicon oxide may not be etched in time, hindering the reaction; if the hydrofluoric acid concentration is too high, it may weaken the selective advantage (directional advantage) of UV irradiation-enhanced oxidation and increase the risk of erosion of the hard mask layer 207. Furthermore, when using ozone water as the oxidizing solution, the ozone content (mass fraction) in the ozone water can be from 1 ppm to 50 ppm. This concentration range can provide a sufficient oxidizing solution while avoiding bubble formation, reaction runaway, or uniformity problems caused by excessive ozone concentration.

[0059] It is understandable that the aforementioned ultraviolet irradiation may include light of other wavelengths in addition to ultraviolet light. For example, visible light can also be used, provided that the intensity of ultraviolet light is ensured, as long as the light can induce the oxidation reaction.

[0060] Next, as Figure 10 As shown, step S400 is executed, and the substrate 100 is continued to be wet-etched along the initial trench 300, so that the initial trench 300 becomes a sigma trench 310.

[0061] The initial trench 300 can have a rectangular cross-sectional shape. By wet etching, the substrate 100 is etched downwards along the initial trench 300 to modify the cross-sectional shape of the initial trench 300 and transform it into a sigma shape.

[0062] In some embodiments, such as Figure 10 As shown, substrate 100 can be a silicon substrate, first region A1 can be a PMOS region, and the etching solution for wet etching substrate 100 can be an alkaline solution. The alkaline solution can be selected from at least one of TMAH (tetramethylammonium hydroxide), potassium hydroxide or ammonia water. The sigma trench 310 is formed by etching the sidewalls and bottom wall of the initial trench 300 along the corresponding crystal orientation. The cross-sectional shape of the sigma trench 310 is approximately the Greek letter sigma (Σ), so it is often called a sigma trench.

[0063] In summary, this application provides a method for fabricating a semiconductor device, which includes: providing a substrate having a first region and a second region; the first region having a first gate structure, a first photoblocking layer, and a sidewall layer; the first photoblocking layer covering the top wall of the first gate structure, and the sidewall layer covering the sidewall of the first gate structure; forming a second photoblocking layer and a hard mask layer, the second photoblocking layer and the hard mask layer sequentially conformally covering the surface of the second region and exposing the first gate structure and the substrate surface of the first region; irradiating the substrate with ultraviolet light along the longitudinal direction, and performing a wet oxidative etching process on the substrate on both sides of the first gate structure to form an initial trench; and continuing to wet etch the substrate along the initial trench to transform the initial trench into a sigma trench. The initial trenches for forming sigma trenches are formed by etching the substrate using a wet oxidation etching process, thereby avoiding damage to the top of the first gate structure during dry etching. Simultaneously, during the wet oxidation etching process, ultraviolet light is irradiated onto the substrate along the longitudinal direction, giving the wet oxidation etching process an anisotropic (directional) characteristic, enabling the initial trenches to be formed by etching the substrate along the longitudinal direction. Furthermore, the surface of the second region is covered by a second light-blocking layer, which absorbs ultraviolet light, preventing it from being reflected / refracted to other directions (different from the longitudinal direction) and incident into the first region, thus affecting the etching direction of the wet oxidation etching process. Additionally, replacing the mask layer at the top of the first gate structure with the first light-blocking layer increases the etching selectivity with the substrate and further absorbs ultraviolet light, preventing it from being reflected / refracted to other directions.

[0064] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0065] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0066] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0067] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate having a first region and a second region, the first region having a first gate structure, a first light blocking layer and a sidewall layer, the first light blocking layer covering the top wall of the first gate structure, and the sidewall layer covering the sidewall of the first gate structure. A second light-blocking layer and a hard mask layer are formed, wherein the second light-blocking layer and the hard mask layer sequentially cover the surface of the second region in a conformal manner, and expose the first gate structure and the substrate surface of the first region; The substrate is irradiated with ultraviolet light along the longitudinal direction, and a wet oxidative etching process is performed on the substrates on both sides of the first gate structure to form an initial trench. The substrate is further wet-etched along the initial trench to transform the initial trench into a sigma trench.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The wet oxidative etching process etches a substrate with a selectivity ratio of 10:1 to that of the first photoblocking layer.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, Under the irradiation of the ultraviolet light, the ratio of the rate of longitudinal etching of the substrate to the rate of transverse etching of the substrate in the wet oxidative etching process is greater than or equal to 5:

1.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first light-blocking layer and / or the second light-blocking layer have an absorption rate of more than 95% for the ultraviolet light.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The first light-blocking layer comprises a carbon layer and / or a metal oxide layer; and / or, the second light-blocking layer comprises a carbon layer and / or a metal oxide layer.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate is made of silicon, and the etching solution of the wet oxidative etching process includes a mixed solution of hydrofluoric acid and an oxidant.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The oxidant includes at least one of ozone and nitric acid.

8. The method for fabricating a semiconductor device according to claim 6 or 7, characterized in that, The etching solution in the wet oxidative etching process includes hydrofluoric acid and ozone, wherein, The content of the hydrofluoric acid is 100ppm to 100,000ppm, and the content of the ozone is 1ppm to 50ppm.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second region has a second gate structure, the first light-blocking layer also covers the top wall of the second gate structure, the sidewall layer also covers the sidewall of the second gate structure, and the second light-blocking layer conformally covers the surface of the substrate, the sidewall layer and the first light-blocking layer of the second region.

10. The method for fabricating a semiconductor device according to claim 1 or 9, characterized in that, The second light-blocking layer also covers the top wall of the sidewall layer within the first area.

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