A power semiconductor device and a manufacturing method thereof

Abstract

This application discloses a power semiconductor device and its manufacturing method, including a substrate, an epitaxial structure, a split gate structure, an interlayer dielectric layer, a front metal layer, and a back metal layer. The epitaxial structure is formed on the substrate and includes a well region, a source region, and a trench contact region. The well regions have a second conductivity type and are spaced apart along a first cross-sectional direction. The epitaxial structure between adjacent well regions is a first junction field-effect region. The source regions have a first conductivity type and are correspondingly arranged with the well regions. The trench contact regions are spaced apart along a second cross-sectional direction, and the epitaxial structure between adjacent trench contact regions is a second junction field-effect region. The split gate structure is disposed above the epitaxial structure. The front metal layer contacts the first and second junction field-effect regions to form a Schottky diode. The forward voltage of the Schottky diode is lower than that of the body diode. This application improves the bipolar degradation problem of the body diode by using a dual Schottky diode in conjunction with the split gate structure.

Description

[0001] This application claims priority to Chinese Patent Application No. 202610548997.7, filed on April 23, 2026, entitled "A Power Semiconductor Device and a Method for Manufacturing the Same", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a power semiconductor device and a method for manufacturing the same. Background Technology

[0003] Power MOSFETs, with their superior characteristics such as high temperature resistance, high breakdown electric field, and high switching frequency, have been widely used in power electronics fields such as new energy vehicles, industrial control, and photovoltaic power generation. As related equipment develops towards higher frequencies and higher efficiency, the industry's requirements for the long-term reliability, switching performance, and conduction characteristics of MOSFETs continue to increase, driving the continuous optimization and improvement of device structures.

[0004] In practical applications, MOSFETs face two key technical challenges: First, the "bipolar degradation" phenomenon of the body diode. When the device operates in freewheeling or third quadrant mode, the parasitic body diode conduction injects minority carriers. These carriers recombine at crystal defects, potentially leading to defect proliferation and causing the on-resistance to change over time, affecting the long-term reliability of the device. Second, the limitation of gate-drain capacitance (Cgd) on switching performance. In traditional gate structures, a large Cgd affects switching speed, increases switching losses, and may even trigger Miller current, causing the device to falsely turn on. This is especially true for silicon carbide (SiC) MOSFETs, restricting the full utilization of the high-speed characteristics of the SiC material itself. Furthermore, in conventional structures, there is a mutual constraint between conduction performance, reverse recovery performance, and breakdown voltage characteristics. How to achieve an optimal balance while ensuring these key performance indicators is a continuously focused technical direction in the industry.

[0005] To address these challenges, the industry has explored relevant technologies aimed at mitigating bipolar degradation, optimizing switching performance, and improving the balance between various characteristics. However, existing solutions still have room for improvement in overall performance and structural compatibility, making it difficult to meet the stringent requirements of high-end applications for high reliability, low loss, and high power density. Therefore, a more rationally designed power semiconductor device solution is needed to achieve simultaneous optimization of reliability, switching performance, and conduction characteristics. Summary of the Invention

[0006] To address the aforementioned technical problems, this application provides a power semiconductor device and a method for manufacturing the same.

[0007] Firstly, the power semiconductor device provided in this application adopts the following technical solution: A power semiconductor device includes a substrate, an epitaxial structure, a split gate structure, an interlayer dielectric layer, a front metal layer, and a back metal layer. The substrate has a first conductivity type. The epitaxial structure is formed on the substrate and includes a base epitaxial layer with the same conductivity type as the substrate. A well region, a source region, and a trench contact region are disposed within the base epitaxial layer. The well regions have a second conductivity type and are disposed on the upper surface of the base epitaxial layer. Multiple well regions are spaced apart along a first cross-sectional direction perpendicular to the thickness. The base epitaxial layer between adjacent well regions is defined as a first junction field-effect region. The source regions have a first conductivity type and are disposed corresponding to the well regions, on the surface of the corresponding well regions. The trench contact regions have a second conductivity type and are disposed within the base epitaxial layer. Along the first cross-sectional direction, the trench contact regions are adjacent to the well regions and far from the first junction field-effect region. Along a second cross-sectional direction perpendicular to the thickness and orthogonal to the first cross-sectional direction... Multiple trench contact regions are spaced apart, and the base epitaxial layer between adjacent trench contact regions defines a second junction field-effect region. A split gate structure is disposed above the epitaxial structure, including two spaced gate portions, the gap between the two gate portions corresponding to the first junction field-effect region in the vertical direction. An interlayer dielectric layer covers the split gate structure and the epitaxial structure, and has contact openings that expose the source region, trench contact region, first junction field-effect region, and second junction field-effect region. A front metal layer is disposed above the interlayer dielectric layer and fills the contact openings, forming ohmic contacts OC with the source region and trench contact region respectively; forming Schottky contacts SC with the first junction field-effect region and second junction field-effect region respectively, constituting a Schottky diode. A back metal layer is formed on the side of the substrate away from the epitaxial structure. The forward conduction voltage of the Schottky diode is lower than the forward conduction voltage of the built-in body diode.

[0008] By adopting the above technical solution, the split gate structure is integrated with the Schottky diode (SBD). The split gate structure can reduce the gate leakage capacitance, weaken the electric field coupling, improve the switching speed of the device and reduce the switching loss, and enhance the anti-misleading turn-on capability. The forward conduction voltage of the dual Schottky diode is lower than that of the body diode. When the freewheeling or third quadrant is in operation, the current preferentially passes through the Schottky diode, preventing minority carrier injection and recombination, thereby improving the "bipolar degradation" problem of the body diode and ensuring the long-term reliability of the device.

[0009] Optionally, a trench structure for reducing the inter-cell spacing of the device is provided on the base epitaxial layer, and the trench contact area is located at the bottom of the trench structure.

[0010] By adopting the above technical solution, the trench contact structure can reduce the cell pitch size of the device, prevent the on-resistance (Rsp) from rising while integrating the Schottky diode, achieve an optimized trade-off between characteristic on-resistance and reverse recovery performance, and improve the overall electrical performance of the device.

[0011] Optionally, the Schottky diode includes a first Schottky diode and a second Schottky diode, wherein the first Schottky diode is formed at the interface between the first junction field-effect region and the front metal layer, and the second Schottky diode is formed at the interface between the second junction field-effect region and the front metal layer.

[0012] By adopting the above technical solution, the specific formation position of the dual Schottky diode is defined, so that the first and second Schottky diodes correspond to the first and second junction field-effect regions respectively, forming a bidirectional current conduction channel, further widening the current flow path, ensuring that the current can preferentially flow through the Schottky diode when operating in freewheeling or third quadrant, thereby reducing the conduction share of the body diode, strengthening the anti-bipolar degradation effect, and improving the current carrying capacity and operating stability of the device.

[0013] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0014] By adopting the above technical solutions, different circuit design requirements can be flexibly adapted, and conventional semiconductor manufacturing processes can be compatible. This ensures that the device can form a PN junction and various functional regions normally, guarantees the stability of the device's electrical performance, and improves the versatility and applicability of the solution.

[0015] Optionally, the power semiconductor device also includes a protective layer that covers the front metal layer for surface protection. By adopting the above technical solution, the protective layer can isolate external moisture, impurities and other substances from corroding the internal structure of the device, prevent the metal layer from oxidizing or being damaged, and improve the device's environmental adaptability and long-term operational reliability.

[0016] Optionally, the protective layer includes a passivation layer and a resin layer, with the resin layer covering the upper surface of the passivation layer. The material of the passivation layer includes silicon dioxide, silicon nitride, or silicon oxynitride, and the thickness of the passivation layer is 0.10-20 μm. The material of the resin layer includes polyimide, polyamide, or polybenzoxazole, and the thickness of the resin layer is 1-50 μm.

[0017] By adopting the above technical solutions, the double-layer structure can further enhance the protection effect, adapt to the protection requirements of different devices, and ensure protection stability.

[0018] Optionally, the substrate material includes silicon, silicon carbide, or gallium nitride, the gate material is polycrystalline silicon, and the interlayer dielectric layer material includes silicon dioxide or silicon nitride.

[0019] By adopting the above technical solutions, the high-voltage and high-frequency operating requirements of the devices can be met, ensuring the structural stability and electrical performance of the devices, and they are compatible with conventional semiconductor manufacturing processes.

[0020] Optionally, the material of the front metal layer is selected from at least one of titanium, nickel, and molybdenum, and the material of the back metal layer is selected from at least one of titanium, nickel, silver, palladium, and gold.

[0021] By adopting the above technical solution, the front metal layer uses titanium, nickel, molybdenum, and their alloys or combinations as barrier metals, which can precisely adjust the Schottky barrier height and achieve a better balance between forward voltage drop and reverse leakage current. The materials selected for the back metal layer not only have a certain barrier adjustment auxiliary effect, but also enhance the bonding force between the device and the package structure, ensuring the reliability of back conductivity. At the same time, the reasonable combination of specific front and back metals has good compatibility with conventional semiconductor manufacturing processes, and can further optimize the overall electrical performance of the device and improve its operational stability, based on achieving low specific on-resistance and suppressing reverse leakage current of Schottky diodes.

[0022] Secondly, the manufacturing method of a power semiconductor device provided in this application adopts the following technical solution: A method for manufacturing a power semiconductor device includes the following steps: S1. Provide a substrate and form a basic epitaxial layer on the substrate to form an epitaxial structure; S2. Along a first cross-sectional direction perpendicular to the device thickness, a plurality of well regions with a second conductivity type are formed at intervals on the surface of the basic epitaxial layer. S3. Form a source region with a first conductivity type corresponding to each well region on the surface of each well region. Form a plurality of trench contact regions with a second conductivity type at intervals in the base epitaxial layer along a second cross-sectional direction that is perpendicular to the device thickness and orthogonal to the first cross-sectional direction. Make the trench contact regions adjacent to the well regions along the first cross-sectional direction. S4. Form a first junction field-effect region in the base epitaxial layer between adjacent well regions, and form a second junction field-effect region in the base epitaxial layer between adjacent trench contact regions. S5. A gate oxide layer and a polysilicon layer are formed above the epitaxial structure. The polysilicon layer is processed into two spaced gate portions to form a split gate structure, such that the gap between the two gate portions corresponds to the first junction field-effect region in the vertical direction. S6. An interlayer dielectric layer is deposited above the split gate structure, and the interlayer dielectric layer and the gate oxide layer are perforated to form contact openings at the corresponding positions of the source region, trench contact region, first junction field-effect region and second junction field-effect region, respectively. S7. Form a front metal layer, so that the front metal layer forms ohmic contacts with the source region and the trench contact region through the contact opening, and forms Schottky contacts with the first junction field-effect region and the second junction field-effect region, respectively. S8. A protective layer is formed above the front metal layer. The side of the substrate away from the epitaxial structure is thinned. A back metal layer is formed on the back side of the thinned substrate to form the drain electrode, thus completing the device fabrication.

[0023] By adopting the above technical solution, functional units such as the basic epitaxial layer, well region, source region, split gate structure, trench contact region, and metal layer are precisely formed step by step, achieving the integration of the split gate and the dual Schottky diode. The process steps are clear, controllable, and highly compatible, requiring no complex or special equipment. Simultaneously, through a reasonable process sequence design, the split gate structure's functions of reducing gate-drain capacitance and improving switching speed are ensured, while also guaranteeing a reliable connection between the dual Schottky diode and the device body. This results in a power semiconductor device that combines resistance to bipolar degradation, high switching speed, low loss, and excellent conduction characteristics, meeting the application requirements of high-frequency, high-efficiency power electronic devices.

[0024] Optionally, in step S3, the specific steps for forming the trench contact area include: S31. Deposit mask layer, define P+ source region pattern through photolithography, and use ion implantation process to implant impurities of the second conductivity type into the base epitaxial layer to form P+ source region. S32. Based on the existing P+ source region pattern, an etching process is used to etch the P+ source region downwards along the pattern to form multiple shallow trenches that correspond one-to-one with the P+ source region, and the shallow trenches end inside the P+ source region to form a trench contact area.

[0025] By adopting the above technical solution, the P+ source region can be prepared and shallow trench etching can be completed using the same photolithography pattern, reducing photolithography steps and manufacturing costs. At the same time, the trench structure can reduce the inter-cell spacing of the device and optimize the conductivity of the device.

[0026] In summary, this application includes at least one of the following beneficial technical effects: 1. Improve the "bipolar degradation" problem of MOSFET body diode by integrating dual Schottky diodes to allow current to preferentially pass through the majority carrier channel, prevent minority carrier injection and recombination, and ensure long-term device reliability; 2. The trench contact structure can reduce the cell pitch of the device, preventing the on-resistance (Rsp) from increasing while integrating a Schottky diode. This achieves an optimized trade-off between characteristic on-resistance and reverse recovery performance, improving the overall electrical performance of the device. 3. It has strong process compatibility and flexible design, supports multiple structural combinations and process adaptations, can meet the performance requirements of different application scenarios, and has a standardized manufacturing process, which is conducive to mass production and promotion, and provides reliable device support for high-frequency and high-efficiency power electronic devices. Attached Figure Description

[0027] Figure 1This is a cross-sectional schematic diagram of a power semiconductor device provided in an embodiment of this application; Figure 2 This is a top view schematic diagram of a power semiconductor device provided in an embodiment of this application; Figure 3 This is a flowchart illustrating a method for fabricating a power semiconductor device according to an embodiment of this application; Figures 4 to 20 This is a schematic diagram of the fabrication process of the power semiconductor device provided in the embodiments of this application.

[0028] Explanation of reference numerals in the attached figures: 10. Substrate; 20. Epitaxial structure; 21. Basic epitaxial layer; 211. Source region; 212. Well region; 213. Trench contact region; 214. First junction field-effect region; 215. Second junction field-effect region; 30. Gate oxide layer; 40. Interlayer dielectric layer; 50. Front metal layer; 51. Schottky contact region; 52. Ohmic contact region; 60. Protective layer; 61. Passivation layer; 62. Resin layer; 70. Back metal layer; 80. Polysilicon layer; 81. Gate portion. Detailed Implementation

[0029] The following is in conjunction with the appendix Figure 1-20 This application will be described in further detail.

[0030] This application discloses a power semiconductor device. Power semiconductor devices can be widely used in various fields such as new energy, industrial control, rail transportation, and high-end electronics. For example, in the field of new energy vehicles, they are used in main drive inverters, on-board chargers (OBCs), and DC-DC converters as power switching devices to realize the conversion of electrical energy between the power battery and the motor, the conversion of mains power and the charging and discharging of the power battery, and the stable output of power supplies at different voltage levels, ensuring vehicle power output and energy utilization efficiency. In the photovoltaic / wind power field, they are integrated into grid-connected inverters to complete the conversion of DC power output from the new energy power generation system to AC power, while simultaneously realizing voltage stabilization, filtering, and grid-connected control of electrical energy, improving the efficiency of renewable energy generation. Energy grid connection reliability; in energy storage systems, it is applied to bidirectional converter modules to realize bidirectional power transmission control between energy storage units and the grid, supports flexible switching of charging and discharging modes, and ensures the efficient operation of energy storage systems; in the rail transit field, it is used in traction converter systems to control the start, stop and speed regulation of traction motors, realize precise allocation and efficient utilization of power, and reduce the energy consumption of rail transit; in the industrial and high-end electronics fields, it can be used in industrial servo drives, data center power supplies and high-end consumer electronics fast charging adapters to realize high-precision speed regulation control of motors, efficient power supply of server power supplies, and small-volume, high-efficiency power conversion of fast charging equipment.

[0031] In one embodiment, this application specifically describes a power MOSFET with a split gate and an integrated Schottky diode (SBD), such as a silicon-based MOSFET (Si MOSFET), a silicon carbide-based MOSFET (SiC MOSFET), a gallium nitride-based MOSFET (GaN MOSFET), or other wide-bandgap and conventional semiconductor-based devices. Preferably, it is fabricated using silicon carbide (SiC) or gallium nitride (GaN) wide-bandgap semiconductor materials, combining the mature process compatibility of silicon-based devices with the high voltage, high frequency, and low loss characteristics of wide-bandgap semiconductors. (Refer to...) Figure 1 This is a cross-sectional view of a semiconductor device cell provided in the embodiments of this application, including a substrate 10, an epitaxial structure 20, a split gate structure, an interlayer dielectric layer 40, a front metal layer 50, and a back metal layer 70. The epitaxial structure 20 is provided with a plurality of well regions 212, a plurality of source regions 211, and a plurality of trench contact regions 213.

[0032] Specifically, refer to Figure 1 and Figure 2 In one embodiment, the substrate 10 has a first conductivity type, for example, N-type conductivity formed by N+ doping; the epitaxial structure 20 is formed on the substrate 10, for example, it can be composed of a base epitaxial layer 21 (N-Epi) formed on the substrate 10 by an epitaxial process, the conductivity type of the base epitaxial layer 21 is the same as that of the substrate 10, but the doping concentration is lower than that of the substrate 10, for example, the doping concentration is N-; two well regions 212 (P-well) are provided in one cell, the well regions 212 have a second conductivity type, specifically P-type conductivity, and the doping concentration is P-, the P-well well regions 212 are disposed in the base epitaxial layer 212. The surface layer of the device has two well regions 212 spaced apart along a first cross-sectional direction (defined as the X direction) perpendicular to the device thickness. A base epitaxial layer 21 between adjacent well regions 212 defines a first junction field-effect region 214 (JFET). A source region 211, having a first conductivity type, such as N+, is disposed corresponding to each well region 212, specifically on the surface layer of the corresponding well region 212. A trench contact region 213, having a second conductivity type, such as P+, is disposed within the base epitaxial layer 21. Along the first cross-sectional direction, the trench contact region 213 is adjacent to the well region 212 and away from the first junction field-effect region 214. (Refer to...) Figure 2 This diagram shows a top view of a power semiconductor device. For ease of demonstration, the surface protective layer 60 and the front metal layer 50 have been removed from the top view. Figure 2 As shown, trench contact areas 213 are spaced apart along a second cross-sectional direction (defined as the Y direction) that is perpendicular to the thickness and orthogonal to the direction of the first cross-section, and the base epitaxial layer 21 between adjacent trench contact areas 213 is defined as a second junction field-effect region 215.

[0033] Continue to refer to Figure 1A split gate structure is disposed above the epitaxial structure 20, including two spaced gate portions 81. The gate portion 81 is preferably made of polysilicon. The gap between the two gate portions 81 corresponds vertically to the first junction field-effect region 214, forming a split planar gate. This reduces the overlap area between the gate and drain, lowers the gate-drain charge (Qgd) and reverse transfer capacitance (Cgd), thereby increasing the device switching frequency and reducing switching losses. At the same time, the spaced layout optimizes the electric field distribution in the JFET region, improving the electric field concentration problem caused by the traditional integral gate structure. Interlayer dielectric layer 40 The dielectric (ILD) covers the split gate structure and epitaxial structure 20, and has contact openings 41 that expose the source region 211, trench contact region 213, first junction field-effect region 214 and second junction field-effect region 215; the front metal layer 50 is disposed above the interlayer dielectric layer 40 and fills the contact openings 41. The front metal layer 50 contacts the trench contact region 213 to form an ohmic contact OC, and correspondingly forms an ohmic contact region 52; the front metal layer 50 contacts the first junction field-effect region 214 and the second junction field-effect region 215 to form a Schottky contact SC, and correspondingly forms Schottky contact regions 51 (Schottky1 and Schottky2, etc.). Figure 18 As shown in the figure, the Schottky junction formed at the interface between the Schottky contact region 51 and the epitaxial structure 20 is equivalent to a Schottky diode (SBD) integrated on the device. In this application, a first Schottky diode is formed corresponding to the first junction field-effect region 214, and a second Schottky diode is formed at the second junction field-effect region 215. The bidirectional current conduction channel formed can further widen the current flow path, reduce the conduction share of the body diode, and enhance the anti-bipolar degradation effect. By reasonably setting the material or work function of the Schottky barrier metal, the forward conduction voltage of the Schottky diode is lower than the forward conduction voltage of the built-in body diode of the device (for example, the forward conduction voltage of the Schottky diode is 0.1-0.5V lower than that of the built-in body diode of the device), thereby preferentially conducting under freewheeling conditions, suppressing the turn-on of the built-in body diode, and reducing reverse recovery loss and bipolar degradation risk. The back metal layer 70 is formed on the side of the substrate 10 away from the epitaxial structure 20, and serves as the drain electrode of the device to realize the collection of drain current and electrical connection with external circuits.

[0034] Understandably, this application integrates a split-gate structure with a Schottky diode (SBD). The split-gate structure reduces gate-drain capacitance, weakens electric field coupling, improves device switching speed, reduces switching losses, and enhances anti-misleading turn-on capability. The forward conduction voltage of the dual Schottky diode is lower than that of the parasitic body diode inside the device. When operating in freewheeling or third quadrant (reverse freewheeling), the current preferentially passes through the Schottky diode, preventing minority carrier injection and recombination, thereby improving the "bipolar degradation" problem of the body diode, ensuring the long-term reliability of the device, and further reducing switching losses. This structure is particularly suitable for wide bandgap semiconductor devices such as silicon carbide (SiC), which can fully leverage the high voltage, high frequency, and low loss performance advantages of wide bandgap materials, expanding the application scenarios of the device in the field of high voltage power electronics.

[0035] Reference Figure 1 In one embodiment, a trench structure for reducing the device cell pitch is provided on the base epitaxial layer 21. The trench contact area 213 is located at the bottom of the trench structure and extends into the base epitaxial layer 21 to form a trench-type contact structure. By using this trench-type contact structure, the trench contact area 213 can be extended and arranged in the vertical direction, releasing the horizontal layout space on the device surface, thereby achieving a compact arrangement of the trench contact area 213 and the main device cell area (P-well-JFET-P-well), reducing the cell pitch and improving the device integration.

[0036] Understandably, in traditional devices, reducing reverse recovery charge (Qrr) requires weakening the conductivity of the parasitic diode, which often leads to obstructed current transport paths and increased specific on-resistance (Rsp, on-resistance per unit area). Conversely, increasing the current channel width to reduce Rsp increases minority carrier injection into the parasitic diode, raising Qrr. It is difficult to achieve a balance between these two factors. The power semiconductor device of this application improves the inherent contradiction between specific on-resistance (Rsp) and reverse recovery charge (Qrr) in traditional structures. On the one hand, a smaller pitch ensures a relatively low Rsp; on the other hand, the integrated SBD can shunt reverse current, reducing Qrr. Therefore, this invention achieves an optimized trade-off between low-loss conduction and fast reverse recovery characteristics, improving the overall electrical performance of the device.

[0037] Continue to refer to Figure 1 In one embodiment, the power semiconductor device further includes a protective layer 60, which covers the front metal layer 50 to achieve surface protection and electrical isolation of the device, such as... Figure 1As shown, the protective layer 60 adopts a double-layer stacked structure, including a surface passivation layer 61 and a resin layer 62 (PI) stacked sequentially. The surface passivation layer 61 can be made of at least one of silicon nitride (SiN), silicon dioxide (SiO2), or silicon oxynitride (SiON), and the thickness of the passivation layer 61 is preferably 0.10-20μm. It can block the intrusion of impurities such as water vapor and ions, and protect the active area and metal interconnect structure on the surface of the device. The resin layer 62 can be made of at least one of polyimide (PI), polyamide (PA), and polybenzoxazole (PBO), and the thickness of the resin layer 62 is 1-50μm. It has both excellent mechanical protection performance and insulation stability, further improving the device's resistance to environmental stress.

[0038] Understandably, the protective layer 60 isolates the active region and metal interconnect structure of the device from external moisture, ionic impurities, and environmental pollutants. Simultaneously, it inhibits oxidation, corrosion, or physical damage to the front-side metal layer, improving the device's environmental adaptability in humid and hot environments and complex industrial settings. This ensures the structural integrity and electrical performance stability of the device under long-term high-voltage, high-frequency operating conditions, extending its lifespan. The dual-layer structure further enhances the protective effect, adapting to the protection needs of different devices and ensuring protection stability.

[0039] In one embodiment, the material of the front metal layer 50 in this application is selected from at least one of titanium, nickel, and molybdenum, or any combination thereof, and may also be selected from multi-element alloy systems such as titanium-nickel and nickel-molybdenum.

[0040] It is understandable that by selecting metal materials with specific work functions, the Schottky barrier height can be adjusted, thereby achieving an optimal trade-off between the forward voltage drop and the reverse leakage current of the device, ensuring low loss characteristics during forward conduction while suppressing the increase in leakage current under reverse bias.

[0041] In one embodiment, the material of the back metal layer 70 is selected from at least one of titanium, nickel, silver, palladium, and gold.

[0042] Understandably, the material selected for the back metal layer 70 not only provides a certain barrier modulation assistance but also enhances the bonding force between the device and the package structure, ensuring the reliability of back conductivity. Simultaneously, the appropriate combination of the specific front metal and the back metal exhibits good compatibility with conventional semiconductor manufacturing processes. This allows for the further optimization of the device's overall electrical performance and improvement of operational stability, building upon the achievement of low specific on-resistance and suppression of reverse leakage current in Schottky diodes.

[0043] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0044] It is understood that the device design in this application is not only applicable to the above-mentioned N-type system, but also supports P-type conductivity design: when the device as a whole adopts a P-type system (i.e., the substrate 10 and the basic epitaxial layer 21 are both P-type), the conductivity type of all doped regions needs to be reversed accordingly (e.g., the original P-well region is changed to an N-well region) to ensure the rationality of the internal PN junction structure and current transport mechanism of the device; in terms of material selection, in addition to selecting a work function metal that is compatible with P-type semiconductors to optimize the Schottky contact characteristics, the impurity type of ion implantation and the annealing activation process parameters also need to be adjusted accordingly. At the same time, the carrier (hole) mobility characteristics of the device under the P-type system need to be taken into consideration in the design. By matching the corresponding doping concentration and structural size, the device can be guaranteed to have the advantages of low conduction loss and high blocking reliability under the P-type design, and the performance balance under different conductivity type requirements can be achieved.

[0045] like Figure 3 As shown in the embodiments, this application also discloses a method for manufacturing a power semiconductor device, including the following steps: S1. Provide a substrate 10 and form a basic epitaxial layer 21 on the substrate 10 to form an epitaxial structure 20; S2. Along a first cross-sectional direction perpendicular to the thickness of the device, a plurality of well regions 212 with a second conductivity type are formed on the surface of the base epitaxial layer 21 at intervals. S3. A source region 211 with a first conductivity type is formed on the surface of each well region 212, corresponding one-to-one with the well region 212. A plurality of trench contact regions 213 with a second conductivity type are formed in the base epitaxial layer 21 along a second cross-sectional direction that is perpendicular to the device thickness and orthogonal to the first cross-sectional direction. The trench contact regions 213 are adjacent to the well regions 212 along the first cross-sectional direction. S4. Form a first junction field-effect region 214 in the base epitaxial layer 21 between adjacent well regions 212, and form a second junction field-effect region 215 in the base epitaxial layer 21 between adjacent trench contact regions 213. S5. A gate oxide layer 30 and a polysilicon layer 80 are formed above the epitaxial structure 20. The polysilicon layer 80 is processed into two spaced gate portions 81 to form a split gate structure, such that the gap between the two gate portions 81 corresponds to the first junction field-effect region 214 in the vertical direction. S6. An interlayer dielectric layer 40 is deposited above the split gate structure, and the interlayer dielectric layer 40 and the gate oxide layer 30 are perforated to form contact openings 41 at the corresponding positions of the source region 211, the trench contact region 213, the first junction field effect region 214 and the second junction field effect region 215, respectively. S7. Form a front metal layer 50, so that the front metal layer 50 forms ohmic contacts with the source region 211 and the trench contact region 213 through the contact opening 41, and forms Schottky contacts with the first junction field effect region 214 and the second junction field effect region 215, respectively. S8. A protective layer 60 is formed above the front metal layer 50. The side of the substrate 10 away from the epitaxial structure 20 is thinned. A back metal layer 70 is formed on the back side of the thinned substrate 10 to form a drain electrode, thus completing the device fabrication.

[0046] Specifically, such as Figure 4 As shown, a substrate 10 (Sub) of the first conductivity type is provided, and a basic epitaxial layer 21 (N-Epi) of the same conductivity type as the substrate 10 is formed on the substrate 10 by an epitaxial process. The basic epitaxial layer 21 constitutes the epitaxial structure 20 of the device. The material of the substrate 10 can be semiconductor materials such as silicon (Si), silicon carbide (SiC), and silicon nitride (SiN). The first conductivity type can be selected as N-type or P-type according to the actual application requirements. In this application, the basic epitaxial layer 21 is set to N-type to adapt to the design logic of mainstream power devices. If the basic epitaxial layer 21 is selected as P-type, the conductivity type of all doped regions in the subsequent embodiment steps will be changed to the opposite type to ensure the rationality of the internal PN junction structure and current transport mechanism of the device.

[0047] like Figure 5 As shown, in the first cross-sectional direction, a mask layer is first formed on the surface of the basic epitaxial layer 21. After the pattern is defined by photolithography, an ion implantation opening at a preset position is formed on the mask layer by etching process. Then, according to the design requirements, the implantation dose and energy are controlled to implant P-type impurity ions into the region of the basic epitaxial layer 21 corresponding to the opening, and finally a P-well trap region 212 is formed, laying the foundation for the subsequent active region structure preparation.

[0048] like Figure 6 As shown, an N+ source region 211 is formed on the surface of each P-well region 212 by ion implantation. Specifically, a mask layer for ion implantation is first deposited, then photoresist is coated and patterned by photolithography to expose the target area where the N+ source region 211 needs to be formed; then N+ impurity ions are implanted into the target area to form the N+ source region 211 corresponding to the P-well region 212.

[0049] like Figure 7 , Figures 8-10 As shown, in the second section direction (Y direction) orthogonal to the first section direction, multiple spaced trench contact regions 213 (P+ source regions) are formed within the base epitaxial layer 21. Figure 7 This is a top view diagram of the power semiconductor device corresponding to this step. Figure 8 For along Figure 7A schematic diagram of the cross-section corresponding to one cell element along line AA in the middle. Figure 9 For along Figure 7 A schematic diagram of a cross-section of a single cell along the BB line. Figure 10 For along Figure 7 A cross-sectional schematic diagram of the CC line is shown. Specifically, the P+ source region pattern is first defined by depositing a mask layer and photolithography. The P+ source region is then formed using ion implantation, a process largely consistent with the fabrication of the N+ source region. Ion implantation methods include mask-implantation and self-aligned implantation. Subsequently, ion implantation is performed on the JFET region to reduce the device's specific on-resistance (Rsp), thereby forming a first conductivity type JFET region (i.e., the first junction field-effect region 214) between two adjacent P-well regions 212, and another first conductivity type JFET region (i.e., the second junction field-effect region 215) between two adjacent trench contact regions 213. As shown in the figure, the first junction field-effect region 214 is located between two adjacent P-well regions 212 in the first cross-sectional direction. Figure 8 The second junction field-effect region 215 is arranged alternately with the groove contact region 213 in the second cross-sectional direction. Figure 10 ).

[0050] like Figure 11 As shown, a gate oxide layer 30 (SiO2) and a polysilicon layer 80 are formed on top of the basic epitaxial layer 21 (epitaxy structure 20). The specific steps are as follows: First, a carbon film is sputtered onto the surface of the ion-implanted wafer. This carbon film serves as a protective layer during the high-temperature annealing process to prevent damage to the wafer surface. Then, high-temperature laser annealing is performed in an argon (Ar) environment to repair the lattice damage caused by ion implantation and to activate the implanted impurity ions. After annealing, the wafer surface is subjected to high-temperature oxidation treatment, and then the oxide layer on the surface is removed. A gate oxide layer 30 (SiO2) is formed on the wafer surface through processes such as thermal oxidation or chemical vapor deposition (CVD). Finally, the polysilicon layer 80 is deposited through chemical vapor deposition (CVD) to provide the gate electrode base material for the subsequent patterning etching of the split gate structure.

[0051] like Figure 12As shown, the polysilicon layer 80 is patterned and etched to form a split gate structure. The specific steps are as follows: First, the split gate pattern is defined and a mask opening is formed using photolithography. Then, the polysilicon layer 80 is etched using a dry etching process to divide it into two independent gate portions 81 (denoted as Poly1 and Poly2, respectively), ultimately forming the split gate structure. The design ensures that the gap between the two gate portions 81 is aligned vertically with the first junction field-effect region 214, with an alignment deviation not exceeding 0.5 μm, to ensure the gate's electric field modulation effect on the JFET region. The fabrication process of the split gate structure in this application is not limited to this; selective deposition, post-deposition etching, and other semiconductor industry processes can also be used to achieve the same results, all of which can meet the requirements for device gate isolation and electric field modulation.

[0052] like Figure 13 As shown, an ILD interlayer dielectric layer 40 is deposited above the split gate structure using a chemical vapor deposition (CVD) process. Specifically, the ILD interlayer dielectric layer 40 covers two independent polysilicon gate portions 81. The ILD layer deposited in this step connects with the gate oxide layer 30 formed in the previous step to form a closed-loop insulating protection structure, which together achieves isolation between the gate structure and other regions. The material of the ILD layer can be silicon dioxide (SiO2), silicon nitride (SiN), or a composite dielectric system of both, all of which can meet the device's requirements for insulation reliability, density, and process compatibility.

[0053] like Figure 2 , Figures 14-16 As shown, contact openings are made in the deposited interlayer dielectric layer 40 to achieve electrical connection between the source, junction field-effect region and subsequent metal electrode, and to define the isolation boundaries of each region: Figure 2 This is a top view of the power semiconductor device after this step is completed. Figure 14 For along Figure 2 Schematic diagram of the cross section of line AA in the middle. Figure 15 For along Figure 2 Schematic diagram of the cross section of the BB line. Figure 16 For along Figure 2A cross-sectional schematic diagram of the CC line. The specific process steps are as follows: First, the contact area pattern is defined using photolithography. Dry etching is used to create openings in the interlayer dielectric layer 40. Contact openings 41 are formed at corresponding positions in the N+ source region 211, trench contact region 213, first junction field-effect region 214, and second junction field-effect region 215. The interlayer dielectric layer 40 and gate oxide layer 30 located in the gap between the two gate portions 81 are etched away until the surfaces of the first junction field-effect region 214, the second junction field-effect region 215, the N+ source region 211, and the trench contact region 213 are exposed. Simultaneously, a portion of the gate oxide layer 30 and a portion of the interlayer dielectric layer 40 are retained to form an isolation region, which enables electrical isolation between different contact areas. Subsequently, based on the formed P+ source region pattern, the trench contact region 213 (P+ source region) is etched to form a shallow trench structure (Trench) for reducing the device cell spacing. Based on the existing P+ source region pattern, an etching process is used to etch the base epitaxial layer 21 downwards along the pattern to form multiple shallow trenches corresponding to the P+ source regions. The shallow trenches do not penetrate the P+ source regions and end inside the P+ source regions. The specific depth is 1 / 3 to 1 / 2 of the original P+ doped region thickness and is lower than the lower surface of the N+ source region 211, so that the P+ source regions form a trench structure. It should be noted that this process uses the existing photolithographic mask pattern in the existing P+ source region pattern to directly perform trench etching, achieving the combined process effect of one photolithography and dual purpose. This reduces the number of photolithography steps and mask costs required to independently prepare trenches, and reduces the overall manufacturing cost of the device. The preparation process of the contact opening 41 in this application is not limited to the above method. Mask-defined processes, self-aligned processes, and other semiconductor industry technologies can also be used, all of which can meet the design requirements of contact reliability and isolation effectiveness.

[0054] refer to Figure 2 , Figures 17-19 A front-side metal layer 50 is formed through a sputtering process. Figure 17 For along Figure 2 Schematic diagram of the cross section of line AA in the middle. Figure 18 For along Figure 2 Schematic diagram of the cross section of the BB line. Figure 19 For along Figure 2A cross-sectional schematic diagram of the CC line. The front metal layer 50 forms electrical contacts with the source region 211, the trench contact region 213, and each junction field-effect region through the contact opening 41. An ohmic contact OC is formed at the interface with the N+ source region 211 and the trench contact region 213 (P+ source region), and a Schottky contact SC is formed at the interface with the first junction field-effect region 214 and the second junction field-effect region 215. Correspondingly, Schottky contact regions 51 (Schottky1, Schottky2) and ohmic contact regions 52 are formed. The Schottky junction formed at the interface between the Schottky contact region 51 and the epitaxial structure 20 is equivalent to a Schottky diode (SBD) integrated on the device. Specifically, the sputtering material includes, but is not limited to, metals and polysilicon. A corresponding Schottky contact region 51 (Schottky1, the first Schottky diode) is formed on the surface above the first junction field-effect region 214 which is not covered by the oxide layer. Another Schottky contact region 51 (Schottky2, the second Schottky diode) is formed on the surface of the second junction field-effect region 215. An ohmic contact region 52 is formed on the surface of the N+ source region 211 and the trench contact region 213 (P+ source region). The material of the front metal layer includes, but is not limited to, titanium (Ti), nickel (Ni), molybdenum (Mo), any alloy thereof, or any combination thereof.

[0055] It should be noted that, Figure 17 The ohmic contact region 52 corresponding to the N+ source region 211 is not explicitly shown, but it is known to those skilled in the art that the N+ source region, as a heavily doped region, primarily functions to achieve low-resistance current transport. The low contact resistance characteristics of the ohmic contact match this function, making it a conventional design choice for source current inflow and outflow. Figure 17 The ohmic contact region 52 of the trench contact region 213 (P+ source region) is highlighted because the structure of the trench contact region 213 is formed by etching the P+ source region. This trench structure not only provides the basis for the integration of the second Schottky diode, but also forms an ohmic contact with the metal layer by retaining the heavily doped characteristics of the P+ source region, thus achieving low-resistance conduction in conjunction with the ohmic contact of the N+ source region 211. This diagrammatic approach clarifies the correspondence between "shallow trench structure - ohmic contact - P+ source conduction" and "second junction field-effect region 215 - Schottky contact - SBD2 function," making the contact type distribution and structural design logic of the device easier to understand.

[0056] like Figure 20As shown, a protective layer 60 is formed above the front metal layer 50. Specifically, it is formed by sequentially depositing a surface passivation layer 61 and a resin layer 62 (PI). The surface passivation layer 61 is made of materials including, but not limited to, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or combinations thereof, with a thickness of 0.10-20 μm. The resin layer 62 is made of at least one of polyimide (PI), polyamide (PA), and polybenzoxazole (PBO), with a thickness ranging from 1 to 50 μm. In this embodiment, polyimide is preferred as the material of the resin layer 62, with a thickness ranging from 10 to 15 μm.

[0057] like Figure 1 As shown, in Figure 20 Based on the corresponding structure, the subsequent fabrication of the device is completed: First, the side of the substrate 10 away from the epitaxial structure 20 is thinned. After thinning, the thickness of the substrate 10 (Sub) ranges from 80 to 250 μm, and in this embodiment, the preferred thickness range is 150 to 200 μm. Then, a back metal layer 70 is formed on the back side of the thinned substrate 10 by sputtering. This back metal layer 70 serves as the drain electrode, thus completing the device fabrication. The material of the back metal layer 70 includes, but is not limited to, titanium (Ti), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), any alloy thereof, or any combination thereof.

[0058] Understandably, this application achieves the integration of a split gate and a dual Schottky diode by forming functional units such as the basic epitaxial layer 21, well region 212, source region 211, split gate structure, trench contact region 213, and metal layer in stages. The process steps are clear, controllable, and highly compatible, requiring no complex or special equipment. Simultaneously, through a reasonable process sequence design, it ensures both the split gate structure's ability to reduce gate-drain capacitance and improve switching speed, and the reliable connection between the dual Schottky diode and the device body. This results in a power semiconductor device that combines resistance to bipolar degradation, high switching speed, low loss, and good conduction characteristics, meeting the application requirements of high-frequency, high-efficiency power electronic devices.

[0059] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A power semiconductor device, characterized in that, include: Substrate (10) has a first conductivity type; An epitaxial structure (20) is formed on the substrate (10) and includes a base epitaxial layer (21). The conductivity type of the base epitaxial layer (21) is the same as that of the substrate (10). A well region (212), a source region (211), and a trench contact region (213) are disposed in the base epitaxial layer (21). The well region (212) has a second conductivity type and is disposed on the upper surface of the base epitaxial layer (21). A plurality of well regions (212) are spaced apart along a first cross-sectional direction perpendicular to the device thickness. The base epitaxial layer (21) between adjacent well regions (212) defines a first junction field-effect region (214). The source region (211) has a first... The conductivity type is configured one-to-one with the well region (212) and is disposed on the upper surface layer corresponding to the well region (212). The trench contact region (213) has a second conductivity type and is disposed within the base epitaxial layer (21). Along the first cross-sectional direction, the trench contact region (213) is adjacent to the well region (212) and far away from the first junction field-effect region (214). Along the second cross-sectional direction perpendicular to the device thickness and orthogonal to the first cross-sectional direction, a plurality of trench contact regions (213) are spaced apart. The base epitaxial layer (21) between adjacent trench contact regions (213) is defined as a second junction field-effect region (215). A split gate structure is disposed above the epitaxial structure (20) and includes two spaced gate portions (81), the gap between the two gate portions (81) corresponding to the first junction field-effect region (214) in the device thickness direction; An interlayer dielectric layer (40) covers the split gate structure and the epitaxial structure (20), and has a contact opening (41) that exposes the source region (211), the trench contact region (213), the first junction field effect region (214) and the second junction field effect region (215). A front metal layer (50) is disposed above the interlayer dielectric layer (40) and fills the contact opening (41). The front metal layer (50) forms ohmic contacts with the source region (211) and the trench contact region (213), respectively; and forms Schottky contacts with the first junction field-effect region (214) and the second junction field-effect region (215), respectively, to form a Schottky diode. A back metal layer (70) is formed on the side of the substrate (10) away from the epitaxial structure (20); The forward conduction voltage of the Schottky diode is lower than that of the built-in body diode of the device.

2. The power semiconductor device according to claim 1, characterized in that, The basic epitaxial layer (21) is provided with a trench structure for reducing the spacing between device cells, and the trench contact area (213) is located at the bottom of the trench structure.

3. The power semiconductor device according to claim 1, characterized in that, The Schottky diode includes a first Schottky diode and a second Schottky diode. The first Schottky diode is formed at the interface between the first junction field-effect region (214) and the front metal layer (50), and the second Schottky diode is formed at the interface between the second junction field-effect region (215) and the front metal layer (50).

4. The power semiconductor device according to claim 1, characterized in that, The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

5. The power semiconductor device according to claim 1, characterized in that, It also includes a protective layer (60) that covers the front metal layer (50) for device surface protection.

6. The power semiconductor device according to claim 5, characterized in that, The protective layer (60) includes a passivation layer (61) and a resin layer (62). The resin layer (62) covers the upper surface of the passivation layer (61). The material of the passivation layer (61) includes silicon dioxide, silicon nitride, or silicon oxynitride, and the thickness of the passivation layer (61) is 0.10-20 μm. The material of the resin layer (62) includes polyimide, polyamide, or polybenzoxazole, and the thickness of the resin layer (62) is 1-50 μm.

7. The power semiconductor device according to claim 1, characterized in that, The substrate (10) is made of silicon, silicon carbide or gallium nitride, the gate portion (81) is made of polycrystalline silicon, and the interlayer dielectric layer (40) is made of silicon dioxide or silicon nitride.

8. The power semiconductor device according to claim 1, characterized in that, The material of the front metal layer (50) is selected from at least one of titanium, nickel, and molybdenum, and the material of the back metal layer (70) is selected from at least one of titanium, nickel, silver, palladium, and gold.

9. A method for manufacturing a power semiconductor device, characterized in that, Includes the following steps: S1. Provide a substrate (10) and form a basic epitaxial layer (21) on the substrate (10) to form an epitaxial structure (20). S2. Along a first cross-sectional direction perpendicular to the thickness of the device, a plurality of spaced well regions (212) with a second conductivity type are formed on the surface of the base epitaxial layer (21). S3. A source region (211) with a first conductivity type is formed on the surface of each well region (212) corresponding to the well region (212). A plurality of trench contact regions (213) with a second conductivity type are formed in the base epitaxial layer (21) along a second cross-sectional direction that is perpendicular to the device thickness and orthogonal to the first cross-sectional direction. The trench contact regions (213) are adjacent to the well regions (212) along the first cross-sectional direction. S4. Form a first junction field-effect region (214) between the base epitaxial layer (21) between adjacent well regions (212), and form a second junction field-effect region (215) between the base epitaxial layer (21) between adjacent trench contact regions (213). S5. A gate oxide layer (30) and a polysilicon layer (80) are formed above the epitaxial structure (20). The polysilicon layer (80) is processed into two spaced gate portions (81) to form a split gate structure, such that the gap between the two gate portions (81) corresponds to the first junction field-effect region (214) in the vertical direction. S6. An interlayer dielectric layer (40) is deposited above the split gate structure, and the interlayer dielectric layer (40) and the gate oxide layer (30) are perforated to form contact openings (41) at the corresponding positions of the source region (211), the trench contact region (213), the first junction field effect region (214) and the second junction field effect region (215). S7. Form a front metal layer (50), such that the front metal layer (50) forms ohmic contacts with the source region (211) and the trench contact region (213) respectively through the contact opening (41), and forms Schottky contacts with the first junction field effect region (214) and the second junction field effect region (215) respectively. S8. A protective layer (60) is formed above the front metal layer (50), and the side of the substrate (10) away from the epitaxial structure (20) is thinned. A back metal layer (70) is formed on the back side of the thinned substrate (10) to form a drain electrode, thus completing the device fabrication.

10. The manufacturing method according to claim 9, characterized in that, In step S3, the specific steps for forming the trench contact area (213) include: S31. Deposit a mask layer, define the P+ source region pattern through photolithography, and implant impurities of the second conductivity type into the basic epitaxial layer (21) to form the P+ source region using ion implantation. S32. Based on the formed P+ source region pattern, the P+ source region is etched downward along the pattern using an etching process to form multiple shallow trenches that correspond one-to-one with the P+ source region, and the shallow trenches end inside the P+ source region to form the trench contact area (213).

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