A method for reducing and inhibiting the transformation of SiC epitaxial layer bump defects into trapezoidal defects

Abstract

This invention discloses a method for reducing bump defects in SiC epitaxial layers and suppressing their transformation into trapezoidal defects. The method includes the following steps: in-situ purification of the chamber; pretreatment of the SiC substrate surface; etching of the SiC substrate surface; and growth of an epitaxial layer on the SiC substrate surface. This invention, starting from the root of defect transformation kinetics, for the first time uses the defect "transformation critical point" as the core basis for process design. By employing a three-step synergistic control strategy of "pretreatment-in-situ etching-epitaxygdral growth" and precise process window design, the transformation path from bump to trapezoidal defects is systematically and reliably completely blocked. This simultaneously achieves low bump defect density and effectively blocks the transformation path from bump defects to trapezoidal defects, significantly improving the quality of the epitaxial layer. Furthermore, it is compatible with existing equipment, easy to implement, economical, has high practical value, and promising application prospects.

Description

Technical Field

[0001] This invention belongs to the field of third-generation semiconductor silicon carbide (SiC) material preparation technology, and relates to a method for reducing bump defects in SiC epitaxial layers and suppressing their transformation into trapezoidal defects. Background Technology

[0002] As a core material for third-generation semiconductors, the defect density of SiC epitaxial layers directly determines key performance characteristics of power devices, such as breakdown voltage and leakage current. Among these, bump defects and trapezoidal defects are typical surface morphology defects in SiC epitaxial layers. Our experience shows that these two defects do not exist in isolation but can transform into each other under specific process conditions. This means that conventional methods of reducing one type of defect often lead to an increase in the other, creating a "cost-benefit" dilemma. Specifically, when the process temperature is too high and the etching time is too long, bump defects are highly likely to transform into larger trapezoidal defects that are more detrimental to device performance.

[0003] Existing technologies primarily focus on reducing the number of bump defects, such as by optimizing substrate cleaning or adjusting etching parameters to reduce surface particles. However, these methods often overlook the defect morphology evolution that subsequent processes may induce. For example, while simply extending the etching time can reduce the number of bumps, once the critical window is reached, it can actually cause residual bumps to transform into trapezoidal defects, leading to an overall decrease in epitaxial wafer quality. Similarly, simply lowering the growth temperature may suppress this transformation, but it may result in an excessive number of other defects in the epitaxial layer, such as bump defects and triangular defects. Therefore, existing technologies suffer from the following problems: (1) The contradiction between etching time and bump defects: If the etching time is too short, the number of bumps will exceed the standard; if it is too long, it will easily trigger the transformation into trapezoidal defects.

[0004] (2) Critical risk of epitaxial temperature: If the epitaxial temperature is too high, for example, when the temperature is higher than 1620℃, even if the number of bumps is small, it will still be transformed into trapezoidal defects.

[0005] (3) The effect of residual impurities after etching: SiO2 and microparticles remaining on the substrate surface after etching will become new nucleation sites for bumps.

[0006] In addition, existing research has not found a temperature-etching time-driven transformation relationship between the two, especially failing to realize that excessively high temperature and excessively long etching time are precisely the critical conditions for the transformation of bump into trapezoidal defects; existing technology does not regard "substrate pretreatment-in-situ etching-epitaxy layer growth" as a whole, and lacks in-depth treatment of residual impurities after etching (such as SiO2, carbides, etc.).

[0007] For the reasons stated above, this invention is proposed. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a method for reducing bump defects in SiC epitaxial layers and suppressing their transformation into trapezoidal defects.

[0009] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A method for reducing bump defects in SiC epitaxial layers and suppressing their transformation into trapezoidal defects includes the following steps: S1. Heat the chamber temperature to 700℃~900℃ and introduce H2 to perform in-situ purification of the chamber. S2. Place the SiC substrate into the reaction chamber, raise the chamber temperature to 1400℃~1500℃, and introduce a mixture of HCl and H2 gas A to pretreat the surface of the SiC substrate; the volume fraction of HCl gas in the mixture A is 0.2%~0.5%; S3. Under H2 atmosphere, the chamber temperature is raised to 1620℃ or below, and the surface of the SiC substrate is etched; the etching time is ≤8min. S4. Maintain the chamber temperature at or below 1620℃ and grow an epitaxial layer on the SiC substrate surface.

[0010] In a further improvement to the above method, in step S1, the flow rate of H2 is 20 slm to 40 slm.

[0011] In a further improvement to the above method, in step S1, the in-situ purification treatment is repeated 1 to 3 times; the time for each in-situ purification treatment is 2 to 4 minutes; and the chamber pressure is reduced to below 50 mbar after each in-situ purification treatment.

[0012] In a further improvement to the above method, in step S2, after the chamber temperature is raised to 1400℃~1500℃, H2 is introduced; after the chamber pressure is reduced to 60mbar~120mbar, HCl gas is introduced to form a mixture of HCl and H2, A, to pretreat the SiC substrate surface; the flow rate of H2 is 60 slm~140 slm.

[0013] In a further improvement to the above method, in step S2, the pretreatment time is 1 min to 3 min; after the pretreatment is completed, the HCl gas is stopped.

[0014] In a further improvement to the above method, in step S3, the chamber pressure is maintained at 60 mbar to 120 mbar and the H2 flow rate is 80 slm to 140 slm, and the chamber temperature is raised to 1580℃ to 1620℃ to etch the surface of the SiC substrate.

[0015] In a further improvement to the above method, step S3 further includes: introducing HCl gas to form a mixture of HCl and H2 gas B, which is used to etch the surface of the SiC substrate; the volume fraction of HCl gas in the mixture of HCl and H2 gas B is 0.2% to 0.5%.

[0016] In a further improvement to the above method, in step S3, the etching time is 4 min to 6 min; after the etching is completed, the HCl gas is stopped.

[0017] In a further improvement to the above method, in step S4, the chamber temperature is maintained at 1580℃~1620℃, the chamber pressure at 80mbar~100mbar, and the H2 flow rate at 100 slm~120 slm, while a silicon source and a carbon source are introduced to grow an epitaxial layer on the surface of the SiC substrate.

[0018] In a further improvement to the above method, in step S4, the silicon source is trichlorosilane; the carbon source is ethylene or propane; the C / Si ratio is controlled to be 0.8 to 0.9 during the growth of the epitaxial layer, the growth rate is 30 μm / h to 70 μm / h; and the thickness of the epitaxial layer is 5 μm to 20 μm.

[0019] Compared with the prior art, the advantages of the present invention are as follows: To address the problem of poor control of bump defects and their easy transformation into trapezoidal defects in existing technologies, this invention delves into the critical conditions for the mutual transformation between bump and trapezoidal defects. Based on this, a three-step synergistic control strategy of "pretreatment-in-situ etching-epitaxy growth" is proposed. This strategy aims to simultaneously achieve low bump defect density and effectively block the transformation path from bump defects to trapezoidal defects. The core of this approach is as follows: First, before substrate loading, the chamber is in-situ purified using pure H2 at 700℃~900℃ to remove any loose deposits that may exist on the reaction chamber walls. After substrate loading, the SiC substrate surface is pretreated at 1400℃~1500℃ using a mixture of HCl and H2 with a volume fraction of 0.2%~0.5% (HCl + H2). In this mixture, HCl acts as an impurity remover, and H2 is the carrier gas. The SiC substrate reacts with SiO2 to generate volatile SiCl4, which, under the action of H2, rapidly and thoroughly removes the native oxide layer and attached microparticles on the substrate surface, reducing the nucleation source of bump defects from the outset. Subsequently, the SiC substrate surface is etched within the critical temperature (≤1620℃) and time (≤8min) range to maximize the removal of surface micro-damage and microparticles, effectively reducing the bump defect density while avoiding over-etching that could induce trapezoidal defects. In addition, if a mixture of HCl and H2 with a volume fraction of 0.2%–0.5% is introduced during this period for auxiliary etching, the ability to remove surface microparticles can be further enhanced, thus ensuring that the prepared epitaxial layer meets the requirements for use. Finally, epitaxial layer growth is completed below the critical temperature (≤1620℃), which thermodynamically blocks the path of bump defects extending to the downstream bottom edge of the trapezoid, thereby fundamentally blocking the transformation path of bump defects. This invention, starting from the root of defect transformation dynamics, for the first time uses the defect "transformation critical point" as the core basis for process design. By employing a three-step synergistic control strategy of "pretreatment-in-situ etching-epitaxy growth" and precise process window design, it systematically and reliably completely blocks the transformation path from bump to trapezoid, achieving synergistic suppression of both types of defects, significantly improving the quality of the epitaxial layer, and achieving the following unexpected technical effects: (1) Fundamental innovation: This invention takes the "critical condition for defect morphology transformation" as the core control target of process design for the first time, and proposes the idea of ​​eliminating defects by identifying and avoiding the "critical window for transformation". This is a methodological innovation. Specifically, by avoiding the transformation condition of "temperature > 1620℃ + etching time > 8min" and constructing a "safe process window" to avoid defect transformation, the transformation of bump defects into trapezoidal defects is fundamentally avoided.

[0020] (2) Precise prevention: This invention clearly defines the coordinated parameter range of "pretreatment conditions-etching time-epitaxy temperature". By precisely defining the boundaries of the two key parameters of temperature and time, the generation of trapezoidal defects is prevented from the source, rather than repaired afterward, and the effect is more thorough.

[0021] (3) High compatibility, ease of implementation, and economy: This invention does not require any modification to existing commercial SiC epitaxial equipment, does not introduce additional expensive steps or materials, and can be achieved simply by optimizing and strictly controlling existing process parameters. It is very easy to promote on existing production lines and has broad industrialization prospects.

[0022] (4) Synergistic Efficiency: This invention employs a three-step synergistic control strategy of "pretreatment-in-situ etching-epitaxy growth" to achieve a "double low" control effect on bump and trapezoidal defects. While successfully suppressing the transformation of bumps into trapezoidal defects, the bump defect density itself is also maintained at a low level. Experiments show that this method can stably control the bump defect density to less than 15 defects / wafer (6-inch substrate), while completely suppressing the transformation of bump defects into trapezoidal defects. Attached Figure Description

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0024] Figure 1 This is a topographic image of bump defects in an existing SiC epitaxial layer.

[0025] Figure 2 This is a topographic image of a trapezoidal defect in an existing SiC epitaxial layer.

[0026] Figure 3 The diagram shows the distribution of the number of bump defects on the surface of the SiC epitaxial layer under the etching conditions of Example 1 and Comparative Examples 2-4 of this invention.

[0027] Figure 4 The image shows the morphological changes of the trapezoidal defects on the surface of the SiC epitaxial layer under the etching conditions of Example 1, Comparative Examples 1 and 4 of this invention. Detailed Implementation

[0028] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Figure 1This is a topographic image of bump defects in an existing SiC epitaxial layer. Figure 1 In the diagram, (a) represents a surface signal feedback, and (b) represents a signal without PL feedback.

[0030] Figure 2 This is a topographic image of a trapezoidal defect in an existing SiC epitaxial layer. Figure 2 In the figure, (a) shows the area with surface signal feedback, (b) is a magnified view of the area within the red box in (a), and (c) shows the area without PL signal feedback.

[0031] To address the problem of poor control of bump defects and their easy transformation into trapezoidal defects in existing technologies, this invention delves into the critical conditions for the mutual transformation between bump and trapezoidal defects. Based on this, a three-step synergistic control strategy of "pretreatment-in-situ etching-epitaxy growth" is proposed. This strategy aims to simultaneously achieve low bump defect density and effectively block the transformation path from bump defects to trapezoidal defects. The core of this approach is as follows: First, before substrate loading, the chamber is in-situ purified using pure H2 at 700℃~900℃ to remove any loose deposits that may exist on the reaction chamber walls. After substrate loading, the SiC substrate surface is pretreated at 1400℃~1500℃ using a mixture of HCl and H2 with a volume fraction of 0.2%~0.5%. In this mixture, HCl acts as an impurity remover, and H2 acts as a carrier gas. The HCl reacts with SiO2 to generate volatile SiCl4, which, under the action of H2, rapidly and thoroughly removes the native oxide layer and attached microparticles from the substrate surface, reducing bump defects at their source. Defect nucleation source; subsequently, within the critical temperature (≤1620℃) and time (≤8min) range, the SiC substrate surface is etched to maximize the removal of surface micro-damage and microparticles, effectively reducing the Bump defect density while avoiding over-etching and inducing trapezoidal defects. In addition, if a mixture of HCl and H2 with a volume fraction of 0.2% to 0.5% is introduced again during this period for auxiliary etching, the ability to remove surface microparticles can be further enhanced, thereby ensuring that the prepared epitaxial layer meets the application requirements. Finally, epitaxial layer growth is completed below the critical temperature (≤1620℃), which thermodynamically blocks the path of Bump defects extending to the downstream bottom edge of the trapezoid, thereby fundamentally blocking the transformation path of Bump defects.

[0032] To better understand the innovative aspects of this invention, this invention provides a method for reducing bump defects in SiC epitaxial layers and suppressing their transformation into trapezoidal defects, comprising the following steps: S1. Heat the chamber temperature to 700℃~900℃ and introduce pure H2 to perform in-situ purification of the chamber. S2. Place the SiC substrate into the reaction chamber, raise the chamber temperature to 1400℃~1500℃, and introduce a mixture of HCl and H2 gas A to pretreat the surface of the SiC substrate; the volume fraction of HCl gas in the mixture A is 0.2%~0.5%; S3. Under H2 atmosphere, the chamber temperature is raised to 1620℃ or below, and the surface of the SiC substrate is etched; the etching time is ≤8min. S4. Maintain the chamber temperature at or below 1620℃ and grow an epitaxial layer on the SiC substrate surface.

[0033] In some embodiments, in step S1, the flow rate of H2 is controlled to be 20 slm to 40 slm during the in-situ purification process of the chamber.

[0034] In some embodiments, in step S1, the in-situ purification treatment is repeated 1 to 3 times, and the time for a single in-situ purification treatment is 2 to 4 minutes.

[0035] In some embodiments, in step S1, after each in-situ purification treatment, the chamber pressure is reduced to below 50 mbar.

[0036] In some embodiments, in step S2, after the chamber temperature is raised to 1400°C to 1500°C, H2 is introduced. After the chamber pressure is reduced to 60 mbar to 120 mbar, HCl gas is introduced to form a mixture of HCl and H2 gas A, which is used to pretreat the surface of the SiC substrate.

[0037] In some embodiments, during step S2, the flow rate of H2 is controlled to be 60 slm to 140 slm during the pretreatment of the SiC substrate surface.

[0038] In some embodiments, in step S2, the time for pretreating the SiC substrate surface is 1 min to 3 min.

[0039] In some embodiments, in step S2, after the pretreatment is completed, the HCl gas is stopped.

[0040] In some embodiments, in step S3, the chamber pressure is maintained at 60 mbar to 120 mbar and the H2 flow rate is 80 slm to 140 slm, and the chamber temperature is raised to 1580°C to 1620°C to etch the surface of the SiC substrate.

[0041] In some embodiments, step S3 further includes: introducing HCl gas to form a mixture of HCl and H2 gas B, which is used to etch the surface of the SiC substrate.

[0042] In some embodiments, during step S3, the volume fraction of HCl gas in the HCl and H2 mixture B is controlled to be 0.2% to 0.5% during the etching process on the SiC substrate surface.

[0043] In some embodiments, in step S3, the etching time for the SiC substrate surface is 4 min to 6 min.

[0044] In some embodiments, in step S3, after etching is completed, the HCl gas supply is stopped.

[0045] In some embodiments, in step S4, the chamber temperature is maintained at 1580°C to 1620°C, the chamber pressure is maintained at 80 mbar to 100 mbar, and the H2 flow rate is maintained at 100 slm to 120 slm. A silicon source and a carbon source are introduced to grow an epitaxial layer on the surface of the SiC substrate.

[0046] In some embodiments, in step S4, the silicon source is trichlorosilane, and the carbon source is ethylene or propane.

[0047] In some embodiments, during step S4, the C / Si ratio is controlled to be 0.8 to 0.9 and the growth rate is 30 μm / h to 70 μm / h during the growth of the epitaxial layer.

[0048] In some embodiments, in step S4, the thickness of the epitaxial layer is 5 μm to 20 μm.

[0049] The following are specific embodiments and comparative examples: Example 1 A method for reducing bump defects in SiC epitaxial layers and suppressing their transformation into trapezoidal defects, specifically involving the fabrication of a SiC epitaxial layer on the surface of a SiC wafer, includes the following steps: Substrate: 4° off-center, 6-inch n-type 4H-SiC.

[0050] Step 1: In-situ purification + substrate pretreatment Cavity cleaning: Before loading the wafer, the temperature of the reaction chamber is kept constant at 900°C and the pressure is at atmospheric pressure (e.g., 1000 mbar). H2 is introduced into the reaction chamber at a flow rate of 30 slm to perform in-situ purification of the chamber for 2 minutes. Then, the chamber pressure is reduced to below 50 mbar and backfilled with hydrogen to atmospheric pressure. The above steps are repeated twice to remove any loose deposits that may be present on the walls of the reaction chamber.

[0051] Substrate surface pretreatment: At a chamber temperature of 900℃ and atmospheric pressure (chamber pressure of 1000mbar), after the wafer is transferred to the reaction chamber, the temperature of the reaction chamber is raised to a constant 1500℃, the hydrogen flow rate is increased to 120slm, and the chamber pressure is reduced to 100mbar. HCl gas is then introduced to form an atmosphere of HCl and H2 mixture (HCl volume fraction of 0.2%). The SiC substrate surface is pretreated with the HCl and H2 mixture for 1 minute. During this process, HCl gas is used as an impurity remover. HCl reacts with SiO2 to generate volatile SiCl4. H2 is then used as a carrier gas, and under the action of H2, the native oxide layer and attached microparticles on the substrate surface are quickly and thoroughly removed, reducing the nucleation source of bump defects from the source. The HCl gas is then turned off, and the chamber pressure (100mbar) and hydrogen flow rate (120slm) are kept constant. The temperature is raised to 1620℃.

[0052] Step 2: Precision Etching The process temperature (1620℃), chamber pressure (100mbar), and hydrogen flow rate (120slm) remained constant, and the SiC substrate surface was etched under these conditions for 6 minutes.

[0053] In this step, the SiC substrate surface is etched within the critical temperature (≤1620℃) and time (≤8min) range to maximize the removal of surface micro-damage, effectively reducing the Bump defect density while avoiding over-etching that could induce trapezoidal defects.

[0054] Meanwhile, the etching process also includes: introducing a small amount of HCl gas to form a mixture of HCl and H2 (the volume fraction of HCl gas in the mixture is 0.2%), and using the mixture of HCl and H2 gas for auxiliary etching to enhance the ability to remove surface microparticles.

[0055] Step 3: SiC epitaxial layer growth under the safety window After etching, the process temperature (1620℃), (100mbar), and hydrogen flow rate (120slm) remain unchanged. The HCl gas is turned off, and the silicon source (trichlorosilane) and carbon source (ethylene) are introduced to maintain the C / Si ratio at about 0.85. The growth rate is maintained at 60μm / h. An appropriate amount of n-type doping gas (such as nitrogen or ammonia) is introduced according to the product specifications. The epitaxial layer thickness is maintained at about 10μm by controlling the time, thus completing the growth of the epitaxial layer on the SiC substrate surface.

[0056] Step 4: Epitaxial wafer inspection The surface of the SiC epitaxial wafer was inspected using a defect tester, specifically a Lasertec SICA 88 from Japan.

[0057] Comparative Example 1: A method for preparing a SiC epitaxial layer is basically the same as that in Example 1, except that the etching temperature is 1640℃ and the etching time is 10 minutes.

[0058] Comparative Example 2: A method for preparing a SiC epitaxial layer is basically the same as that in Example 1, except that the etching time is 2 minutes.

[0059] Comparative Example 3: A method for preparing a SiC epitaxial layer is basically the same as that in Example 1, except that HCl gas is not introduced throughout the process.

[0060] Comparative Example 4: A method for preparing a SiC epitaxial layer is basically the same as that in Example 1, except that the etching time is 10 minutes.

[0061] Figure 3 The diagram shows the distribution of the number of bump defects on the surface of the SiC epitaxial layer under the etching conditions of Example 1 and Comparative Examples 2-4 of this invention. Figure 3 In the examples, (a) etching for 2 min with HCl involved (Comparative Example 2); (b) etching for 6 min with HCl involved (Example 1); (c) etching for 6 min without HCl involved (Comparative Example 3); and (d) etching for 10 min with HCl involved (Comparative Example 4).

[0062] Figure 4 The image shows the morphological changes of the trapezoidal defects on the surface of the SiC epitaxial layer under the etching conditions of Example 1, Comparative Examples 1 and 4 of this invention. Figure 4 In the images, (a) 1640 °C, etched for 10 minutes, bottom edge length 3.5 mm (Comparative Example 1); (a1) is an enlarged view of (a); (b) 1620 °C, etched for 10 minutes, bottom edge length 1.8 mm (Comparative Example 4); (b1) is an enlarged view of (b); (c) 1620 °C, etched for 6 minutes, trapezoidal defect transformed into Bump (Example 1); (c1) is an enlarged view of (c).

[0063] Depend on Figure 3-4 The results show that: like Figure 3 b and Figure 4In Example 1 shown in c, the number of bump defects was 12, and no trapezoidal defects were observed. This result indicates that within a process window where HCl is involved in assisted etching, the etching temperature does not exceed 1620 °C, and the etching time does not exceed 8 min, bump defects can be significantly reduced, and the transformation of bump defects into trapezoidal defects can be suppressed. This process window is considered a good one.

[0064] like Figure 4 As shown in Figure a, in Comparative Example 1, although the number of bump defects is not large, trapezoidal defects with a base length exceeding 2 mm have appeared. This result indicates that although excessive etching time and excessively high etching temperature can effectively reduce the number of bumps, they also induce the transformation of bump defects into trapezoidal defects.

[0065] like Figure 3 As shown in Figure a, in Comparative Example 2, there are 1000 bump defects, while Figure 3 Only 12 bump defects were found in sample b. This phenomenon indicates that if the etching time is too short, even with HCl-assisted etching, it is impossible to fully remove the microparticles on the substrate surface, ultimately leading to the derivation of numerous bump defects after epitaxy.

[0066] like Figure 3 As shown in c, in Comparative Example 3, there are 200 bump defects and no trapezoidal defects, while Figure 3 Only 12 bump defects were found in b, which proves that HCl can further reduce bumps.

[0067] like Figure 3 d and Figure 4 As shown in b, in Comparative Example 4, there are 10 bump defects, including trapezoidal defects; while Figure 3 b and Figure 4 There are 12 bump defects in c. In Example 1, there are no trapezoidal defects. This phenomenon indicates that under the condition of HCl participating in assisted etching, when the etching time is too long, the number of bump defects remains basically unchanged, but gradually transforms into trapezoidal defects.

[0068] As can be seen from the above results, the method of this invention, starting from the root of defect transformation dynamics, takes the defect "transformation critical point" as the core basis for process design for the first time. By adopting a three-step synergistic control strategy of "pretreatment-in-situ etching-epitaxy growth" and precise process window design, it systematically and reliably completely blocks the transformation path from bump to trapezoid, achieving synergistic suppression of the two types of defects, significantly improving the quality of the epitaxial layer, and achieving the following unexpected technical effects: (1) Fundamental innovation: This invention takes the "critical condition for defect morphology transformation" as the core control target of process design for the first time, and proposes the idea of ​​eliminating defects by identifying and avoiding the "critical window for transformation". This is a methodological innovation. Specifically, by avoiding the transformation condition of "temperature > 1620℃ + etching time > 8min" and constructing a "safe process window" to avoid defect transformation, the transformation of bump defects into trapezoidal defects is fundamentally avoided.

[0069] (2) Precise prevention: This invention clearly defines the coordinated parameter range of "pretreatment conditions-etching time-epitaxy temperature". By precisely defining the boundaries of the two key parameters of temperature and time, the generation of trapezoidal defects is prevented from the source, rather than repaired afterward, and the effect is more thorough.

[0070] (3) High compatibility, ease of implementation, and economy: This invention does not require any modification to existing commercial SiC epitaxial equipment, does not introduce additional expensive steps or materials, and can be achieved simply by optimizing and strictly controlling existing process parameters. It is very easy to promote on existing production lines and has broad industrialization prospects.

[0071] (4) Synergistic Efficiency: This invention employs a three-step synergistic control strategy of "pretreatment-in-situ etching-epitaxy growth" to achieve a "double low" control effect on bump and trapezoidal defects. While successfully suppressing the transformation of bumps into trapezoidal defects, the bump defect density itself is also maintained at a low level. Experiments show that this method can stably control the bump defect density to less than 15 defects / wafer (6-inch substrate), while completely suppressing the transformation of bump defects into trapezoidal defects.

[0072] The above embodiments are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for controlling the reduction of bump defects in SiC epitaxial layers and suppressing their transformation into trapezoidal defects, characterized in that, Includes the following steps: S1. Heat the chamber temperature to 700℃~900℃ and introduce pure H2 to perform in-situ purification of the chamber. S2. Place the SiC substrate into the reaction chamber, raise the chamber temperature to 1400℃~1500℃, and introduce a mixture of HCl and H2 gas A to pretreat the surface of the SiC substrate; the volume fraction of HCl gas in the mixture A is 0.2%~0.5%; S3. Under H2 atmosphere, the chamber temperature is raised to 1620℃ or below, and the surface of the SiC substrate is etched; the etching time is ≤8min. S4. Maintain the chamber temperature at or below 1620℃ and grow an epitaxial layer on the SiC substrate surface.

2. The method according to claim 1, characterized in that, In step S1, the flow rate of H2 is 20 slm to 40 slm.

3. The method according to claim 2, characterized in that, In step S1, the in-situ purification treatment is repeated 1 to 3 times; the time for each in-situ purification treatment is 2 to 4 minutes; after each in-situ purification treatment, the chamber pressure is reduced to below 50 mbar.

4. The method according to any one of claims 1 to 3, characterized in that, In step S2, after the chamber temperature is raised to 1400℃~1500℃, H2 is introduced. After the chamber pressure is reduced to 60mbar~120mbar, HCl gas is introduced to form a mixture of HCl and H2, A, to pretreat the SiC substrate surface. The flow rate of H2 is 60 slm~140 slm.

5. The method according to claim 4, characterized in that, In step S2, the pretreatment time is 1 min to 3 min; after the pretreatment is completed, the HCl gas is stopped.

6. The method according to claim 5, characterized in that, In step S3, the chamber pressure is maintained at 60 mbar to 120 mbar and the H2 flow rate is 80 slm to 140 slm. The chamber temperature is raised to 1580℃ to 1620℃ to etch the surface of the SiC substrate.

7. The method according to claim 6, characterized in that, In step S3, the etching process further includes: introducing HCl gas to form a mixture of HCl and H2 gas B, which is used to etch the surface of the SiC substrate; the volume fraction of HCl gas in the mixture of HCl and H2 gas B is 0.2% to 0.5%.

8. The method according to claim 7, characterized in that, In step S3, the etching time is 4 min to 6 min; after the etching is completed, the HCl gas is stopped.

9. The method according to claim 8, characterized in that, In step S4, the chamber temperature is maintained at 1580℃~1620℃, the chamber pressure is 80mbar~100mbar, and the H2 flow rate is 100 slm~120 slm. A silicon source and a carbon source are introduced to grow an epitaxial layer on the surface of the SiC substrate.

10. The method according to claim 9, characterized in that, In step S4, the silicon source is trichlorosilane; the carbon source is ethylene or propane; the C / Si ratio is controlled to be 0.8 to 0.9 and the growth rate is 30 μm / h to 70 μm / h during the growth of the epitaxial layer; the thickness of the epitaxial layer is 5 μm to 20 μm.

Images