A method and system for automatic labeling of semiconductor manufacturing test cases

Abstract

This invention relates to the field of semiconductor intelligent manufacturing and testing technology, and particularly to an automatic labeling method and system for semiconductor manufacturing test cases. The method includes: providing multiple test cases, which describe a wafer processing sequence, defining the wafer processing equipment required to complete a set processing task, and the time or order in which the wafer processing equipment is accessed; identifying the task type of each test case, and generating a corresponding standard label for each test case based on the task type, the standard label defining the task of the test case; and checking whether the test case needs additional labels. This invention helps to achieve automated and accurate parsing of test cases, solving the problems of low efficiency and poor accuracy of manual and static methods.

Description

Technical Field

[0001] This invention relates to the field of semiconductor intelligent manufacturing and testing technology, and in particular to an automatic labeling method and system for semiconductor manufacturing test cases. Background Technology

[0002] In the field of semiconductor manufacturing testing, efficient management and accurate classification of test cases are crucial for ensuring test quality and the reliability of algorithm verification. Currently, the industry primarily relies on manual annotation for test case management, such as manually classifying and describing test cases based entirely on the personal experience of test engineers. This method suffers from high subjectivity, inconsistent standards, and low efficiency, making it difficult to cope with the management needs of massive numbers of test cases.

[0003] In addition, traditional technologies have proposed some solutions to improve the efficiency of simulation testing.

[0004] For example, patent application CN116594996A discloses a data traceability method, apparatus, and electronic device for semiconductor testing. The data traceability method for semiconductor testing includes: determining a target test plan for the target semiconductor silicon based on the test type of the target semiconductor and the preset test standards corresponding to each test type; determining a target test case library corresponding to the target test plan and a target test code corresponding to each target test case in the target test case library based on the target test plan; and associating the target test plan, each target test case, and each target test code according to a relationship table between the preset test plan, test cases, and test codes to achieve traceability of target test results and target test data.

[0005] For example, patent application CN121387756A proposes an automatic simulation testing system and method for a semiconductor EAP system, belonging to the field of semiconductor intelligent manufacturing. Specifically, it includes defining test scenarios through test case coding; constructing a test environment using equipment simulation modules and external system simulation modules; driving the test process of the EAP program under test through an automated execution engine and generating real-time output data corresponding to the EAP program under test; comparing the real-time output data generated by the automated execution engine with the expected results to generate a test report.

[0006] For example, patent application CN120654622A discloses a simulation testing method, apparatus, computer equipment, and storage medium, relating to the field of semiconductor technology. The method includes performing simulation testing on the design under test, and counting down the operating clock of the design under test based on a preset timer; detecting the output result of the design under test; and stopping the simulation test if no output result is detected when the count ends. This invention determines whether there is an abnormal state in the design under test by real-time detection of its output; if an abnormal state is found, the simulation is automatically stopped.

[0007] However, the above solutions are insufficient to fully capture the complexity and diversity of semiconductor manufacturing scenarios. Therefore, there is an urgent need for a test case management method that is more capable of describing complex scenarios. Summary of the Invention

[0008] The purpose of this invention is to provide an automatic labeling method and system for semiconductor manufacturing test cases, which partially solves or alleviates the above-mentioned shortcomings in the prior art, and can help to realize the automation and accurate analysis of test cases, solving the problems of low efficiency and poor accuracy of manual and static methods.

[0009] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution: A first aspect of the present invention is to provide an automatic labeling method for semiconductor manufacturing test cases, comprising: S101, provides multiple test cases, the test cases are used to describe the wafer processing sequence, the processing sequence is used to define the wafer equipment that needs to be passed to complete the set processing task, and the time or order of passing through the wafer equipment; S102, identify the task type of the test case, and generate a corresponding standard label for the test case according to the task type. The standard label is used to define the task of the test case. S103, check whether the test cases need additional labels; wherein, S103 includes: S1031, Identify whether the test case has a quick detection indicator, wherein the quick detection indicator includes at least one of the following: (1) Fixed mode, which means that the main machines in the test cases are all limited to a device number; (2) Exclusive mode, whereby the test case involves only one set of wafers; (3) Non-fixed mode, wherein the non-fixed mode refers to the test case having at least two options for the machine; S1032, based on the rapid detection index and a set recommended scale, a recommended re-inspection mode is given. The re-inspection mode includes at least one of the following: re-entry mode, resource contention mode, and parallel processing mode. The re-entry mode refers to the presence of at least one repeated sequence in the test case. The resource contention mode refers to the presence of at least two processing sub-tasks on the same wafer rig during the same time period in the test case. The process of a wafer being processed once by the wafer rig is considered as the processing sub-task. The parallel processing mode refers to the presence of at least two identical sub-sequences in the test case, and the at least two identical sub-sequences running in parallel during the same time period. S1033, when the test case has the re-inspection mode, a supplementary label is generated for the test case according to the corresponding re-inspection mode. The supplementary label includes: re-entry label, resource contention label and / or parallel processing label.

[0010] In some embodiments, when the rapid detection index is in machine fixed mode, the recommended re-inspection modes include: re-entry mode and resource contention mode; When the rapid detection index is in the exclusive mode, the recommended re-detection mode includes: re-entry mode; And / or, when the rapid detection index is in a non-fixed mode, the recommended re-inspection mode includes: parallel processing mode.

[0011] In some embodiments, the primary machine refers to one or more machines used to complete a proportion exceeding a set task.

[0012] In some embodiments, S103 further includes: When the test case does not have a quick detection metric, the full detection mode is recommended for the test case.

[0013] In some embodiments, when one of the test cases is set with at least two supplementary labels, corresponding label weights are set for different supplementary labels.

[0014] In some embodiments, when the supplementary tag is a resource contention tag, the corresponding method further includes the step of: Identify competing devices in the test cases; Identify the scheduling capabilities of the competing devices in the historical scheduling logs; When the scheduling capacity exceeds a set capacity threshold, the label weight of the resource contention label is reduced accordingly.

[0015] In some embodiments, the steps further include: S104, Identify the first supplement ratio in the tag generation process during the first tagging cycle, wherein the supplement ratio = test cases with supplementary tags / all test cases; S105, when the supplement ratio is less than the set first threshold, the recommended scale is expanded.

[0016] In some embodiments, the steps further include: S106, Identify the second supplement ratio in the label generation process during the second labeling cycle; S107, Calculate the degree of difference between the second supplement ratio and the first supplement ratio; S108, when the degree of difference is less than a set threshold and the second supplement ratio is less than a set second threshold, the re-inspection parameters of the re-inspection mode are updated.

[0017] A second aspect of the present invention is to provide an automated labeling system for semiconductor manufacturing test cases, comprising: The test case providing module is used to provide multiple test cases, which are used to describe the wafer processing sequence. The processing sequence is used to define the wafer machines that need to be traversed to complete the set processing task, as well as the time or order in which the wafer machines are traversed. A type identification module is used to identify the task type of the test case and generate a corresponding standard label for the test case based on the task type. The standard label is used to define the task of the test case. A tag checking module is used to check whether the test cases need additional tags; wherein, the tag checking module includes: A rapid detection metric identification unit is used to identify whether the test case has a rapid detection metric, wherein the rapid detection metric includes at least one of the following: (1) Fixed mode, which means that the main machines in the test cases are all limited to a device number; (2) Exclusive mode, whereby the test case involves only one set of wafers; (3) Non-fixed mode, wherein the non-fixed mode refers to the test case having at least two options for the machine; A recommendation mode providing unit is used to provide a recommended re-examination mode according to the rapid detection index and a set recommendation scale. The re-examination mode includes at least one of the following: re-entry mode, resource contention mode, and parallel processing mode. The re-entry mode refers to the presence of at least one repeated sequence in the test case. The resource contention mode refers to the presence of at least two processing sub-tasks on the same wafer rig during the same time period in the test case. The wafer is considered to have undergone one processing cycle on the wafer rig as a processing sub-task. The parallel processing mode refers to the presence of at least two identical sub-sequences in the test case, and these at least two identical sub-sequences are run in parallel during the same time period. The supplementary tag generation unit is used to generate supplementary tags for the test case according to the corresponding re-inspection mode when the test case has the re-inspection mode. The supplementary tags include: re-entry tag, resource contention tag and / or parallel processing tag.

[0018] In some embodiments, when the rapid detection index is in machine fixed mode, the recommended re-inspection modes include: re-entry mode and resource contention mode; When the rapid detection index is in the exclusive mode, the recommended re-detection mode includes: re-entry mode; And / or, when the rapid detection index is in a non-fixed mode, the recommended re-inspection mode includes: parallel processing mode.

[0019] Beneficial technical effects: This invention performs a re-examination of test cases with fast detection metrics, avoiding full-scale testing. With relatively low computational cost, it can initially filter out a large number of wafer test cases unlikely to contain complex scenarios, thus concentrating limited computing resources on test case simulations with a high probability of reentrancy, contention, and parallelism. Therefore, triggering a re-examination of test cases that meet fast detection metrics helps avoid or reduce the high costs of timing analysis and sequence comparison on massive numbers of test cases.

[0020] Furthermore, the rapid detection indicators correspond to typical wafer testing scenarios and can screen out most high-risk test cases. Even if a small number of real re-entry test cases are not detected because they do not meet the exclusive mode or fixed mode, it will not affect the completion of the overall test task. Therefore, with the help of this invention, we can provide enough representative complex scenario cases for semiconductor production line simulation testing.

[0021] In other words, to control the resource cost of automatic labeling of wafer test cases, a preliminary screening using quick indicators is performed before conducting specific checks on special scenarios (i.e., reentrancy, resource contention, or parallel processing). If the probability of a test case being present in a particular scenario is clearly low, detailed checks are not recommended. Alternatively, this invention can guide engineers to a certain extent through labels during test case checks or before test case invocation, thereby reducing resource consumption when labeling massive amounts of test cases.

[0022] Furthermore, this invention assigns weights to different supplementary tags, allowing users to quickly locate the most valuable test cases by sorting or filtering them according to their testing objectives (such as prioritizing re-entry scenarios) when a large number of test cases are retrieved. By identifying the historical scheduling capabilities of competing equipment, the weight of resource competition tags for equipment emphasizing scheduling capabilities (such as lithography machines) is dynamically reduced, avoiding an overestimation of the risks behind all resource competition tags. This helps identify situations that will actually be high-risk during simulation testing, ensuring that simulation resources are always focused on the real weaknesses of the current production line.

[0023] In this invention, to provide sufficient test cases for simulation testing, the recommended scale is adjusted when the first supplement ratio is small. This ensures that enough test cases have the opportunity to enter the re-examination, thus avoiding the situation where a large number of actual test cases containing re-entry, competition, and parallel features are judged as lacking fast detection indicators due to an excessively small recommended scale (e.g., too few recommended re-examination modes), and are ultimately skipped or only subjected to low-priority detection. Furthermore, by comparing the changes in the supplement ratio under two periods, if the difference is not significant and the second supplement ratio is still small, it may indicate that the detection rules are not adapted to the current scenario, resulting in too many missed labels. In this case, the re-examination parameters can be further updated based on expanding the recommended scale to ensure that sufficient re-entry / competition cases can still be produced in subsequent periods. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0025] Figure 1 A flowchart illustrating an automatic labeling method for semiconductor manufacturing test cases provided by the present invention; Figure 2 This is a schematic diagram of the structure of an automated labeling system for semiconductor manufacturing test cases provided by the present invention; Figure 3 This is a schematic block diagram of the structure of a computer device provided by the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0027] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0028] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0031] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0032] As used in this specification, the term "about" typically means + / -5% of the value, more typically + / -4% of the value, more typically + / -3% of the value, more typically + / -2% of the value, even more typically + / -1% of the value, and even more typically + / -0.5% of the value.

[0033] In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within those ranges. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This rule applies regardless of the breadth of the range.

[0034] The term "wafer set" (or simply "set") mentioned in this invention should be interpreted broadly. It can refer not only to a complete semiconductor equipment with full processing capabilities (such as a lithography machine, etching machine, deposition equipment, cleaning equipment, etc.), but also to functional units within the equipment, such as robotic arms, processing chambers, buffer stations, sensors, or detection units, depending on actual production management and scheduling needs.

[0035] For example, if an etching machine is considered a single workstation, when a processing subtask occupies that workstation, the entire machine is locked, preventing other processing tasks from using it simultaneously. For more granular scheduling modeling (e.g., avoiding robot arm conflicts or chamber preemption), the etching machine can be further divided into multiple independent "workstations," such as a robot arm, chamber A, and chamber B. In this case, a processing subtask might first occupy the robot arm for wafer transfer, and then occupy chamber A for etching; the two subtasks can compete for resources of different granularities.

[0036] Example 1: In the semiconductor chip manufacturing process, large-scale simulation testing is typically performed before the official production line starts. Engineers write corresponding test code—i.e., test cases—based on the requirements of each specific process step in the production task. These test cases simulate the flow path, time sequence, and resource usage of wafers between equipment to identify various conflicts that may occur in the actual production, such as equipment occupancy conflicts, deadlock risks, transmission bottlenecks, and low production efficiency.

[0037] However, the semiconductor manufacturing process itself is extremely complex, which puts simulation testing under pressure from two aspects: on the one hand, a complete process flow often involves complex procedures, and each procedure involves multiple optional machines, chambers or robots, which rapidly expands the possibilities of test cases; on the other hand, different process tasks (such as photolithography, etching, deposition, cleaning, etc.) have different requirements for the accuracy, time granularity and scheduling strategy of the simulation model, which further increases the difficulty of maintaining simulation test cases.

[0038] In practice, engineers need to generate and maintain a large number of test cases for different variants of the same product batch, different machine configurations, and different scheduling strategies. These test cases are not only numerous (often tens of thousands), but also have structural similarities and differences. For example, some test cases only modify the optional machine for a certain step, while others completely rearrange the entire production sequence. As product models are updated, machine maintenance is performed, or process parameters are adjusted, existing test cases need to be updated frequently, and new test cases are constantly being generated.

[0039] For this, please see Figure 1 This invention provides an automatic labeling method for semiconductor manufacturing test cases, comprising: S101, provides multiple test cases, the test cases are used to describe the wafer processing sequence, the processing sequence is used to define the wafer equipment that needs to be passed to complete the set processing task, and the time or order of passing through the wafer equipment; S102, identify the task type of the test case, and generate a corresponding standard label for the test case according to the task type. The standard label is used to define the task of the test case. S103, check whether the test cases need additional labels; wherein, S103 includes: S1031, Identify whether the test case has a quick detection indicator, wherein the quick detection indicator includes at least one of the following: (1) Fixed mode, which means that the main machines in the test cases are all limited to a device number; (2) Exclusive mode, whereby the test case involves only one set of wafers; (3) Non-fixed mode, wherein the non-fixed mode refers to the test case having at least two options for the machine; S1032, based on the rapid detection index and a set recommended scale, a recommended re-inspection mode is given. The re-inspection mode includes at least one of the following: re-entry mode, resource contention mode, and parallel processing mode. The re-entry mode refers to the presence of at least one repeated sequence in the test case. The resource contention mode refers to the presence of at least two processing sub-tasks on the same wafer rig during the same time period in the test case. The process of a wafer being processed once by the wafer rig is considered as the processing sub-task. The parallel processing mode refers to the presence of at least two identical sub-sequences in the test case, and the at least two identical sub-sequences running in parallel during the same time period. S1033, when the test case has the re-inspection mode, a supplementary label is generated for the test case according to the corresponding re-inspection mode. The supplementary label includes: re-entry label, resource contention label and / or parallel processing label.

[0040] In this context, reentrancy refers to the wafer repeatedly accessing the same physical machine or the same type of process module within a processing sequence, manifesting as a repetitive structure in the sequence (e.g., symmetric reentrancy A*M + B*N + A*M, asymmetric reentrancy A*M + B*N, complete repetition). Here, A and B represent subsequences; M and N represent the number of reentries.

[0041] Resource contention mode refers to a situation where multiple processing subtasks need to process the same physical machine (PM) within the same time period (or within the same task scope), resulting in multiple tasks competing for that machine. This manifests as the same machine being used multiple times within a task (occurrence count > 1). For example, across the entire task scope, the total number of occurrences of the module name (pm_name) of each physical machine PM is counted; if any pm_name occurs more than once, it indicates a resource contention mode.

[0042] Parallel processing mode refers to the existence of two or more identical sub-sequences (or steps) that can run simultaneously on different selectable machines within the same time period. This is typically manifested as: a single step having multiple selectable machines (selectable_pm_count>=2) that can process it simultaneously, or at least one of multiple steps having parallel processing capabilities.

[0043] In some embodiments, under a fixed model, the resource requirements of each job step in a test case depend on a specific device number (such as PM_ETCH_03), rather than a group of devices with multiple options. These test cases are not distributed across multiple devices, but rather the test tasks are executed only on a relatively fixed set of devices.

[0044] For example, fixed-pattern test cases typically occur in scenarios such as early-stage analog chip production lines where equipment cannot be flexibly configured. Test cases written by engineers can only strictly follow the actual machine routing; for example, the wafer must first go to cleaning machine 1 and then to furnace tube 2, meaning that each process step is locked to a specific machine.

[0045] In other words, since a LOT (i.e., a set of wafers) may return to the same device (such as furnace tube 2) multiple times at different steps, fixed-pattern test cases may involve reentrancy.

[0046] Alternatively, if multiple products or lots are locked to the same machine, resource competition may arise. Also, if different processing subtasks (possibly from different time slices of the same batch, or different batches) have overlapping time windows, they may compete for the same machine.

[0047] In some embodiments, only one LOT exists in the entire simulation environment, and the machine equipment is exclusively occupied by that LOT.

[0048] For example, a typical scenario for exclusive mode test cases is when developers create a clean test case with a single Lot and multiple loops to verify the anti-deadlock capability of a machine. The configuration contains only one Lot, which repeatedly enters and exits the same lithography machine five times, or each machine uses only this one Lot.

[0049] In exclusive mode, it's highly unlikely that other wafer processing tasks will compete for the equipment, so there's less competition for equipment resources, and this can be skipped in the resource contention analysis. Instead, we can analyze whether the multiple access windows of this LOT overlap, causing a deadlock in the task itself.

[0050] Reusing the same set of wafers on the same machine is entirely possible in exclusive mode (e.g., etching → cleaning → re-etching). Furthermore, since there is only one set of wafers, re-entry detection only requires scanning the processing sequence of that set, resulting in extremely low cost, so it is recommended.

[0051] In some embodiments, if the total number of Lots = 1, and during the scanning process it is found that the resource requirement of a certain step is a group of selectable wafer equipment, such as furnace tube area can select furnace tube A, furnace tube B, and furnace tube C, instead of PM being limited to furnace tube A, then it can be determined that this situation belongs to a non-fixed mode.

[0052] It should be understood that the present invention can set a non-fixed mode to skip the re-entry mode because if the machine is optional (non-fixed mode), even if there is repeated access to a certain "machine type" in the sequence logic (e.g., "etching machine" is needed multiple times), the scheduler can select a different physical machine each time it is accessed (e.g., using etching machine A the first time and etching machine B the second time).

[0053] In some embodiments, under non-fixed conditions, there are multiple selectable machines for the process, so it is very likely that two or more identical sub-sequences will run simultaneously at the same time. In this case, parallel processing may occur, so parallel processing and re-inspection mode is recommended.

[0054] Alternatively, in other embodiments, if there is overlap in the selectable machines for different processes under the non-fixed mode, the corresponding recommended re-inspection mode can also be a re-entry mode. For example, the machines corresponding to process 1 are PM3-1 and PM1-1; the machines corresponding to the subsequent process 2 are also PM3-1 and PM1-1. If PM1-1 is selected for both process 1 and process 2, the non-fixed mode also involves the re-entry situation.

[0055] In some embodiments, non-fixed-pattern test cases are typically used to test whether the scheduling strategy can maximize the use of parallel acceleration and correctly merge when a Lot can be split into multiple furnace tubes for parallel processing. This can be achieved by examining the maximum number of parallel subtasks that can run simultaneously after task splitting, and how long these subtasks need to wait for each other when finally merging (i.e., the extra time spent waiting for the slowest subtask).

[0056] Furthermore, in some embodiments, there is some overlap in the definitions of various rapid detection indicators and re-inspection modes. Therefore, a use case can have multiple rapid detection indicators, and a use case can also be applicable to multiple re-inspection modes.

[0057] For example, a use case can be either a fixed pattern or a non-fixed pattern. For instance, a use case could be PM1 → PM2 / PM3, where PM1 handles 90% of the processing tasks, is the primary machine, and has a defined equipment number, thus exhibiting a fixed pattern of quick inspection indicators; PM2 / PM3 handles 10% of the tasks, meaning PM2 / PM3 are not primary machines, but this step can be performed using either PM2 or PM3, thus exhibiting a non-fixed pattern of quick inspection indicators.

[0058] In some embodiments, for efficiency reasons, only the quick detection metrics corresponding to the main machines in the use case can be used as the quick detection metrics for the entire use case, while quick detection metrics corresponding to non-main machines can be retained.

[0059] For example, in a machine tool, the main machine tool can refer to the chamber module; the non-main machine tool can refer to modules such as a robot arm or a vacuum lock for transmission.

[0060] For example, the proportion of tasks completed by a machine can be determined based on the processing time. For instance, the longer the processing time, the higher the proportion of tasks completed, and the more likely it is to be identified as a key machine.

[0061] In some embodiments, a subsequence refers to information about at least one wafer fab that is required to complete a portion of a processing task (such as cleaning) within a processing sequence.

[0062] In some embodiments, the recommendation scale can be used to define the number of recommended re-inspection patterns. For example, a larger recommendation scale results in fewer recommended re-inspection patterns, meaning a more lenient inspection process.

[0063] The recommended criteria can be set as levels or scores; for example, the higher the level or score, the larger the criteria.

[0064] In some embodiments, the recommended criteria can be preset by the user.

[0065] Alternatively, in some embodiments, the recommended re-examination modes corresponding to the rapid detection index and the re-examination modes not recommended by the rapid detection index are respectively preset with priorities. For example, the recommended re-examination modes are the first-level modes, and the unrecommended re-examination modes are the second-level modes. If the number of recommended re-examination modes (i.e., the number of recommended scales) is greater than the number of first-level modes, a re-examination mode can be randomly selected from the second-level modes until the number requirement of recommended scales is met.

[0066] Alternatively, each retesting mode can be assigned a testing priority relative to a rapid testing indicator. For example, a recommendation criterion can be set as a priority threshold, and retesting modes with a testing priority higher than the priority threshold can be selected as recommended retesting modes.

[0067] In some embodiments, the task types of test cases include Job (including cjob cluster tasks, pjob process tasks, etc.), Route, Clean, Dummy, Recalculate, etc.

[0068] The applicant noted that in the actual wafer test case generation process, it is acceptable for some real reentrant or contested test cases not to be identified, because what users really need are sufficient representative reentrant / contested cases for purposes such as scheduling algorithm verification and deadlock testing. Missing a small number of cases has a limited impact on the overall test results, but the saved computational resources are considerable.

[0069] This embodiment performs a re-inspection on test cases with fast detection indicators to avoid full detection. With a low computational load, it can initially screen out a large number of wafer test cases that are unlikely to contain complex scenarios, thereby concentrating limited computing resources on test case simulations that are highly likely to contain features such as reentrancy, competition, and parallelism.

[0070] Therefore, triggering a re-inspection for use cases that meet the rapid detection criteria helps to avoid or reduce the high costs of time series analysis and sequence comparison on a massive number of use cases.

[0071] Furthermore, the rapid detection indicators correspond to typical wafer testing scenarios and can screen out most high-risk test cases. Even if a small number of real re-entry test cases are not detected because they do not meet the exclusive mode or fixed mode, it will not affect the completion of the overall test task. Therefore, with the help of this invention, we can provide enough representative complex scenario cases for semiconductor production line simulation testing.

[0072] In other words, to control the resource cost of automatic labeling of wafer test cases, a preliminary screening using quick indicators is performed before conducting specific checks on special scenarios (i.e., reentrancy, resource contention, or parallel processing). If the probability of a test case being present in a particular scenario is clearly low, detailed checks are not recommended. Alternatively, this invention can guide engineers to a certain extent through labels during test case checks or before test case invocation, thereby reducing resource consumption when labeling massive amounts of test cases.

[0073] In some embodiments, when the rapid detection index is in machine fixed mode, the recommended re-inspection modes include: re-entry mode and resource contention mode; When the rapid detection index is in the exclusive mode, the recommended re-detection mode includes: re-entry mode; And / or, when the rapid detection index is in a non-fixed mode, the recommended re-inspection mode includes: parallel processing mode.

[0074] In some embodiments, the primary machine refers to one or more machines used to complete a proportion exceeding a set task.

[0075] For example, a test case may involve 10 machines, where the main machines may refer to the 7 machines that complete 90% of the processing tasks.

[0076] In this embodiment, the present invention filters out the key machines that undertake most of the processing tasks by the proportion of completed tasks, thereby improving the recognition rate of fixed patterns and enabling more actual high-risk use cases to be correctly identified and labeled with supplementary tags.

[0077] In some embodiments, S103 further includes: When the test case does not have a quick detection metric, the full detection mode is recommended for the test case.

[0078] In some embodiments, the full inspection mode refers to the process where, when a test case cannot be classified into any of the fixed, exclusive, or non-fixed modes, selective guidance is no longer based on quick inspection indicators. Instead, all preset re-inspection modes are executed simultaneously on the test case, such as checking: re-entry mode (whether there is a repeating sequence); resource contention mode (whether there are multiple sub-tasks on the same machine at the same time); and parallel processing mode (whether the same sub-sequence runs in parallel at the same time).

[0079] In some embodiments, when one of the test cases is set with at least two supplementary labels, corresponding label weights are set for different supplementary labels.

[0080] In some embodiments, the label weights can be preset by the user. For example, the user can set the label weights of the test cases based on engineering experience or testing requirements.

[0081] In some embodiments, the label weight can also be automatically set by the computer based on the number of times each machine in the use case appears in the re-inspection mode corresponding to the supplementary label. For example, if the main machines in a certain use case all have resource contention mode, that is, the resource contention mode appears frequently, then the weight of the resource contention label can be set to be higher.

[0082] In this embodiment, weights are assigned to different supplementary tags, so that when a large number of test cases are retrieved, users can sort or filter them by weight according to their own testing goals (such as prioritizing reentrancy scenarios) to quickly locate the most valuable test cases.

[0083] For example, a scenario for filtering use cases based on the weight of supplementary labels will be introduced: For example, an engineer performs a search in the test case library (e.g., with the keyword "etching process"), and the results return 100 relevant test cases. Among these 100 test cases, some are labeled with the reentrancy tag, some with the resource contention tag, some with the parallel processing tag, and some with multiple supplementary tags.

[0084] If the user's core requirement is to verify the scheduling algorithm's deadlock handling capability in reentrancy scenarios, then the user will prefer to see the test cases with the most typical and severe reentrancy characteristics first. In this case, test cases with higher label weights can be selected from a massive number of test cases.

[0085] In some embodiments, when the supplementary tag is a resource contention tag, the corresponding method further includes the step of: Identify competing devices in the test cases; Identify the scheduling capabilities of the competing devices in the historical scheduling logs; When the scheduling capacity exceeds a set capacity threshold, the label weight of the resource contention label is reduced accordingly.

[0086] Among them, competing equipment can refer to machine tools that need to complete multiple processing tasks simultaneously.

[0087] The scheduling capability of a competing device can be evaluated based on its scheduling performance in historical scheduling logs (such as average response time, conflict resolution success rate, and whether it has caused deadlocks or severe delays). For example, a higher conflict resolution success rate indicates a stronger scheduling capability.

[0088] For example, the percentage of tag weight reduction can be assessed based on the rating or score of scheduling capability; the higher the rating or score of scheduling capability, the greater the percentage of tag weight reduction.

[0089] In some embodiments, a use case is set with at least two supplementary labels, such as a reentrancy label and a resource contention label. Engineers may want to retest the possibility of reentrancy on the machine, but do not want the use case to contain severe resource contention (because resource contention can interfere with the analysis of reentrancy).

[0090] In this embodiment, to ensure a sufficient number of use cases with reentrancy tags while reducing the likelihood of resource contention among these use cases, the tag weight of the resource contention tag can be reduced based on the scheduling capabilities of the competing devices (because competing devices with strong scheduling capabilities usually have some ability to resolve conflicts), for example, from 0.5 to 0.2. This allows for the filtering out of some use cases with artificially high resource contention tag weights when sorting multiple use cases.

[0091] In other words, some test cases may actually have relatively high resource contention pressure, meaning the resource contention tag has a relatively high weight. However, because the machines actually allocated to these test cases have strong scheduling capabilities, the impact of resource contention in the actual simulation process can be weakened to some extent. Therefore, these test cases can relatively highlight the simulation effect of reentrancy mode.

[0092] For example, in some embodiments, test cases can be filtered based on the user's key simulation requirements (such as a greater focus on reentrancy). For instance, when the number of selected test cases is large, a secondary filtering can be performed based on key simulation requirements. For example, when the user focuses on reentrancy simulation, the weight threshold of the corresponding reentrancy label is set as the decision threshold, and test cases whose reentrancy label weight is greater than the decision threshold are selected as the final simulation test cases.

[0093] It should be understood that in semiconductor manufacturing, directly executing real production tasks can lead to serious problems such as wafer scrap, equipment damage, and production line shutdowns if equipment conflicts, deadlocks, or scheduling errors occur. Therefore, during the simulation testing phase, engineers generally hope to identify as many potential risks as possible. However, simulation resources (computation time, server load, and manual analysis effort) are also limited.

[0094] In this embodiment, by identifying the historical scheduling capabilities of competing equipment, the resource competition label weight of equipment with high priority capabilities (such as lithography machines) is dynamically reduced. This avoids overestimating the risks behind all resource competition labels in a one-size-fits-all manner, thereby identifying situations that will actually be high-risk during the simulation test. This ensures that simulation resources are always focused on the real weak links of the current production line.

[0095] From another perspective, this approach allows for more efficient allocation of computing resources based on the scheduling capabilities of competing devices, thereby avoiding the unnecessary investment of simulation resources in low-risk competition.

[0096] In some embodiments, the steps further include: S104, Identify the first supplement ratio in the tag generation process during the first tagging cycle, wherein the supplement ratio = test cases with supplementary tags / all test cases; S105, when the supplement ratio is less than the set first threshold, the recommended scale is expanded.

[0097] In this embodiment, in order to provide sufficient test case support for simulation testing, the present invention chooses to adjust the recommendation scale when the first supplement ratio is small, so that enough test cases have the opportunity to enter the re-examination, thereby avoiding the situation where a large number of actual test cases containing reentrancy, competition, and parallel features are judged as not having fast detection indicators due to the recommendation scale being set too small (such as too few recommended re-examination modes being given), and finally skipping the re-examination or only performing low-priority detection.

[0098] In some embodiments, the steps further include: S106, Identify the second supplement ratio in the label generation process during the second labeling cycle; S107, Calculate the degree of difference between the second supplement ratio and the first supplement ratio; S108, when the degree of difference is less than a set threshold and the second supplement ratio is less than a set second threshold, the re-inspection parameters of the re-inspection mode are updated.

[0099] In some embodiments, the retest parameter can be used to define the stringency of the conditions for determining whether a test case has a fast test metric.

[0100] For example, for the quick detection indicator of fixed pattern, the re-inspection parameter can refer to the main machine task proportion threshold. For instance, the lower the main machine task proportion threshold (such as decreasing from 90% to 80%), the fewer machines will be included in the main machine range. In this case, the fixed pattern is easier to meet, and therefore the corresponding stringency is less.

[0101] For example, for the exclusive mode as a quick detection metric, the re-detection parameter can refer to the similarity threshold of wafers in the wafer group (used to determine whether all wafers in the wafer group must belong to the same lot / batch). For instance, the lower the wafer similarity threshold, the more wafers from different batches are allowed, making the exclusive mode easier to satisfy, and thus the corresponding stringency is lower.

[0102] For example, for the quick detection metric of non-exclusive mode, the re-examination parameter can refer to the sources of available machines (i.e., from which data sources to determine whether there are options, such as equipment structure information, historical scheduling records, and configuration libraries). For instance, if a step in the historical log has used different machines, it is also considered as having options. In this case, the non-fixed mode is easier to satisfy, and therefore the corresponding stringency is less.

[0103] The degree of difference can be defined based on the magnitude of the difference between the second supplement ratio and the first supplement ratio. For example, the larger the difference, the greater the degree of difference.

[0104] It should be understood that in this embodiment, the present invention compares the changes in the supplementation ratio under two cycles. If the difference is not obvious and the second supplementation ratio is still small, it may indicate that the detection rule is not adapted to the current scenario and too many labels are missed. In this case, the re-inspection parameters can be further updated on the basis of expanding the recommendation scale to ensure that sufficient re-entry / competition cases can still be produced in subsequent cycles.

[0105] In some embodiments, adjusting the recommendation scale affects the types of supplementary tags for each test case, while updating the re-examination parameters changes the number of test cases tagged with supplementary tags. By first adjusting the recommendation scale (increasing the number of re-examination modes for each recommended test case and mining potential tags for recommended test cases), and then updating the re-examination parameters (relaxing the conditions for the quick detection metrics) if the supplementation ratio is still insufficient, the supplementation ratio can be gradually increased in conjunction with the time dimension to ensure that there are enough test cases available for subsequent use.

[0106] Please see Figure 2 The present invention also provides an automated labeling system for semiconductor manufacturing test cases, comprising: The test case providing module is used to provide multiple test cases, which are used to describe the wafer processing sequence. The processing sequence is used to define the wafer machines that need to be traversed to complete the set processing task, as well as the time or order in which the wafer machines are traversed. A type identification module is used to identify the task type of the test case and generate a corresponding standard label for the test case based on the task type. The standard label is used to define the task of the test case. A tag checking module is used to check whether the test cases need additional tags; wherein, the tag checking module includes: A rapid detection metric identification unit is used to identify whether the test case has a rapid detection metric, wherein the rapid detection metric includes at least one of the following: (1) Fixed mode, which means that the main machines in the test cases are all limited to a device number; (2) Exclusive mode, whereby the test case involves only one set of wafers; (3) Non-fixed mode, wherein the non-fixed mode refers to the test case having at least two options for the machine; A recommendation mode providing unit is used to provide a recommended re-examination mode according to the rapid detection index and a set recommendation scale. The re-examination mode includes at least one of the following: re-entry mode, resource contention mode, and parallel processing mode. The re-entry mode refers to the presence of at least one repeated sequence in the test case. The resource contention mode refers to the presence of at least two processing sub-tasks on the same wafer rig during the same time period in the test case. The wafer is considered to have undergone one processing cycle on the wafer rig as a processing sub-task. The parallel processing mode refers to the presence of at least two identical sub-sequences in the test case, and these at least two identical sub-sequences are run in parallel during the same time period. The supplementary tag generation unit is used to generate supplementary tags for the test case according to the corresponding re-inspection mode when the test case has the re-inspection mode. The supplementary tags include: re-entry tag, resource contention tag and / or parallel processing tag.

[0107] In some embodiments, when the rapid detection index is in machine fixed mode, the recommended re-inspection modes include: re-entry mode and resource contention mode; When the rapid detection index is in the exclusive mode, the recommended re-detection mode includes: re-entry mode; And / or, when the rapid detection index is in a non-fixed mode, the recommended re-inspection mode includes: parallel processing mode.

[0108] This invention enables automated and precise analysis of test cases, addressing the issues of low efficiency and poor accuracy associated with manual and static methods. Furthermore, it establishes a standardized description specification (hierarchical tagging system) applicable to the semiconductor manufacturing field, resolving the problem of insufficient tag standardization, enabling fully automated tag generation, and addressing the issues of low intelligence and difficulty in knowledge accumulation, thereby significantly improving management efficiency and consistency.

[0109] In some embodiments, this application also provides a schematic block diagram of the structure of a computer device, please see... Figure 3 Computer programs can be used in situations such as Figure 3 It runs on the computer device shown. Figure 3As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The memory may include non-volatile storage media and internal memory. The non-volatile storage media may store an operating system and computer programs. The computer programs include program instructions that, when executed, cause the processor to perform arbitrary methods. The processor provides computational and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the execution of the computer programs in the non-volatile storage media; when executed by the processor, these programs cause the processor to perform arbitrary methods. The network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 3 The structures shown are merely block diagrams of a portion of the structure related to the present application and do not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements. It should be understood that the processor may be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0110] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0111] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0112] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A method for automatic labeling of semiconductor manufacturing test cases, characterized by, include: S101, provides multiple test cases, the test cases are used to describe the wafer processing sequence, the processing sequence is used to define the wafer equipment that needs to be passed to complete the set processing task, and the time or order of passing through the wafer equipment; S102, identify the task type of the test case, and generate a corresponding standard label for the test case according to the task type. The standard label is used to define the task of the test case. S103, check whether the test cases need additional labels; wherein, S103 includes: S1031, Identify whether the test case has a quick detection indicator, wherein the quick detection indicator includes at least one of the following: (1) Fixed mode, which means that the main machines in the test cases are all limited to a device number; (2) Exclusive mode, whereby the test case involves only one set of wafers; (3) Non-fixed mode, wherein the non-fixed mode refers to the test case having at least two selectable device numbers; S1032, based on the rapid detection index and according to a set recommended scale, a recommended re-inspection mode is given. The recommended re-inspection mode includes at least one of the following: re-entry mode, resource contention mode, and parallel processing mode. The re-entry mode refers to the presence of at least one repeated sequence in the test case. The resource contention mode refers to the presence of at least two processing sub-tasks on the same wafer rig during the same time period in the test case. The process of a wafer being processed once by the wafer rig is considered as the processing sub-task. The parallel processing mode refers to the presence of at least two identical sub-sequences in the test case, and the at least two identical sub-sequences running in parallel during the same time period. S1033, when the test case has the re-inspection mode, a supplementary label is generated for the test case according to the corresponding re-inspection mode. The supplementary label includes: re-entry label, resource contention label and / or parallel processing label.

2. The method of claim 1, wherein, When the rapid inspection index is in machine fixed mode, the recommended re-inspection modes include: re-entry mode and resource contention mode; And / or, when the rapid detection index is the exclusive mode, the recommended re-detection mode includes: re-entry mode; And / or, when the rapid detection index is in a non-fixed mode, the recommended re-inspection mode includes: parallel processing mode.

3. The method of claim 1, wherein, The main machine refers to one or more machines used to complete a proportion of tasks exceeding the set target.

4. The method of claim 1, wherein, S103 also includes: When the test case does not have a quick detection metric, the full detection mode is recommended for the test case.

5. The method of claim 1, wherein, When one of the test cases is set with at least two supplementary labels, set the corresponding label weights for the different supplementary labels.

6. The method of claim 5, wherein, When the supplementary tag is a resource contention tag, the corresponding method further includes the following steps: Identify competing devices in the test cases; Identify the scheduling capabilities of the competing devices in the historical scheduling logs; When the scheduling capacity exceeds a set capacity threshold, the label weight of the resource contention label is reduced accordingly.

7. The method of claim 1, wherein, It also includes the following steps: S104, Identify the first supplement ratio in the tag generation process during the first tagging cycle, wherein the supplement ratio = test cases with supplementary tags / all test cases; S105, when the supplement ratio is less than the set first threshold, the recommended scale is expanded.

8. The method of claim 7, wherein, It also includes the following steps: S106, Identify the second supplement ratio in the label generation process during the second labeling cycle; S107, Calculate the degree of difference between the second supplement ratio and the first supplement ratio; S108, when the degree of difference is less than a set threshold and the second supplement ratio is less than a set second threshold, the re-inspection parameters of the re-inspection mode are updated.

9. A system for automatic labeling of semiconductor manufacturing test cases, characterized by, include: The test case providing module is used to provide multiple test cases, which are used to describe the wafer processing sequence. The processing sequence is used to define the wafer machines that need to be traversed to complete the set processing task, as well as the time or order in which the wafer machines are traversed. A type identification module is used to identify the task type of the test case and generate a corresponding standard label for the test case based on the task type. The standard label is used to define the task of the test case. A tag checking module is used to check whether the test cases need additional tags; wherein, the tag checking module includes: A rapid detection metric identification unit is used to identify whether the test case has a rapid detection metric, wherein the rapid detection metric includes at least one of the following: (1) Fixed mode, which means that the main machines in the test cases are all limited to a device number; (2) Exclusive mode, whereby the test case involves only one set of wafers; (3) Non-fixed mode, wherein the non-fixed mode refers to the test case having at least two selectable device numbers; A recommendation mode providing unit is used to provide a recommended re-examination mode according to the rapid detection index and a set recommendation scale. The re-examination mode includes at least one of the following: re-entry mode, resource contention mode, and parallel processing mode. The re-entry mode refers to the presence of at least one repeated sequence in the test case. The resource contention mode refers to the presence of at least two processing sub-tasks on the same wafer rig during the same time period in the test case. The wafer is considered to have undergone one processing cycle on the wafer rig as a processing sub-task. The parallel processing mode refers to the presence of at least two identical sub-sequences in the test case, and these at least two identical sub-sequences are run in parallel during the same time period. The supplementary tag generation unit is used to generate supplementary tags for the test case according to the corresponding re-inspection mode when the test case has the re-inspection mode. The supplementary tags include: re-entry tag, resource contention tag and / or parallel processing tag.

10. The system of claim 9, wherein, When the rapid inspection index is in machine fixed mode, the recommended re-inspection modes include: re-entry mode and resource contention mode; When the rapid detection index is in the exclusive mode, the recommended re-detection mode includes: re-entry mode; And / or, when the rapid detection index is in a non-fixed mode, the recommended re-inspection mode includes: parallel processing mode.

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