A storage chip 3D heterogeneous integration packaging method and system based on an adapter plate interposer

Abstract

This application relates to a method and system for 3D heterogeneous integrated packaging of memory chips based on an interposer interposer layer, belonging to the field of intelligent inspection technology for semiconductor packaging. It includes: constructing a characteristic impedance standard model corresponding to the physical structure of the package under test, which includes an ideal impedance fingerprint and an impedance fingerprint range set based on Monte Carlo simulation; injecting a step signal with a rise time of 10 picoseconds to 30 picoseconds through test pads on the interposer board; performing a differential comparison between the curve and the characteristic impedance standard model to extract the impedance offset; and determining the defect type and physical location based on the polarity and slope characteristics of the impedance offset within the corresponding physical layer time window. This application can effectively identify hidden interconnect defects such as micro-voids and micro-bump solder joints inside through-silicon vias (TSVs), achieving precise defect location and non-destructive testing, and is suitable for quality assessment and process feedback in high-density 3D heterogeneous integrated packaging.

Description

Technical Field

[0001] This application belongs to the field of intelligent inspection technology for semiconductor packaging, specifically relating to a method and system for 3D heterogeneous integrated packaging of memory chips based on the interposer layer of an adapter board. Background Technology

[0002] With the rapid development of semiconductor integrated circuit technology, three-dimensional heterogeneous integration technology has become a core evolutionary direction for surpassing Moore's Law and improving system computing power and storage density. Three-dimensional heterogeneous integration effectively shortens interconnect path lengths, significantly improves data exchange bandwidth, and reduces system power consumption by stacking chips with different functions in a vertical dimension. This technology involves complex micro-nano manufacturing processes and multi-level physical connections, and is a key support for realizing high-performance computing and large-scale data storage.

[0003] Among these, the stacking of memory chips based on the interposer layer of the adapter board is a key path to achieving high-bandwidth memory. By setting high aspect ratio through-silicon vias and high-density microbump arrays in the adapter board, high-speed signal transmission between memory chips and logic chips can be achieved. This structure places extremely high demands on the stability of interconnect quality. Any minute physical imperfections can have a profound impact on signal integrity in a complex electromagnetic environment, and the reliability of its interconnect structure directly determines the performance of the final packaged product.

[0004] However, existing interconnect detection methods primarily rely on DC resistance measurements, which can only identify macroscopic failures such as fully open circuits or short circuits. They cannot effectively detect hidden interconnect defects such as microscopic voids inside through-silicon vias (TSVs) and poor wetting at microbumps. These microscopic defects exhibit pseudo-conduction characteristics at conventional test frequencies, but can cause significant impedance mismatches during high-frequency signal transmission, resulting in severe signal reflections and timing shifts, leading to a significant decrease in the reliability of high-speed memory links. Furthermore, due to the enclosed space of 3D packaging, traditional physical destructive testing methods struggle to balance testing efficiency and non-destructiveness, making it impossible to provide high-precision real-time feedback and quantitative evaluation of internal interconnect quality after packaging.

[0005] Therefore, a method and system for 3D heterogeneous integration packaging of memory chips based on the interposer layer of the adapter board is desired. Summary of the Invention

[0006] The purpose of this invention is to provide a 3D heterogeneous integration packaging method and system for memory chips based on an interposer plate interposer layer, which can effectively solve the problems in the background art mentioned above.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A 3D heterogeneous integration packaging method for memory chips based on an interposer board interposer layer includes the following specific steps: A characteristic impedance standard model corresponding to the physical structure of the package under test is constructed. The characteristic impedance standard model includes the ideal impedance fingerprint under defect-free conditions, as well as the impedance fingerprint range based on Monte Carlo simulation that covers normal process fluctuations. A step signal with a preset rise time, between 10 picoseconds and 30 picoseconds, is injected into the internal interconnect network of the package under test through the test pads on the adapter board. The reflected waveforms generated by impedance discontinuities when a step signal propagates in the interconnection path are acquired in real time. Parasitic parameters of the external path are eliminated by de-embedding processing, and multiple reflection interferences are eliminated step by step by the layer-stripping algorithm. The processed reflected waveforms are then converted into time-domain impedance distribution curves. The impedance distribution curve in the time domain is compared with the standard model of characteristic impedance to extract the impedance offset that reflects interconnect defects. Based on the polarity and slope characteristics of the impedance offset within the time window of the corresponding physical level, the defect type and physical location are determined.

[0008] Furthermore, the rise time of the step signal is determined based on the characteristic size of the interconnect structure under test. For an interconnect structure with a characteristic size on the order of 10 micrometers, a rise time of 20 picoseconds is selected. The amplitude of the step signal is set to 10% to 20% of the breakdown voltage of the insulating medium in the interconnect structure, and the stability of the signal amplitude is maintained within the preset amplitude fluctuation range through the automatic level control function of the time domain reflectometer. A high-frequency probe with a bandwidth of no less than 70 GHz is used to contact the test pad. The surface of the test pad is formed with a hard gold layer with a thickness of 0.5 micrometers to 2 micrometers through an electroplating process, so that the contact resistance change rate is less than a preset change rate threshold after multiple contact tests.

[0009] Furthermore, by employing equivalent sampling techniques, the reflected voltage signal is captured with a preset time resolution of 100 femtoseconds to 500 femtoseconds; The de-embedding process is based on the pre-measured scattering parameters of the open-circuit standard, short-circuit standard, and load standard, and the contributions of the probe and cable are removed from the total reflection response through vector operations. The layer-stripping algorithm starts from the first impedance discontinuity closest to the test probe, calculates its impedance value based on the reflection coefficient of that point, and removes the reflection effect generated by that point from the total reflection response. It then proceeds step by step to the deeper points, eventually obtaining the true impedance distribution at each location along the entire propagation path.

[0010] Furthermore, a physical parameterized model of the interconnect structure is established, and the physical properties of the redistribution layer of the adapter board, through-silicon vias, and microbump array are digitally modeled. The modeling parameters include geometric dimensions and material properties. Electromagnetic simulation is performed to obtain impedance fingerprints under defect-free conditions. A step excitation signal with a rise time of 10 picoseconds is applied to the input of the model. Monitoring points are set at equal intervals along the signal propagation path to record transient voltage and current responses. The impedance values ​​at each position along the signal propagation path are obtained and arranged in order to form a standard impedance fingerprint. An impedance fingerprint range covering process fluctuations is defined, and key geometric and material parameters are defined as variables that follow a specific statistical distribution. Multiple electromagnetic simulations are run to obtain a set of impedance fingerprint curves. The impedance values ​​at each location in the set are statistically analyzed, and the upper and lower boundaries of the impedance fluctuation at that location are determined according to the preset confidence level. The upper and lower boundaries at all locations are connected to form the upper and lower envelopes of the impedance fingerprint range.

[0011] Furthermore, before performing a differential comparison between the time-domain impedance distribution curve and the characteristic impedance standard model, the method further includes: using an autocorrelation alignment algorithm, with the characteristic impedance standard model as a reference template, calculating the cross-correlation coefficient between the time-domain impedance distribution curve and the characteristic impedance standard model, searching for the time offset that maximizes the cross-correlation coefficient, and shifting the time-domain impedance distribution curve as a whole by this offset to ensure that the zero points of the two completely coincide on the time axis; To compensate for frequency-dependent losses during signal propagation, the real-time curve is converted to the frequency domain using a fast Fourier transform, and each frequency component is multiplied by the corresponding gain coefficient to compensate for the attenuation effect of conductor loss and dielectric loss on the impedance curve amplitude. Differential comparison introduces a dynamic threshold mechanism, which sets different judgment thresholds for interconnect structures at different locations based on the sensitivity of the structure to signal integrity. Specifically, for the core data bus path, the impedance offset threshold is set to a first preset offset threshold, and for the power or ground path, the impedance offset threshold is set to a second preset offset threshold that is greater than the first preset offset threshold.

[0012] Furthermore, within the corresponding time window of the through-silicon via, if the impedance offset shows an increasing trend and the peak value of the offset exceeds the third preset offset threshold, it is determined that there is an inductive deviation defect at that location. The inductive deviation defect corresponds to a void or break inside the through-silicon via. If, within the time window at the corresponding microbump connection, the maximum slope value of the impedance offset curve exceeds the preset slope threshold and the impedance peak shows a sharp inductive abrupt change, then the microbump is determined to have a defect of poor soldering or poor wetting. The third preset offset threshold is set to 1.2 to 1.5 times the difference between the upper limit of the impedance fingerprint interval at that location in the standard model and the standard ideal impedance value, and the preset slope threshold is taken as twice the maximum slope value within the impedance fingerprint interval at that location in the standard model.

[0013] Furthermore, the physical location is determined by the time-of-flight positioning formula in the time-domain reflection principle. The formula states that the physical distance between the defect and the test pad is equal to the speed of signal propagation in the medium multiplied by half the time difference of the reflected wave on the time axis. For signals in multilayer stacked structures that need to penetrate different media, the equivalent dielectric constant method is used to calibrate the propagation speed; Based on the calculated physical distance and the spatial location range of each physical level defined in the standard model, defects are automatically classified into the corresponding physical level. The physical levels include the redistribution layer of the adapter board, the through-silicon via segment, and the microbumps of each layer of memory chips.

[0014] Furthermore, for the multi-layer memory chip stacking structure, the internal interconnect path of each layer of memory chip is parameterized layer by layer, and the interconnect structure model of each layer is established. They are then connected in a cascading manner to form a complete vertical interconnect channel model. To address the complex reflection environment caused by multilayer stacking, a high-order de-embedding algorithm based on a 16-term error model is adopted. When calculating the reflection coefficient, broadband modeling for the skin effect is introduced, and a series resistance term proportional to the square root of the frequency is added to the transmission line model to correct the nonlinear attenuation caused by the propagation of high-frequency signals in multilayer conductive substrates. By using time window gating technology, the reflected signal is divided into multiple independent time periods, each corresponding to the vertical interconnect area of ​​each layer of memory chip. Only the reflected signal falling into the corresponding window is used for defect determination of that layer.

[0015] Furthermore, when the impedance offset is detected to show a slow upward trend and the slope change rate is less than the preset small value, the system determines it to be a uniform thinning or oxidation diffusion of the copper layer on the inner wall of the through silicon via. The preset small value is set according to 0.5 times the minimum slope change rate in the impedance fingerprint range at that position in the standard model. By collecting impedance data from multiple consecutive packages, the arithmetic mean of the impedance at each level and its drift curve with the package number are calculated. When the mean drift exceeds the process control limit, an early warning signal is generated, providing parameter feedback for upstream chemical mechanical planarization and deep reactive ion etching processes.

[0016] A 3D heterogeneous integrated packaging system for memory chips based on an interposer board interposer layer includes: The model building module is used to construct a characteristic impedance standard model corresponding to the physical structure of the package under test. The characteristic impedance standard model includes the ideal impedance fingerprint under defect-free conditions, as well as the impedance fingerprint range based on Monte Carlo simulation that covers normal process fluctuations. This module performs digital modeling of the physical characteristics of the redistribution layer of the adapter board, through-silicon vias and microbump arrays, performs electromagnetic simulation to obtain the impedance fingerprint under defect-free conditions, and sets the upper and lower envelopes of the impedance fingerprint range in combination with the statistical distribution of process parameters. The signal injection module is used to inject a step signal with a preset rise time (between 10 picoseconds and 30 picoseconds) into the internal interconnect network of the package under test through the test pads on the adapter board. The module uses a high-frequency probe with a bandwidth of not less than 70 GHz to contact the test pads and uses the automatic level control function of the time domain reflectometer to maintain the stability of the signal amplitude, ensuring that the excitation signal has sufficient spectral width to excite micro-defects to generate a detectable reflection response. The curve generation module is used to acquire the reflected waveforms generated by impedance discontinuities when a step signal propagates in the interconnection path in real time. It eliminates parasitic parameters of the external path through de-embedding processing and uses a layer-stripping algorithm to eliminate multiple reflection interferences step by step, converting the processed reflected waveforms into time-domain impedance distribution curves. This module captures reflected voltage signals at a preset time resolution based on equivalent sampling technology, uses the scattering parameters of open-circuit, short-circuit, and load standard components to perform vector calculations to strip the parasitic contributions of probes and cables, and restores the true impedance value of each location step by step through the layer-stripping method. The differential comparison module is used to perform differential comparison between the time-domain impedance distribution curve and the characteristic impedance standard model to extract the impedance offset reflecting interconnect defects. This module uses an autocorrelation alignment algorithm to achieve accurate registration of the curve on the time axis, compensates for frequency-dependent loss, and introduces a dynamic threshold mechanism to set differentiated judgment thresholds for different signal paths. Finally, the impedance offset at each physical location is obtained through point-to-point differential operation. The defect determination module is used to determine the defect type and physical location based on the polarity and slope characteristics of the impedance offset within the time window of the corresponding physical layer. This module defines the time window according to the spatial position of each physical layer defined in the standard model. By identifying the increasing trend of impedance offset, peak exceeding the limit, or abrupt slope changes, it distinguishes defect types such as internal void fracture of through-silicon vias and micro-bump solder joint failure. It also uses the time-of-flight positioning formula combined with equivalent dielectric constant calibration to accurately locate the defect to the redistribution layer of the adapter board, the through-silicon via segment, or the micro-bump layer of each memory chip.

[0017] In summary, this application includes at least one of the following beneficial technical effects: 1. This invention overcomes the limitation of traditional DC resistance testing in identifying latent defects. By injecting an ultrafast step signal of a predetermined magnitude, this method can capture high-frequency reflection information, thereby achieving sensitive detection of latent interconnect defects such as micro-voids, cracks, and poor solder joints at micro-bumps inside through-silicon vias. Its detection accuracy reaches the quantification level of physical morphology changes of a predetermined magnitude, enabling the identification of microscopic physical defects that are difficult to detect by traditional electrical methods and only cause signal reflection and timing jitter under high-frequency operating environments, significantly improving the reliability assessment capability of 3D heterogeneous integrated packaging.

[0018] 2. This invention utilizes the time-of-flight characteristics of signals propagating in interconnect paths to achieve precise defect location. Because the system possesses a preset order of magnitude of time resolution, it can accurately map the time axis of the time-domain reflected signal to the physical depth of the package structure. Through algorithmic processing, this invention can clearly indicate whether the defect occurs in the redistribution layer of the adapter board, inside a through-silicon via at a specific depth, or at a specific micro-bump level. This spatial positioning capability provides intuitive guidance for improving packaging processes, significantly shortens the failure analysis cycle, and avoids the high cost of blindly searching for defect locations using traditional destructive slicing.

[0019] 3. This invention achieves transparent inspection of the internal closed structure of the package entirely based on electrical testing methods, exhibiting typical non-destructive characteristics. Compared with existing methods such as cross-sectional microscopy and transparent scanning, this method does not require physical damage to the chip and can be repeatedly tested at any stage after packaging. Furthermore, due to the use of real-time waveform acquisition and automated differential comparison algorithms, the detection and judgment process for a single interconnect channel can be completed in a very short time. This highly efficient detection mode allows for seamless integration into automated semiconductor production lines, achieving full-volume testing rather than sampling inspection, fundamentally ensuring the long-term operational stability of the memory chips leaving the factory.

[0020] 4. This invention, by constructing a characteristic impedance standard model, can flexibly adapt to 3D heterogeneous integration schemes with different numbers of layers and interconnect densities. The system has an automatically generated defect map function, which can intuitively display the weak points within the package. Combined with dynamic threshold judgment and temperature compensation logic, this method has extremely high robustness in complex industrial production environments and can provide quantitative quality feedback for parameter optimization of 3D packaging processes. Through in-depth analysis of impedance fingerprints, it achieves a leap from qualitative judgment to quantitative evaluation of package interconnect quality, laying a solid foundation for hardware security in high-performance computing and large-scale storage systems. Attached Figure Description

[0021] Figure 1 This is a flowchart of a 3D heterogeneous integration packaging method for memory chips based on an adapter board interposer layer.

[0022] Figure 2 This is a schematic diagram of the core principle of defect detection based on the time-domain reflection principle and impedance fingerprint comparison.

[0023] Figure 3 This is a flowchart for constructing a standard characteristic impedance model that includes the impedance fingerprint range of physical feature points.

[0024] Figure 4 This is a schematic diagram of the data flow from the acquisition of reflected voltage signals to the conversion of time-domain impedance distribution curves.

[0025] Figure 5 This is a flowchart for classifying and accurately locating defect types based on the polarity and slope characteristics of impedance offset. Detailed Implementation Example 1

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0027] First, the 3D heterogeneous integration packaging method for memory chips based on an adapter board interposer layer disclosed in this application is implemented according to the following steps: The first step, S1, involves constructing a standard model of the characteristic impedance of the 3D package interconnect path. Step S1 establishes a standard model of characteristic impedance that precisely corresponds to the physical structure of the package under test. This model not only includes the ideal impedance characteristics under defect-free conditions but also reasonably covers the impedance variation range allowed by normal process fluctuations, thus providing a basis for comparison in subsequent real-time testing. This is achieved through the following sub-steps.

[0028] Step S101: Establish a physical parameterized model of the interconnect structure; perform digital modeling of the physical characteristics of the transmission paths at all levels in the 3D heterogeneous integrated structure of the memory chip, including the redistribution layer of the adapter board, through-silicon vias, and microbump array.

[0029] When building the model, the distribution parameters of each level path are first extracted using an electromagnetic field solver, including the inductance L and capacitance C per unit length.

[0030] The extraction process is based on the geometry and material properties of each layer: for the interposer layer, the modeling parameters need to be set in detail, such as the thickness of the silicon substrate, typically 100 micrometers; at the same time, the relative permittivity range is set to 3.9 to 11.7, the loss tangent range is set to 0.001 to 0.02, and the conductivity is set.

[0031] The model needs further refinement to the geometric dimensions of the metal interconnects, such as linewidth, line thickness, and line spacing. Additionally, the characteristics of the insulating dielectric layers between the metal layers, such as the dielectric constant and thickness of polyimide or silicon dioxide, also need to be included in the model. These geometric dimensions and material parameters can be obtained directly from the package design documents or set using process capability statistics.

[0032] Step S102: Perform electromagnetic simulation to obtain impedance fingerprint under defect-free conditions; Based on the parameterized model established in step S101, use computational electromagnetics to simulate the propagation behavior of electromagnetic waves in non-uniform transmission lines, specifically using finite element analysis or finite-difference time-domain method.

[0033] During the simulation, the geometric structure and material parameters established in step S101 are imported into the simulation software. A step excitation signal with a rise time of 10 picoseconds is applied to the input end of the model, and monitoring points are set at equal intervals along the signal propagation path to record the transient voltage and current response at each monitoring point.

[0034] The simulation process must take into account the frequency dependence of electromagnetic parameters, especially the effect of the skin effect on conductor resistance and internal inductance under high-frequency conditions.

[0035] By performing the above simulation, the impedance values ​​at various locations along the signal propagation path under ideal, defect-free conditions are obtained. Arranging these impedance values ​​in order of propagation time or spatial location forms a standard impedance fingerprint, hereinafter referred to as the standard curve. This standard curve is a continuous curve with propagation time or spatial location as the abscissa and impedance value as the ordinate.

[0036] Step S103: Set an impedance fingerprint range that covers process fluctuations; since normal process fluctuations inevitably exist in actual production, relying solely on ideal impedance values ​​cannot accurately distinguish between defects and process deviations. Therefore, it is necessary to set an impedance fingerprint range.

[0037] This range is set based on the Monte Carlo simulation method: the key geometric parameters and material parameters involved in step S101 are defined as variables that follow a specific statistical distribution. For example, the metal linewidth is defined as following a normal distribution, with the mean taken from the design value and the standard deviation set to a fluctuation range of ±10% according to the process capability index.

[0038] The dielectric constant is defined as following a uniform distribution, with the fluctuation range set according to data provided by the material supplier. Subsequently, multiple electromagnetic simulations are run, with each simulation randomly selecting a set of values ​​for the aforementioned variables to calculate an impedance fingerprint curve. This process is repeated a sufficient number of times, such as 500 or 1000 times, to obtain a set of impedance fingerprint curves.

[0039] Perform statistical analysis on the impedance values ​​at each spatial location or time point in the set, and calculate the mean and standard deviation of the impedance values ​​at that location. Determine the upper and lower boundaries of the impedance fluctuation at that location based on a preset confidence level, such as 95% or 99%.

[0040] Connecting the upper and lower boundaries at all locations forms the upper and lower envelopes of the impedance fingerprint region. This region covers impedance variations caused by normal process fluctuations, including variations in photoresist thickness, metal linewidth fluctuations of ±10% due to etching rate deviations, and dielectric constant variations caused by batch differences in material properties.

[0041] In summary, step S1 completes the construction of the characteristic impedance standard model. This model includes the ideal impedance fingerprint under defect-free conditions, and the impedance fingerprint range established based on Monte Carlo simulation reasonably covers the impedance variation range caused by normal process fluctuations. Thus, a digital benchmark that can objectively reflect the "health" state of the package is obtained, providing a foundation for subsequent real-time detection and comparison of actual samples.

[0042] Next, in step S2, a step signal with a preset rise time is injected through the test pads on the adapter board. Step S2 injects a step signal with an ultrafast rise time into the internal interconnect network of the package under test to excite various defects in the interconnect structure to generate high-frequency reflected signals that can be captured. The quality of this signal and the injection method directly affect the accuracy and reliability of subsequent testing. This is specifically achieved through the following sub-steps.

[0043] Step S201: Select and configure the test equipment. A time-domain reflectometer (TDR) is selected as the test equipment, with a system bandwidth of at least 70 GHz to support the generation and acquisition of ultrafast step signals. The output of the TDR is connected to a high-frequency probe via a coaxial cable. The bandwidth of the high-frequency probe must also meet the requirement of at least 70 GHz to ensure that the signal is not distorted during transmission. A low-loss, phase-stable coaxial cable with a characteristic impedance of 50 ohms and a length not exceeding 1 meter is selected to reduce signal attenuation and dispersion during transmission.

[0044] Step S202: Set the rise time and amplitude of the step signal; set the rise time of the step signal to a preset time value, which is between 10 picoseconds and 30 picoseconds, and 20 picoseconds is selected in this embodiment. By controlling such a short rise time, the signal spectrum is ensured to cover the frequency range from DC to tens of GHz, thereby enabling the detection system to identify interconnect defects with physical dimensions at the micrometer or even submicrometer level.

[0045] The specific rise time value is determined based on the feature size of the interconnect structure under test: for interconnect structures with a feature size on the order of 10 micrometers, a rise time of 20 picoseconds is sufficient to generate enough spectral components; for structures with smaller feature sizes, a shorter time, such as 10 picoseconds, is selected.

[0046] The amplitude of the step signal is set to a preset voltage value, which is determined based on the withstand voltage capability of the interconnect structure under test. Specifically, the breakdown voltage of the insulating medium in the interconnect structure is obtained by consulting the package design documents, and the amplitude of the step signal is set to 10% to 20% of the breakdown voltage to ensure safety, typically between 200 mV and 500 mV.

[0047] During signal injection, the automatic level control function of the time domain reflectometer keeps the signal amplitude stable within a preset amplitude fluctuation range of ±1 millivolt, so as to ensure a high signal-to-noise ratio in the subsequent differential comparison process.

[0048] Step S203: Arrange the test pads and control the contact quality; the test pads are pre-arranged on the top layer of the adapter board, and their layout follows the standard probe station spacing requirements, with the spacing between adjacent contacts set within a preset range of 40 micrometers to 150 micrometers. This spacing range matches the layout density of the test pads in the package design, ensuring that the probe card can simultaneously form reliable contact with all test pads.

[0049] A hard gold layer, ranging from 0.5 to 2 micrometers in thickness, is formed on the surface of the test pads through an electroplating process to ensure impedance stability after multiple contact tests. The presence of the hard gold layer ensures that the contact resistance change rate is less than a preset threshold of 1%.

[0050] The preset rate of change threshold is verified by measuring the initial contact resistance when the probe makes its first contact with the test pad, followed by 1000 repeated contacts, measuring the contact resistance every 100 contacts, calculating the rate of change between adjacent measurements, and ensuring that the rate of change is always less than 1%.

[0051] Step S204: Perform signal injection operation; precisely align the tip of the high-frequency probe with the test pad on the surface of the adapter board. The alignment accuracy is achieved by the automatic optical alignment system of the probe station, ensuring that the deviation between the tip and the center of the pad does not exceed 10% of the pad diameter.

[0052] After alignment, a preset contact force is applied by the vertical drive mechanism of the probe station. This preset contact force is set according to the probe specifications and is usually between 2 and 10 grams to ensure that the probe and the pad form a stable and reliable electrical contact, while avoiding damage to the pad surface due to excessive contact force.

[0053] A pre-set step signal is output to the probe via a time-domain reflectometer (TDRI). The signal passes through the probe and test pads before entering the adapter board. The triggering time of the signal injection is controlled by the internal clock of the TDRI, ensuring that the signal injection is synchronized with the timing of the subsequent acquisition system.

[0054] Step S205, signal transmission path within the package: The injected step signal first enters the redistribution layer conductor through the test pad on the top layer of the adapter board. The redistribution layer conductor guides the signal to the top entrance of the through-silicon via (TSV). The signal then propagates vertically downwards along the TSV, and enters the next layer of memory chip or logic chip through a microbump array at the bottom of the TSV.

[0055] For multilayer stacked structures, the signal continues to pass sequentially through the microbumps and through-silicon vias of each subsequent layer until it reaches a predetermined termination position. The predetermined termination position is either the far-end ground terminal of the package or a specific signal termination structure, ensuring that the signal encounters a sufficient number of interconnect interfaces during propagation, thereby fully reflecting the quality of the entire interconnect path.

[0056] In summary, step S2 completes the generation, injection, and transmission of the step signal. By controlling the signal's rise time, amplitude stability, and the contact quality of the test pads, sufficient bandwidth and fidelity are ensured for the excitation signal to propagate effectively in the interconnect path and fully respond to various microscopic defects. After successful injection, the signal will propagate in the interconnect path and be reflected due to impedance discontinuities, providing raw data for subsequent reflection waveform acquisition and impedance analysis.

[0057] For step S3, the reflected waveform is acquired in real time and converted into a time-domain impedance distribution curve. Step S3 aims to capture the reflected waveform generated by impedance discontinuities when a step signal propagates in the interconnect path, and convert it into a time-domain impedance distribution curve that can intuitively reflect the internal impedance characteristics of the package. The quality of this conversion process directly determines the accuracy of subsequent defect identification. This is specifically achieved through the following sub-steps.

[0058] Step S301: Configure the sampling system and set the time resolution; use a high-speed sampling circuit to capture reflected voltage signals generated by impedance discontinuities on the interconnect path. To achieve accurate capture of ultrafast signals, an equivalent sampling technique is used. This technique reconstructs the complete waveform by triggering multiple acquisitions, each acquisition being offset by a small time step within the signal period. The time resolution of the sampling system is set to a preset time resolution of 100 femtoseconds to 500 femtoseconds.

[0059] With such high temporal resolution, the system can precisely map the time-of-flight of electrical signals to physical lengths at the nanometer or micrometer level. The specific value of the temporal resolution is determined based on the longitudinal dimension of the package being measured: for packages with a total thickness on the order of 100 micrometers, a temporal resolution of 500 femtoseconds is sufficient to meet the positioning accuracy requirements; for thinner structures or those requiring higher positioning accuracy, a shorter time, such as 100 femtoseconds, is selected.

[0060] Step S302: Perform reflected waveform acquisition; switch the time-domain reflectometer to acquisition mode and receive the voltage signal reflected from the interconnect path through the same high-frequency probe. The acquisition system discretely samples the reflected signal at the time resolution set in step S301, recording the voltage value at each sampling moment. The acquired raw data is a discrete set of points containing time series and voltage amplitude, with each data point consisting of the sampling moment and the corresponding reflected voltage amplitude.

[0061] Step S303: Perform de-embedding processing to eliminate parasitic parameters; the acquired reflected waveform contains parasitic effects introduced by external paths such as test interfaces and probe cables. The analysis system eliminates these parasitic parameters through the de-embedding algorithm, ensuring that the final impedance curve only reflects the true interconnect characteristics inside the package.

[0062] The de-embedding process is based on pre-measured scattering parameters of open-circuit, short-circuit, and load standards. The specific steps are as follows: First, using the same probes and cables as in the actual test, contact the open-circuit, short-circuit, and load standards respectively, and record the time-domain reflection waveforms under each of the three conditions. Second, input these three waveforms as calibration data into the analysis system. Finally, perform vector operations between the actual test-acquired reflection waveforms and the calibration data to separate the contributions of the probes and cables from the total reflection response, thereby obtaining the pure reflection response generated solely by the internal interconnect structure of the package.

[0063] Step S304: Convert the reflected waveform into an impedance distribution curve; the conversion process follows the transmission line impedance calculation logic. For the de-embedding processed reflected waveform, first calculate the reflection coefficient ρ at each sampling time. The reflection coefficient ρ is calculated by the ratio of the reflected voltage to the incident voltage acquired in real time.

[0064] Where V_{ref} represents the reflected voltage amplitude, and V_{inc} represents the incident voltage amplitude. The incident voltage amplitude has been set and recorded in step S202, and the reflected voltage amplitude is acquired in step S302.

[0065] Subsequently, based on transmission line theory, the reflection coefficient is converted into a characteristic impedance value, and the conversion formula is as follows:

[0066] Where Z represents the calculated characteristic impedance value, Z_{0} represents the system reference impedance, which is taken as 50 ohms, and ρ represents the reflection coefficient at that sampling moment. The above calculation is performed sequentially for all sampling moments to obtain the characteristic impedance value corresponding to each moment.

[0067] Step S305: Eliminate multiple reflection interference; during the conversion process, the system analysis considers the impact of multiple reflections. When the signal propagates to the deep layers of the package, impedance discontinuities in the preceding stage will generate reflections. Some of the reflected waves will propagate forward again and generate secondary or even multiple reflections at subsequent discontinuities. These multiple reflections superimposed on the original reflection response will form interference. The system uses a layer-by-layer stripping algorithm to calculate the impedance step by step to eliminate these interferences.

[0068] The specific implementation of the layer-stripping algorithm is as follows: Starting from the first impedance discontinuity closest to the test probe, the impedance value is calculated based on the reflection coefficient of that point, and the reflection effect generated by that point is removed from the total reflection response. Subsequently, the remaining reflection response after removal is used as input to continue calculating the next discontinuity at a more distant location; and so on, progressing step by step deeper, until the true impedance distribution at each location along the entire propagation path is obtained. This algorithm removes spurious signals through iterative calculations, restoring the true physical layer impedance distribution.

[0069] Step S306: Generate the measured time-domain impedance distribution curve; arrange the characteristic impedance values ​​at each location calculated in steps S304 and S305 according to the signal propagation time or spatial location to generate the measured time-domain impedance distribution curve, hereinafter referred to as the measured curve. The measured curve uses the horizontal axis to represent the signal propagation time or corresponding spatial location, and the vertical axis to represent the impedance value. The correspondence between spatial location and propagation time is given by the formula... Here, d represents the spatial distance, v represents the signal propagation speed in the medium, and t represents the propagation time. The propagation speed v is set based on the relative permittivity of the adapter board and chip materials, and the specific calculation formula is as follows: Where c is the speed of light in a vacuum, and its value is 3 x 10⁸ meters per second. is the relative permittivity of the medium.

[0070] In summary, step S3 completes the acquisition of reflected waveforms, de-embedding processing, impedance transformation, and multiple reflection elimination, ultimately generating a time-domain impedance distribution curve that accurately reflects the internal impedance characteristics of the package. This curve provides the data basis for subsequent differential comparison with the standard model. Each feature point on the curve corresponds to a specific physical location inside the package, and its impedance value reflects the interconnect quality at that location.

[0071] Next, in step S4, the real-time curve is differentially compared with the standard model, and the impedance offset is extracted. Step S4 aims to compare the time-domain impedance distribution curve generated in step S3 with the characteristic impedance standard model constructed in step S1, and extract the impedance offset reflecting interconnect defects through differential operations. The quality of this comparison process directly determines the accuracy and reliability of defect identification. This is specifically achieved through the following sub-steps.

[0072] Step S401: Perform curve spatial location mapping and time axis alignment; the real-time generated time-domain impedance distribution curve is first mapped to the spatial location axis. The mapping process is based on the propagation speed and time-space transformation relationship set in step S306, converting the curve's horizontal axis from propagation time to the corresponding physical spatial location.

[0073] Differential alignment is performed in the time domain. To eliminate the time offset error caused by the instant the test probe contacts the target, the system employs an autocorrelation alignment algorithm. The specific implementation of this algorithm is as follows: using the standard model curve constructed in step S1 as a reference template, a time window is slid along the time axis of the real-time curve, and the cross-correlation coefficient between the real-time curve and the standard model curve at each sliding position is calculated. The formula for calculating the cross-correlation coefficient is:

[0074] in, This represents the cross-correlation coefficient at a time offset of τ. The standard model curve at time t The impedance value, This represents the mean impedance of the standard model curve. Indicates the real-time curve at time [time]. The impedance value, The impedance mean of the real-time curve is represented by , and n represents the total number of sampling points. The time offset used to search for the maximum cross-correlation coefficient is . The real-time curve will be shifted as a whole. This ensures that the real-time curve and the zero point of the standard model on the time axis are completely coincident.

[0075] Step S402: Perform frequency-dependent loss compensation; before performing point-to-point differential calculations, the system automatically compensates for frequency-dependent loss during signal propagation. Because high-frequency components attenuate faster during propagation, the impedance curve amplitude at the far end is lower, affecting the accuracy of the comparison.

[0076] The compensation algorithm is based on the attenuation factor set in the standard model in step S1. The attenuation factor is obtained through electromagnetic simulation in step S102, and is specifically represented as the attenuation coefficient of different frequency components on a unit length propagation path.

[0077] During compensation, the real-time curve is converted to the frequency domain using a Fast Fourier Transform (FFT). Each frequency component is multiplied by a corresponding gain coefficient, which is an exponential function of the product of the reciprocal of the attenuation coefficient at that frequency and the propagation distance. Gain correction is applied to the signal at the far end, i.e., far from the test probe, to compensate for the attenuation effect of conductor and dielectric losses on the impedance curve amplitude. After compensation, the signal is restored to the time domain using an Inverse Fourier Transform (IFT).

[0078] Step S403: Perform point-to-point differential calculation and extract impedance offset; after alignment and compensation, perform point-to-point differential calculation between the real-time curve and the standard model curve. For each spatial location point, calculate the difference between the impedance value of the real-time curve at that point and the impedance value of the corresponding location on the standard model curve. This difference is the impedance offset at that location.

[0079] The expression for difference operations is:

[0080] in, This represents the impedance offset at position x. This represents the impedance value of the real-time curve at position x. This represents the impedance value of the standard model curve at position x.

[0081] Through the above corrections and calculations, the pure impedance offset at each physical feature point can be extracted. The feature data extracted by the system includes the peak value, extreme value location, and waveform slope characteristic of the offset. The peak value refers to the maximum absolute value of the offset, the extreme value location refers to the coordinates of the position where the peak value appears, and the waveform slope characteristic refers to the rate of change of the offset curve within a specific interval.

[0082] Step S404: A dynamic threshold mechanism is applied for preliminary judgment; the differential comparison process introduces a dynamic threshold mechanism. For interconnect structures at different locations, the system sets differentiated judgment thresholds based on the sensitivity of that structure to signal integrity.

[0083] The dynamic threshold is set based on the following: For the core data bus path, which carries high-speed data signals, the impedance matching requirements are extremely high. The impedance offset threshold is set to a strict first preset offset threshold. For example, when the impedance offset exceeds 3%, it is considered abnormal.

[0084] For power or ground paths, which transmit DC or low-frequency signals and are not sensitive to high-frequency impedance fluctuations, the threshold is relaxed to a second preset offset threshold; for example, an impedance offset exceeding 10% is considered abnormal. For other normal signal paths, the threshold setting is between the two.

[0085] In addition, for specific defect types such as internal voids in through-silicon vias and poor soldering of micro-bumps, the system also has an independent third preset offset threshold and corresponding judgment logic, the specific values ​​and setting basis of which will be detailed in subsequent steps.

[0086] In summary, step S4 completes the comparison, alignment, compensation, differential calculation, and dynamic threshold determination of the time-domain impedance distribution curve with the standard model, ultimately extracting the impedance offset at each physical feature point. This offset carries key information about interconnect defects, including the existence, severity, and approximate location range of the defects, providing a quantitative basis for subsequent defect type determination and precise location.

[0087] Finally, step S5 determines the defect type and physical location based on the extreme values ​​and slope of the impedance offset. This step aims to utilize the impedance offset features extracted in step S4, combined with electromagnetic principles and time-domain reflection theory, to identify and spatially locate defects in the interconnect path. This determination process transforms abstract offset data into specific defect information, providing a direct basis for packaging quality assessment and process improvement. This is specifically implemented through the following sub-steps.

[0088] Step S501: Identify characteristic time windows in the impedance offset curve. The system first delineates corresponding time windows on the impedance offset curve based on the physical layer positions defined in the standard model constructed in step S1. Each time window corresponds to a specific physical region in the package structure. For example, the redistribution layer of the adapter board corresponds to the first time window, the through-silicon via segment corresponds to the second time window, the first layer microbumps correspond to the third time window, and the second layer memory chip interconnect area corresponds to the fourth time window.

[0089] The boundaries of the time window are determined based on the propagation speed and time-space transformation relationship set in step S306. For each physical region, its starting and ending positions each correspond to a propagation time value, and the interval between these two time values ​​is the time window for that region. The system will independently determine defects within each time window.

[0090] Step S502: Determine if there are voids or fractures inside the through-silicon via (TSV). Within the time window corresponding to the TSV, the system detects the change characteristics of the impedance offset. If the impedance value is observed to show an increasing trend relative to the standard model within the window, and the peak value of the offset exceeds the third preset offset threshold, the system determines that there is an inductive deviation defect at that location.

[0091] The third preset offset threshold is set based on the upper limit of the impedance fingerprint range at that location in the standard model. Specifically, the difference between the upper boundary value of the impedance fingerprint range at that location and the standard ideal impedance value is used as the reference threshold, and the third preset offset threshold is set to 1.2 to 1.5 times this reference threshold. When the measured impedance offset exceeds this threshold, it is judged as a defect.

[0092] The physical basis for the judgment logic is as follows: voids or sidewall fractures reduce the effective cross-sectional area of ​​the conductor. According to transmission line theory, inductance per unit length is inversely proportional to the cross-sectional area of ​​the conductor, thus increasing the inductance. Simultaneously, impedance is directly proportional to inductance and inversely proportional to capacitance; an increase in inductance leads to an increase in impedance. The system, considering the characteristic that the polarity of the impedance offset is positive (i.e., impedance increases), classifies this as the presence of a filling void or fracture within the through-silicon via (TSV).

[0093] Step S503: Determine if there is a cold solder joint or poor wetting at the micro-bump; within the time window corresponding to the micro-bump connection, the system detects the slope characteristics of the impedance offset curve. If an abnormal increase in the slope of the impedance curve is observed within this window, and the impedance peak shows a sharp inductive abrupt change, the system determines that there is a cold solder joint or poor wetting at the micro-bump.

[0094] The criterion for determining an abnormally large slope is as follows: calculate the maximum slope value of the impedance offset curve within the specified time window. If this slope value exceeds a preset slope threshold, it is considered abnormal. The preset slope threshold is set based on the slope variation range of the impedance fingerprint interval at that location in the standard model, and is taken as twice the maximum slope value within the fingerprint interval.

[0095] The physical basis for the judgment logic is as follows: poor soldering or inadequate wetting leads to tiny physical gaps on the contact surface. Under the action of an ultrafast step signal, these gaps create a significant inductive effect, manifested as a sharp abrupt change in the impedance curve. Such defects may appear as conduction under DC or low-frequency testing, but will cause obvious impedance discontinuities under high-frequency excitation.

[0096] Step S504: Calculate the physical location of the defect; for feature points identified as defects in steps S502 or S503, the system further calculates their precise physical location. The physical location determination utilizes the time-of-flight positioning formula from the time-domain reflectometry principle:

[0097] Where L represents the physical distance between the defect and the test pad, in meters; v represents the speed of signal propagation in the medium, in meters per second, which is directly calculated and set in step S306; Δt represents the time difference of the reflected wave on the time axis, in seconds.

[0098] The time difference Δt is obtained as follows: from the time domain impedance distribution curve after alignment in step S401, read the propagation time value corresponding to the defect feature point, subtract the starting time value at the test pad, and the resulting time difference is Δt.

[0099] For signals in multi-layer stacked structures that need to penetrate different media, the system uses the equivalent dielectric constant method to calibrate the propagation speed. The specific calibration method has been described in detail in step S306 and will not be repeated here.

[0100] Step S505: Classify the defect to a specific physical level; The system automatically classifies the defect to the corresponding physical level based on the physical distance L calculated in step S504 and the spatial location range of each physical level defined in the standard model in step S1.

[0101] The classification logic is as follows: if the L value falls within the thickness range of the redistribution layer of the adapter board, the defect is determined to be located in the redistribution layer of the adapter board; if the L value falls within the depth range of the through-silicon via (TSV) segment, the defect is determined to be located in the TSV segment; if the L value falls within the height range of the first layer microbump, the defect is determined to be located in the first layer memory chip microbump; and so on. For multi-layer stacked structures, the system compares the spatial position range of each subsequent layer in turn until the exact layer where the defect is located is determined.

[0102] In summary, step S5 completes the analysis of impedance offset characteristics, the determination of defect types, the precise calculation of physical locations, and the classification of defect levels. This determination transforms the existence, type, severity, and spatial location of defects into quantifiable output information, providing an intuitive basis for packaging quality assessment.

[0103] Example 2 This embodiment describes in detail the implementation process of the method for a high-density 3D heterogeneous integrated structure with four layers of memory chip stack. This structure includes a more complex through-silicon via network and a microbump array with smaller spacing.

[0104] In step S1, when constructing the characteristic impedance standard model, the increased vertical path length due to the four-layer stacking is taken into account. The modeling process parameterizes the internal interconnect paths of each memory chip layer hierarchically, that is, it establishes separate interconnect structure models for the first to fourth layers of memory chips. Distributed parameters are extracted independently for each model according to the method in step S101. Then, the models are cascaded to form a complete vertical interconnect channel model. The thickness of the interposer layer is set to 80 micrometers, the diameter of the through-silicon via (TSV) is set to 8 micrometers, and the aspect ratio reaches 10:1. The TSV is filled with conductive copper, and a silicon dioxide insulating layer with a thickness of 200 to 500 nanometers is deposited on the sidewalls. An interconnect load model between each layer of memory chips is added to the model. This load model adopts a lumped π-type circuit structure, including equivalent resistance, equivalent inductance, and equivalent capacitance. Its parameter values ​​are extracted through electromagnetic simulation to accurately simulate the impedance continuity change of signals when penetrating the multilayer structure.

[0105] In step S2, the step rise time of the injected signal is shortened to 15 picoseconds. To accommodate the higher density of test pad layouts, a vertical pin array is used for the test probes. The probe contact force is closed-loop regulated and controlled between 3 and 5 grams by the servo control system of the probe station to ensure penetration of the surface oxide layer without damaging the ultrathin hard gold plating. The upper limit of the injected signal's spectrum is increased to 40 GHz, which is determined based on the signal rise time using the formula... The calculation shows that, among which With a rise time of 15 picoseconds, the calculated frequency is approximately 23.3 GHz. However, considering the contribution of higher harmonics, 40 GHz is taken as the upper limit of the effective spectrum.

[0106] In step S3, to address the complex reflection environment caused by multi-layer stacking, a high-order de-embedding algorithm is employed in the real-time acquisition of reflected waveforms. This algorithm is based on a 16-term error model from vector network analyzer calibration technology. In addition to open-circuit, short-circuit, and load standards, a through-circuit standard is added. A complete error network equation is constructed through four calibration measurements, thereby more accurately removing the multiple reflection contributions from probes, cables, and test fixtures. Since multiple reflection interfaces exist in the four-layer stacked structure, broadband modeling for the skin effect is introduced when calculating the reflection coefficient. This involves adding a series resistance term proportional to the square root of the frequency to the transmission line model to correct the nonlinear attenuation caused by high-frequency signals propagating through the multi-layer conductive substrate. The time resolution of the sampling system is locked at 80 femtoseconds.

[0107] In step S4, the differential comparison process performs nonlinear mapping on the longitudinal position of the multilayer structure. Since the signal velocity varies when passing through silicon layers with different doping concentrations and microbumps of different materials, the system dynamically adjusts the conversion coefficient from the time axis to the spatial axis using a piecewise mapping method based on the dielectric constant gradient of each layer. That is, a propagation velocity value is independently set for each layer, with constant velocity processing within each layer, and the time-space coordinate connection is adjusted based on the dielectric constant ratio of adjacent layers during inter-layer conversion. The extracted impedance offset is further combined with frequency domain analysis. By performing a Fast Fourier Transform on the reflected signal, the amplitude characteristics of the return loss at 10GHz, 20GHz, and 30GHz are analyzed, and the return loss values ​​at these three frequencies are compared with the simulated values ​​of the corresponding frequencies in the standard model. If the deviation at any frequency exceeds a preset frequency domain threshold, a defect is identified.

[0108] In step S5, the judgment logic adds the identification of "soft failure" defects. When the impedance offset is detected to show a slow upward trend and the slope change rate is less than a preset minimum value, the system determines it to be uniform thinning or oxidation diffusion of the copper layer on the inner wall of the through-silicon via. The preset minimum value is set according to the minimum slope change rate within the impedance fingerprint interval at that location in the standard model, usually 0.5 times the minimum slope change rate within the fingerprint interval. The accuracy of physical location positioning is improved to ±3 micrometers, which is ensured by setting the time resolution to 80 femtoseconds in step S301 and the precise calibration of the propagation speed in step S306. For a 4-layer stacked structure, the system uses time window gating technology to divide the reflected signal into 4 independent time periods, corresponding to the vertical interconnect areas of the 4 layers of memory chips. The time window gating technology is specifically implemented as follows: within the time window defined in step S501, a time window boundary is set independently for each layer, and only the reflected signal falling within the window is used for defect judgment of that layer, while the signal outside the window is filtered out.

[0109] The system-generated quality report further integrates failure trend analysis functionality. By collecting impedance data from 1000 consecutive packages, the arithmetic mean of the impedance at each level and its drift curve with package number are calculated. The drift curve is compared with process control limits, and an early warning signal is generated when the mean drift exceeds the process control limit. This early warning signal provides parameter feedback to the upstream chemical mechanical planarization (CMP) and deep reactive ion etching (DRIE) processes. Specifically, the feedback method involves outputting an empirical correlation model between the drift amount and the process parameter adjustment amount to the manufacturing execution system (MES), which then automatically adjusts the parameter settings for CMP and DES processes.

[0110] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects.

[0111] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for 3D heterogeneous integration and packaging of memory chips based on an interposer board interposer layer, characterized in that, A characteristic impedance standard model corresponding to the physical structure of the package under test is constructed. The characteristic impedance standard model includes the ideal impedance fingerprint under defect-free conditions, as well as the impedance fingerprint range based on Monte Carlo simulation that covers normal process fluctuations. A step signal with a preset rise time, between 10 picoseconds and 30 picoseconds, is injected into the internal interconnect network of the package under test through the test pads on the adapter board. The reflected waveforms generated by impedance discontinuities when a step signal propagates in the interconnection path are acquired in real time. Parasitic parameters of the external path are eliminated by de-embedding processing, and multiple reflection interferences are eliminated step by step by the layer-stripping algorithm. The processed reflected waveforms are then converted into time-domain impedance distribution curves. The impedance distribution curve in the time domain is compared with the standard model of characteristic impedance to extract the impedance offset that reflects interconnect defects. Based on the polarity and slope characteristics of the impedance offset within the time window of the corresponding physical level, the defect type and physical location are determined.

2. The 3D heterogeneous integration packaging method for memory chips based on an interposer interposer layer according to claim 1, characterized in that, The rise time of the step signal is determined based on the feature size of the interconnect structure under test. For interconnect structures with feature sizes on the order of 10 micrometers, a rise time of 20 picoseconds is selected. The amplitude of the step signal is set to 10% to 20% of the breakdown voltage of the insulating medium in the interconnect structure, and the stability of the signal amplitude is maintained within the preset amplitude fluctuation range through the automatic level control function of the time domain reflectometer. A high-frequency probe with a bandwidth of no less than 70 GHz is used to contact the test pad. The surface of the test pad is formed with a hard gold layer with a thickness of 0.5 micrometers to 2 micrometers through an electroplating process, so that the contact resistance change rate is less than a preset change rate threshold after multiple contact tests.

3. The 3D heterogeneous integration packaging method for memory chips based on an interposer interposer layer according to claim 1, characterized in that, The reflected voltage signal is captured by using equivalent sampling technology with a preset time resolution of 100 femtoseconds to 500 femtoseconds; The de-embedding process is based on the pre-measured scattering parameters of the open-circuit standard, short-circuit standard, and load standard, and the contributions of the probe and cable are removed from the total reflection response through vector operations. The layer-stripping algorithm starts from the first impedance discontinuity closest to the test probe, calculates its impedance value based on the reflection coefficient of that point, and removes the reflection effect generated by that point from the total reflection response. It then proceeds step by step to the deeper points, eventually obtaining the true impedance distribution at each location along the entire propagation path.

4. The 3D heterogeneous integration packaging method for memory chips based on an interposer interposer layer according to claim 1, characterized in that, A physical parameterized model of the interconnect structure is established, and the physical properties of the redistribution layer of the adapter board, through-silicon vias and microbump arrays are digitally modeled. The modeling parameters include geometric dimensions and material properties. Electromagnetic simulation is performed to obtain impedance fingerprints under defect-free conditions. A step excitation signal with a rise time of 10 picoseconds is applied to the input of the model. Monitoring points are set at equal intervals along the signal propagation path to record transient voltage and current responses. The impedance values ​​at each position along the signal propagation path are obtained and arranged in order to form a standard impedance fingerprint. An impedance fingerprint range covering process fluctuations is defined, and key geometric and material parameters are defined as variables that follow a specific statistical distribution. Multiple electromagnetic simulations are run to obtain a set of impedance fingerprint curves. The impedance values ​​at each location in the set are statistically analyzed, and the upper and lower boundaries of the impedance fluctuation at that location are determined according to the preset confidence level. The upper and lower boundaries at all locations are connected to form the upper and lower envelopes of the impedance fingerprint range.

5. The 3D heterogeneous integration packaging method for memory chips based on an interposer interposer layer according to claim 1, characterized in that, Before performing a differential comparison between the time-domain impedance distribution curve and the characteristic impedance standard model, the method further includes: using an autocorrelation alignment algorithm, with the characteristic impedance standard model as a reference template, calculating the cross-correlation coefficient between the time-domain impedance distribution curve and the characteristic impedance standard model, searching for the time offset that maximizes the cross-correlation coefficient, and shifting the time-domain impedance distribution curve as a whole by the offset to ensure that the zero points of the two completely coincide on the time axis. To compensate for frequency-dependent losses during signal propagation, the real-time curve is converted to the frequency domain using a fast Fourier transform, and each frequency component is multiplied by the corresponding gain coefficient to compensate for the attenuation effect of conductor loss and dielectric loss on the impedance curve amplitude. Differential comparison introduces a dynamic threshold mechanism, which sets different judgment thresholds for interconnect structures at different locations based on the sensitivity of the structure to signal integrity. Specifically, for the core data bus path, the impedance offset threshold is set to a first preset offset threshold, and for the power or ground path, the impedance offset threshold is set to a second preset offset threshold that is greater than the first preset offset threshold.

6. The 3D heterogeneous integration packaging method for memory chips based on an interposer interposer layer according to claim 1, characterized in that, If, within the corresponding time window of the through-silicon via, the impedance offset shows an increasing trend and the peak value of the offset exceeds the third preset offset threshold, it is determined that there is an inductive deviation defect at that location. The inductive deviation defect corresponds to a void or break inside the through-silicon via. If, within the time window at the corresponding microbump connection, the maximum slope value of the impedance offset curve exceeds the preset slope threshold and the impedance peak shows a sharp inductive abrupt change, then the microbump is determined to have a defect of poor soldering or poor wetting. The third preset offset threshold is set to 1.2 to 1.5 times the difference between the upper limit of the impedance fingerprint interval at that location in the standard model and the standard ideal impedance value, and the preset slope threshold is taken as twice the maximum slope value within the impedance fingerprint interval at that location in the standard model.

7. The 3D heterogeneous integration packaging method for memory chips based on an interposer interposer layer according to claim 1, characterized in that, The physical location is determined by the time-of-flight positioning formula in the time-domain reflection principle. The formula states that the physical distance between the defect and the test pad is equal to the speed of signal propagation in the medium multiplied by half the time difference of the reflected wave on the time axis. For signals in multilayer stacked structures that need to penetrate different media, the equivalent dielectric constant method is used to calibrate the propagation speed; Based on the calculated physical distance and the spatial location range of each physical level defined in the standard model, defects are automatically classified into the corresponding physical level. The physical levels include the redistribution layer of the adapter board, the through-silicon via segment, and the microbumps of each layer of memory chips.

8. The 3D heterogeneous integration packaging method for memory chips based on an interposer interposer layer according to claim 1, characterized in that, For a multi-layer memory chip stacking structure, the internal interconnection path of each layer of memory chip is parameterized layer by layer, and the interconnection structure model of each layer is established. Then, they are connected in a cascading manner to form a complete vertical interconnection channel model. To address the complex reflection environment caused by multilayer stacking, a high-order de-embedding algorithm based on a 16-term error model is adopted. When calculating the reflection coefficient, broadband modeling for the skin effect is introduced, and a series resistance term proportional to the square root of the frequency is added to the transmission line model to correct the nonlinear attenuation caused by the propagation of high-frequency signals in multilayer conductive substrates. By using time window gating technology, the reflected signal is divided into multiple independent time periods, each corresponding to the vertical interconnect area of ​​each layer of memory chip. Only the reflected signal falling into the corresponding window is used for defect determination of that layer.

9. The 3D heterogeneous integration packaging method for memory chips based on an interposer interposer layer according to claim 1, characterized in that, When the impedance offset is detected to show a slow upward trend and the slope change rate is less than the preset minimum value, the system determines it to be a uniform thinning or oxidation diffusion of the copper layer on the inner wall of the through silicon via. The preset minimum value is set according to 0.5 times the minimum slope change rate in the impedance fingerprint range at that position in the standard model. By collecting impedance data from multiple consecutive packages, the arithmetic mean of the impedance at each level and its drift curve with the package number are calculated. When the mean drift exceeds the process control limit, an early warning signal is generated, providing parameter feedback for upstream chemical mechanical planarization and deep reactive ion etching processes.

10. A 3D heterogeneous integrated packaging system for memory chips based on an interposer board interposer layer, characterized in that, include: The model building module is used to build a characteristic impedance standard model corresponding to the physical structure of the package under test. The characteristic impedance standard model includes the ideal impedance fingerprint under defect-free conditions, as well as the impedance fingerprint range based on Monte Carlo simulation that covers normal process fluctuations. The signal injection module is used to inject a step signal with a preset rise time into the internal interconnect network of the package under test through the test pads on the adapter board. The preset rise time is between 10 picoseconds and 30 picoseconds. The curve generation module is used to collect the reflected waveforms generated by impedance discontinuities when a step signal propagates in the interconnection path in real time. It eliminates parasitic parameters of the external path through de-embedding processing and uses a layer-stripping algorithm to eliminate multiple reflection interferences step by step, and converts the processed reflected waveforms into time-domain impedance distribution curves. The differential comparison module is used to perform differential comparison between the time-domain impedance distribution curve and the characteristic impedance standard model to extract the impedance offset that reflects interconnect defects. The defect determination module is used to determine the defect type and physical location based on the polarity and slope characteristics of the impedance offset within the time window of the corresponding physical level.

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