A semiconductor device having spaced apart cross-over air gaps and a method of manufacturing the same

Abstract

The application relates to the technical field of gate structure design, and discloses a semiconductor device containing interval-crossing air gaps and a manufacturing method thereof. In the semiconductor device, the interval-crossing air gaps comprise a plurality of interval-crossing first air gaps and second air gaps, the air gap between the gate and the side wall is no longer a complete'slit', but is composed of a plurality of cross-symmetrical air cavities, and the structure is more stable. Moreover, the opening directions of the first groove and the second groove are opposite, so that the first groove and the second groove can be alternately and symmetrically arranged, so that the cavities are more compact, and the effect of reducing the parasitic capacitance by using the air side wall is improved. Finally, the air cavities in the application are formed through cooperation of the dielectric layer and the groove structure, as long as the formation of the dielectric layer is accurately controlled, the success rate and controllability of the air cavity manufacturing are higher, and the process compatibility is good.

Description

Technical Field

[0001] This invention relates to the field of gate structure design technology, and in particular to a semiconductor device containing interleaved air gaps and a method for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit industry has experienced sustained high-speed development. With the continuous advancement of technology nodes, the feature size of devices has entered 10nm and even more advanced technology nodes. In this process of continuous miniaturization, the gate structure and its surrounding components face increasingly severe parasitic capacitance challenges. As the physical distance between the gate and the source / drain regions continues to shorten, the stray capacitance between the gate and source / drain contacts increases significantly, leading to reduced device switching speed, increased switching power consumption, and deteriorated coupling noise, severely restricting further improvements in device performance.

[0003] In traditional CMOS processes, gate spacers are typically made of materials such as silicon dioxide (SiO2, with a relative permittivity of approximately 3.9) or silicon nitride (SiN, with a relative permittivity of approximately 7.0). Their functions include defining the source / drain injection regions, protecting the gate structure, and isolating the gate from source / drain contacts in subsequent processes. However, as device dimensions continue to shrink, the parasitic capacitance of the gate sidewall region accounts for a significantly larger proportion of the total device capacitance. Especially at advanced technology nodes, sidewall parasitic capacitance has become a key factor limiting high-frequency performance and power consumption optimization.

[0004] To address these challenges, existing technologies employ low-k dielectric materials to replace traditional SiO2 or SiN sidewall materials. For example, low-k dielectric materials with a dielectric constant below 4 are used as sidewall insulators to reduce parasitic coupling between the gate and source / drain regions. However, the dielectric constant of low-k dielectric materials is typically above 2.5, and as devices continue to shrink to the nanoscale, the distance between the gate and source / drain contacts further decreases. Even with low-k dielectric materials, the reduction in parasitic capacitance is still insufficient to meet the performance requirements of advanced nodes.

[0005] Air, with a relative permittivity of approximately 1, is one of the lowest natural dielectric materials. Introducing air into the gate sidewall region can theoretically achieve the maximum reduction in parasitic capacitance. Studies have shown that air sidewall structures can reduce transistor-level overlap capacitance by 15%–25% and ring oscillator-level effective capacitance by 10%–15%. In FinFET devices, air sidewalls have also been proven to effectively reduce overall device capacitance, thereby improving high-frequency performance. In recent years, academia and industry have proposed various fabrication schemes for air sidewall (air spacer or air-gap spacer) structures, such as using carbon-based materials as sacrificial layers to form encapsulated air sidewalls, or introducing air gaps in the gate sidewall.

[0006] However, existing air sidewall technology still faces several prominent challenges in integration and application. First, the formation of air sidewalls often relies on the deposition and selective removal of sacrificial layers, a process involving multiple additional steps that increases process complexity and manufacturing costs, and places high demands on process compatibility. Second, air sidewall structures exhibit poor mechanical stability, making them prone to collapse or deformation during subsequent processes such as interlayer dielectric deposition and chemical mechanical polishing, affecting device yield and reliability.

[0007] Therefore, developing a novel gate sidewall structure that is structurally stable, has good process compatibility, and can reduce parasitic capacitance has become an important technical issue in the current field of high-density, high-performance integrated circuit manufacturing. Summary of the Invention

[0008] This invention discloses a semiconductor device with interleaved air gaps and a method for manufacturing the same, which provides a novel gate sidewall structure that is structurally stable, has good process compatibility, and can reduce parasitic capacitance.

[0009] The first aspect of this invention discloses a semiconductor device having interlaced air gaps, the semiconductor device comprising: A gate and sidewalls on both sides of the gate, wherein a spaced, intersecting air gap is formed between the gate and either sidewall; The intersecting air gap includes multiple intersecting first air gaps and second air gaps; The first air gap includes a first groove embedded in the gate and a first dielectric layer formed on the first groove, wherein the first dielectric layer and the first groove form a cavity; The second air gap includes a second groove embedded in the sidewall and a second medium layer formed on the second groove, wherein the second medium layer and the second groove form a cavity.

[0010] As an optional implementation, in a first aspect of the present invention, the gate and the sidewall are located on a substrate, and a high dielectric constant layer and a third dielectric layer are further formed between the gate and the substrate, wherein the high dielectric constant layer is closer to the substrate and the third dielectric layer is closer to the sidewall. The third dielectric layer and the second dielectric layer are made of the same material, so that the third dielectric layer and the second dielectric layer encapsulate the gate.

[0011] As an optional implementation, in a first aspect of the present invention, the first groove and the second groove are integrally formed so that a plurality of intersecting first grooves and second grooves form an integral support and protective layer, the support and protective layer being located between the first dielectric layer and the second dielectric layer. The first dielectric layer is located between the sidewall and the support protective layer, and the second dielectric layer is located between the gate and the support protective layer.

[0012] As an optional implementation, in a first aspect of the invention, the first groove and the second groove are groove-shaped oxide layers, the thickness of which is 20. -30 .

[0013] As an optional implementation, in a first aspect of the present invention, the first dielectric layer is a silicon nitride layer, and the sidewall includes a multilayer dielectric structure located on the silicon nitride layer, the multilayer dielectric structure being composed of alternately stacked silicon nitride layers and silicon oxide layers.

[0014] As an optional implementation, in a first aspect of the present invention, the second dielectric layer is a titanium nitride layer and / or a first alloy layer, and the gate includes a second alloy layer located on the second dielectric layer.

[0015] A second aspect of the present invention discloses a method for manufacturing a semiconductor device having interleaved air gaps, the method comprising: Provide substrate; A dummy gate is formed on the substrate, the dummy gate comprising multiple first and second sacrificial layers formed sequentially and intersectingly along the substrate upwards; The first sacrificial layer is selectively etched to a predetermined depth along both sides parallel to the substrate direction, so that a groove is formed on both sides of each first sacrificial layer on the dummy gate. A support and protective layer is formed on the dummy gate, such that a plurality of first grooves are formed on the outer side of the support and protective layer; A first dielectric layer and a sidewall are sequentially formed on the outside of the support protective layer, so that the first dielectric layer forms a cavity with the first groove. Remove the dummy gate to form a plurality of second grooves on the inner side of the support protective layer, the second grooves being distributed alternately with the first grooves at intervals; A second dielectric layer and a gate are sequentially formed inside the support protective layer, so that the second dielectric layer forms a cavity in the second groove.

[0016] As an optional implementation, in a second aspect of the invention, forming a dummy gate on the substrate includes: Multiple first and second sacrificial layers are sequentially and intermittently formed on the substrate; The dummy gate position is defined on the multilayer first and second sacrificial layers formed by the spaced cross; The non-dummy gate location region is etched using the substrate as an etch stop layer to obtain the dummy gate.

[0017] As an optional implementation, in a second aspect of the invention, forming a support protective layer on the dummy gate includes: A support protective layer is deposited on a substrate in which a dummy gate is formed, and the support protective layer on the top of the dummy gate and on the substrate is removed so that a support protective layer is formed on the side of the dummy gate, and a plurality of first grooves are formed on the outside of the support protective layer.

[0018] As an optional implementation, in a second aspect of the invention, a first dielectric layer and a sidewall are sequentially formed outside the supporting protective layer, comprising: A first dielectric layer is formed on the outside of the support and protective layer; Perform at least one cycle process on the first dielectric layer, the cycle process comprising: (i) Deposit a silicon nitride supplementary layer; (ii) Deposit a silicon oxide protective layer on the silicon nitride supplementary layer; (iii) Etching the silicon oxide protective layer and the underlying silicon nitride supplementary layer to reduce the sidewall width or form a stepped profile; Repeat the loop process until the target sidewall morphology is obtained.

[0019] As an optional implementation, in a second aspect of the present invention, the substrate is an active region substrate; the formation of the dummy gate on the substrate specifically includes: A high dielectric constant layer and a third sacrificial layer are sequentially formed on the substrate; Multiple first and second sacrificial layers are sequentially and intersectingly formed on the third sacrificial layer; The dummy gate position is defined on the multilayer first and second sacrificial layers formed by the spaced cross; The non-dummy gate location region is etched using the substrate as an etch stop layer to obtain the dummy gate.

[0020] As an optional implementation, in a second aspect of the invention, removing the dummy gate includes: The first sacrificial layer, the second sacrificial layer, and the third sacrificial layer in the dummy gate are etched back; so that a third groove and a plurality of second grooves are formed inside the support protection layer, wherein the second groove is formed after the second sacrificial layer is removed, the third groove is formed after the third sacrificial layer is removed, the second grooves are spaced apart and intersected with the first grooves and have opposite opening directions, and the second grooves have the same opening direction as the third grooves; And, the step of sequentially forming a second dielectric layer and a gate inside the support protective layer includes: A third dielectric layer is formed on the high dielectric constant layer within the support protective layer using an atomic layer deposition process, so that the third dielectric layer completely fills the third groove; A second dielectric layer and a gate are sequentially formed inside the support and protective layer.

[0021] As an optional implementation, in a second aspect of the invention, forming a dummy gate on the substrate specifically includes: Multiple first and second sacrificial layers are sequentially and intermittently formed on the substrate; A fourth sacrificial layer is formed on the multiple first and second sacrificial layers formed by the intersecting intervals; A pseudo-gate location is defined on the fourth sacrificial layer; The non-dummy gate location region is etched using the substrate as an etch stop layer to obtain the dummy gate.

[0022] As an optional implementation, in a second aspect of the invention, removing the dummy gate includes: All the first sacrificial layers, the second sacrificial layer, and the fourth sacrificial layer in the dummy gate are etched back to form a target gate space and a top gate space within the support protection layer. The target gate space is the space formed after removing the first sacrificial layer and the second sacrificial layer, and the top gate space is the space formed after removing the fourth sacrificial layer. And, the step of sequentially forming a second dielectric layer and a gate inside the support protective layer includes: A second dielectric layer and a gate material are sequentially formed inside the support protective layer. The gate material includes a target gate located in the target gate space and a top gate located in the top gate space. The top gate is ground flat and removed, leaving the target gate.

[0023] As an optional implementation, in a second aspect of the invention, the first sacrificial layer is a silicon germanium layer, the second sacrificial layer is a polycrystalline silicon layer, and the supporting protective layer is an oxide layer with a thickness of 20 mm. -30 The first dielectric layer is a silicon nitride layer, the second dielectric layer is a titanium nitride layer and / or a first alloy layer, and the gate is a metal gate.

[0024] Compared with the prior art, the present invention can produce the following unexpected technical effects: In the semiconductor device of this invention, a spaced-apart air gap is formed between the gate and any sidewall. This spaced-apart air gap includes multiple spaced-apart first air gaps and second air gaps. The first air gap includes a first groove embedded in the gate and a first dielectric layer formed on the first groove. The second air gap includes a second groove embedded in the sidewall and a second dielectric layer formed on the second groove. A cavity is formed between the second dielectric layer and the second groove, and a cavity is formed between the first dielectric layer and the first groove. In this invention, the air gap between the gate and the sidewall is no longer a complete "slit," but rather composed of multiple symmetrically spaced air cavities, resulting in a more stable structure. Furthermore, the opening directions of the first and second grooves are opposite, allowing them to be arranged alternately and symmetrically, thus making the cavities more compact and improving the effect of reducing parasitic capacitance using the air sidewalls. Finally, the air cavities in this invention are formed through the cooperation of the dielectric layer and the groove structure. As long as the formation of the dielectric layer is accurately controlled, the success rate and controllability of air cavity fabrication are high, and the process compatibility is good. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a semiconductor device structure containing intersecting air gaps, as disclosed in an embodiment of the present invention. Figure 2 This is a schematic diagram of another semiconductor device structure containing intersecting air gaps disclosed in an embodiment of the present invention; Figure 3 This is a state diagram of the formation of a dummy gate on the substrate; Figure 4 This is a schematic diagram showing the formation of grooves on both sides of each first sacrificial layer; Figure 5 This is a schematic diagram showing the formation of a support and protective layer on the dummy gate. Figure 6 This is a schematic diagram showing the formation of the first dielectric layer on the outside of the supporting protective layer; Figure 7 This is a diagram showing the state after the first medium layer and sidewalls are formed sequentially on the outside of the supporting protective layer; Figure 8 This is a schematic diagram showing the state after the dummy gate has been removed; Figure 9 It is a state diagram that defines the dummy gate positions on the first and second sacrificial layers; Figure 10This is a state diagram showing the deposition of a support protective layer on a substrate including the dummy gate; Figure 11 This is a state diagram showing the sequential formation of a high dielectric constant layer and a third sacrificial layer on a substrate. Figure 12 This is a state diagram showing multiple layers of first and second sacrificial layers formed sequentially and intersectingly on the third sacrificial layer. Figure 13 This is a state diagram of etching non-dummy gate locations using the substrate as the etch stop layer; Figure 14 This is a pseudo-gate state diagram obtained after selectively etching the first sacrificial layer; Figure 15 This is another schematic diagram showing the state after removing the dummy gate; Figure 16 This is a schematic diagram showing the state in which the second dielectric layer and the gate are sequentially formed inside the support protective layer; Figure 17 This is a schematic diagram showing the deposition of the first dielectric layer across the entire device surface. Figure 18 This is a schematic diagram of another state in which the first dielectric layer is deposited on the entire surface of the device; Figure 19 This is a schematic diagram showing the state of the first dielectric layer on both sides of the gate after the first dielectric layer has been modified.

[0027] In the figure: 110 - gate; 210 - first dielectric layer; 230 - support and protection layer; 220 - second dielectric layer; 200 - spaced cross air gap; 310 - sidewall; 410 - first sacrificial layer; 420 - second sacrificial layer; 430 - high dielectric constant layer; 440 - third sacrificial layer; 450 - fourth sacrificial layer. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or end that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or ends.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] This invention discloses a semiconductor device with interlaced air gaps and a method for manufacturing the same, providing a novel gate sidewall structure that is structurally stable, has good process compatibility, and reduces parasitic capacitance. Detailed descriptions follow.

[0032] Example 1 In existing technologies, the air gap between the gate and sidewalls relies on the deposition and selective removal of the sacrificial layer, such as the air gap obtained after removing the insulating layer in Chinese patent application publication CN115394846A. However, constructing an integrated air gap on a very small gate size results in poor structural stability. To address this, the present invention creatively transforms the originally integrated trench-shaped air gap into a spaced-apart air gap, and based on this, proposes a semiconductor device containing spaced-apart air gaps, such as... Figure 1 As shown, the semiconductor device includes at least: The gate 110 and the sidewalls 310 on both sides of the gate 110 are provided, wherein a spaced cross air gap 200 is formed between the gate 110 and any sidewall 310. The gate 110 can be formed on a substrate, and the gate 110 and the substrate constitute a corresponding semiconductor functional device, such as a radio frequency device, a high-voltage integrated circuit, a low-power logic circuit, a high-frequency communication device, an optoelectronic integrated device, a MOSFET, etc. For example, for a common MOSFET, the gate 110 can be polysilicon formed on the substrate.

[0033] The interlaced air gap 200 includes multiple interlaced first air gaps and second air gaps; such as Figure 1 The first and second air gaps in the right-side gate structure, Figure 1The markings indicate the first and second air gaps on different side walls. For the intersecting air gaps 200 on one side of the same side wall, there are multiple intersecting first and second air gaps.

[0034] in: The first air gap includes a first groove embedded in the gate 110 and a first dielectric layer 210 formed on the first groove, wherein the first dielectric layer 210 and the first groove form a cavity; The second air gap includes a second groove embedded in the sidewall 310 and a second medium layer 220 formed on the second groove, wherein the second medium layer 220 and the second groove form a cavity.

[0035] The term "embedded" here means that the first groove is a structure that contacts the gate 110 and partially penetrates the gate 110, or the second groove is a structure that contacts the sidewall 310 and partially penetrates the sidewall 310. The material of the groove is not limited.

[0036] Forming cavities within the dielectric layer and the groove can be achieved by first forming the groove, and then depositing the dielectric layer within it. Since the groove is an open shape with a certain depth, the deposition rate can be controlled during dielectric layer deposition so that the deposition is completed before the groove is completely filled. For example, using a rapid deposition method, the groove, due to its depth, will form cavities during rapid deposition. Figure 1 or Figure 2 A dielectric layer with a certain curved surface structure is formed at the groove, and a semi-circular groove is formed between the dielectric layer and the groove. In this embodiment of the invention, the first dielectric layer 210 and the second dielectric layer 220 are used to cooperate with the groove to form a cavity, and the materials of the two are not limited.

[0037] In this embodiment of the invention, the gate 110 is adjacent to the sidewall 310. The first groove is embedded in the gate 110 and the second groove is embedded in the sidewall 310, which means that the opening directions of the first groove and the second groove are opposite. The unexpected technical effect of this design is that the first groove and the second groove can be arranged alternately and symmetrically, thereby making the cavity more compact and improving the effect of reducing parasitic capacitance by utilizing the air sidewall; and the stability of the alternating symmetrical groove structure is greatly improved.

[0038] In this embodiment of the invention, the intersecting air gap 200 includes a plurality of intersecting first air gaps and second air gaps. The number of first air gaps and second air gaps in the intersecting air gap 200 is not limited. For example, the intersecting air gap 200 can be arranged from bottom to top as first air gap-second air gap-first air gap-second air gap, in which case the intersecting air gap 200 includes 2 first air gaps and 2 second air gaps. Alternatively, it can be as follows: Figure 1 and Figure 2 In the middle, the intersecting air gap 200 has two first air gaps and one second air gap, or one first air gap and two second air gaps; in practical applications, its number and arrangement density can be flexibly adjusted according to the process accuracy and electrical performance requirements to achieve the optimal balance between parasitic capacitance suppression and structural reliability.

[0039] In this embodiment of the invention, the type and material of the substrate and sidewall 310 can be designed according to the actual semiconductor device process requirements. The materials of the first groove, the second groove, the first dielectric layer 210, and the second dielectric layer 220 can also be selected by those skilled in the art according to the actual process requirements.

[0040] Compared with the prior art, the embodiments of the present invention can produce the following unexpected technical effects: In the semiconductor device of this embodiment, a spaced-apart air gap 200 is formed between the gate 110 and any sidewall 310. The spaced-apart air gap 200 includes a plurality of spaced-apart first air gaps and second air gaps. The first air gap includes a first groove embedded in the gate 110 and a first dielectric layer 210 formed on the first groove. The second air gap includes a second groove embedded in the sidewall 310 and a second dielectric layer 220 formed on the second groove. A cavity is formed between the second dielectric layer 220 and the second groove, and a cavity is formed between the first dielectric layer 210 and the first groove. In this embodiment, the air gap between the gate 110 and the sidewall 310 is no longer a complete "gap," but is composed of multiple symmetrically arranged air cavities, resulting in a more stable structure. Furthermore, the opening directions of the first and second grooves are opposite, allowing the first and second grooves to be arranged alternately and symmetrically, thereby making the cavities more compact and improving the effect of reducing parasitic capacitance using the air sidewalls. Finally, in the embodiments of the present invention, the air cavity is formed by the combination of a dielectric layer and a groove structure. As long as the formation of the dielectric layer is accurately controlled, the success rate and controllability of the air cavity fabrication are very high, and the process compatibility is good.

[0041] It is particularly important to note that the interlaced air gaps proposed in this embodiment of the invention differ from the air gaps based on stacked layers in the prior art (e.g., the air gaps based on stacked layers disclosed in Chinese patent applications CN116959988A and CN113192888A). The interlaced air gaps proposed in this embodiment are first and second air gaps formed in closely adjacent first and second grooves, respectively. The first groove is embedded in the gate 110, and the second groove is embedded in the sidewall 310. This means that the opening directions of the first and second grooves are opposite, and the first and second grooves can be arranged alternately and symmetrically. In contrast, air gaps based on stacked layers can only form air cavities in a specific layer, and cannot achieve the tightly arranged, alternately symmetrical air cavity structure of this embodiment of the invention, nor can they be used for air isolation between the gate 110 and the sidewall 310.

[0042] like Figure 2 As shown, Figure 2 It is a MOSFET device. Figure 2 The gate 110 is located on a substrate with a trench isolation structure, and a high dielectric constant layer 430 (e.g., ...) can be disposed at the bottom of the gate 110. Figure 2 (middle purple layer) and third dielectric layer (such as Figure 2 (The red layer above the purple layer), wherein the high dielectric constant layer 430 is closer to the substrate side and the third dielectric layer is closer to the sidewall 310 side; The third dielectric layer and the second dielectric layer 220 are made of the same material, so that the third dielectric layer and the second dielectric layer 220 enclose the gate 110.

[0043] In this embodiment of the invention, the spaced-apart air gap 200 actually includes a first dielectric layer 210 contacting the sidewall 310 and a second dielectric layer 220 contacting the gate 110. In an optional embodiment, the first and second grooves are integrally formed so that the spaced-apart first and second grooves form an integral support and protective layer 230. The support and protective layer 230 is located between the first dielectric layer 210 and the second dielectric layer 220, the first dielectric layer 210 is located between the sidewall 310 and the support and protective layer 230, and the second dielectric layer 220 is located between the gate 110 and the support and protective layer 230. Since the first and second grooves are integrally formed in the form of the support and protective layer 230, its manufacturing process is more convenient; and since the support and protective layer 230 is composed of first and second grooves with different opening directions arranged in a spaced-apart pattern, its stability is better.

[0044] In yet another alternative embodiment, the first and second grooves are groove-shaped oxide layers, such as silicon oxide, with a thickness of 20 mm. -30 .

[0045] In another optional embodiment, the first dielectric layer 210 is a silicon nitride layer, and the sidewall 310 includes a multilayer dielectric structure located on the silicon nitride layer, the multilayer dielectric structure being composed of alternately stacked silicon nitride layers and silicon oxide layers. For example, the sidewall 310 formed by an etching cycle process is the aforementioned multilayer dielectric structure. Further optionally, the second dielectric layer 220 is a titanium nitride layer and / or a first alloy layer, and the gate 110 includes a second alloy layer located on the second dielectric layer 220.

[0046] In this optional embodiment, the gate 110 can be a metal gate, and the material of the gate 110 can be a metal alloy commonly used for metal gates, such as a copper-aluminum alloy. Those skilled in the art will understand that the gate 110 in this embodiment is a gate in a narrow sense; for ease of description, those skilled in the art can also refer to the entire structure, including the second dielectric and the high dielectric constant layer 430, as a gate. Further optionally, an interlayer dielectric layer can be disposed between the multiple gates 110, for example... Figure 1 and Figure 2 In the diagram, the yellow portion between multiple gates 110 is an interlayer dielectric layer, which may be selected from silicon oxide. Furthermore, in this embodiment of the invention, the first dielectric layer 210 may be made of silicon nitride.

[0047] Example 2 This invention discloses a method for manufacturing a semiconductor device containing an interlaced air gap 200, used to manufacture the semiconductor device in Embodiment 1 of this invention. Specifically, the method may include: Step 101: Provide a substrate and form a dummy gate on the substrate.

[0048] like Figure 3 As shown, Figure 3 This is a state diagram showing the formation of a dummy gate on a substrate. The dummy gate includes multiple layers of first sacrificial layers 410 and second sacrificial layers 420 formed sequentially and alternately upwards along the substrate. Specifically, the first sacrificial layers 410 and 420 can be formed alternately by alternating deposition / epitaxy growth. The first sacrificial layers 410 and 420 are made of different materials, allowing for selective removal of one sacrificial layer while retaining the other. For example, the first sacrificial layer 410 can be a germanium-silicon layer, and the second sacrificial layer 420 can be a single-crystal silicon layer.

[0049] Step 102: Selectively etch the first sacrificial layer 410 to a predetermined depth along both sides parallel to the substrate direction, so that a groove is formed on both sides of each first sacrificial layer 410 on the dummy gate.

[0050] Those skilled in the art will understand that so-called selective etching is achieved by setting the etching process (e.g., ion selection in dry etching or solution selection in wet etching) to partially remove the first sacrificial layer 410. For example, for the first sacrificial layer 410 of germanium-silicon material, peracetic acid and isopropanol are used for etching, while the second sacrificial layer 420 is unaffected during the etching process.

[0051] It should be noted that in this embodiment of the invention, the sacrificial layer is divided into a first sacrificial layer 410 and a second sacrificial layer 420 only to distinguish different sacrificial layer materials. In step 102, the second sacrificial layer 420 can also be selectively etched while the first sacrificial layer 410 remains unaffected.

[0052] In this embodiment of the invention, since the first sacrificial layer 410 and the second sacrificial layer 420 are stacked, after partially etching the first sacrificial layer 410, as... Figure 4 As shown, a groove will be formed on both sides of each first sacrificial layer 410, with the opening of the groove pointing outward from the dummy gate, which is the side where the sidewall 310 will be formed later. This groove will provide the basis for the formation of the subsequent first groove.

[0053] Step 103: A support protection layer 230 is formed on the dummy gate, so that a plurality of first grooves are formed on the outer side of the support protection layer 230.

[0054] like Figure 5 As shown, a support and protection layer 230 is formed on the dummy gate. Since grooves have been formed on both sides of each first sacrificial layer 410 on the dummy gate in step 102, multiple first grooves will be formed on the outer side of the support and protection layer 230 at the groove locations. Here, "outer side" refers to the direction extending to both sides along the gate 110. The support and protection layer 230 can be made of any material that can provide support and protection, such as an oxide layer like silicon oxide.

[0055] Step 104: A first medium layer 210 and a sidewall 310 are sequentially formed on the outside of the support protective layer 230 so that the first medium layer 210 forms a cavity with the first groove.

[0056] In this embodiment of the invention, a first dielectric layer 210 is formed on the outside of the support protective layer 230. Since the groove on the outside of the support protective layer 230 is an open shape with a certain depth, when forming the dielectric layer (e.g., by deposition), the formation speed can be controlled so that the dielectric layer is formed before it completely fills the groove. For example, when using a rapid deposition method, the groove, due to its depth, will form a cavity during rapid deposition. Figure 6In the middle, a medium layer with a certain curved surface structure is formed at the groove, and a semi-circular groove is formed between the medium layer and the groove. The first medium layer 210 is used to cooperate with the first groove to form a cavity, and its material is not limited.

[0057] like Figure 7 As shown, Figure 7 This is a state diagram after the first medium layer 210 and the sidewall 310 are formed sequentially on the outside of the support protective layer 230.

[0058] It should be noted that, in this embodiment of the invention, the morphology of the material layer finally formed on the dummy gate can be achieved by controlling the material formation rate and thickness. For example, for the support protective layer 230, a conventional deposition scheme can be used, controlling the protective layer material deposition rate to be less than a set rate threshold, and the protective layer thickness to be relatively small (10). (The following) can form a protective layer that closely adheres to the surface of the dummy gate, the morphology of which is consistent with that of the dummy gate and does not produce cavities. However, for the first dielectric layer 210, a rapid deposition scheme can be adopted, controlling the deposition rate of the dielectric layer material to be greater than a set rate threshold, and the dielectric layer thickness to be relatively large (20). -30 This allows the dielectric layer to be formed before the dielectric material has completely filled the groove, for example... Figure 6 A dielectric layer with a certain curved surface structure is formed at the groove, and a semi-circular groove is formed between the dielectric layer and the groove. For the formation of a material layer through deposition, the deposition rate can be controlled by controlling the temperature and material concentration.

[0059] Step 105: Remove the dummy gate to form a plurality of second grooves on the inner side of the support protective layer 230, with the second grooves and the first grooves being distributed at intervals and crosses.

[0060] like Figure 8 As shown, the dummy gate includes a first sacrificial layer 410 and a second sacrificial layer 420. Since there is a second groove between the first dielectric layer 210 and the cavity formed in the first groove, its air isolation effect is poor. In order to form a cavity in the second groove, the dummy gate is removed in this embodiment of the invention. Since the support protective layer 230 has been designed as a series of intersecting grooves, after the dummy gate is removed, multiple second grooves are formed inside the support protective layer 230. The second grooves are formed after the original second sacrificial layer 420 is removed.

[0061] In an optional embodiment, an interlayer dielectric layer may be formed between the plurality of gates 110 before removing the dummy gates, for example... Figure 8 The yellow portion between multiple gates 110, the interlayer dielectric layer may be selected from silicon oxide.

[0062] In yet another alternative embodiment, removing the dummy gate may include: The first sacrificial layer 410, the second sacrificial layer 420, and the third sacrificial layer 440 in the dummy gate are etched back to form a third groove and a plurality of second grooves inside the support protection layer 230. The second groove is formed after the second sacrificial layer 420 is removed, and the third groove is formed after the third sacrificial layer 440 is removed. The second grooves are spaced apart and intersected with the first grooves and have opposite opening directions. The second grooves have the same opening direction as the third grooves.

[0063] Step 106: A second dielectric layer 220 and a gate 110 are sequentially formed inside the support protective layer 230, so that the second dielectric layer 220 forms a cavity in the second groove.

[0064] like Figure 1 As shown, the principle of forming a cavity between the second dielectric layer 220 and the second groove is the same as the principle of forming a cavity between the first dielectric layer 210 and the second groove, and will not be repeated in this embodiment of the invention. For example, a third dielectric layer can be formed on the high dielectric constant layer 430 within the support protective layer 230 using an atomic layer deposition process, so that the third dielectric layer completely fills the third groove; then the second dielectric layer 220 and the gate 110 are sequentially formed inside the support protective layer 230.

[0065] Compared with the prior art, the embodiments of the present invention can produce the following unexpected technical effects: In the semiconductor device of this embodiment, a spaced-apart air gap 200 is formed between the gate 110 and any sidewall 310. The spaced-apart air gap 200 includes a plurality of spaced-apart first air gaps and second air gaps. The first air gap includes a first groove embedded in the gate 110 and a first dielectric layer 210 formed on the first groove. The second air gap includes a second groove embedded in the sidewall 310 and a second dielectric layer 220 formed on the second groove. A cavity is formed between the second dielectric layer 220 and the second groove, and a cavity is formed between the first dielectric layer 210 and the first groove. In this embodiment, the air gap between the gate 110 and the sidewall 310 is no longer a complete "gap," but is composed of a plurality of cross-symmetrical air cavities. The supporting protective layer 230 can firmly support the plurality of air cavities, making the air gap structure in this embodiment more stable. Furthermore, the opening directions of the first groove and the second groove are opposite, allowing the first groove and the second groove to be arranged alternately and symmetrically, thereby making the cavities more compact and improving the effect of reducing parasitic capacitance using the air sidewalls.

[0066] Furthermore, in this embodiment of the invention, a dummy gate 110 is constructed by stacking a first sacrificial layer 410 and a second sacrificial layer 420, and then a sacrificial layer is selectively etched to create multiple first grooves. Then, by removing the dummy gate, a second groove can also be formed inside the gate 110, making the air cavity formed in the groove more compact. Compared to the prior art where a small-sized, deep air "gap" is directly formed between the gate 110 and the sidewall 310, the semiconductor device manufacturing method proposed in this invention has a high success rate and controllability, and good process compatibility.

[0067] In an optional embodiment, forming a dummy gate on the substrate includes: Multiple first sacrificial layers 410 and second sacrificial layers 420 are sequentially and intermittently formed on the substrate; The dummy gate location is defined on the multilayer first sacrificial layer 410 and second sacrificial layer 420 formed by the spaced intersections; such as Figure 9 As shown, the dummy gate position can be defined using a corresponding photolithography template, for example, by defining the dummy gate position through photolithography; this dummy gate position is the photoresist left after development, such as... Figure 9 The yellow photoresist portion protects the underlying material from etching, thus forming a dummy gate of the same size as the photoresist.

[0068] The non-dummy gate location region is etched using the substrate as an etch stop layer to obtain the dummy gate.

[0069] Those skilled in the art will understand that, based on the substrate material or the control of the etching time, the substrate can be made into an etching stop layer, and the non-dummy gate positions on the first sacrificial layer 410 and the second sacrificial layer 420 can be etched away, leaving the first sacrificial layer 410 and the second sacrificial layer 420 to form dummy gates.

[0070] In yet another alternative embodiment, a support protective layer 230 is formed on the dummy gate, comprising: A support and protective layer 230 is deposited on the substrate where the dummy gate is formed, such as... Figure 10 As shown, the support protective layer 230 on top of the dummy gate and on the substrate is then removed, as... Figure 5 As shown, a support protection layer 230 is formed on the side of the dummy gate, and a plurality of first grooves are formed on the outer side of the support protection layer 230.

[0071] In another optional embodiment, a first dielectric layer 210 and a sidewall 310 are sequentially formed on the outside of the support protective layer 230, including: A first dielectric layer 210 is formed on the outside of the support protective layer 230; At least one cycle process is performed on the first dielectric layer 210, the cycle process comprising: (i) Deposit a silicon nitride supplementary layer; (ii) Deposit a silicon oxide protective layer on the silicon nitride supplementary layer; (iii) Etch the silicon oxide protective layer and the underlying silicon nitride supplementary layer to reduce the width of the sidewall 310 or form a stepped profile; Repeat the loop processing until the target sidewall morphology is obtained, for example... Figure 7 The morphology of sidewall 310 is shown.

[0072] In this embodiment of the invention, an etching cycle method is used to fabricate the sidewall 310. The sidewall 310 includes a multilayer dielectric structure located on a silicon nitride layer. The multilayer dielectric structure is composed of alternating stacked silicon nitride layers and silicon oxide layers.

[0073] In yet another optional embodiment, the substrate is an active region substrate; forming a dummy gate on the substrate specifically includes: A high dielectric constant layer 430 and a third sacrificial layer 440 are sequentially formed on the substrate, such as Figure 11 As shown; Multiple layers of first sacrificial layers 410 and second sacrificial layers 420 are sequentially and intersectingly formed on the third sacrificial layer 440, such as... Figure 12 As shown; The dummy gate position is defined on the multilayer first sacrificial layer 410 and second sacrificial layer 420 formed by the spaced cross; The non-dummy gate location region is etched using the substrate as an etch stop layer to obtain the dummy gate.

[0074] In this optional embodiment, a high-dielectric-constant layer 430 and a third sacrificial layer 440 are sequentially formed on the substrate. The removal of the third sacrificial layer 440 creates a space at the bottom of the dummy gate, which is used to form other dielectric layers, such as a third dielectric layer, during the subsequent formation of the gate 110. Figure 2 As shown, Figure 2 It is a MOSFET device. Figure 2 The gate 110 is located on a substrate with a trench isolation structure, and a high dielectric constant layer 430 (e.g., ...) can be disposed at the bottom of the gate 110. Figure 2 (middle purple layer) and third dielectric layer (such as Figure 2 (The red layer above the purple layer), wherein the high dielectric constant layer 430 is closer to the substrate side and the third dielectric layer is closer to the sidewall 310 side; The third dielectric layer and the second dielectric layer 220 are made of the same material, so that the third dielectric layer and the second dielectric layer 220 enclose the gate 110.

[0075] For gate 110, in the actual structure or process design, adaptive structures can be added above and below it as needed. For example, in the process flow, a top gate 110 can be designed above gate 110, and then the top gate 110 can be ground flat and removed, thereby achieving more precise control over the height of gate 110. Therefore, in another optional embodiment, a dummy gate 110 is formed on the substrate, which may specifically include: Multiple first sacrificial layers 410 and second sacrificial layers 420 are sequentially and intermittently formed on the substrate; A fourth sacrificial layer 450 is formed on the multiple layers of first sacrificial layer 410 and second sacrificial layer 420 formed by interlacing; The pseudo-gate position is defined on the fourth sacrificial layer 450; The non-dummy gate location region is etched using the substrate as an etch stop layer to obtain the dummy gate, such as... Figure 13 As shown, the fourth sacrificial layer 450 can be made of silicon nitride. The fourth sacrificial layer 450 may also include multiple sub-layers, for example, from bottom to top, a silicon oxide layer, a silicon nitride layer, and a carbon-based material. In this case, after selectively etching the first sacrificial layer 410, the resulting dummy gate is as follows... Figure 14 As shown.

[0076] Furthermore, the operation of removing the dummy gate may include: All the first sacrificial layers 410, second sacrificial layers 420, and fourth sacrificial layers 450 in the dummy gate are etched back to form a target gate space and a top gate space within the support protection layer 230. The target gate space is the space formed after removing the first sacrificial layer 410 and the second sacrificial layer 420, and the top gate space is the space formed after removing the fourth sacrificial layer 450. Figure 15 As shown, Figure 15 The space formed by two smooth inner walls above the middle gate 110 is the top gate space. The space with intersecting grooves on both sides below the top gate space is the target gate space. The gate formed in the target gate space is the final gate required, while the top gate needs to be ground flat and removed.

[0077] Therefore, a second dielectric layer 220 and a gate 110 are sequentially formed inside the support protective layer 230, including: A second dielectric layer 220 and a gate material are sequentially formed inside the support protective layer 230. The gate material includes a target gate located in the target gate space and a top gate located in the top gate space, such as... Figure 16 As shown; Remove the top gate by grinding it flat, leaving the target gate intact. Figure 2 As shown.

[0078] In this embodiment of the invention, the first sacrificial layer 410 can be a silicon germanide layer, the second sacrificial layer 420 can be a polysilicon layer, and the support and protective layer 230 can be an oxide layer with a thickness of 20 mm. -30 The first dielectric layer 210 can be a silicon nitride layer, the second dielectric layer 220 can be a titanium nitride layer and / or a first alloy layer, and the gate 110 can be a metal gate.

[0079] In an optional embodiment, the first dielectric layer 210 is formed in the following manner: like Figure 17 As shown in Figure 18, after the support and protective layer 230 is formed, a first dielectric layer 210 is formed on the entire device surface using a rapid deposition method. This prevents the first dielectric layer 210 from filling the grooves in time, creating cavities at the grooves. Subsequently, the first dielectric layer 210 is trimmed, removing the first dielectric layer 210 at the top of the gate and the substrate surface, retaining the first dielectric layers on both sides of the gate, as shown in Figure 18. Figure 19 or Figure 6 As shown.

[0080] Finally, it should be noted that the above embodiments are merely preferred embodiments of the present invention and are only used to illustrate the technical solutions of the present invention, not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device comprising interlaced air gaps, characterized in that, The semiconductor device includes: A gate and sidewalls on both sides of the gate, wherein a spaced, intersecting air gap is formed between the gate and either sidewall; The intersecting air gap includes multiple intersecting first air gaps and second air gaps; The first air gap includes a first groove embedded in the gate and a first dielectric layer formed on the first groove, wherein the first dielectric layer and the first groove form a cavity; The second air gap includes a second groove embedded in the sidewall and a second medium layer formed on the second groove, wherein the second medium layer and the second groove form a cavity; in: The first groove and the second groove are integrally formed so that the multiple intersecting first grooves and second grooves form an integral support and protective layer, which is located between the first dielectric layer and the second dielectric layer. The first dielectric layer is located between the sidewall and the support protective layer, and the second dielectric layer is located between the gate and the support protective layer.

2. The semiconductor device with interlaced air gaps according to claim 1, characterized in that, The gate and the sidewall are located on the substrate, and a high dielectric constant layer and a third dielectric layer are formed between the gate and the substrate, wherein the high dielectric constant layer is closer to the substrate and the third dielectric layer is closer to the sidewall. The third dielectric layer and the second dielectric layer are made of the same material, so that the third dielectric layer and the second dielectric layer encapsulate the gate.

3. The semiconductor device containing interlaced air gaps according to claim 1, characterized in that, The first and second grooves are groove-shaped oxide layers, and the thickness of the oxide layer is 20. -30 .

4. The semiconductor device with interlaced air gaps according to claim 1, characterized in that, The first dielectric layer is a silicon nitride layer, and the sidewall includes a multilayer dielectric structure located on the silicon nitride layer, the multilayer dielectric structure being composed of alternately stacked silicon nitride layers and silicon oxide layers.

5. The semiconductor device with interlaced air gaps according to claim 1, characterized in that, The second dielectric layer is a titanium nitride layer and / or a first alloy layer, and the gate includes a second alloy layer located on the second dielectric layer.

6. A method for manufacturing a semiconductor device containing interlaced air gaps, characterized in that, The method includes: Provide substrate; A dummy gate is formed on the substrate, the dummy gate comprising multiple first and second sacrificial layers formed sequentially and intersectingly along the substrate upwards; The first sacrificial layer is selectively etched to a predetermined depth along both sides parallel to the substrate direction, so that a groove is formed on both sides of each first sacrificial layer on the dummy gate. A support and protective layer is formed on the dummy gate, such that a plurality of first grooves are formed on the outer side of the support and protective layer; A first dielectric layer and a sidewall are sequentially formed on the outside of the support protective layer, so that the first dielectric layer forms a cavity with the first groove. Remove the dummy gate to form a plurality of second grooves on the inner side of the support protective layer, the second grooves being distributed alternately with the first grooves at intervals; A second dielectric layer and a gate are sequentially formed inside the support protective layer, so that the second dielectric layer forms a cavity in the second groove.

7. The method for manufacturing a semiconductor device with interlaced air gaps according to claim 6, characterized in that, The formation of the dummy gate on the substrate includes: Multiple first and second sacrificial layers are sequentially and intermittently formed on the substrate; The dummy gate position is defined on the multilayer first and second sacrificial layers formed by the spaced cross; The non-dummy gate location region is etched using the substrate as an etch stop layer to obtain the dummy gate.

8. The method for manufacturing a semiconductor device with interlaced air gaps according to claim 6, characterized in that, The formation of a support and protective layer on the dummy gate includes: A support protective layer is deposited on a substrate in which a dummy gate is formed, and the support protective layer on the top of the dummy gate and on the substrate is removed so that a support protective layer is formed on the side of the dummy gate, and a plurality of first grooves are formed on the outside of the support protective layer.

9. The method for manufacturing a semiconductor device with interlaced air gaps according to claim 6, characterized in that, A first dielectric layer and a sidewall are sequentially formed on the outside of the supporting protective layer, including: A first dielectric layer is formed on the outside of the support and protective layer; Perform at least one cycle process on the first dielectric layer, the cycle process comprising: (i) Deposit a silicon nitride supplementary layer; (ii) Deposit a silicon oxide protective layer on the silicon nitride supplementary layer; (iii) Etching the silicon oxide protective layer and the underlying silicon nitride supplementary layer to reduce the sidewall width or form a stepped profile; Repeat the loop process until the target sidewall morphology is obtained.

10. The method for manufacturing a semiconductor device with interlaced air gaps according to claim 7, characterized in that, The substrate is an active region substrate; the formation of the dummy gate on the substrate specifically includes: A high dielectric constant layer and a third sacrificial layer are sequentially formed on the substrate; Multiple first and second sacrificial layers are sequentially and intersectingly formed on the third sacrificial layer; The dummy gate position is defined on the multilayer first and second sacrificial layers formed by the spaced cross; The non-dummy gate location region is etched using the substrate as an etch stop layer to obtain the dummy gate.

11. The method for manufacturing a semiconductor device with interlaced air gaps according to claim 10, characterized in that, The removal of the dummy gate includes: The first sacrificial layer, the second sacrificial layer, and the third sacrificial layer in the dummy gate are etched back; so that a third groove and a plurality of second grooves are formed inside the support protection layer, wherein the second groove is formed after the second sacrificial layer is removed, the third groove is formed after the third sacrificial layer is removed, the second grooves are spaced apart and intersected with the first grooves and have opposite opening directions, and the second grooves have the same opening direction as the third grooves; And, the step of sequentially forming a second dielectric layer and a gate inside the support protective layer includes: A third dielectric layer is formed on the high dielectric constant layer within the support protective layer using an atomic layer deposition process, so that the third dielectric layer completely fills the third groove; A second dielectric layer and a gate are sequentially formed inside the support and protective layer.

12. The method for manufacturing a semiconductor device with interlaced air gaps according to claim 7, characterized in that, The formation of the dummy gate on the substrate specifically includes: Multiple first and second sacrificial layers are sequentially and intermittently formed on the substrate; A fourth sacrificial layer is formed on the multiple first and second sacrificial layers formed by the intersecting intervals; A pseudo-gate location is defined on the fourth sacrificial layer; The non-dummy gate location region is etched using the substrate as an etch stop layer to obtain the dummy gate.

13. The method for manufacturing a semiconductor device with interlaced air gaps according to claim 12, characterized in that, The removal of the dummy gate includes: All the first sacrificial layers, the second sacrificial layer, and the fourth sacrificial layer in the dummy gate are etched back to form a target gate space and a top gate space within the support protection layer. The target gate space is the space formed after removing the first sacrificial layer and the second sacrificial layer, and the top gate space is the space formed after removing the fourth sacrificial layer. And, the step of sequentially forming a second dielectric layer and a gate inside the support protective layer includes: A second dielectric layer and a gate material are sequentially formed inside the support protective layer. The gate material includes a target gate located in the target gate space and a top gate located in the top gate space. The top gate is ground flat and removed, leaving the target gate.

14. The method for manufacturing a semiconductor device with interlaced air gaps according to claim 6, characterized in that, The first sacrificial layer is a silicon germanide layer, the second sacrificial layer is a polysilicon layer, and the supporting protective layer is an oxide layer with a thickness of 20 mm. -30 The first dielectric layer is a silicon nitride layer, the second dielectric layer is a titanium nitride layer and / or a first alloy layer, and the gate is a metal gate.

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