Void-free metal growth hole filling method for glass vias and conductive interconnect substrates

Abstract

The application discloses a cavity-free metal growth hole filling method for glass through holes and a conductive interconnection substrate. The method comprises the following steps: S1, providing a glass substrate with a through hole and pretreating; S2, preparing an electrode layer on a flexible substrate, vacuum adsorbing the glass substrate to the electrode layer, and forming a peelable cathode assembly; S3, reverse pulse metal growth hole filling: placing the peelable cathode assembly connected to a negative electrode of a power supply in a metal growth solution, cooperating with a metal anode, and enabling metal ions to deposit from the bottom of the through hole to the hole opening layer by layer from bottom to top, so as to realize cavity-free and gap-free full filling; and S4, separating and planarizing to obtain a metalized through hole glass substrate. The application combines the reverse pulse metal growth and the movable flow shielding plate technology, eliminates the electric field edge effect and the "clamping opening" phenomenon, realizes the dense deposition of the metal from bottom to top, enables the glass through hole filling to be cavity-free, gap-free and strong in adhesion, solves the problems of uneven thickness and substrate warping, and improves the interconnection reliability and product yield.

Description

Technical Field

[0001] This invention belongs to the field of advanced packaging, and particularly relates to a method for filling glass through-holes with void-free metal growth and a conductive interconnect substrate thereof. Background Technology

[0002] Through-Glass Via (TGV) technology, a key vertical interconnect solution in the field of 3D integrated packaging, achieves high-density electrical signal transmission and efficient heat dissipation by fabricating through-holes on a glass substrate and filling them with a conductive medium. Currently, TGV hole-forming processes mainly include sandblasting, ultrasonic drilling, laser-induced etching, and electrochemical discharge machining, which can fabricate through-hole structures with apertures of 10-100 μm and aspect ratios of 5:1 to 20:1 or even higher. However, in the subsequent metallization filling stage to achieve conductive interconnection, existing technologies still face significant technical bottlenecks. While Chinese patent CN117877989A, a method and apparatus for metal growth and solid copper filling of glass through-holes, can solve the problem of metallization filling to some extent, the filling difficulty increases exponentially when the aspect ratio exceeds 10:1.

[0003] To ensure good adhesion between the metal layer on the hole wall and the glass substrate and to achieve void-free filling, traditional processes typically require the pre-fabrication of a continuous conductive seed layer on the inner wall of the through-hole. However, this seed-layer-dependent process has the following inherent drawbacks: (1) The process is lengthy and complex: Before the seed layer is deposited, the glass pore walls need to undergo strict cleaning, roughening, activation, sensitization and drying processes. After deposition, the metal growth thickening process is also required, which significantly prolongs the overall manufacturing process and seriously restricts production efficiency.

[0004] (2) High manufacturing cost: The existing TGV process uses full-process PVD sputtering to prepare the seed layer for the through hole sidewall, which results in a large amount of target material per unit area and low material utilization. As the number of subsequent redistribution layers (RDL) increases and the wiring density increases, the demand for large-area coating on the entire surface is increasing. At the same time, the consumption of photoresist in the photolithography process has also increased significantly, which has comprehensively increased the overall manufacturing cost.

[0005] (3) Insufficient thermal matching reliability: The coefficient of thermal expansion (CTE) of the commonly used metal materials in the seed layer differs significantly from that of the glass substrate (glass CTE is about 0.55-3 ppm / ℃, and copper CTE is about 16.7 ppm / ℃). In subsequent thermal cycling or high-temperature processes, this difference can easily accumulate thermal stress, causing interface delamination, microcracks, or even film peeling, ultimately leading to the failure of the conductive path.

[0006] (4) Poor uniformity of deep-hole coverage: For through-holes with a large depth-to-width ratio (e.g., ≥10:1), traditional PVD sputtering methods are limited by their line-of-sight transmission characteristics, making it difficult to achieve uniform and dense seed layer coverage at the bottom of the hole and the sidewalls of the deep hole. During the deposition process, the ion flow preferentially deposits near the hole opening, which easily leads to a "bottleneck effect" or "jamming" phenomenon due to excessive deposition at the hole opening and insufficient deposition at the bottom of the hole. This results in discontinuous subsequent metal filling and induces void defects (e.g., Figure 1 (As shown). The larger the aspect ratio, the more prominent this phenomenon becomes. When the aspect ratio reaches 15:1 or higher, the seed layer thickness at the bottom of the hole is often less than 10% of the hole opening. At the same time, when ordinary metal growth equipment fills glass through-holes with a diameter of 100μm, the void ratio is as high as 20% to 30%, making it almost impossible to achieve effective filling.

[0007] (5) Deterioration of surface smoothness: Inhomogeneity of seed layer deposition can easily lead to local bulges or arc deformation on the surface of the glass substrate (e.g. Figure 2 As shown in the figure, this significantly reduces the via filling yield, which seriously affects the alignment accuracy and yield of subsequent planarization processes such as photolithography and rewiring (RDL). The industry statistics show that the yield is only 75% to 85%.

[0008] In summary, existing TGV metallization processes relying on seed layers suffer from significant drawbacks, including cumbersome procedures, high costs, poor filling quality, and low yield. This is particularly true for metallization of vias with high aspect ratios (≥10:1), where efficient and reliable solutions are still lacking. Therefore, there is an urgent need to develop a direct glass via metallization technology that eliminates the need for a seed layer and simplifies the process, thereby overcoming the current bottlenecks in TGV interconnect technology and meeting the pressing demands of 3D integrated packaging for high-density, high-reliability interconnects. Summary of the Invention

[0009] In order to overcome the shortcomings and deficiencies of the existing technology, the purpose of this invention is to provide a void-free metal growth and filling method for glass through-holes, so as to solve the prominent problems of cumbersome procedures, high costs, poor filling quality and low yield in the existing glass through-hole metallization process that relies on seed layers.

[0010] The objective of this invention is achieved through the following technical solution: A method for filling void-free metal growth in glass through-holes, characterized by comprising the following steps: S1: Provide a glass substrate with a through hole, and pre-treat the glass substrate; S2: An electrode layer is prepared on the surface of a flexible substrate, and the glass substrate is vacuum adsorbed onto the electrode layer to prepare a peelable cathode assembly. S3: Reverse pulse metal growth and hole filling: The peelable cathode assembly is connected to the negative terminal of the power supply and placed in the metal growth solution. It works together with the metal anode to allow metal ions in the metal growth solution to be deposited layer by layer from the bottom of the through hole to the opening under the drive of the electric field, thereby achieving full filling of the through hole without voids or gaps. S4: Separate the glass substrate from the electrode layer and perform planarization treatment on the surface of the glass substrate to obtain a glass substrate with metallized through holes.

[0011] In one specific embodiment, the pretreatment in step S1 includes: performing precision cleaning, roughening of the hole walls, and surface activation treatment on the glass substrate as a whole and the hole walls in sequence to remove impurities on the surface and inside the hole, constructing metal catalytic nucleation sites on the hole wall surface, and enhancing the bonding and adhesion between the subsequently deposited metal and the hole wall.

[0012] In one specific embodiment, the peelable cathode assembly in step S2 further includes a conductive base plate, a flexible substrate, and an electrode layer arranged sequentially. The electrode layer and the conductive base plate are electrically connected through a conductive connector. The glass substrate is attached to the surface of the electrode layer by vacuum adsorption to form the peelable cathode assembly.

[0013] In one specific embodiment, the flexible substrate is made of flexible glass, plastic or metal, the electrode layer is made of one or more of copper, titanium, nickel and chromium, and the thickness of the electrode layer is 10nm-300nm.

[0014] In one specific embodiment, the electrode layer is a patterned electrode, which includes a plurality of conductive units, the conductive units covering the through holes of the glass substrate, and the conductive units being interconnected.

[0015] In one specific embodiment, the electrode layer surface is provided with a passivation layer, the thickness of the passivation layer is 1nm-10nm, and the passivation layer is an oxide, fluoride or nitride.

[0016] In one specific embodiment, step S3 further includes setting a baffle plate between the peelable cathode assembly and the metal anode. The baffle plate is provided with mesh holes, the period of which ranges from 0.55mm to 60mm, and the aperture of which ranges from 0.5mm to 40mm. The aperture of the mesh holes on the baffle plate is distributed in a gradually increasing pattern from the edge to the center, or the density of the mesh holes is distributed in a gradually increasing pattern from the edge to the center.

[0017] In one embodiment, the baffle is mounted on a movable mechanism, which drives the baffle to move between the strippable cathode assembly and the metal anode.

[0018] In one specific embodiment, step S4 specifically includes: after the metal growth is completed, the glass substrate is first separated from the electrode layer by a peeling process, and then the residual material on the surface of the glass substrate is removed and annealing is performed.

[0019] The present invention provides a conductive interconnect substrate, comprising a glass substrate with metallized vias prepared by the above-described method of filling vias with void-free metal growth using glass vias, wherein seed layers are provided on both sides of the glass substrate with metallized vias, and metal circuit layers are provided on the seed layers, wherein the thickness of the metal circuit layers is 5μm-20μm.

[0020] In one specific embodiment, the seed layer is formed by depositing a metal material on the glass substrate with metallized vias using vapor deposition, magnetron sputtering, or atomic layer deposition processes. The metal material includes one or more of titanium, chromium, nickel, or copper, and the thickness of the seed layer is 30 nm to 200 nm.

[0021] In one specific embodiment, the metal circuit layer is formed by the following steps: The glass substrate with metallized through-holes having the seed layer is placed in the cathode of a metal growth tank. A baffle is set between the cathode and the metal anode. Under the action of the baffle, a uniform metal layer is formed on the surface of the seed layer using the seed layer as a conductive substrate through a metal growth process. Photoresist is coated on the metal layer, and exposure and development are performed according to the preset line area. The preset line area covers the metal end face of the glass through hole, so that the photoresist in the line area is retained, the photoresist in the non-line area is removed, and the metal layer is exposed. The exposed metal layer and the underlying seed layer are removed sequentially using an etching process, and finally the remaining photoresist is removed to form the metal circuit layer.

[0022] In one specific embodiment, the metal circuit layer is formed by the following steps: Photoresist is coated on the seed layer, and exposure and development are performed according to the preset line area. The preset line area covers the metal end face of the glass via, so that the photoresist in the non-line area is retained, the photoresist in the line area is removed, and the seed layer is exposed. The glass substrate with metallized through-holes and photoresist is placed in the cathode of a metal growth tank. A baffle is placed between the cathode and the metal anode. Under the action of the baffle, a uniform metal layer is formed in the circuit area by metal growth process, using the seed layer as a conductive substrate. Remove the photoresist in the non-circuit areas and then remove the seed layer in the non-circuit areas using a full-surface rapid etching process.

[0023] In one specific embodiment, the metal circuit layer is formed by the following steps: Using the glass substrate with metallized through-holes as a base, photoresist is coated on the glass substrate with metallized through-holes, and exposure and development are performed according to a preset line area. The preset line area covers the metal end face of the glass through-hole, so that the photoresist in the line area is removed and the photoresist in the non-line area is retained, and the metal end face inside the glass through-hole is exposed in the line area. Seed layer material is deposited in the circuit region, so that the seed layer is attached to the sidewall of the photoresist in the circuit region and the surface in contact with the metal pillar end face of the glass via. The glass substrate with metallized through-holes and seed layer is placed in the cathode of a metal growth tank. A baffle is placed between the cathode and the metal anode. Under the action of the baffle, a metal layer is grown in the circuit area using the seed layer as a conductive substrate through a metal growth process to form a uniform metal layer. The photoresist and seed layer material attached thereto in the non-circuit area are removed to form a metal circuit layer.

[0024] In one specific embodiment, a barrier layer is provided between the seed layer and the glass substrate with metallized through-holes. The barrier layer is made of titanium or tantalum and has a thickness of 20nm-50nm.

[0025] The beneficial effects of this invention are as follows: 1. In filling glass vias (TGVs), this invention utilizes the synergistic effect of the auxiliary homogenizing electric field of a baffle plate and the reverse pulse metal growth process to guide metal ions to deposit densely layer by layer from the bottom of the via towards the opening. This technical solution effectively eliminates the electric field edge effect and "jamming" phenomenon commonly found in traditional metal growth processes, achieving void-free and gapless filling of the via, significantly improving the interconnect reliability of glass vias (TGVs). Simultaneously, because the metal deposition process is uniform and controllable, the resulting metal layer has a smooth surface and consistent thickness, improving polishing efficiency and providing a good surface foundation for subsequent high-precision wiring.

[0026] 2. The current-shielding plate designed in this invention can precisely adjust the current density distribution on the cathode (glass substrate) surface, effectively suppressing the unfavorable phenomenon of preferential deposition at the orifice during metal growth, and simultaneously optimizing the filling rate of vias at different locations. Furthermore, the current-shielding plate is mounted on a movable mechanism and reciprocates between the cathode and anode during metal growth, further homogenizing the electric field and mass transfer distribution, eliminating local deposition differences, and significantly improving the consistency and density of metal filling within the glass via (TGV), ensuring the stability of interconnect quality in mass production.

[0027] 3. The cathode assembly of this invention uses a flexible substrate or incorporates a passivation layer, enabling the glass substrate to be separated from the electrode layer without damage after metal growth, effectively avoiding glass substrate warping. This avoids the physical damage or chemical contamination caused to the glass substrate by mechanical grinding in traditional methods. This design not only improves the integrity and cleanliness of the glass substrate but also creates favorable conditions for the smooth implementation of subsequent processes.

[0028] 4. Based on the glass substrate with metallized through-holes prepared by the method described above, this invention allows for further surface wiring integration. Due to the high flatness of the metal pillar end faces of the through-holes and controllable positional accuracy, the alignment accuracy during the wiring process is significantly improved, effectively reducing open circuits or high impedance defects caused by alignment deviations, thereby greatly improving product yield. Furthermore, this invention allows for flexible selection of corresponding metal line formation processes (such as etching after full-surface plating or selective deposition) according to the actual needs of different application scenarios such as RF and power devices, demonstrating good process adaptability and industrialization value. Attached Figure Description

[0029] Figure 1 A schematic diagram of the glass through-hole filling process in the prior art.

[0030] Figure 2 A schematic diagram of the glass through-hole filling process in the prior art.

[0031] Figure 3 Example 1: Schematic diagram of a void-free metal growth and filling method for glass through-holes.

[0032] Figure 4 Schematic diagram of the strippable cathode assembly structure in Example 1.

[0033] Figure 5 Schematic diagram of electrode layer structure in Example 1.

[0034] Figure 6 Example 1: Schematic diagram of the process flow for a void-free metal growth and filling method for glass through-holes.

[0035] Figure 7 Example 2: One of the schematic diagrams of the conductive interconnect substrate fabrication process.

[0036] Figure 8 Example 2: Schematic diagram of the conductive interconnect substrate fabrication process (Part 2).

[0037] Figure 9 Example 3: Schematic diagram of the conductive interconnect substrate fabrication process.

[0038] Figure 10 Example 4: Schematic diagram of the conductive interconnect substrate fabrication process.

[0039] In the figure: 1. Flexible substrate; 2. Electrode layer; 3. Glass substrate; 4. Shielding plate; 5. Metal growth trench; 6. Seed layer; 7. Metal layer; 7'. Metal circuit layer; 8. Photoresist; 9. Barrier layer; 10. Conductive base plate. Detailed Implementation

[0040] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of the method for manufacturing a planar capacitor without layering or wrinkles according to the present invention: Example 1 like Figures 3 to 6 As shown, this embodiment provides a void-free metal growth filling method for through-glass vias (TGV), aiming to solve the problems of voids and gaps easily generated during TGV filling in the prior art, as well as poor compatibility between the filling process and subsequent circuit integration. Specifically, it includes the following steps: Step S1: Provide a glass substrate 3 with a through hole and pre-treat the glass substrate 3.

[0041] In one specific embodiment, a glass substrate 3 with a through-hole is provided. The through-hole can be formed by laser-induced wet etching or other methods, and the hole diameter ranges from 10 μm to 200 μm. The glass substrate 3 as a whole and the hole walls are sequentially subjected to precision cleaning, hole wall roughening, and surface activation treatment to remove surface and internal impurities, construct metal catalytic nucleation sites on the hole wall surface, enhance the adhesion between the subsequently deposited metal and the hole wall, and prevent delamination or cracking during subsequent processes.

[0042] The pretreatment of the glass substrate 3 specifically includes: performing precision cleaning on the entire glass substrate 3 and the hole walls of the through holes in sequence, for example, using acetone, isopropanol and deionized water for ultrasonic cleaning; roughening the through hole walls, for example, using hydrofluoric acid or plasma etching, to increase the roughness of the hole walls and improve the adhesion of the hole walls; and further performing surface activation treatment using silane coupling agents, etc.

[0043] Step S2: An electrode layer 2 is prepared on the surface of a flexible substrate 1, and a glass substrate 3 is vacuum adsorbed onto the electrode layer 2 to form a peelable cathode assembly.

[0044] In one specific embodiment, the flexible substrate 1 includes materials such as flexible glass, plastic or metal, and an electrode layer 2 is prepared on the surface of the flexible substrate 1 by metal deposition processes such as magnetron sputtering or evaporation. The material of the electrode layer 2 includes one or more of copper, titanium, nickel and chromium, and the thickness of the electrode layer 2 is 10nm-300nm.

[0045] In another specific implementation, such as Figure 4As shown, the peelable cathode assembly also includes a conductive base plate 10, a flexible substrate 1, and an electrode layer 2 in sequence. The electrode layer 2 and the conductive base plate 10 are electrically connected by a conductive connector, such as a metal connector or conductive adhesive. The glass substrate 3 is attached to the surface of the electrode layer 2 by vacuum adsorption to form a peelable cathode assembly.

[0046] Furthermore, such as Figure 5 As shown, electrode layer 2 is a patterned electrode, comprising a plurality of conductive units. These conductive units cover the vias in the glass substrate, and are interconnected (conductively connected). The pattern of a single conductive unit can be a circle, rectangle, square, or irregular shape that is interconnected, ensuring coverage of the vias in the glass substrate 3. This invention does not impose any limitations on this. The patterned design of electrode layer 2 can regulate the electric field distribution on the surface of the flexible substrate 1, ensuring uniform current density in the desired area. Through the pre-designed electrode pattern, the range of metal deposition can be precisely defined, ensuring that metal grows only in the area covered by the patterned electrode (i.e., the location corresponding to the vias in the glass substrate 3). Since metal deposition only occurs in the patterned area, no metal is deposited in the non-patterned areas of the flexible substrate 1, reducing the difficulty of subsequent separation. Because the flexible substrate 1 is prone to warping or deformation during electrodeposition due to internal stress in the metal layer, a well-designed pattern of the patterned electrode (such as a grid or stripe pattern) can effectively disperse and release the internal stress generated by metal deposition, maintaining substrate flatness and ensuring the quality of via filling.

[0047] Preferably, a passivation layer is further provided on the surface of the electrode layer 2. The passivation layer material can be an oxide, fluoride, or nitride, and the thickness of the passivation layer is 1nm-10nm. Subsequently, the glass substrate 3 pretreated in step S1 is tightly attached to the surface of the passivation layer by vacuum adsorption to ensure that the bottom port of the through hole forms a good and uniform electrical contact with the passivation layer, thereby forming a complete peelable cathode assembly.

[0048] In this embodiment, a flexible substrate 1 is used in the peelable cathode assembly, or a passivation layer is added to the peelable cathode assembly, so that the glass substrate 3 can be separated from the electrode layer 2 without damage after metal growth, effectively avoiding the problems of glass substrate warping and cracking. At the same time, it avoids the physical damage or chemical contamination caused to the glass substrate 3 by mechanical grinding to remove the substrate in traditional methods. This design not only improves the integrity and cleanliness of the glass substrate 3, but also creates favorable conditions for the smooth implementation of subsequent processes.

[0049] Step S3: Reverse pulse metal growth to fill the holes.

[0050] In one specific embodiment, the peelable cathode assembly prepared in step S2 is connected to the negative terminal of a power supply and placed in the metal growth solution of the metal growth tank 5. Working together with the metal anode, metal ions in the metal growth solution are deposited layer by layer from the bottom to the opening of the through-hole under the drive of an electric field, thus achieving complete filling of the through-hole without voids or gaps. A movable baffle 4 is placed between the peelable cathode assembly and the metal anode. The baffle 4 has mesh openings with a period ranging from 0.55mm to 60mm and a aperture ranging from 0.5mm to 40mm. To compensate for the edge effect of the electric field, the aperture size of the mesh openings on the baffle 4 is distributed in a gradually increasing pattern from the edge to the center, or the mesh density is distributed in a gradually increasing pattern from the edge to the center. This distribution design can precisely adjust the current density distribution on the surface of the cathode (peelable cathode assembly), effectively suppress the preferential deposition phenomenon at the opening, and simultaneously optimize the filling rate. Meanwhile, the baffle plate 4 is mounted on a movable mechanism that can reciprocate between the cathode (strippable cathode assembly) and the anode (metal anode) during the metal growth process. It can be applied to glass substrates 3 with different aperture sizes, further homogenize the electric field and mass transfer distribution, eliminate local deposition differences, improve the consistency and density of metal filling in the glass via (TGV), and ensure the stability of interconnect quality in mass production.

[0051] The vias are filled using a reverse pulse metal growth process: during the forward pulse (cathodic deposition), metal ions are reduced and deposited; during the reverse pulse (anodic dissolution), the excessively rapid growth of protruding parts at the via edge is effectively dissolved. Under the combined effect of the homogenizing electric field assisted by the baffle plate 4 and the reverse pulse, metal ions are mainly driven by the electric field, and are densely deposited layer by layer from the bottom of the via to the opening. This effectively eliminates the electric field edge effect and the "clamping" phenomenon, achieving void-free and gapless filling of the vias, significantly improving interconnect reliability. Simultaneously, due to the uniform metal deposition, the surface is flat and of consistent thickness, providing a good surface foundation for subsequent high-precision wiring.

[0052] Step S4: Separate the glass substrate 3 from the electrode layer 2, and perform planarization treatment on the surface of the glass substrate 3 to obtain a glass substrate 3 with metallized through holes.

[0053] In one specific embodiment, after the metal growth is completed, the glass substrate 3 is first separated from the electrode layer 2 without damage by a peeling process, and then the residual material on the surface of the glass substrate 3 is removed and annealing is performed.

[0054] Specifically, after the metal growth and filling are completed, the deformation of the flexible substrate 1 is used to achieve non-destructive separation between the glass substrate 3 and the electrode layer 2. Alternatively, an ultrathin passivation layer can be used to effectively reduce the bonding force between the glass substrate 3 and the electrode layer 2. This passivation layer, as a weak interface for stress release, can induce cracks to propagate along its interior or at the interface between the passivation layer and the electrode layer 2 / glass substrate 3, thereby achieving non-destructive and easy separation. Subsequently, chemical mechanical polishing or short-time plasma etching is used to remove any thin layer of metal or impurities that may remain on the surface of the glass substrate 3, ultimately obtaining a glass substrate 3 with flat upper and lower surfaces and metal pillar end faces flush with the glass surface in the through-hole.

[0055] Example 2 like Figure 7 As shown, this embodiment provides a conductive interconnect substrate, which uses a glass substrate 3 with metallized through holes prepared by the method described in Embodiment 1, on which subsequent circuit layers are constructed.

[0056] Specifically, seed layers 6 are formed on both sides of the glass substrate 3 with metallized vias. The seed layers 6 are formed by depositing metal material on the glass substrate 3 with metallized vias using vapor deposition, magnetron sputtering, or atomic layer deposition (ALD) processes. The seed layers 6 are made of one or more of titanium, chromium, nickel, or copper, and have a thickness of 30 nm to 200 nm. The seed layers 6 support subsequent metal growth while avoiding lateral erosion problems caused by excessively thick seed layers 6 during etching. They also balance good adhesion to the glass and excellent conductivity, serving as a reliable transition layer from the glass substrate 3 with metallized vias to the functional circuitry. Subsequently, a metal circuit layer 7' is formed on the seed layer 6, with a thickness of 5 μm to 20 μm.

[0057] In one specific embodiment, the specific steps for forming the metal circuit layer 7' in this embodiment include: First, a glass substrate 3 with metallized through-holes that has a seed layer 6 is placed in the cathode of a metal growth tank 5, and a baffle plate 4 is set between the cathode and the metal anode. With the assistance of the baffle plate 4 (as described in Example 1), a uniform metal layer 7 is formed on the surface of the seed layer 6 using the seed layer 6 as a conductive substrate through a metal growth process.

[0058] Next, photoresist 8 is coated on the metal layer 7, and exposure and development are performed according to the preset line area. The preset line area covers the metal end face of the glass via, and it is ensured that the photoresist 8 in the line area is retained and the photoresist 8 in the non-line area is removed to expose the underlying metal layer 7.

[0059] Finally, an etching process is used to sequentially remove the exposed metal layer 7 and its corresponding seed layer 6 below it. The remaining photoresist 8 in the circuit area is then removed, ultimately forming a precise metal circuit layer 7'.

[0060] In one specific implementation, such as Figure 8 As shown, a barrier layer 9 is provided between the seed layer 6 and the glass substrate 3 with metallized vias. This barrier layer 9 is made of titanium or tantalum and has a thickness of 20nm-50nm. For example, when the vias contain copper, the barrier layer 9 has a dense crystalline structure and does not react with copper, effectively preventing the copper in the vias from diffusing into the interior of the glass substrate 3 and the surrounding circuit area. This avoids problems such as increased leakage current, short circuits, or decreased insulation performance caused by copper migration, thereby ensuring the long-term stability and reliability of the interconnect structure. The fabrication process of the subsequent metal circuit layer 7' is the same as described above and will not be repeated here.

[0061] It is worth noting that in this embodiment, when the thickness of the metal circuit layer 7' is relatively thin, the metal layer 7 can be directly formed by repeating the metal deposition process multiple times when setting the seed layer 6, so as to simplify the manufacturing process and save the preparation cost.

[0062] This embodiment employs a process route of full-surface plating followed by etching. This process is mature, the equipment is highly versatile, and it is easy to quickly implement on existing production lines. The use of a current shield 4 to assist in homogenizing the electric field effectively ensures the uniformity of the plating thickness, thereby improving the consistency of the etched circuit dimensions. The circuit area covers the metal pillar end face of the through-glass via (TGV), ensuring a low-resistance transition between vertical and horizontal interconnects, avoiding open circuits or high impedance problems caused by alignment misalignment, and significantly improving product yield. Furthermore, this embodiment can be flexibly adjusted according to different application scenarios to meet the actual needs of RF, power devices, and other fields for low impedance and high current carrying capacity. This solution achieves integrated vertical interconnects via glass vias and horizontally redistributed circuitry on the surface, providing a high-performance basic interconnect substrate for 3D packaging and system-in-package.

[0063] Example 3 like Figure 9 As shown, this embodiment provides a conductive interconnect substrate. The difference from Embodiment 2 is that the specific steps for forming the metal circuit layer 7' in this embodiment include: First, photoresist 8 is coated on the seed layer 6, and exposure and development are performed according to the preset line area. The preset line area covers the metal end face of the glass via, so that the photoresist 8 in the non-line area is retained and the photoresist 8 in the line area is removed, thus exposing the seed layer 6. The seed layer 6 is made of one or more of titanium, chromium, nickel or copper, and its thickness is 30nm-200nm.

[0064] Next, a glass substrate 3 with metallized through-holes and photoresist 8 is placed in the cathode of the metal growth tank 5. A baffle plate 4 is set between the cathode and the metal anode. Under the auxiliary homogenizing electric field of the baffle plate 4, a uniform metal layer 7 is formed only in the circuit area using the exposed seed layer 6 as the conductive substrate.

[0065] Finally, the photoresist 8 in the non-circuit area is removed. Then, a full-surface fast etching (flash etching) is performed to remove the thin seed layer that was previously covered by the photoresist 8 and is now exposed. Since the thickness of the metal layer 7 in the circuit area is much greater than that of the seed layer 6, this step has almost no impact on the linewidth and thickness of the circuit layer, ultimately resulting in the metal circuit layer 7'.

[0066] In other embodiments, a barrier layer may be added between the seed layer 6 and the glass substrate 3 with metallized through-holes, as described in Embodiment 1.

[0067] The core difference between this embodiment and Embodiment 2 lies in the use of selective deposition technology, which deposits metal only in the desired circuit area, rather than plating the entire surface before etching. Due to the significant reduction in the deposition area, the utilization rate of metal materials is significantly improved, greatly saving the cost of precious metals (such as copper and titanium), reducing material consumption and the amount of chemical reagents required for subsequent etching, thus aligning with the concept of green manufacturing.

[0068] The circuit area and the metal pillar end face of the through-glass via (TGV) are directly connected through precise alignment, avoiding circuit misalignment or dimensional inconsistencies caused by etching deviations during the full-surface plating process. This precise alignment ensures seamless integration of the vertical interconnects of the vias and the horizontal circuitry on the surface, resulting in a tight interface that effectively reduces contact resistance, thereby improving signal transmission efficiency and interconnect reliability. This embodiment achieves low-cost, high-precision metallization integration of through-glass vias (TGV) while maintaining interconnect performance, making it particularly suitable for large-scale packaging applications with high requirements for cost and integration density.

[0069] Example 4 like Figure 10 As shown, this embodiment provides a conductive interconnect substrate. The difference from Embodiment 2 is that the specific steps for forming the metal circuit layer 7' in this embodiment include: First, using the glass substrate 3 with metallized vias prepared in Example 1 as a substrate, photoresist 8 is coated on its surface. Exposure and development are performed according to a preset line area, which covers the metal end face of the glass via (TGV), so that the photoresist 8 in the line area is removed and the photoresist 8 in the non-line area is retained, thereby exposing the metal end face of the glass via (TGV) in the line area.

[0070] Next, a seed layer material is deposited on the entire surface of the glass substrate 3 with metallized vias. Since the non-circuit areas are covered by photoresist 8, the seed layer material is deposited in the circuit areas, so that the seed layer 6 is attached to the sidewalls of the photoresist 8 in the circuit areas and the surface in contact with the metal pillar end face of the glass via (TGV). The seed layer 6 is made of one or more of titanium, chromium, nickel or copper, and its thickness is 30nm-200nm.

[0071] A glass substrate 3 with metallized through-holes and a seed layer 6 is placed at the cathode of a metal growth tank 5. A flow shield 4 is placed between the cathode and the metal anode. Under the action of the flow shield 4, a metal layer 7 is grown in the circuit area using the seed layer 6 as a conductive substrate through a metal growth process. Finally, the photoresist 8 in the non-circuit area and the seed layer material attached to the photoresist 8 are removed to form the metal circuit layer 7'.

[0072] In other embodiments, a barrier layer may be added to the glass substrate 3 with metallized vias before the photoresist 8 is coated. The barrier layer is specifically as described in Embodiment 1.

[0073] This embodiment completely eliminates the overall etching step of the seed layer, avoiding the erosion of the metal circuit sidewalls by the etching solution and potential damage to the glass substrate. In this method, the circuit region directly contacts and grows with the end face of the glass-to-glass via (TGV) metal pillar, forming a continuous integrated metal structure of the metal pillar and the metal circuit layer. This eliminates the contact resistance between different interfaces and further improves the electrical performance of the interconnect. At the same time, the process flow is simplified, the yield is significantly improved, and it is particularly suitable for the fabrication of ultra-fine circuits.

[0074] In summary, the conductive interconnect substrate of this invention, based on a glass substrate with metallized through-holes prepared by this method, further integrates surface wiring. Due to the high flatness of the metal pillar end faces of the through-holes and controllable positional accuracy, the alignment accuracy during the wiring process is significantly improved, effectively reducing open circuits or high impedance defects caused by alignment deviations, thereby greatly improving product yield. Furthermore, this invention allows for flexible selection of corresponding metal line formation processes according to the actual needs of different application scenarios such as RF and power devices, possessing good process adaptability and industrialization value.

[0075] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for filling void-free metal growth in glass through-holes, characterized in that, Includes the following steps: S1: Provide a glass substrate with a through hole, and pre-treat the glass substrate; S2: Prepare a peelable cathode assembly, the peelable cathode assembly comprising a conductive base plate, a flexible substrate and an electrode layer arranged sequentially, the preparation method comprising: preparing an electrode layer on the surface of the flexible substrate, the electrode layer being conductively connected to the conductive base plate through a conductive connector, and the glass substrate being attached to the surface of the electrode layer by vacuum adsorption. The electrode layer is a patterned electrode, which includes a plurality of conductive units. The conductive units cover the through holes of the glass substrate and are interconnected. The patterned design of the electrode layer is used to regulate the electric field distribution on the surface of the flexible substrate to ensure that the current density is uniform in the required area. The electrode layer surface is provided with a passivation layer, which is used to reduce the bonding force between the glass substrate and the electrode layer; S3: Reverse pulse metal growth and hole filling: The peelable cathode assembly is connected to the negative terminal of the power supply and placed in the metal growth solution. It works together with the metal anode to cause the metal ions in the metal growth solution to be deposited layer by layer from the bottom of the through hole to the opening under the drive of the electric field, thereby achieving full filling of the through hole without voids or gaps. S4: Separate the glass substrate from the electrode layer and perform planarization treatment on the surface of the glass substrate to obtain a glass substrate with metallized through holes.

2. The method for filling void-free metal growth in glass through-holes as described in claim 1, characterized in that, The pretreatment in step S1 includes: sequentially cleaning, roughening and surface activation of the glass substrate as a whole and the hole walls of the through holes to remove impurities on the surface and inside the through holes, constructing metal catalytic nucleation sites on the hole wall surface, and enhancing the bonding and adhesion between the subsequently deposited metal and the hole wall.

3. The method for filling void-free metal growth in glass through-holes as described in claim 1, characterized in that, The flexible substrate is made of flexible glass, plastic or metal, and the electrode layer is made of one or more of copper, titanium, nickel and chromium. The thickness of the electrode layer is 10nm-300nm.

4. The method for filling void-free metal growth in glass through-holes as described in claim 1, characterized in that, The passivation layer has a thickness of 1 nm to 10 nm and is an oxide, fluoride, or nitride.

5. The method for filling void-free metal growth in glass through-holes as described in claim 1, characterized in that, Step S3 further includes setting a baffle plate between the peelable cathode assembly and the metal anode. The baffle plate is provided with mesh holes. The period of the mesh holes ranges from 0.55mm to 60mm, and the aperture ranges from 0.5mm to 40mm. The aperture of the mesh holes on the baffle plate is distributed in a gradually increasing pattern from the edge to the center, or the density of the mesh holes is distributed in a gradually increasing pattern from the edge to the center.

6. The method for filling void-free metal growth in glass through-holes as described in claim 5, characterized in that, The baffle is mounted on a movable mechanism, which drives the baffle to move between the strippable cathode assembly and the metal anode.

7. The method for filling void-free metal growth in glass through-holes as described in claim 1, characterized in that, Step S4 specifically includes: after the metal growth is completed, the glass substrate is first separated from the electrode layer by a peeling process, and then the residual material on the surface of the glass substrate is removed and annealing is performed.

8. A conductive interconnect substrate, characterized in that, The invention includes a glass substrate with metallized through-holes prepared by the voidless metal growth and filling method for glass through-holes according to any one of claims 1-7, wherein a seed layer is provided on both sides of the glass substrate with metallized through-holes, and a metal circuit layer is provided on the seed layer, wherein the thickness of the metal circuit layer is 5μm-20μm.

9. The conductive interconnect substrate as claimed in claim 8, characterized in that, The seed layer is formed by depositing a metal material on a glass substrate with metallized vias using vapor deposition, magnetron sputtering, or atomic layer deposition processes. The metal material includes one or more of titanium, chromium, nickel, or copper, and the thickness of the seed layer is 30 nm to 200 nm.

10. The conductive interconnect substrate as claimed in claim 9, characterized in that, The metal circuit layer is formed through the following steps: The glass substrate with metallized through-holes having the seed layer is placed in the cathode of the metal growth tank. A baffle is set between the cathode and the metal anode. Under the action of the baffle, a uniform metal layer is formed on the surface of the seed layer using the seed layer as a conductive substrate through the metal growth process. Photoresist is coated on the metal layer, and exposure and development are performed according to the preset line area. The preset line area covers the metal end face of the glass through hole, so that the photoresist in the line area is retained, the photoresist in the non-line area is removed, and the metal layer is exposed. The exposed metal layer and the underlying seed layer are removed sequentially using an etching process, and finally the remaining photoresist is removed to form the metal circuit layer.

11. The conductive interconnect substrate as claimed in claim 9, characterized in that, The metal circuit layer is formed through the following steps: Photoresist is coated on the seed layer, and exposure and development are performed according to the preset line area. The preset line area covers the metal end face of the glass via, so that the photoresist in the non-line area is retained, the photoresist in the line area is removed, and the seed layer is exposed. The glass substrate with metallized through-holes and photoresist is placed in the cathode of the metal growth tank. A baffle is set between the cathode and the metal anode. Under the action of the baffle, a uniform metal layer is formed in the circuit area by metal growth process using the seed layer as a conductive substrate. Remove the photoresist in the non-circuit areas and then remove the seed layer in the non-circuit areas through a full-surface etching process.

12. The conductive interconnect substrate as claimed in claim 8, characterized in that, The metal circuit layer is formed through the following steps: Using the glass substrate with metallized through-holes as a base, photoresist is coated on the glass substrate with metallized through-holes, and exposure and development are performed according to a preset line area. The preset line area covers the metal end face of the glass through-hole, so that the photoresist in the line area is removed and the photoresist in the non-line area is retained, and the metal end face inside the glass through-hole is exposed in the line area. Seed layer material is deposited in the circuit region, so that the seed layer is attached to the sidewall of the photoresist in the circuit region and the surface in contact with the metal pillar end face of the glass via. The glass substrate with metallized through-holes having the seed layer is placed in the cathode of the metal growth tank. A baffle is set between the cathode and the metal anode. Under the action of the baffle, a metal layer is grown in the circuit area using the seed layer as a conductive substrate through a metal growth process to form a uniform metal layer. Remove the photoresist and seed layer material attached to the non-circuit area to form a metal circuit layer.

13. The conductive interconnect substrate as claimed in claim 8, characterized in that, A barrier layer is provided between the seed layer and the glass substrate with metallized through-holes. The barrier layer is made of titanium or tantalum and has a thickness of 20nm-50nm.

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