Glass-based double-sided multi-layer wiring substrate, method for manufacturing the same, and application thereof

Abstract

The application discloses a glass-based double-sided multilayer wiring substrate and a preparation method and application thereof. The glass-based double-sided multilayer wiring substrate comprises a glass substrate, and PI layers and copper wiring layers are alternately and sequentially arranged on two sides of the glass substrate. The total number of the PI layers and the total number of the copper wiring layers on any side of the glass substrate are the same, and both are three or more. The surface of the glass substrate is a PI layer, and the outermost layer is a copper wiring layer. From the surface of the glass substrate to the outermost layer, the thermal expansion coefficients of the PI layers are in a gradient structure from low to high and then to low, and the thermal expansion coefficient of the PI layer on the surface of the glass substrate is smaller than that of the outermost PI layer. The PI layer CTE of the application presents a low-high-medium gradient, realizes step-by-step matching of thermal expansion, reduces the interface stress and warping degree of the glass-based double-sided multilayer wiring substrate, and is suitable for high-density glass-based packaging.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging substrate technology, specifically relating to a glass-based double-sided multilayer wiring substrate, its preparation method, and its application. Background Technology

[0002] With the rapid development of fifth-generation mobile communication (5G), artificial intelligence, high-performance computing, and other fields, semiconductor packaging is constantly evolving towards higher density, higher frequency, and higher reliability. Glass substrates, due to their low coefficient of thermal expansion (CTE≈3~5 ppm / ℃), high flatness, and high insulation, have become the preferred carrier for high-density advanced packaging. When constructing multilayer wiring structures on glass substrates, it is necessary to alternately form insulating layers and copper wiring layers on the glass substrate surface.

[0003] However, existing technologies mostly use a single-component insulating resin layer, such as a polyimide (PI) insulating layer. The thermal expansion coefficients of the glass substrate and the copper wiring layer (CTE≈16~18 ppm / ℃) and the insulating resin layer are significantly different, which easily leads to stress concentration at the interface, resulting in warping and serious problems such as delamination and cracking.

[0004] Therefore, reducing the warpage of glass-based multilayer wiring substrates has significant industrial implications. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, this invention provides a glass-based double-sided multilayer wiring substrate, its fabrication method, and its applications. This invention reduces warpage by employing a low-to-high-to-medium gradient design of the thermal expansion coefficient of the PI insulating layer; simultaneously, it achieves high reliability and high-density wiring through functional partitioning and thickness redundancy design of each copper wiring layer.

[0006] The technical solution adopted by this invention to solve its technical problem is: This invention provides a glass-based double-sided multilayer wiring substrate, comprising a glass substrate, wherein a PI layer and a copper wiring layer are alternately stacked on both sides of the glass substrate; the total number of PI layers and the total number of copper wiring layers on either side of the glass substrate are the same, both being three or more layers; the surface of the glass substrate is a PI layer, and the outermost layer is a copper wiring layer; from the surface of the glass substrate to the outermost layer, the coefficient of thermal expansion of each PI layer is a gradient structure from low to high and then back to low, and the coefficient of thermal expansion of the PI layer on the surface of the glass substrate is less than that of the outermost PI layer (i.e., the PI layer on the side of the outermost copper wiring layer closest to the glass substrate).

[0007] Preferably, the total number of PI layers and the total number of copper wiring layers on either side of the glass substrate are three layers, and the glass substrate is provided with a first PI layer, a first copper wiring layer, a second PI layer, a second copper wiring layer, a third PI layer and a third copper wiring layer stacked sequentially on both sides. The coefficient of thermal expansion of the first PI layer is smaller than that of the third PI layer, and the coefficient of thermal expansion of the second PI layer is larger than that of the third PI layer.

[0008] More preferably, the coefficient of thermal expansion of the first PI layer is 8~12 ppm / ℃; the coefficient of thermal expansion of the second PI layer is 16~20 ppm / ℃; and the coefficient of thermal expansion of the third PI layer is 13~15 ppm / ℃.

[0009] More preferably, the first PI layer is a rigid aromatic siloxane-containing polyimide; the second PI layer is a fluorinated modified polyimide; and the third PI layer is a polyimide-polysiloxane copolymer. This satisfies the above requirements for the coefficient of thermal expansion, while the rigid aromatic siloxane-containing polyimide in the first PI layer has high interfacial adhesion to the glass substrate, and the fluorinated modified polyimide in the second PI layer has low dielectric constant and dielectric loss.

[0010] More preferably, the rigid aromatic siloxane-containing polyimide is obtained by polymerization of dianhydride monomer ODPA, diamine monomer ODA and diamine monomer GAPD; wherein the molar amount of dianhydride monomer ODPA and the total molar amount of diamine monomer ODA and diamine monomer GAPD are equal, and the molar ratio of diamine monomer ODA to diamine monomer GAPD is (80-90):(10-20). The fluorinated modified polyimide is obtained by polymerizing the dianhydride monomer hexafluorodianhydride (6FDA) and the diamine monomer 2,2'-bis(trifluoromethyl)-4,4'-diaminobiphenyl (TFMB); wherein the molar amounts of the dianhydride monomer hexafluorodianhydride (6FDA) and the diamine monomer 2,2'-bis(trifluoromethyl)-4,4'-diaminobiphenyl (TFMB) are equal. The polyimide-polysiloxane copolymer is obtained by polymerizing dianhydride monomer 3,3',4,4'-biphenyltetracarboxylic dianhydride (BPDA), diamine monomer 4,4'-diaminodiphenyl ether (ODA), and diamine monomer aminopropyl-terminated polydimethylsiloxane (PDMS). The molar amounts of dianhydride monomer 3,3',4,4'-biphenyltetracarboxylic dianhydride (BPDA) and the total molar amounts of diamine monomer 4,4'-diaminodiphenyl ether (ODA) and diamine monomer aminopropyl-terminated polydimethylsiloxane (PDMS) are equal, the molar ratio of diamine monomer 4,4'-diaminodiphenyl ether (ODA) to diamine monomer aminopropyl-terminated polydimethylsiloxane (PDMS) is (85-95):(5-15), and the number-average molecular weight Mn of diamine monomer aminopropyl-terminated polydimethylsiloxane (PDMS) is 1000-2000.

[0011] More preferably, the linewidth of the first copper wiring layer is ≥10μm; the linewidth of the second copper wiring layer is ≤5μm; the linewidth of the third copper wiring layer is ≤5μm, and the surface roughness Ra is ≤50nm.

[0012] More preferably, the second copper wiring layer has higher ductility than the first copper wiring layer.

[0013] More preferably, the second copper wiring layer is annealed copper or copper with trace alloying. Annealed copper is obtained by copper annealing treatment at a temperature of 240-260°C for 30-60 minutes.

[0014] Preferably, the glass substrate is borosilicate glass.

[0015] Preferably, the total thickness of the PI layer on any side of the glass substrate is not less than 1.2 times the total thickness of the copper wiring layer.

[0016] Preferably, the surface of the outermost copper wiring layer is covered with a Ni / Au barrier layer.

[0017] Preferably, the PI layers are all formed by a stepped temperature curing process, which includes: holding at 75-85℃, 115-125℃, 145-155℃, 175-185℃, 215-225℃ and 245-255℃ for 20-40 minutes each, and the stepped temperature curing process is carried out in a protective atmosphere.

[0018] More preferably, the stepped temperature curing process includes: holding at 80℃, 120℃, 150℃, 180℃, 220℃, and 250℃ for 30 minutes each.

[0019] Further preferably, the protective atmosphere is a nitrogen atmosphere.

[0020] This invention provides a method for preparing the above-mentioned glass-based double-sided multilayer wiring substrate, comprising the following steps: (1) Cleaning and plasma activation treatment of the glass substrate; (2) Spin-coating the PI layer precursor solution onto both sides of the glass substrate and then performing step-by-step temperature increase curing to form the PI layer; (3) A copper wiring layer was prepared using a semi-additive method; (4) Spin-coating the PI layer precursor solution and then performing step-by-step temperature increase curing to form the PI layer; (5) A copper wiring layer was prepared using a semi-additive method; (6) Repeat steps (4) and (5) to prepare the PI layer and copper wiring layer to obtain a glass-based double-sided multilayer wiring substrate.

[0021] Preferably, chemical mechanical planarization is performed on the final copper wiring layer after its preparation.

[0022] Preferably, Ni / Au is plated onto the final copper wiring layer after it has been prepared.

[0023] This invention provides an application of the above-mentioned glass-based double-sided multilayer wiring substrate in semiconductor packaging.

[0024] To address the problems of CTE mismatch, stress concentration, single function of copper wiring layer, and poor process compatibility in existing glass-based wiring substrates, this invention achieves low warpage, high reliability, and high-density wiring through the synergistic design of CTE gradient PI insulating layer and functional partitioning of copper wiring layer.

[0025] The beneficial effects of this invention are: (1) The PI layer CTE of the present invention has a low → high → medium gradient, which realizes the thermal expansion matching step by step and reduces the interface stress and warpage of the glass-based double-sided multilayer wiring substrate. (2) The copper wiring layer of the present invention is divided into power / ground layer (line width ≥ 10 μm), signal layer (line width ≤ 5 μm), and surface functional layer (line width ≤ 5 μm, low roughness) according to its position, so as to realize differentiated design, improve wiring density and reliability, and is suitable for high-density glass substrate packaging. Attached Figure Description

[0026] Figure 1 This is a process flow diagram of the preparation method of the glass-based double-sided multilayer wiring substrate in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of the glass-based double-sided multilayer wiring substrate of Embodiment 1 of the present invention; Figure 3 This is an optical microscope image of a chip packaged on a glass-based double-sided multilayer wiring substrate according to Embodiment 1 of the present invention. Figure 4 This is an optical microscope image of a chip packaged on a glass-based double-sided multilayer wiring substrate, which is Comparative Example 1 of this invention. Detailed Implementation

[0027] The present invention will be further described below with reference to embodiments.

[0028] The following will clearly and completely describe the concept, specific solutions, and technical effects of the present invention with reference to embodiments, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. The various technical features in the present invention can be combined interactively without contradicting each other.

[0029] Existing technologies lack gradient thermal expansion matching between the glass substrate and copper, and lack stepped curing processes and thickness redundancy design, failing to achieve gradual stress release. Furthermore, existing technologies do not differentiate copper wiring layers at different locations; all copper layers use the same materials and processes, leading to fatigue fracture of inner copper wires and insufficient surface roughness for high-density wiring requirements. Therefore, there is an urgent need for a holistic solution integrating a CTE gradient insulating layer and copper wiring functional partitioning.

[0030] The present invention provides a glass-based double-sided multilayer wiring substrate, comprising a glass substrate, wherein a first PI (insulating) layer, a first copper wiring layer, a second PI layer, a second copper wiring layer, a third PI layer and a third copper wiring layer (from the inside to the outside) are sequentially stacked on both sides of the glass substrate. The glass substrate is borosilicate glass; The first PI layer has a thickness of 5~8μm and a CTE of 8~12 ppm / ℃ (low CTE). The second PI layer has a thickness of 8~10μm and a CTE of 16~20 ppm / ℃ (high CTE). The third PI layer has a thickness of 5~8μm and a CTE of 13~15 ppm / ℃ (medium CTE). The first PI layer, the second PI layer, and the third PI layer form a gradient structure of CTE from low to high and then to medium, achieving a stepwise thermal expansion matching between glass, PI, and copper. The glass substrate, the first PI layer, the second PI layer, and the third PI layer are each provided with through holes, which are filled with copper to connect the first copper wiring layer, the second copper wiring layer, and the third copper wiring layer.

[0031] In some embodiments, the first PI layer is a rigid aromatic siloxane-containing polyimide; the siloxane-containing structure has high interfacial adhesion to the glass substrate; The second PI layer is a fluorinated modified polyimide; the fluorinated structure has a low dielectric constant. The third PI layer is a polyimide-polysiloxane copolymer.

[0032] In some embodiments, the first copper wiring layer has a line width ≥10μm, a line spacing ≥8μm, and a thickness of 3~5μm; it is used for power distribution networks or ground planes. The second copper wiring layer has a line width of ≤5μm and a thickness of 3~5μm; it is made of annealed copper or copper with added trace amounts of alloys (with higher ductility than the first copper wiring layer); it is used for high-density signal wiring. The third copper wiring layer has a linewidth of ≤5μm, a thickness of 3~5μm, and a surface that has been planarized with a surface roughness Ra≤50nm; the surface is covered with a Ni / Au (3~5μm / 0.05~0.1μm) barrier layer.

[0033] Based on the different positions of each copper wiring layer in the thickness direction, functional zoning design is carried out, giving each layer different structural and process characteristics: The first copper wiring layer (adjacent to the first PI layer): primarily serves as the power distribution network or ground plane, with a linewidth ≥ 10 μm. The design is based on the following: the first copper wiring layer is adjacent to the glass substrate, which has extremely low CTE (3~5 ppm / ℃). During thermal cycling, the expansion and contraction of the copper wires are strongly constrained by the glass. Narrower linewidths result in greater strain per unit cross-sectional area, increasing the risk of fatigue fracture. A wider linewidth (≥ 10 μm) provides a larger cross-sectional area and a larger contact area with the PI layer, thereby enhancing fatigue resistance and interfacial adhesion, and reducing the risk of peeling. Simultaneously, the power / ground network needs to carry a large current; a wider linewidth reduces IR voltage drop.

[0034] The second copper wiring layer (located between the second and third PI layers): serving as a high-density signal wiring layer with a line width ≤ 5μm. The design is based on the following: this layer is located in the middle, surrounded by PI layers on both sides, resulting in a relatively balanced stress environment. Furthermore, the high CTE (16~20 ppm / ℃) of the second PI layer provides good flexibility, absorbing some thermal deformation. The fine line width (≤ 5μm) significantly increases wiring density, meeting the requirements of high-density interconnection. Simultaneously, the copper wires in this layer undergo annealing treatment or the addition of trace alloys to further improve ductility and resist the greater thermal deformation of the intermediate layer.

[0035] The third copper wiring layer (surface layer): As a functional wiring layer, the linewidth is ≤5μm, the surface is chemically and mechanically planarized with a roughness Ra≤50nm, and covered with a Ni / Au barrier layer. The design is based on the following: the surface copper lines need to be in direct contact with chip solder balls, bumps, or test probes; the fine linewidth allows for smaller chip-to-substrate spacing and higher I / O density; low surface roughness ensures good solderability and high-frequency signal integrity; the Ni / Au barrier layer prevents copper oxidation and improves solderability.

[0036] The aforementioned "coarse inside, fine outside" differentiated design is the result of systematic optimization based on thermodynamics and electrical performance, rather than an arbitrary choice. Different linewidths can be achieved on the same substrate using a semi-additive process (SAP). This only requires designing feature sizes for different regions on the photomask and setting a tapered transition structure at the abrupt changes in linewidth to avoid stress concentration.

[0037] In some embodiments, the total thickness of the PI layer on either side of the glass substrate is not less than 1.2 times the total thickness of the copper wiring layer; Through thickness redundancy design, the total thickness of the PI layer is not less than 1.2 times the total thickness of the copper wiring layer, forming stress buffer and insulation redundancy.

[0038] In some implementations, the PI layer is formed by a stepped temperature curing process, specifically including holding at 80°C, 120°C, 150°C, 180°C, 220°C, and 250°C for 30 minutes each, in a nitrogen atmosphere throughout.

[0039] The CTE gradient design of this invention controls the maximum CTE difference between layers to within 8 ppm / ℃, and the theoretical interfacial shear stress is reduced by more than 50% compared with a single PI layer. The copper wiring layer functional partition design of this invention is as follows: inner layer (line width ≥ 10μm) is fatigue resistant and suitable for power distribution; middle layer (line width ≤ 5μm) is for high-density signal wiring; surface layer (line width ≤ 5μm, low roughness) is suitable for high-frequency transmission and soldering. The thickness redundancy and stepped curing of this invention work together to significantly reduce the risk of warping and cracking, and improve insulation reliability.

[0040] Example 1 A glass-based double-sided multilayer wiring substrate, structural schematic diagram shown below. Figure 2 It includes a glass substrate, on both sides of which a first PI layer, a first copper wiring layer, a second PI layer, a second copper wiring layer, a third PI layer, and a third copper wiring layer are stacked sequentially (from the inside to the outside). The glass substrate is made of Schott Borofloat® 33 borosilicate glass with a thickness of 500 μm, a coefficient of thermal expansion (CTE) of 3.25 ppm / ℃ (25~300℃), a Young's modulus of 64 GPa, and a surface roughness Ra<1 nm. The glass substrate is pre-processed with TGV through-holes (50 μm diameter, 100 μm pitch), and Ti / Cu seed layers (Ti 50 nm, Cu 300 nm) are sputtered into the holes before being electroplated with copper filler. First PI layer: 5μm thick, CTE=10 ppm / ℃, rigid aromatic siloxane PI; First copper wiring layer: 3μm thick, 12μm line width, 10μm line spacing (power line), the line width of the connection line transitioning from the power area to the signal area gradually narrows from 12μm to 8μm; line width 15μm, line spacing 12μm (ground line). Second PI layer: 8μm thick, CTE=18 ppm / ℃, fluorine-modified PI; Second copper wiring layer: 3μm thickness, 5μm line width (signal line), annealed copper; Third PI layer: 5μm thickness, CTE=14 ppm / ℃, polyimide-polysiloxane copolymer; The third copper wiring layer has a thickness of 3 μm, a line width of 5 μm, and a Ra of 35 nm after CMP planarization. The surface is plated with Ni / Au.

[0041] The fabrication method of the above-mentioned glass-based double-sided multilayer wiring substrate, the process flow diagram is shown below. Figure 1 This includes the following steps: (1) Clean the glass substrate and perform oxygen plasma activation treatment (power 200W, 5min). (2) Spin-coating the first PI layer precursor solution on both sides of the glass substrate and performing step temperature rise curing to form the first PI layer; laser drilling (hole diameter 10μm) is performed on the TGV through hole of the glass substrate corresponding to the first PI layer to form a through hole through the first PI layer. The first PI layer precursor solution is polymerized in NMP solvent by dianhydride monomer ODPA and diamine monomer (ODA to GAPD molar ratio 85:15) in an equimolar ratio, with a solid content of 20 wt% and a viscosity of 2000-3000 cP (25℃). (3) The first copper wiring layer is prepared by a semi-addition method (sputtering Ti / Cr seed layer, photolithography, electroplating) and the vias of the first PI layer are filled at the same time; Semi-additive method: First, a Ti / Cr seed layer (Ti 50nm, Cr 100nm) is deposited by DC magnetron sputtering, followed by spin-coating of a positive photoresist (AZ4620, 5μm thickness), exposure and development to form the wiring pattern, and then copper electroplating (acidic copper plating solution, current density 1.5 A / dm³). 2 After removing the adhesive, the exposed copper seed layer is etched with ammonium persulfate to the preset thickness, and then the Cr layer is removed with Cr etching solution (cerium ammonium nitrate). (4) The first copper wiring layer is cleaned by oxygen plasma, the precursor solution of the second PI layer is spin-coated, and the second PI layer is cured by step temperature increase to form the second PI layer; the second PI layer is laser-drilled (hole diameter 10μm) to form a through hole through the second PI layer. The second PI layer precursor solution is prepared by polymerizing the dianhydride monomer hexafluorodianhydride (6FDA) and the diamine monomer 2,2'-bis(trifluoromethyl)-4,4'-diaminobiphenyl (TFMB) in an equimolar ratio in a solvent. The solvent is a mixed solvent of γ-butyrolactone (GBL) and N-methylpyrrolidone (NMP) (volume ratio 1:1), with a solid content of 25 wt% and a viscosity controlled at 2500~3500 cP (25℃). (5) The second copper wiring layer is prepared by a semi-addition method (sputtering Ti / Cr seed layer, photolithography, electroplating, refer to step (3)), while filling the vias of the second PI layer and performing annealing treatment. The annealing temperature was 250℃ and the time was 60 minutes. (6) The second copper wiring layer is cleaned by oxygen plasma, the precursor solution of the third PI layer is spin-coated, and the layer is cured by step temperature increase to form the third PI layer; the third PI layer is laser-drilled (hole diameter 10μm) to form a through hole through the third PI layer. The third PI layer precursor solution is polymerized from dianhydride monomer 3,3',4,4'-biphenyltetracarboxylic dianhydride (BPDA) and diamine monomer (4,4'-diaminodiphenyl ether (ODA) and aminopropyl-terminated polydimethylsiloxane (PDMS, number average molecular weight Mn≈1500, ODA:PDMS molar ratio = 90:10) in an equimolar ratio. The solvent is a NMP / toluene mixed solvent (volume ratio 4:1), the solid content is 22 wt%, and the viscosity is controlled at 1500~2500 cP (25℃). (7) The third copper wiring layer is prepared by a semi-addition method (sputtering Ti / Cr seed layer, photolithography, electroplating, refer to step (3)), and the vias of the third PI layer are filled at the same time. Then, chemical mechanical planarization is performed to the roughness Ra≤50nm, and Ni / Au (3μm / 0.1μm) is plated. The stepwise heating and curing process in steps (2), (4), and (6) above is as follows: each temperature is maintained at 80℃ / 120℃ / 150℃ / 180℃ / 220℃ / 250℃ for 30 minutes, with a heating rate of 5℃ / min, and the process is carried out in a nitrogen atmosphere throughout.

[0042] Comparative Example 1 A single PI layer (polyimide-polysiloxane copolymer) with a CTE of 14 ppm / ℃ was used, without a CTE gradient design; that is, the first, second, and third PI layers were all polyimide-polysiloxane copolymers with a CTE of 14 ppm / ℃. The polyimide-polysiloxane copolymer precursor solution was the same as the third PI layer precursor solution in Example 1. Everything else was the same as in Example 1.

[0043] After encapsulating chips on the glass-based double-sided multilayer wiring substrates of Example 1 and Comparative Example 1, the surface morphology was observed using an optical microscope. The results are as follows: Figure 3 , Figure 4 As shown: Example 1 has a smooth surface, without warping or cracking. Figure 3 ); Comparative Example 1 showed obvious microcracks and wrinkles ( Figure 4 This demonstrates that the CTE gradient design of the present invention effectively reduces interfacial thermal stress and avoids the generation of microcracks.

[0044] According to the thermoelastic multilayer beam model, the interfacial shear stress τ is proportional to the CTE difference Δα between adjacent layers. In Embodiment 1 of this invention, the CTEs of the three PI layers are 10 ppm / ℃, 18 ppm / ℃, and 14 ppm / ℃, respectively, with the maximum interlayer CTE difference being 8 ppm / ℃ (between the first and second layers) and 4 ppm / ℃ (between the second and third layers). In Comparative Example 1, the PI layer CTE is uniformly 14 ppm / ℃, and the CTE difference between the PI and the glass substrate (CTE≈3.25 ppm / ℃) is approximately 10.75 ppm / ℃, with this difference concentrated at a single interface, lacking gradient buffering. Theoretical calculations show that the gradient structure of this invention can reduce the maximum interfacial shear stress by more than 50%, thereby significantly reducing the risk of warping deformation and interfacial cracking. Those skilled in the art will understand that the above theoretical derivation is based on classical thermoelasticity, and the technical effects of this invention can be reasonably expected without relying on specific measured data. Therefore, this invention represents a significant technical advancement compared to Comparative Example 1.

[0045] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A glass-based double-sided multilayer wiring substrate, characterized in that, The system includes a glass substrate, on both sides of which PI layers and copper wiring layers are alternately stacked. The total number of PI layers and the total number of copper wiring layers on either side of the glass substrate are the same, both being three or more layers. The surface of the glass substrate is a PI layer, and the outermost layer is a copper wiring layer. From the surface of the glass substrate to the outermost layer, the coefficient of thermal expansion of each PI layer is a gradient structure from low to high and then back to low. The coefficient of thermal expansion of the PI layer on the surface of the glass substrate is less than that of the outermost PI layer.

2. The glass-based double-sided multilayer wiring substrate according to claim 1, characterized in that, The total number of PI layers and the total number of copper wiring layers on either side of the glass substrate are three. The glass substrate is provided with a first PI layer, a first copper wiring layer, a second PI layer, a second copper wiring layer, a third PI layer, and a third copper wiring layer stacked sequentially on both sides. The coefficient of thermal expansion of the first PI layer is smaller than that of the third PI layer, and the coefficient of thermal expansion of the second PI layer is larger than that of the third PI layer.

3. The glass-based double-sided multilayer wiring substrate according to claim 2, characterized in that, The coefficient of thermal expansion of the first PI layer is 8~12 ppm / ℃; the coefficient of thermal expansion of the second PI layer is 16~20 ppm / ℃; and the coefficient of thermal expansion of the third PI layer is 13~15 ppm / ℃.

4. The glass-based double-sided multilayer wiring substrate according to claim 2, characterized in that, The first PI layer is a rigid aromatic siloxane-containing polyimide; the second PI layer is a fluorine-modified polyimide; and the third PI layer is a polyimide-polysiloxane copolymer.

5. The glass-based double-sided multilayer wiring substrate according to claim 2, characterized in that, The linewidth of the first copper wiring layer is ≥10μm; the linewidth of the second copper wiring layer is ≤5μm; the linewidth of the third copper wiring layer is ≤5μm, and the surface roughness Ra is ≤50nm. The second copper wiring layer has higher ductility than the first copper wiring layer; The second copper wiring layer is annealed copper or copper with trace amounts of alloys added.

6. The glass-based double-sided multilayer wiring substrate according to any one of claims 1-5, characterized in that, The glass substrate is borosilicate glass; The total thickness of the PI layer on any side of the glass substrate shall not be less than 1.2 times the total thickness of the copper wiring layer; The outermost copper wiring layer is covered with a Ni / Au barrier layer.

7. The glass-based double-sided multilayer wiring substrate according to any one of claims 1-5, characterized in that, The PI layers are all formed by a stepped temperature curing process, which includes holding at 75-85℃, 115-125℃, 145-155℃, 175-185℃, 215-225℃ and 245-255℃ for 20-40 minutes each, and the stepped temperature curing process is carried out in a protective atmosphere.

8. The method for preparing a glass-based double-sided multilayer wiring substrate according to any one of claims 1-7, characterized in that, Includes the following steps: (1) Cleaning and plasma activation treatment of the glass substrate; (2) Spin-coating the PI layer precursor solution onto both sides of the glass substrate and then performing step-by-step temperature increase curing to form the PI layer; (3) A copper wiring layer was prepared using a semi-additive method; (4) Spin-coating the PI layer precursor solution and then performing stepwise temperature increase curing to form the PI layer; (5) A copper wiring layer was prepared using a semi-additive method; (6) Repeat steps (4) and (5) to prepare the PI layer and copper wiring layer to obtain a glass-based double-sided multilayer wiring substrate.

9. The method for preparing a glass-based double-sided multilayer wiring substrate according to claim 8, characterized in that, After preparing the final copper wiring layer, chemical mechanical planarization is performed on it. After preparing the final copper wiring layer, Ni / Au is plated onto it.

10. The application of the glass-based double-sided multilayer wiring substrate according to any one of claims 1-7 or the glass-based double-sided multilayer wiring substrate prepared by the preparation method according to any one of claims 8-9 in semiconductor packaging.

Images