Packaging structure and method for chip staggered stacking and interconnection by 3D printing

Abstract

This invention relates to the field of semiconductor packaging technology, specifically a packaging structure and method for achieving staggered stacking and interconnection of chips using 3D printing. A packaging structure for achieving staggered stacking and interconnection of chips using 3D printing includes chips, characterized in that: a plurality of chip units are stacked vertically and staggered from bottom to top on a substrate; the plurality of chip units are interconnected with pads using 3D printing material; each chip unit includes a wafer, pads, and a buffer protective layer; the top of the wafer is connected to the pads; the surfaces of the wafer and the pads are coated with a buffer protective layer; adjacent chip units are bonded together using a DAF film. Compared with the prior art, this invention provides a packaging structure and method for achieving staggered stacking and interconnection of chips using 3D printing, realizing the connection between upper and lower chips and between chips, and aligning and stacking chips together.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, specifically a packaging structure and method for achieving staggered stacking and interconnection of chips through 3D printing. Background Technology

[0002] With the ever-increasing demands for data storage capacity and access speed from consumer electronics, data centers, and mobile devices, achieving higher storage density flash memory devices within limited physical space has become a core requirement for industry development. Current methods in the packaging field to increase storage density involve integrating multiple chips vertically, thereby significantly improving storage capacity and integration without substantially increasing the planar area of ​​the package.

[0003] In stacked interconnect solutions, wire bonding has long been one of the mainstream technologies for realizing multi-layer flash memory chip stacking due to its advantages such as mature technology, low cost, wide process adaptability, and compatibility with existing packaging infrastructure. The basic process of this technology is as follows: First, multiple qualified flash memory chips are stacked layer by layer using an adhesive and a lead frame or substrate as a carrier; then, using a high-precision wire bonding machine, through the combined action of heat, pressure, and ultrasonic energy, one end of a fine metal wire (usually gold or copper wire) is bonded to the chip's pad, and the other end is bonded to the corresponding pin on the substrate or lead frame, thus forming an electrical interconnect path from the chip to the external world, such as... Figure 1 As shown.

[0004] Although wire bonding technology is widely used, its inherent technical limitations are becoming increasingly apparent when it comes to flash memory stacking applications with higher layer counts, smaller pitches, and higher speeds. These limitations are mainly reflected in the following aspects:

[0005] 1. There are limitations on the number of stackable layers and the "staircase" structure. To expose all chip pads, stacked chips typically need to be designed in a "pyramid" or "staircase" shape, meaning the upper chip must be smaller than the lower chip to expose the pad area of ​​the lower chip. This structure not only limits the maximum number of stackable chip layers but also increases the overall package height and complexity.

[0006] 2. Bottlenecks exist in interconnect length and electrical performance. The metal leads formed by wire bonding inherently possess high inductance and resistance. As the number of stacked layers increases, the lead length leading to the top-layer chip increases significantly, leading to signal transmission delay, increased resistance loss, and stronger parasitic inductance and capacitance effects. This severely restricts the operating performance of flash memory devices at high frequencies and increases the design difficulty of signal integrity.

[0007] 3. Challenges in I / O density and pad spacing. As chip functions become more complex, the number of I / Os continues to increase, while the miniaturization of chip size requires a continuous reduction in pad spacing. Wire bonding technology has a physical limit; when the pad spacing is too small, short circuits or interference between leads are very likely to occur, limiting the realization of high-density interconnects.

[0008] Therefore, there is an urgent need in the field for a new stacked interconnect solution that can overcome or mitigate the defects of the above-mentioned wire bonding technology, in order to further improve the electrical performance, reliability and production efficiency of flash memory devices while maintaining high integration. Summary of the Invention

[0009] To overcome the shortcomings of the prior art, this invention provides a packaging structure and method for achieving staggered stacking and interconnection of chips through 3D printing, realizing the connection between upper and lower chips and between chips, and aligning and stacking chips.

[0010] To achieve the above objectives, a packaging structure for staggered stacking and interconnection of chips via 3D printing is designed, comprising chips, characterized in that: a plurality of chip units are stacked vertically and staggered from bottom to top on a substrate, and the plurality of chip units are interconnected with pads by 3D printing material; each chip unit includes a wafer, pads, and a buffer protective layer, the top of the wafer is connected to the pads, and the surfaces of the wafer and the pads are coated with a buffer protective layer; adjacent chip units are bonded together by a DAF film.

[0011] The substrate is encapsulated with molding compound on the outside of several chip units and 3D printing materials, and balls are implanted at the bottom of the substrate.

[0012] The 3D printing material is 3D printing metal.

[0013] The buffer protective layer is polyimide.

[0014] The buffer protective layer is provided with a copper layer.

[0015] The pads are independently printed and are connected to the copper layer.

[0016] A method for achieving a staggered stacking and interconnection packaging structure of chips using 3D printing, characterized by the following specific process:

[0017] S1, Wafer arrival, cleaning and other preparation work: pads are drawn on the wafer surface;

[0018] S2, Draw grooves in the scribe line near the wafer pads;

[0019] S3, polyimide is coated on the surface of the wafer where the circuit has been fabricated as a buffer protective layer, and then the pad openings are precisely etched out by standard photolithography process.

[0020] S4, Electroplated copper layer: Connects the pads to the dicing groove;

[0021] S5, thin the back side of the wafer; or first thin it to a certain distance from the polyimide layer, and then continue to thin it until the polyimide layer is exposed by etching or dry plasma etching.

[0022] S6, Dicing: Retaining the copper layer in the dicing groove to form a chip unit structure with a copper layer on one side;

[0023] S7, several chip units are stacked vertically and staggered on the substrate in sequence;

[0024] S8, 3D printing or dispensing: Vertical interconnection of pads is achieved by printing metal connections individually or printing composite structures of metal and insulating materials to achieve conductivity and insulation.

[0025] S9, plastic sealing and ball packing;

[0026] S10, the substrate is cut into an independent chip to complete the entire packaging structure.

[0027] In step S2, a groove is formed in the dicing channel adjacent to the wafer pad by laser ablation or blade cutting, which is used in subsequent rewiring processes to form a structure in which copper interconnects climb within the groove.

[0028] The specific process of step S4 is as follows:

[0029] S41, on a wafer that has already formed a polyimide layer and pad openings, an adhesion layer and a copper seed layer are sequentially deposited by physical vapor deposition.

[0030] S42, Subsequently, a patterned photoresist mask is formed in the area to be electroplated using a photolithography process, exposing the predetermined electroplating path to be connected to the pads and the dicing groove.

[0031] S43, Next, the copper electroplating operation is performed: the wafer is used as the cathode and immersed in an electrolyte containing copper ions. Under the action of an external electric field, copper ions are reduced and deposited on the surface of the copper seed layer. Its growth is strictly limited to the photoresist opening area.

[0032] S44, the electroplated copper layer starts from the pad, extends along the preset path and finally fills the groove in the dicing channel, thereby forming a metal connection structure.

[0033] In step S6, before dicing, a DAF film is attached to the back of the wafer for subsequent chip stacking and bonding.

[0034] In step S8, the 3D printing material can interconnect the pads sequentially in the vertical direction, or skip some pads during the connection.

[0035] Compared with the prior art, the present invention provides a packaging structure and method for achieving staggered stacking and interconnection of chips through 3D printing, realizing the connection between upper and lower chips and between chips, and aligning and stacking chips.

[0036] This invention eliminates the metal rewiring structure within the groove and forms a stepped structure, providing support for 3D printed metal interconnects and avoiding the problem of slurry collapse. In particular, due to the protection of the sidewalls, each chip layer is staggered, and there are steps at the edges, so the slurry can be applied from top to bottom by dispensing to complete the manufacturing process. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a traditional chip packaging structure.

[0038] Figure 2 This is a schematic diagram of the chip packaging structure of the present invention.

[0039] Figure 3 This is a schematic diagram of step S1 in the chip packaging method of the present invention.

[0040] Figure 4 This is a schematic diagram of step S2 in the chip packaging method of the present invention.

[0041] Figure 5 This is a schematic diagram of step S3 in the chip packaging method of the present invention.

[0042] Figure 6 This is a schematic diagram of step S4 in the chip packaging method of the present invention.

[0043] Figure 7 This is a schematic diagram of step S5 in the chip packaging method of the present invention.

[0044] Figure 8 This is a schematic diagram of step S6 in the chip packaging method of the present invention.

[0045] Figure 9 This is a schematic diagram of step S7 in the chip packaging method of the present invention.

[0046] Figure 10 This is a schematic diagram of step S8 in the chip packaging method of the present invention.

[0047] Figure 11 This is a schematic diagram of step S9 in the chip packaging method of the present invention.

[0048] Figure 12 This is a schematic diagram of step S10 in the chip packaging method of the present invention.

[0049] Figure 13 This is a top view of the chip package of the present invention.

[0050] Figure 14 for Figure 13 A diagram showing the direction from right to left.

[0051] Figure 15 This is a structural diagram of another simplified embodiment of the present invention.

[0052] Figure 16 for Figure 15 Top view.

[0053] See Figure 2 , Figure 15 1 is the molding material, 2 is the 3D printing material, 3 is the copper layer, 4 is the buffer protective layer, 5 is the solder pad, 6 is the wafer, 7 is the substrate, and 8 is the DAF film. Detailed Implementation

[0054] The present invention will now be further described with reference to the accompanying drawings.

[0055] like Figure 2 As shown, the present invention realizes a packaging structure of staggered stacking and interconnection of chips through 3D printing, including chips. Several chip units are stacked vertically and staggered from bottom to top on a substrate 7. Several chip units are interconnected with pads through 3D printing material 2. The chip unit includes a wafer, pads, and a buffer protective layer. The top of the wafer 6 is connected to the pads 5. The surfaces of the wafer 6 and the pads 5 are coated with a buffer protective layer 4. Adjacent chip units are bonded together by a DAF film 8.

[0056] The substrate 7 is encapsulated by molding material 1 on the outside of several chip units and 3D printing material 2, and the bottom of the substrate 7 is planted with balls.

[0057] 3D printing material 2 is 3D printing metal.

[0058] The buffer protective layer 4 is made of polyimide.

[0059] A copper layer 3 is provided on the buffer protective layer 4.

[0060] Pad 5 is an independently printed pad, and pad 5 is connected to copper layer 3.

[0061] This structure connects the pads of stacked chips via 3D printing. The chips are stacked vertically but staggered, unlike wire-bonded stacks, the staggered distance is smaller, and an insulating layer is created on the sides to protect against leakage or short circuits caused by contact between the 3D-printed metals.

[0062] The metal rewiring structure within the groove was eliminated, and a stepped structure was formed to support the 3D printing of metal interconnects and avoid the problem of slurry collapse.

[0063] In particular, due to the protection of the sidewalls, each chip layer is staggered, and there are steps at the edges. The paste can also be applied from top to bottom by dispensing to complete the manufacturing process.

[0064] The process flow of this invention is as follows:

[0065] like Figure 3 As shown, the first step is: incoming wafers, and preparatory work such as cleaning is carried out.

[0066] Two pads are drawn on the wafer surface. This is understandable, as there is a chip array on the wafer surface. There are more than just two pads drawn; it means there is a pad array corresponding to many chips.

[0067] like Figure 4 As shown, the second step involves dicing grooves within the scribe line near the wafer pads. A groove is formed within the scribe line adjacent to the wafer pads using laser ablation or blade cutting. This groove is used in subsequent redistribution processes to create the structure for copper interconnects to climb within the groove, facilitating the connection between the 3D-printed metal connectors and the chip. Individual copper redistribution layers are often less than 5µm thick, resulting in a small contact area when connecting to the 3D-printed metal connectors. Forming metal interconnects within the groove effectively increases the contact area between the copper redistribution layer and the printed metal connectors.

[0068] like Figure 5 As shown, the third step is to coat the surface of the wafer with the completed circuit fabrication with polyimide (PI) as a buffer protective layer, and then precisely etch the pad openings using standard photolithography processes (including exposure and development).

[0069] like Figure 6 As shown, the fourth step is copper electroplating, which connects the pads to the dicing groove. On the wafer with the polyimide layer and pad openings already formed, an adhesion layer (such as titanium / titanium nitride) and a copper seed layer are sequentially deposited using a physical vapor deposition (PVD) process, such as sputtering. Subsequently, a patterned photoresist mask is formed in the area to be electroplated using a photolithography process, exposing the predetermined electroplating path to connect the pads to the dicing groove. Next, the copper electroplating operation is performed: the wafer is immersed in an electrolyte containing copper ions as the cathode. Under the action of an applied electric field, copper ions are reduced and deposited on the surface of the copper seed layer, and its growth is strictly limited to the photoresist opening area. The electroplated copper layer starts from the pads, extends along the predetermined path, and finally fills the grooves in the dicing groove, thereby forming a metal connection structure.

[0070] like Figure 7 As shown, the fifth step is to thin the back of the chip, which can involve thinning the polyimide layer.

[0071] Alternatively, the layer can be thinned to a certain distance from the polyimide layer, such as 10µm, and then further thinned to expose the polyimide layer by etching or dry plasma etching.

[0072] like Figure 8 As shown, step six: dicing, retaining the copper layer within the dicing groove to form individual structures with copper layers on one side. Before dicing, a DAF film, etc., is attached to the back of the chip for subsequent chip stacking and bonding.

[0073] like Figure 9 As shown, step seven: Chip stacking on the substrate. The difference from ordinary wire bonding is that the chip stacking structure is slightly staggered, providing steps for subsequent 3D printing or dispensing. Simultaneously, because the pads are connected to the chip edges through rewiring, the increased area of ​​the stacked chip is smaller than the area directly exposed for wire bonding.

[0074] like Figure 10 As shown, step eight: Vertically interconnect the pads using 3D printing material or adhesive. This can be achieved by printing individual metal connections or by printing a composite structure of metal and insulating material, thus achieving both electrical conductivity and insulation.

[0075] like Figure 11 As shown, step nine: sealing and ball planting.

[0076] like Figure 12 As shown, step ten: the substrate is cut into individual chip units. This completes the entire packaging structure.

[0077] like Figure 13 As shown, from a top-down view, each pad is an independently printed pad.

[0078] like Figure 14 As shown, the pads required for memory chip packaging are typically connected sequentially. However, some connections need to be bypassed or skipped, which is why 3D printing can still achieve this. The interconnection between the copper layer within the dicing groove and the 3D-printed RDL can skip some pads.

[0079] Because of the steps between the chips in the structure, the 3D-printed interconnects can run horizontally along the steps and then downwards. In the actual structure, the copper is covered by the 3D-printed metal interconnects. For ease of understanding, the copper rewiring areas of the chips in the diagram are still shown as copper.

[0080] Another embodiment, such as Figure 15 As shown, this is a simplified structure. When fabricating the redistribution layer, only a polyimide layer is applied, without an electroplated copper layer, eliminating the need for copper wire fabrication. The layers are directly stacked, and then 3D printed or glued to the pad surface to form connections. Figure 16As shown in the diagram. This structure eliminates the need for copper electroplating, thus reducing costs.

Claims

1. A packaging structure for staggered stacking and interconnection of chips achieved through 3D printing, comprising chips, characterized in that: Several chip units are stacked vertically and staggered from bottom to top on a substrate (7). Several chip units are interconnected with pads by 3D printing material (2). The chip unit includes a wafer, pads, and a buffer protection layer. The top of the wafer (6) is connected to the pads (5). The surfaces of the wafer (6) and the pads (5) are coated with a buffer protection layer (4). Adjacent chip units are bonded together by a DAF film (8).

2. The packaging structure for staggered stacking and interconnection of chips achieved by 3D printing according to claim 1, characterized in that: The outer side of several chip units and 3D printing material (2) is encapsulated by encapsulating material (1), and the bottom of the substrate (7) is planted with balls.

3. The packaging structure for staggered stacking and interconnection of chips achieved through 3D printing according to claim 1, characterized in that: The 3D printing material (2) is a 3D printing metal.

4. The packaging structure for staggered stacking and interconnection of chips achieved by 3D printing according to claim 1, characterized in that: The buffer protective layer (4) is polyimide.

5. The packaging structure for staggered stacking and interconnection of chips achieved by 3D printing according to claim 1, characterized in that: The buffer protective layer (4) is provided with a copper layer (3).

6. The packaging structure for staggered stacking and interconnection of chips achieved by 3D printing according to claim 1, characterized in that: The pad (5) is an independently printed pad, and the pad (5) is connected to the copper layer (3).

7. A method for realizing a packaging structure with staggered chip stacking and interconnection through 3D printing, characterized in that: The specific process is as follows: S1, Wafer arrival, cleaning and other preparation work: pads are drawn on the wafer surface; S2, Draw grooves in the scribe line near the wafer pads; S3, polyimide is coated on the surface of the wafer where the circuit has been fabricated as a buffer protective layer, and then the pad openings are precisely etched out by standard photolithography process. S4, Electroplated copper layer: Connects the pads to the dicing groove; S5, thin the back side of the wafer; or first thin it to a certain distance from the polyimide layer, and then continue to thin it until the polyimide layer is exposed by etching or dry plasma etching. S6, Dicing: Retaining the copper layer in the dicing groove to form a chip unit structure with a copper layer on one side; S7, several chip units are stacked vertically and staggered on the substrate in sequence; S8, 3D printing or dispensing: Vertical interconnection of pads is achieved by printing metal connections individually or printing composite structures of metal and insulating materials to achieve conductivity and insulation. S9, plastic sealing and ball packing; S10, the substrate is cut into an independent chip to complete the entire packaging structure.

8. The method for realizing a packaging structure with staggered chip stacking and interconnection by 3D printing according to claim 6, characterized in that: In step S2, a groove is formed in the dicing channel adjacent to the wafer pad by laser ablation or blade cutting, which is used in subsequent rewiring processes to form a structure in which copper interconnects climb within the groove.

9. The method for realizing a staggered stacking and interconnection packaging structure of chips by 3D printing according to claim 6, characterized in that: The specific process of step S4 is as follows: S41, on a wafer that has already formed a polyimide layer and pad openings, an adhesion layer and a copper seed layer are sequentially deposited by physical vapor deposition. S42, Subsequently, a patterned photoresist mask is formed in the area to be electroplated using a photolithography process, exposing the predetermined electroplating path to be connected to the pads and the dicing groove. S43, Next, the copper electroplating operation is performed: the wafer is used as the cathode and immersed in an electrolyte containing copper ions. Under the action of an external electric field, copper ions are reduced and deposited on the surface of the copper seed layer. Its growth is strictly limited to the photoresist opening area. S44, the electroplated copper layer starts from the pad, extends along the preset path and finally fills the groove in the dicing channel, thereby forming a metal connection structure.

10. The method for realizing a chip staggered stacking and interconnection packaging structure by 3D printing according to claim 6, characterized in that: In step S6, before dicing, a DAF film is attached to the back of the wafer for subsequent chip stacking and bonding.

11. The method for realizing a staggered stacking and interconnection packaging structure of chips by 3D printing according to claim 6, characterized in that: In step S8, the 3D printing material can interconnect the pads sequentially in the vertical direction, or skip some pads during the connection.

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