Automatic precision selection in neural network models

Abstract

Processors, systems, and techniques are disclosed for efficiently selecting different precision numerical encoding formats for processing within a neural network. In at least one embodiment, tensor data for respective layers of a neural network can be quantized during or after training according to a plurality of low-precision formats, and a preferred encoding format is selected based at least on quantization error for the tensor data.

Description

Technical Field

[0001] At least one embodiment relates to a processor or computing system for efficiently selecting a digital encoding format for a neural network. Background Technology

[0002] Training and operating neural networks consumes significant amounts of memory, time, and computational resources. Low-precision encoding formats are often used to enable rapidly growing neural networks, aiming for higher network performance and improved memory efficiency. Existing techniques for selecting encoding formats include manually recommending formats for specific network layers or tensor types. Attached Figure Description

[0003] Figure 1 The illustration shows an example of a machine learning platform according to at least one embodiment, which automatically selects a low-precision data format to process a neural network model; Figure 2 The illustration shows an example of the data distribution of tensors in a neural network model according to at least one embodiment; Figure 3A The illustration shows a low-precision quantization of the data distribution of tensors in a neural network model according to at least one embodiment; Figure 3B The illustration shows the quantization error of low-precision quantization of the data distribution of tensors in a neural network model according to at least one embodiment; Figure 4 This is a flowchart illustrating the automatic selection of a low-precision data format for a portion used in a neural network according to at least one embodiment; Figure 5 This is a flowchart illustrating the calibration of a pre-trained neural network model for automatically selecting low-precision data formats according to at least one embodiment. Figure 6 The illustration shows a mimicry mask for quantization of high-precision data tensors according to at least one embodiment; Figure 7 This is a sequence diagram illustrating the quantization of a high-precision data tensor according to at least one embodiment; Figure 8 This is a flowchart illustrating the quantization of a high-precision data tensor according to at least one embodiment; Figure 9 An example of a machine learning platform according to at least one embodiment is illustrated, which automatically selects a low-precision data format to process a neural network model during model training. Figure 10 The illustration depicts a mimicry mask according to at least one embodiment for automatically selecting a low-precision data format for processing a neural network model during model training. Figure 11This is a flowchart illustrating the automatic selection of a low-precision data format for processing a neural network model during model training, according to at least one embodiment. Figure 12A The logic according to at least one embodiment is shown; Figure 12B The logic according to at least one embodiment is shown; Figure 13 The training and deployment of a neural network according to at least one embodiment are illustrated; Figure 14 An example data center system according to at least one embodiment is shown; Figure 15A An example of an autonomous vehicle according to at least one embodiment is shown; Figure 15B The illustration shows an embodiment according to at least one of the embodiments. Figure 15A Examples of camera positions and field of view for autonomous vehicles; Figure 15C This is an illustration based on at least one embodiment. Figure 15A A block diagram of an example system architecture for an autonomous vehicle; Figure 15D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 15A A diagram of a system for communication between autonomous vehicles; Figure 16 This is a block diagram illustrating a computer system according to at least one embodiment; Figure 17 This is a block diagram illustrating a computer system according to at least one embodiment; Figure 18 A computer system according to at least one embodiment is shown; Figure 19 A computer system according to at least one embodiment is shown; Figure 20A A computer system according to at least one embodiment is shown; Figure 20B A computer system according to at least one embodiment is shown; Figure 20C A computer system according to at least one embodiment is shown; Figure 20D A computer system according to at least one embodiment is shown; Figure 20E and Figure 20F A shared programming model according to at least one embodiment is shown; Figure 21 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown; Figures 22A-22B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown; Figures 23A-23B Additional exemplary graphics processor logic according to at least one embodiment is shown; Figure 24 A computer system according to at least one embodiment is shown; Figure 25A A parallel processor according to at least one embodiment is shown; Figure 25B A partitioning unit according to at least one embodiment is shown; Figure 25C A processing cluster according to at least one embodiment is shown; Figure 25D A graphics multiprocessor according to at least one embodiment is shown; Figure 26 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated; Figure 27 A graphics processor according to at least one embodiment is shown; Figure 28 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Figure 29 A deep learning application processor according to at least one embodiment is shown; Figure 30 A block diagram of an example neuromorphic processor is shown according to at least one embodiment; Figure 31 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 32 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 33 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 34 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Figure 35 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment; Figures 36A-36B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core; Figure 37 A parallel processing unit (“PPU”) according to at least one embodiment is shown. Figure 38A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated. Figure 39 A memory partitioning unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown; Figure 40 A streaming multiprocessor according to at least one embodiment is illustrated; Figure 41 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment; Figure 42 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment; Figure 43 Example illustrations of an advanced computing pipeline for processing imaging data according to at least one embodiment; Figure 44A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment; Figure 44B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment; Figure 45A A data flow diagram of a process for training a machine learning model according to at least one embodiment is shown; Figure 45B This is an example illustration of a client-server architecture for enhancing annotation tools using a pre-trained annotation model, according to at least one embodiment; and Figure 46 Components of a system for accessing a large language model according to at least one embodiment are shown. Specific Implementation Figure 1An example of a machine learning platform according to at least one embodiment is illustrated, which automatically selects a low-precision data format to process a neural network model. In at least one embodiment, in numerical representation or data format, an integer format can store precise values ​​but has a limited dynamic range, where the dynamic range is the ratio between the minimum and maximum values ​​that can be represented in the format. In contrast, in at least one embodiment, a floating-point format can store imprecise values ​​but has a larger dynamic range compared to an integer format of the same size, where the floating-point value is a positive or negative integer with a decimal point, and the floating-point precision describes the number of significant digits that the floating-point value can have after the decimal point. In at least one embodiment, the floating-point format may include a sign bit, a plurality of mantissa bits storing a normalized value, and a plurality of exponent bits representing a normalization operation performed to produce the mantissa value. In at least one embodiment, different floating-point and integer formats can be employed for a given total number of bits to balance dynamic range and precision within a given memory and computational efficiency.

[0005] In at least one embodiment, the neural network may include a high-precision model 100 consisting of a plurality of processing blocks 102, wherein each processing block may include one or more neural network convolutional layers, neural network building blocks, or other portions of the neural network including high-precision tensor data 104. In at least one embodiment, high precision may be a data format that provides both high precision and suitable dynamic range for the application by using a larger number of total data bits. In at least one embodiment, a high-precision model may represent data with low quantization error at the cost of higher memory usage and greater computational cost.

[0006] In at least one embodiment, tensor data can be data that is stored, represented, or processed as tensors. In at least one embodiment, a tensor can be a data structure comprising multiple matrices, wherein each matrix in the tensor can include one or more row values ​​and one or more column values. In at least one embodiment, tensor data can store or represent weight values ​​of a neural network. In at least one embodiment, tensor data can store or represent activation or output values ​​determined as a result of one or more computations (e.g., matrix multiplication) performed at a node or layer of a neural network. In at least one embodiment, the high-precision model 100 can be pre-trained using training data 106 to generate high-precision tensor data 104 for each processing block 102. In at least one embodiment, the high-precision model 100 can use one or more processors (such as those described below). Figure 16The high-precision tensor data can be implemented as shown in the diagram and can be encoded in a high-precision format such as FP32, FP64, and / or INT32. In at least one embodiment, the processing block 102 can implement various functions, including patch partitioning, embedding, transformation, etc. In at least one embodiment, the low-precision format can be partially determined based on the functionality of the processing block 102. In at least one embodiment, low precision can be a data format that uses a small number of data bits and provides a trade-off between precision and dynamic range for the application. In at least one embodiment, the low-precision model introduces high quantization error but provides improvements in memory usage and computational cost.

[0007] In at least one embodiment, a pre-trained high-precision model 100 may be provided to a calibrator 110 to quantize at least a portion of the high-precision tensor data 104 of processing block 102, thereby generating a quantized tensor 112 for each processing block 102 and low-precision format 120. In at least one embodiment, quantization may be a technique for approximating continuous or higher-precision values ​​(such as weights or attention values ​​of a neural network) with a discrete representation of lower precision, thereby reducing memory and / or storage device utilization and decreasing processing utilization. In at least one embodiment, quantization may be applied to reduce the size of the neural network by changing the values, since continuous or higher-precision values ​​can be stored or represented in a larger number format, while lower-precision values ​​can be stored or represented in a smaller number format, wherein the larger format uses more storage space (e.g., bits) and the smaller format uses less storage space. In at least one embodiment, examples of low-precision format 120 include various encodings of integer (e.g., INT8) and floating-point (e.g., FP8) data types, including but not limited to E3M4, E4M3, and E5M2. Other examples of low-precision format 120 may be used in at least one embodiment. In at least one embodiment, low-precision format 120 may exclude some formats that can be used for encoding for reasons such as performance, software support, applicability of processing block types, etc.

[0008] In at least one embodiment, the quantized tensor 112 can be evaluated relative to the corresponding high-precision tensor data 104 to measure the accuracy of the determined corresponding quantization error 114, wherein a low quantization error indicates high accuracy and a high quantization error indicates low accuracy. In at least one embodiment, the quantization error can be determined using, for example, mean square error (MSE) techniques, but any number of techniques can be used to determine the quantization error. In at least one embodiment, once the quantization error 114 of each low-precision format 120 is determined, a format selection operation 116 can be performed by the calibrator 110 to determine the optimal low-precision format 120 for a given processing block 102. In at least one embodiment, format selection can be performed at least in part based on the determined minimum quantization error, but other considerations, such as computational efficiency, can also be taken into account.

[0009] In at least one embodiment, once the calibrator 110 has the selected format for processing block 102, it can generate a low-precision model 130, which includes the tensor data of processing block 132 as low-precision tensor data 134. In at least one embodiment, the low-precision model 130 can then be used to process data input 136 to generate data output 138.

[0010] Figure 2 An example of tensor data distribution in a neural network model according to at least one embodiment is illustrated. In at least one embodiment, tensor data (such as...) Figure 1 When the tensor data 104 is encoded in a high-precision format, it exhibits a tensor data distribution with low quantization error and a value of 200. In at least one embodiment, the tensor data distribution 200 may include a dynamic range and precision that, when quantized to a low-precision format, may dictate the quantization error, as discussed below in Figure 3.

[0011] Figure 3A The illustration shows low-precision quantization of the data distribution of tensors in a neural network model according to at least one embodiment. In at least one embodiment, tensor data (such as...) Figure 1 Tensor data 104, when encoded in a high-precision format, exhibits low quantization error and a tensor data distribution. In at least one embodiment, when quantized to one or more low-precision formats (such as E5M2, E4M3, E3M4, and / or INT8), the tensor data distribution can generate discrete sample values ​​exhibiting significant quantization error. For example, tensor data distributions (such as...) Figure 2 Tensor data distribution 200 can generate discrete, low-precision tensor data distribution 300.

[0012] Figure 3BThe illustration depicts the quantization error of low-precision quantization of tensor data distribution in a neural network model according to at least one embodiment. In at least one embodiment, tensor data (such as...) Figure 1 Tensor data 104) when Figure 2 When the data shown is encoded in various low-precision formats (such as E5M2, E4M3, E3M4, and / or INT8), it exhibits significant quantization errors. In at least one embodiment, the quantization error can be determined using, for example, mean squared error (MSE) techniques, but any number of techniques can be used to determine the quantization error. In at least one embodiment, low-precision tensor data distributions (such as...) Figure 2 The low-precision tensor data distribution shown in Figure 200 will produce quantization error determinations in various formats E5M2, E4M3, E3M4 and / or INT8 310.

[0013] Figure 4 This is a flowchart illustrating the automatic selection of low-precision data formats for various parts of a neural network according to at least one embodiment. In at least one embodiment, the neural network may include a model, such as Figure 1 The high-precision model 100 includes high-precision tensor data, such as... Figure 1 High-precision tensor data 140. In at least one embodiment, the tensor data can store or represent the weight values ​​of a neural network, such as those described below. Figure 13 As discussed in the previous section. In at least one embodiment, tensor data may also store or represent activation or output values ​​determined as the result of one or more computations (e.g., matrix multiplication) performed at a node or layer of a neural network.

[0014] In at least one embodiment, as shown in 400, weights within different parts of the neural network can be quantized or quantized to achieve, for example, improved neural network performance and memory efficiency. In at least one embodiment, quantization is a technique for approximating continuous or higher-precision values ​​(such as weight values ​​or decay values ​​of a neural network) with a lower-precision discrete representation, thereby reducing memory and / or storage device utilization and decreasing processing utilization. In at least one embodiment, quantization can be performed after the neural network has been trained (as shown below). Figure 5 (as discussed in the text), or performed during training (such as below). Figure 9-11 (As discussed in the text).

[0015] In at least one embodiment, as shown in 410, the accuracy of each part of the neural network can then be measured based on the quantization of weights within those parts of the neural network. In at least one embodiment, the accuracy can indicate the quality or correctness of the inference generated by the neural network. In at least one embodiment, the accuracy of a specific part of the neural network (e.g., a layer or individual neurons) can be determined such that different corresponding low-precision formats can be applied to different layers or other parts of the neural network (e.g., quantizing different neural network layers with different low-precision formats in the same neural network) to achieve optimal accuracy for a smaller neural network using weight quantization. In at least one embodiment, identifying and applying quantization using part-specific measurements can allow a smaller neural network to maintain high correctness or high-quality inference. In at least one embodiment, the measured accuracy can produce a characterization of the quantization error of each part of the neural network, where the quantization error can be used to select the optimal low-precision format to minimize the quantization error, as follows: Figure 5 This will be discussed in further detail below. In at least one embodiment, the measured accuracy can be integrated into the loss function to optimize the training of the neural network, as follows: Figure 11 This will be discussed in further detail later.

[0016] Figure 5 This is a flowchart illustrating the calibration of a pre-trained neural network model for automatically selecting low-precision data formats according to at least one embodiment. In at least one embodiment, the neural network model (such as...) Figure 1 A high-precision model 100 can be pre-trained to generate tensor data for one or more neural networks, such as high-precision tensor data 104, wherein the tensor data is encoded in one or more high-precision formats, as shown in 500. In at least one embodiment, as shown in 510, a layer of the neural network (such as...) can be selected. Figure 1 The processing block 102) is calibrated to use a low-precision format (such as, by...). Figure 1 (The calibrator 110). In at least one embodiment, various low-precision formats can be considered, such as Figure 1 The low-precision format 120 includes INT8 and FP8 data types (including E3M4, E4M3, and E5M2). However, these are merely examples and are not intended to be restrictive.

[0017] In at least one embodiment, as shown in 520, the high-precision tensor data can then be quantized and encoded into each of a plurality of low-precision formats. In at least one embodiment, these low-precision formats can be selected for suitability, performance, software support, hardware support, etc. In at least one embodiment, low-precision formats can exclude one or more formats that are unsuitable for the selected layer or are not well supported by hardware or software. In at least one embodiment, the values ​​of tensor data can be quantized from high-precision formats to target low-precision formats in a single operation, while in at least another embodiment, quantization can be performed iteratively, as follows: Figure 6-8 As discussed in [the document]. In at least one embodiment, once a low-precision quantized tensor (such as [the tensor]) has been generated... Figure 1 The quantized tensor (112) can be evaluated relative to the corresponding high-precision tensor data to determine the corresponding quantization error, such as... Figure 1 The quantization error is 114. In at least one embodiment, the quantization error can be determined using, for example, the mean square error (MSE) technique, but any number of techniques can be used to determine the quantization error.

[0018] In at least one embodiment, as shown in 530, a low-precision format, such as, can be selected for the neural network layer, at least based on the minimum quantization error. Figure 1 The format selection 116 is shown. In at least one embodiment, the format selection may be performed at least in part based on the determined minimum quantization error, but other considerations, such as computational efficiency, may also be taken into account.

[0019] In at least one embodiment, if an additional layer remains (as indicated by the positive exit at 540), the process can return to 510. If no additional layer remains (as indicated by the negative exit at 540), the process completes.

[0020] Figure 6 The illustration depicts a mimic mask for quantizing high-precision data tensors according to at least one embodiment. In at least one embodiment, mimic masks or simulation masks 600 and 610 can be used to specify tensor data (such as, e.g., ...). Figure 1The high-precision tensor data 104 and the quantized tensor 112 shown are encoded or simulated in a specific encoding format. In at least one embodiment, the emulation mask 600 may include 25% of randomly distributed elements indicating that a low-precision format should be used or simulated, while the emulation mask 610 may include 50% of randomly distributed elements indicating that a low-precision format should be used or simulated. In at least one embodiment, other elements of the tensor data may remain encoded in a high-precision format. In at least one embodiment, emulation masks with different padding percentages may include overlapping or non-overlapping low-precision elements.

[0021] Figure 7 This is a sequence diagram illustrating the quantization of a high-precision data tensor according to at least one embodiment. In at least one embodiment, the input tensor 700 can be encoded in a high-precision format and using an emulation mask (such as...) Figure 6 The 600-degree imitation mask is used for masking.

[0022] In at least one embodiment, elements of the input tensor 700, specified by the imitation mask as encoded in a low-precision format, are quantized while remaining encoded in the original high-precision format, while other elements remain unchanged. In at least one embodiment, this process produces a masked tensor 720, which, combined with the original input tensor, can be used to perform fine-tuning or re-tuning 730 on a neural network layer using the input tensor. In at least one embodiment, re-tuning 730 can minimize the quantization error of full or partial quantization specified by the imitation mask 710. In at least one embodiment, re-tuning 730 can then generate an output tensor 740, which can include the individual elements quantized in the simulated low-precision format while remaining encoded in the high-precision format. In at least one embodiment, this can then be implemented iteratively. Figure 7 The process shown below, where output tensor 740 is used as input tensor 700 for subsequent iterations, is as follows: Figure 8 As described in [the text].

[0023] Figure 8 This is a flowchart illustrating the quantization of a high-precision data tensor according to at least one embodiment. In at least one embodiment, a mask (such as...) is used to simulate... Figure 6The emulation mask 600 can be associated with an input tensor encoded in a high-precision format. In at least one embodiment, the input tensor can be encoded as high-precision tensor data in a high-precision format, such as FP32, FP64, INT32, etc. In at least one embodiment, the associated emulation mask may include a percentage of randomly distributed elements indicating that a low-precision format should be used or simulated. In at least one embodiment, other elements of the tensor data can remain quantized in a high-precision format, as indicated by the emulation mask.

[0024] In at least one embodiment, as shown in 810, elements of the input tensor to be simulated, which is specified by the mimicry mask as being encoded in a low-precision format, are quantized while remaining encoded in the original high-precision format, while other elements remain unchanged. In at least one embodiment, this process produces a masking tensor, such as... Figure 7 The masking tensor 720. In at least one embodiment, the masking tensor can be evaluated relative to the input tensor to determine the quantization error. In at least one embodiment, the quantization error can be determined using, for example, mean squared error (MSE) techniques, but any number of techniques can be used to determine the quantization error.

[0025] In at least one embodiment, as shown in 820, the combination of the masking tensor and the input tensor can be used to perform fine-tuning or retuning on a neural network layer that employs the input tensor, such as... Figure 7 The recovery tuning 730. In at least one embodiment, the recovery tuning can minimize the quantization error of full or partial quantization specified by the emulation mask. In at least one embodiment, the recovery tuning can then generate an output tensor, such as... Figure 7 The output tensor 740 can include various elements that are quantized in a low-precision analog format while retaining their high-precision encoding.

[0026] In at least one embodiment, if the percentage used in the emulation mask is 100%, as indicated by the positive exit at 820, the input tensor is fully quantized, and the process is complete. If the percentage used in the emulation mask is less than 100%, as indicated by the negative exit at 820, the process can proceed to 840. In at least one embodiment, as shown at 840, the percentage of randomly distributed low-precision elements can be increased, and a new emulation mask can be generated. In at least one embodiment, different emulation masks may include overlapping or non-overlapping low-precision elements. In at least one embodiment, the process can then return to 810.

[0027] Figure 9An example of a machine learning platform according to at least one embodiment is illustrated, which automatically selects a low-precision data format to process a neural network model during model training. In at least one embodiment, the neural network may include a high-precision training model 900 consisting of a plurality of processing blocks 902, wherein each of the processing blocks may include one or more neural network layers (or other portions of the neural network) comprising high-precision tensor data 904. In at least one embodiment, the high-precision training model may be trained using training data 906 to generate high-precision tensor data 904 for each processing block 902. In at least one embodiment, a mimicry mask 906 may be employed to indicate that the individual elements of the high-precision data 904 should mimic the low-precision format 920.

[0028] In at least one embodiment, elements of high-precision tensor data 904 can be quantized according to an emulation mask 906 to simulate low-precision tensor data according to low-precision format 920. Quantization can be considered a technique for approximating continuous or higher-precision values ​​with a discrete representation of lower precision, thereby reducing memory and / or storage device requirements, processing requirements, and the cost of lower precision. In at least one embodiment, examples of low-precision format 120 include various encodings of INT8 and FP8 data types, including E3M4, E4M3, and E5M2. In at least one embodiment, other types of low-precision formats can be implemented, and these examples are not intended to be limiting. In at least one embodiment, low-precision format 120 may exclude some formats that can be used for encoding for reasons such as performance, software support, suitability for processing block types, etc.

[0029] In at least one embodiment, training model 900 can be implemented using one or more processors (such as those described below). Figure 16 As shown in the diagram), high-precision tensor data can be encoded in high-precision formats (such as FP32, FP64, INT32, etc.). Furthermore, in at least one embodiment, processing block 902 can implement various functions, including tile partitioning, embedding, transformation, etc. In at least one embodiment, the low-precision format can be partially determined based on the functionality of processing block 102.

[0030] In at least one embodiment, once training is complete, one or more low-precision formats can be selected based on the lowest loss function observed during training. In at least one embodiment, the loss function may include consideration of the determined minimum quantization error, but may also consider other considerations such as computational efficiency. In at least one embodiment, once a low-precision format has been selected for processing block 102, a low-precision model 930 can be generated, which includes tensor data of processing block 932 as low-precision tensor data 934. In at least one embodiment, the low-precision model 930 can then be used to process data input 936 to generate data output 938.

[0031] Figure 10 The illustration depicts a mimicry mask according to at least one embodiment for automatically selecting a low-precision data format for processing a neural network model during model training.

[0032] In at least one embodiment, the mimic mask or analog mask 1000 can be used to specify tensor data (such as... Figure 1 The high-precision tensor data 104 and the quantized tensor 112 shown are encoded or simulated encoding formats for their respective elements. The emulation mask 1000 may include elements indicating that various low-precision formats should be used or simulated. For example, the emulation mask 1000 indicates that a portion of the tensor data elements (shown in white) should simulate low-precision format A, while other portions of the tensor data elements (shown in black) should simulate low-precision format B. Although... Figure 10 The emulation mask illustrates two different low-precision formats, but this example is not intended to be restrictive and any number of formats can be used.

[0033] Figure 11 This is a flowchart illustrating the automatic selection of a low-precision data format for processing a neural network model during model training, according to at least one embodiment. In at least one embodiment, as shown in 1100, for a specific layer of the neural network, a mimicking mask (such as...) is used. Figure 10 The emulation mask (1000) can be associated with a layer. In at least one embodiment, the associated emulation mask can specify specific elements of the tensor data that should be simulated using various low-precision formats.

[0034] In at least one embodiment, as shown in 1110, performance metrics may be incorporated into the loss function for training the neural network. In at least one embodiment, these metrics may include at least a quantization error metric, but may also incorporate other metrics, such as computational efficiency. In at least one embodiment, the quantization error may be determined using, for example, a mean squared error (MSE) technique, but any number of techniques may be used to determine the quantization error.

[0035] In at least one embodiment, as shown in 1120, the neural network can then be trained and optimized using a modified loss function that incorporates at least a quantization error metric. By training with the modified loss function, in at least one embodiment, the neural network can be optimized to use one or more low-precision formats specified in the mimicry mask.

[0036] In at least one embodiment, as shown in 1130, after training is complete, the minimum loss function can indicate one or more low-precision formats of a specific mimicry mask that should be selected for the corresponding layer of the neural network. In at least one embodiment, as shown in 1140, one or more high-precision formats can be replaced with the selected low-precision format to produce an optimal neural network model optimized according to the loss function, thereby minimizing the quantization error of the selected low-precision format.

[0037] logic Figure 12A A logic 1215 according to at least one embodiment is illustrated. As described elsewhere herein, this logic can be used in one or more devices to perform the operations discussed herein. In at least one embodiment, logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 1215 is inference and / or training logic. The following is in conjunction with... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic for providing the functions or operations described herein, wherein the logic may collectively or individually be embodied as a circuit system forming part of a larger system (e.g., an integrated circuit (IC), a system-on-a-chip (SoC), or one or more processors (e.g., a CPU, a GPU)).

[0038] In at least one embodiment, logic 1215 may include, but is not limited to, code and / or data storage 1201 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, logic 1215 may include or be coupled to code and / or data storage 1201 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 1201 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 1201 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0039] In at least one embodiment, any portion of the code and / or data storage 1201 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1201 may be a cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 1201 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, may depend on the on-chip versus off-chip available storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0040] In at least one embodiment, logic 1215 may include, but is not limited to, code and / or data storage 1205 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in one or more aspects of the embodiments. In at least one embodiment, during training and / or inference using one or more aspects of the embodiments, code and / or data storage 1205 stores weight parameters and / or input / output data of each layer of the neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, logic 1215 may include or be coupled to code and / or data storage 1205 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0041] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 1205 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 1205 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1205 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 1205 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0042] In at least one embodiment, code and / or data storage 1201 and code and / or data storage 1205 may be separate storage structures. In at least one embodiment, code and / or data storage 1201 and code and / or data storage 1205 may be the same storage structure. In at least one embodiment, code and / or data storage 1201 and code and / or data storage 1205 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 1201 and code and / or data storage 1205 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0043] In at least one embodiment, logic 1215 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1210 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 1220, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1201 and / or code and / or data storage 1205. In at least one embodiment, activations stored in activation storage 1220 are generated based on linear algebra and / or matrix-based mathematics performed by ALU 1210 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data storage 1205 and / or code and / or data storage 1201 are used as operands, and other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, may be stored in code and / or data storage 1205 or code and / or data storage 1201 or other on-chip or off-chip storage.

[0044] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 1210, while in another embodiment, one or more ALUs 1210 may be external to the processor or other hardware logic device or the circuitry that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 1210 may be included within an execution unit of a processor, or otherwise included in an ALU bank accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 1201, code and / or data storage 1205, and activation storage 1220 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 1220 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0045] In at least one embodiment, the active memory 1220 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 1220 may be entirely or partially located within or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 1220 is internal to or external to the processor, for example, or including DRAM, SRAM, flash memory, or certain other memory types, may depend on the available on-chip versus off-chip memory, the latency requirements for performing training and / or inference functions, the batch size of the data used in inference and / or training the neural network, or some combination of these factors.

[0046] In at least one embodiment, Figure 12A The logic 1215 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor from Intel (e.g., “Lake Crest”). In at least one embodiment, Figure 12AThe logic 1215 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”).

[0047] Figure 12B A logic 1215 according to at least one embodiment is illustrated. In at least one embodiment, the logic 1215 is inference and / or training logic. In at least one embodiment, the logic 1215 may include, but is not limited to, hardware logic, wherein computational resources, along with weight values ​​or other information corresponding to one or more layers of neurons within a neural network, are used dedicatedly or otherwise exclusively. In at least one embodiment, Figure 12B The logic 1215 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor from Intel (e.g., “Lake Crest”). In at least one embodiment, Figure 12B The logic 1215 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, logic 1215 includes, but is not limited to, code and / or data storage 1201 and code and / or data storage 1205, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 12B In at least one embodiment shown, each of code and / or data storage 1201 and code and / or data storage 1205 is associated with dedicated computing resources (e.g., computing hardware 1202 and computing hardware 1206), respectively. In at least one embodiment, each of computing hardware 1202 and computing hardware 1206 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on the information stored in code and / or data storage 1201 and code and / or data storage 1205, respectively, with the results stored in active storage 1220.

[0048] In at least one embodiment, each of the code and / or data storage 1201 and 1205 and the corresponding computing hardware 1202 and 1206 corresponds to a different layer of the neural network, such that an activation obtained from one storage / computation pair 1201 / 1202 of the code and / or data storage 1201 and computing hardware 1202 is provided as input to the next storage / computation pair 1205 / 1206 of the code and / or data storage 1205 and computing hardware 1206, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 1201 / 1202 and 1205 / 1206 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) may be included in logic 1215 following or paralleling the storage / computation pairs 1201 / 1202 and 1205 / 1206.

[0049] Neural network training and deployment Figure 13 Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 1306 is trained using a training dataset 1302. In at least one embodiment, the training framework 1304 is the PyTorch framework, while in other embodiments, the training framework 1304 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1304 trains the untrained neural network 1306 and enables it to be trained using the processing resources described herein to generate a trained neural network 1308. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner.

[0050] In at least one embodiment, supervised learning is used to train an untrained neural network 1306, wherein the training dataset 1302 includes inputs paired with desired outputs for input, or wherein the training dataset 1302 includes inputs with known outputs and the outputs of the neural network 1306 are manually graded. In at least one embodiment, the untrained neural network 1306 is trained in a supervised manner and processes inputs from the training dataset 1302, comparing the resulting outputs with a set of expected or desired outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 1306. In at least one embodiment, a training framework 1304 adjusts the weights controlling the untrained neural network 1306. In at least one embodiment, the training framework 1304 includes tools for monitoring the degree to which the untrained neural network 1306 converges to a model (such as a trained neural network 1308) suitable for generating correct answers (such as result 1314) based on input data (such as a new dataset 1312). In at least one embodiment, the training framework 1304 repeatedly trains the untrained neural network 1306 while adjusting the weights to refine the output of the untrained neural network 1306 using a loss function and tuning algorithms such as stochastic gradient descent. In at least one embodiment, the training framework 1304 trains the untrained neural network 1306 until the untrained neural network 1306 reaches the desired accuracy. In at least one embodiment, the trained neural network 1308 can then be deployed to implement any number of machine learning operations.

[0051] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1306, wherein the untrained neural network 1306 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1302 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 1306 can learn groupings within the training dataset 1302 and can determine how each input relates to the untrained dataset 1302. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 1308, which is capable of performing operations useful for reducing the dimensionality of the new dataset 1312. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 1312 that deviate from the normal patterns of the new dataset 1312.

[0052] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1302. In at least one embodiment, the training framework 1304 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1308 to adapt to a new dataset 1312 without forgetting the knowledge injected into the trained neural network 1308 during initial training.

[0053] In at least one embodiment, the training framework 1304 is a framework that incorporates processing via a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is, for example, a toolkit developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes or uses logic 1215 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0054] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations, such as human visual simulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0055] In at least one embodiment, OpenVINO supports neural network models for a variety of tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0056] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes the neural network model for execution on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's input (e.g., adjusting the size of the model's input), modifying the size of the model's input (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalizing, standardizing, quantizing (e.g., converting the model's weights from a first representation such as floating-point to a second representation such as integer), and / or variants thereof.

[0057] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to infer input data. In at least one embodiment, the inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0058] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computational processes and / or systems utilizing one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or portions of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., executing a first set of layers on a first device (e.g., a GPU) and a second set of layers on a second device (e.g., a CPU).

[0059] In at least one embodiment, OpenVINO includes various functionalities similar to those associated with CUDA programming models, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0060] Data Center Figure 14 An example data center 1400 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 1400 includes a data center infrastructure layer 1410, a framework layer 1420, a software layer 1430, and an application layer 1440.

[0061] In at least one embodiment, such as Figure 14As shown, the data center infrastructure layer 1410 may include a resource coordinator 1412, grouped computing resources 1414, and node computing resources (“nodes CR”) 1416(1)-1416(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 1416(1)-1416(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1418(1)-1418(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1416(1)-1416(N) may be servers having one or more of the aforementioned computing resources.

[0062] In at least one embodiment, the grouped computing resources 1414 may include individual groups of node CRs housed within one or more racks (not shown), or a plurality of racks housed within data centers (also not shown) in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 1414 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0063] In at least one embodiment, resource coordinator 1412 may be configured or otherwise control one or more nodes CR 1416(1)-1416(N) and / or grouped computing resources 1414. In at least one embodiment, resource coordinator 1412 may include a Software Design Infrastructure (“SDI”) management entity for data center 1400. In at least one embodiment, resource coordinator 1412 may include hardware, software, or some combination thereof.

[0064] In at least one embodiment, such as Figure 14As shown, framework layer 1420 includes job scheduler 1422, configuration manager 1424, resource manager 1426, and distributed file system 1428. In at least one embodiment, framework layer 1420 may include a framework of software 1432 supporting software layer 1430 and / or one or more applications 1442 supporting application layer 1440. In at least one embodiment, software 1432 or application 1442 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1420 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can utilize distributed file system 1428 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1422 may include Spark drivers for facilitating the scheduling of workloads supported by the various layers of data center 1400. In at least one embodiment, configuration manager 1424 may be able to configure different layers, such as software layer 1430 and framework layer 1420 including Spark and distributed file system 1428 for supporting large-scale data processing. In at least one embodiment, resource manager 1426 may be able to manage clustered or grouped computing resources mapped to or allocated to support distributed file system 1428 and job scheduler 1422. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 1414 at data center infrastructure layer 1410. In at least one embodiment, resource manager 1426 may coordinate with resource coordinator 1412 to manage these mapped or allocated computing resources.

[0065] In at least one embodiment, the software 1432 included in the software layer 1430 may include software used by at least portions of nodes CR1416(1)-1416(N), grouped computing resources 1414, and / or the distributed file system 1428 of the framework layer 1420. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0066] In at least one embodiment, one or more applications 1442 included in application layer 1440 may include one or more types of applications used by at least portions of nodes CR 1416(1)-1416(N), grouped computing resources 1414, and / or the distributed file system 1428 of framework layer 1420. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0067] In at least one embodiment, any of the configuration manager 1424, resource manager 1426, and resource coordinator 1412 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1400 and can prevent underutilization and / or poor performance of the data center.

[0068] In at least one embodiment, data center 1400 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1400. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1400 by using weight parameters calculated through one or more training techniques described herein.

[0069] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0070] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12BDetails regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in data center 1400 for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0071] In at least one embodiment, with Figure 12A , Figure 12B , Figure 13 and / or Figure 14 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0072] Autonomous vehicles Figure 15A Examples of autonomous vehicles 1500 according to at least one embodiment are shown. In at least one embodiment, the autonomous vehicle 1500 (which may alternatively be referred to herein as "vehicle 1500") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle accommodating one or more passengers. In at least one embodiment, vehicle 1500 may be a semi-tractor-trailer truck for hauling goods. In at least one embodiment, vehicle 1500 may be an aircraft, robotic vehicle, or other type of vehicle.

[0073] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of that standard). In at least one embodiment, vehicle 1500 may be able to have one or more functions according to levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1500 may be able to have conditional automation (level 3), high automation (level 4), and / or full automation (level 5), depending on the embodiment.

[0074] In at least one embodiment, vehicle 1500 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1500 may include, but is not limited to, propulsion system 1550, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1550 may be connected to the drivetrain of vehicle 1500, which may include, but is not limited to, a transmission, for enabling propulsion of vehicle 1500. In at least one embodiment, propulsion system 1550 may be controlled in response to receiving a signal from throttle / accelerator 1552.

[0075] In at least one embodiment, when the propulsion system 1550 is operating (e.g., when the vehicle 1500 is in motion), the steering system 1554 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1500 (e.g., along a desired path or route). In at least one embodiment, the steering system 1554 may receive signals from the steering actuator 1556. In at least one embodiment, for fully automated (Level 5) functionality, the steering wheel may be optional. In at least one embodiment, the brake sensor system 1546 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1548 and / or brake sensors.

[0076] In at least one embodiment, one or more controllers 1536 may include, but are not limited to, one or more systems-on-a-chip (“SoC”). Figure 15A(not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1500. For example, in at least one embodiment, one or more controllers 1536 may send signals to operate vehicle braking via brake actuator 1548, to operate steering system 1554 via one or more steering actuators 1556, and to operate propulsion system 1550 via one or more throttle / accelerators 1552. In at least one embodiment, one or more controllers 1536 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1500. In at least one embodiment, one or more controllers 1536 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0077] In at least one embodiment, one or more controllers 1536 provide signals for controlling one or more components and / or systems of vehicle 1500 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from, for example, but not limited to, the following sensors: one or more Global Navigation Satellite System (“GNSS”) sensors 1558 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1560, one or more ultrasonic sensors 1562, one or more LIDAR sensors 1564, one or more inertial measurement unit (IMU) sensors 1566 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1596, one or more stereo cameras 1568, one or more wide-angle cameras 1570 (e.g., fisheye cameras), one or more infrared cameras 1572, one or more surround cameras 1574 (e.g., 360-degree cameras), remote cameras ( Figure 15A (not shown in the image), medium-range camera ( Figure 15A(not shown), one or more speed sensors 1544 (e.g., for measuring the speed of vehicle 1500), one or more vibration sensors 1542, one or more steering sensors 1540, one or more brake sensors (e.g., as part of brake sensor system 1546) and / or other sensor types.

[0078] In at least one embodiment, one or more controllers 1536 may receive input (e.g., represented by input data) from the dashboard 1532 of the vehicle 1500 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1534, a voice signaler, a speaker, and / or via other components of the vehicle 1500. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 15A The HMI display 1534 may display information such as (not shown), location data (e.g., the location of vehicle 1500, for example on a map), direction, the location of other vehicles (e.g., occupying a grid), information about objects, and the state of objects perceived by one or more controllers 1536. For example, in at least one embodiment, the HMI display 1534 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers that have been, are being, or will be made (e.g., changing lanes now, reaching exit 34B within two miles, etc.).

[0079] In at least one embodiment, vehicle 1500 further includes a network interface 1524 that can communicate over one or more networks using one or more wireless antennas 1526 and / or one or more modems. For example, in at least one embodiment, network interface 1524 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1526 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0080] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12BDetails regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in vehicle 1500 for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0081] In at least one embodiment, with the attached Figure 1 The corresponding embodiments include one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0082] Figure 15B The illustration shows an embodiment according to at least one of the embodiments. Figure 15A Examples of camera positions and fields of view for the autonomous vehicle 1500. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1500.

[0083] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1500. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red transparent transparent transparent (“RCCC”) color filter array, a red transparent transparent blue (“RCCB”) color filter array, a red blue green transparent (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera having RCCC, RCCB, and / or RBGC color filter arrays, may be used to improve photosensitivity.

[0084] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0085] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D” printed) assembly, to remove stray light and reflected light from within the vehicle 1500 (e.g., reflected light from the dashboard reflected in the windshield mirror), which may interfere with the camera’s image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0086] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including portions of the environment in front of the vehicle 1500 can be used for surround view to help identify the path and obstacles ahead, and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path, with the help of one or more controllers 1536 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions such as traffic sign recognition.

[0087] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1570 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 15BOnly one wide-angle camera 1570 is shown, but in other embodiments, the vehicle 1500 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1598 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1598 can also be used for object detection and classification, as well as basic object tracking.

[0088] In at least one embodiment, any number of stereo cameras 1568 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1568 may include an integrated control unit comprising a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of vehicle 1500, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1568 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from vehicle 1500 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1568 may be used in addition to or instead of those described herein.

[0089] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including portions of the environment on the sides of the vehicle 1500 can be used for surround view, providing information for creating and updating the occupied grid, and generating a side impact collision warning. For example, in at least one embodiment, a surround camera 1574 (e.g., such as...) Figure 15B The four surround cameras shown can be positioned on vehicle 1500. In at least one embodiment, one or more surround cameras 1574 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of vehicle 1500. In at least one embodiment, vehicle 1500 can use three surround cameras 1574 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0090] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including portions of the environment behind the vehicle 1500 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1598 and / or one or more mid-range cameras 1576, one or more stereo cameras 1568, one or more infrared cameras 1572, etc.), as described herein.

[0091] In at least one embodiment, with Figure 15A and / or Figure 15B At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0092] Figure 15C It is shown that according to at least one embodiment Figure 15A A block diagram of an example system architecture for an autonomous vehicle 1500. In at least one embodiment, Figure 15C Each component, feature, and system of vehicle 1500 is shown as connected via bus 1502. In at least one embodiment, bus 1502 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 1500 for assisting in the control of various features and functions of vehicle 1500, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1502 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1502 may be read to locate steering wheel angle, ground speed, engine rotation speed (“RPM”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1502 may be an ASIL B compliant CAN bus.

[0093] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, any number of buses forming bus 1502 may be present, including but not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1502 may communicate with any component of vehicle 1500, and two or more buses in bus 1502 may communicate with corresponding components. In at least one embodiment, each of any number of System-on-Chip (“SoC”) 1504 (e.g., SoC 1504(A) and SoC 1504(B)), each of one or more controllers 1536 and / or each computer within the vehicle can access the same input data (e.g., input from sensors of vehicle 1500) and can be connected to a common bus, such as a CAN bus.

[0094] In at least one embodiment, vehicle 1500 may include one or more controllers 1536, such as those described herein. Figure 15A As described above. In at least one embodiment, controller 1536 can be used for a wide variety of functions. In at least one embodiment, controller 1536 can be coupled to any of various other components and systems of vehicle 1500 and can be used to control vehicle 1500, artificial intelligence of vehicle 1500, infotainment and / or other functions of vehicle 1500.

[0095] In at least one embodiment, vehicle 1500 may include any number of SoCs 1504. In at least one embodiment, each of the SoCs 1504 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1506, a graphics processing unit (“one or more GPUs”) 1508, one or more processors 1510, one or more caches 1512, one or more accelerators 1514, one or more data storage 1516, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1504 may be used to control vehicle 1500 on a wide variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1504 may be combined with a high-definition (“HD”) map 1522 in a system (e.g., the system of vehicle 1500), the HD map 1522 being accessible from one or more servers via a network interface 1524. Figure 15C (Not shown in the image) Get map refresh and / or update.

[0096] In at least one embodiment, one or more CPUs 1506 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1506 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1506 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1506 may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2 megabytes (MB) L2 cache). In at least one embodiment, one or more CPUs 1506 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, which allows any combination of clusters of one or more CPUs 1506 to be active at any given time.

[0097] In at least one embodiment, one or more CPUs 1506 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware blocks to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; power gating of each core independently; clock gating of each core cluster independently when all cores are clock-gated or power-gated; and / or power gating of each core cluster independently when all cores are power-gated. In at least one embodiment, one or more CPUs 1506 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state to input for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein the work is offloaded to the microcode.

[0098] In at least one embodiment, one or more GPUs 1508 may include integrated GPUs (which may alternatively be referred to herein as “iGPUs”). In at least one embodiment, one or more GPUs 1508 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1508 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1508 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 (“L1”) cache (e.g., an L1 cache with at least 96 KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512 KB of storage capacity). In at least one embodiment, one or more GPUs 1508 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1508 may use one or more computation application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1508 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA model).

[0099] In at least one embodiment, one or more GPU 1508s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPU 1508s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a scheduler (e.g., a thread bundle scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for employing a mixture of computation and addressing operations to provide efficient execution of workloads. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0100] In at least one embodiment, one or more GPUs 1508 may include high-bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, used in some examples to provide a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”), such as fifth-generation graphics double data rate type synchronous random access memory (“GDDR5”), may also be used.

[0101] In at least one embodiment, one or more GPUs 1508 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 1508 to directly access the page tables of one or more CPUs 1506. In at least one embodiment, when the memory management unit (“MMU”) of one or more GPUs 1508 experiences a miss, an address translation request can be sent to one or more CPUs 1506. In response, in at least one embodiment, two CPUs of one or more CPUs 1506 can look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1508. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 1506 and one or more GPUs 1508, thereby simplifying the programming of one or more GPUs 1508 and the porting of applications to one or more GPUs 1508.

[0102] In at least one embodiment, one or more GPUs 1508 may include any number of access counters that can track the frequency with which one or more GPUs 1508 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of sharing memory ranges among processors.

[0103] In at least one embodiment, one or more SoCs 1504 may include any number of caches 1512, including those described herein. For example, in at least one embodiment, one or more caches 1512 may include a Level 3 (“L3”) cache that can be used for both one or more CPUs 1506 and one or more GPUs 1508 (e.g., connected to one or more CPUs 1506 and one or more GPUs 1508). In at least one embodiment, one or more caches 1512 may include a write-back cache that can track the state of each row, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, depending on the embodiment, the L3 cache may include 4 MB of memory or more.

[0104] In at least one embodiment, one or more SoCs 1504 may include one or more accelerators 1514 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1504 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1508 and offload some tasks from one or more GPUs 1508 (e.g., to free up more cycles from one or more GPUs 1508 to perform other tasks). In at least one embodiment, one or more accelerators 1514 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0105] In at least one embodiment, one or more accelerators 1514 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, and post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, rapidly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for protection and / or safety-related events.

[0106] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1508, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1508 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1508 and / or one or more accelerators 1514.

[0107] In at least one embodiment, one or more accelerators 1514 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, a PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1538, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, a PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0108] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, depending on the embodiment, the RISC core may use any of a variety of protocols. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0109] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1506. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0110] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly perform programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0111] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Therefore, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general computer vision algorithms, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or different portions of an image. In at least one embodiment, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory for enhancing overall system security.

[0112] In at least one embodiment, one or more accelerators 1514 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1514. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0113] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0114] In at least one embodiment, one or more SoCs 1504 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to rapidly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0115] In at least one embodiment, one or more accelerators 1514 may have broad applications for autonomous driving. In at least one embodiment, PVAs may be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVAs with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVAs perform well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1500, PVAs may be designed to run classical computer vision algorithms, as they can be efficient in object detection and integer mathematical operations.

[0116] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure reconstruction from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0117] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, for example, the PVA is used to perform time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0118] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks, whose output is a measurement of confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence values. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1566 related to vehicle 1500 orientation, distance, and object 3D position estimates obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1564 or one or more RADAR sensors 1560).

[0119] In at least one embodiment, one or more SoCs 1504 may include one or more data stores 1516 (e.g., memory). In at least one embodiment, one or more data stores 1516 may be on-chip memory of one or more SoCs 1504, which may store neural networks to be executed on one or more GPUs 1508 and / or DLAs. In at least one embodiment, one or more data stores 1516 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data stores 1516 may include one or more L2 or L3 caches.

[0120] In at least one embodiment, one or more SoCs 1504 may include any number of processors 1510 (e.g., embedded processors). In at least one embodiment, one or more processors 1510 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security execution. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1504 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1504s, and / or power state management of one or more SoCs 1504s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1504s may use the ring oscillator to detect the temperature of one or more CPUs 1506s, one or more GPUs 1508s, and / or one or more accelerators 1514s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1504s into a lower power state and / or place the vehicle 1500 into a driver safe parking mode (e.g., bring the vehicle 1500 to a safe stop).

[0121] In at least one embodiment, one or more processors 1510 may further include a set of embedded processors that can be used as an audio processing engine, which may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0122] In at least one embodiment, one or more processors 1510 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, support for peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0123] In at least one embodiment, one or more processors 1510 may further include a security cluster engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In a secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1510 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1510 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0124] In at least one embodiment, one or more processors 1510 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video playback applications to generate final images for video post-processing functions required by the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1570, one or more surround cameras 1574, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1504, the neural network being configured to recognize in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0125] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion in the video, denoising appropriately weights spatial information to reduce the weight of information provided by adjacent frames. In at least one embodiment, in the case where the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0126] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereoscopic shot frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1508 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1508 are powered and active for 3D rendering, the video image compositor can be used to offload one or more GPUs 1508 to improve performance and responsiveness.

[0127] In at least one embodiment, one or more SoCs of SoC 1504 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1504 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0128] In at least one embodiment, one or more SoCs of SoC 1504 may further include extensive peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1504 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1564, one or more RADAR sensors 1560, etc., which may be connected via Ethernet channels), data from bus 1502 (e.g., vehicle 1500 speed, steering wheel position, etc.), data from one or more GNSS sensors 1558 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1504 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to free one or more CPUs of SoC 1506 from routine data management tasks.

[0129] In at least one embodiment, one or more SoCs 1504 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for a flexible, reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1504 can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1514, when combined with one or more CPUs 1506, one or more GPUs 1508, and one or more data storage units 1516, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0130] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0131] The embodiments described herein allow for the simultaneous and / or sequential execution of multiple neural networks and allow for the combination of results to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1520) may include text and word recognition, thereby allowing the reading and understanding of traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing a semantic understanding of the signs, and passing this semantic understanding to a path planning module running on a CPU complex.

[0132] In at least one embodiment, multiple neural networks can run simultaneously for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating "Caution: flashing lights indicate icy conditions," along with the lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which informs the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1508.

[0133] In at least one embodiment, the CNN for face recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1500. In at least one embodiment, a normally open sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in a safe mode, it can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1504 provide protection against theft and / or carjacking.

[0134] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1596 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1504 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, such as those identified by one or more GNSS sensors 1558. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1562, to execute emergency vehicle safety routines, such as slowing the vehicle, pulling the vehicle to the side of the road, stopping, and / or idling the vehicle until the emergency vehicle passes.

[0135] In at least one embodiment, vehicle 1500 may include one or more CPUs 1518 (e.g., one or more discrete CPUs or one or more dCPUs) coupled to one or more SoCs 1504 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 1518 may include, for example, x86 processors. One or more CPUs 1518 may be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1504, and / or monitoring the status and health of one or more controllers 1536 and / or on-chip infotainment system (“Infotainment SoC”) 1530. In at least one embodiment, SoC 1504 includes one or more interconnects, and the interconnects may include Fast Peripheral Component Interconnect (PCIe).

[0136] In at least one embodiment, vehicle 1500 may include one or more GPUs 1520 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1504 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1520 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on inputs from sensors of vehicle 1500 (e.g., sensor data).

[0137] In at least one embodiment, vehicle 1500 may further include a network interface 1524, which may include, but is not limited to, one or more wireless antennas 1526 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1524 may be used to enable wireless connectivity to Internet cloud services (e.g., with servers and / or other network devices), with other vehicles, and / or with computing devices (e.g., passenger client devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 1500 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1500 with information about vehicles near vehicle 1500 (e.g., vehicles in front, to the side, and / or behind vehicle 1500). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1500.

[0138] In at least one embodiment, network interface 1524 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1536 to communicate over a wireless network. In at least one embodiment, network interface 1524 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0139] In at least one embodiment, vehicle 1500 may further include one or more data storage units 1528, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoC 1504) storage. In at least one embodiment, one or more data storage units 1528 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0140] In at least one embodiment, the vehicle 1500 may further include one or more GNSS sensors 1558 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1558 may be used, including, for example, but not limited to, GPS sensors using a USB connector with an Ethernet-to-serial interface (e.g., RS-232) bridge.

[0141] In at least one embodiment, vehicle 1500 may further include one or more RADAR sensors 1560. In at least one embodiment, one or more RADAR sensors 1560 may be used by vehicle 1500 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1560 may use a CAN bus and / or bus 1502 (e.g., for transmitting data generated by one or more RADAR sensors 1560) to control and access object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more RADAR sensors 1560 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the RADAR sensors 1560 are pulse Doppler RADAR sensors.

[0142] In at least one embodiment, one or more RADAR sensors 1560 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1560 can help distinguish between stationary and moving objects and can be used by the ADAS system 1538 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1560 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, employing six antennas, the four central antennas can create a focused beammap designed to record the surrounding environment of the vehicle 1500 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling them to quickly detect vehicles entering or leaving the vehicle lane 1500.

[0143] In at least one embodiment, as an example, a mid-range RADAR system may include a range of up to 160m (front) or 80m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1560 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1538 for blind spot detection and / or lane change assistance.

[0144] In at least one embodiment, the vehicle 1500 may further include one or more ultrasonic sensors 1562. In at least one embodiment, one or more ultrasonic sensors 1562, which may be positioned at the front, rear, and / or sides of the vehicle 1500, may be used for parking assistance and / or creating and updating occupancy grids. In at least one embodiment, a wide variety of ultrasonic sensors 1562 may be used, and different ultrasonic sensors 1562 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1562 may operate at ASIL B functional safety level.

[0145] In at least one embodiment, vehicle 1500 may include one or more LiDAR sensors 1564. In at least one embodiment, one or more LiDAR sensors 1564 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1564 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1500 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1564 that can use Ethernet channels (e.g., to provide data to a Gigabit Ethernet switch).

[0146] In at least one embodiment, one or more LiDAR sensors 1564 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1564 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 1564 may include small devices that can be embedded in the front, rear, side, and / or corner locations of a vehicle 1500. In at least one embodiment, one or more LiDAR sensors 1564, in such an embodiment, may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-mounted LiDAR sensors 1564 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0147] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the area around vehicle 1500 up to approximately 200m. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the propagation time of the laser pulse and the reflected light on each pixel, which in turn corresponds to the range from vehicle 1500 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1500. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0148] In at least one embodiment, vehicle 1500 may further include one or more IMU sensors 1566. In at least one embodiment, one or more IMU sensors 1566 may be located at the center of the rear axle of vehicle 1500. In at least one embodiment, one or more IMU sensors 1566 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1566 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1566 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0149] In at least one embodiment, one or more IMU sensors 1566 can be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1566 enable vehicle 1500 to estimate its heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1566, without requiring input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1566 and one or more GNSS sensors 1558 can be combined in a single integrated unit.

[0150] In at least one embodiment, vehicle 1500 may include one or more microphones 1596 placed inside and / or around vehicle 1500. In at least one embodiment, one or more microphones 1596 may be used for emergency vehicle detection and identification.

[0151] In at least one embodiment, vehicle 1500 may further include any number of camera types, including one or more stereo cameras 1568, one or more wide-angle cameras 1570, one or more infrared cameras 1572, one or more surround cameras 1574, one or more long-range cameras 1598, one or more mid-range cameras 1576, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1500. In at least one embodiment, the type of camera used depends on vehicle 1500. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1500. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1500 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, by way of example but not limited to, gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, previously referenced herein... Figure 15A and Figure 15B Each camera is described in more detail.

[0152] In at least one embodiment, the vehicle 1500 may further include one or more vibration sensors 1542. In at least one embodiment, the one or more vibration sensors 1542 may measure vibrations of components of the vehicle 1500 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1542 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0153] In at least one embodiment, vehicle 1500 may include ADAS system 1538. In at least one embodiment, ADAS system 1538 may include, but is not limited to, SoC in some examples. In at least one embodiment, ADAS system 1538 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) system, cooperative adaptive cruise control (“CACC”) system, forward collision warning (“FCW”) system, automatic emergency braking (“AEB”) system, lane departure warning (“LDW”) system, lane keeping assist (“LKA”) system, blind spot warning (“BSW”) system, rear cross traffic warning (“RCTW”) system, collision warning (“CW”) system, lane centering (“LC”) system and / or other systems, features and / or functions.

[0154] In at least one embodiment, the ACC system may use one or more RADAR sensors 1560, one or more LIDAR sensors 1564, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 1500 and automatically adjusts the speed of vehicle 1500 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1500 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0155] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via a wireless link or through a network connection (e.g., via the Internet) via network interface 1524 and / or one or more wireless antennas 1526. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately ahead (e.g., a vehicle immediately in front of vehicle 1500 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicles in front of vehicle 1500, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0156] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1560, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual, haptic, and / or rapid braking pulses.

[0157] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply braking if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1560 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply braking to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or collision proximity braking.

[0158] In at least one embodiment, when vehicle 1500 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is not activated when the driver indicates intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1500 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1500.

[0159] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of the car. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses turn signals. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1560 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback such as a display, speaker, and / or vibration components.

[0160] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when the vehicle 1500 detects an object outside the range of the rear camera while reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1560 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0161] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, vehicle 1500 decides for itself whether to follow the result of the main computer or auxiliary computer (e.g., the first or second controller in controller 1536). For example, in at least one embodiment, ADAS system 1538 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, output from ADAS system 1538 may be provided to a supervisory MCU. In at least one embodiment, if output from the main computer and output from the auxiliary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0162] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU, indicating the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0163] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU may learn when the FCW system is recognizing a metallic object that is not actually dangerous, such as a drain grille or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1504s.

[0164] In at least one embodiment, the ADAS system 1538 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and the not-quite-same software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can have greater confidence that the overall results are correct, and that the vulnerability in the software or hardware on the host computer will not lead to a major error.

[0165] In at least one embodiment, the output of the ADAS system 1538 may be fed into the perception block and / or the dynamic driving task block of the main computer. For example, in at least one embodiment, if the ADAS system 1538 indicates a forward collision warning due to an object directly ahead, the perception block may use the information when the object is identified. In at least one embodiment, as described herein, the assistance computer may have its own neural network, which is trained to reduce the risk of false alarms.

[0166] In at least one embodiment, vehicle 1500 may further include an infotainment SoC 1530 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1530 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1530 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1500. For example, the infotainment SoC 1530 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1534, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1530 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1500, such as information from ADAS system 1538, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0167] In at least one embodiment, the infotainment SoC 1530 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1530 may communicate with other devices, systems, and / or components of the vehicle 1500 via bus 1502. In at least one embodiment, the infotainment SoC 1530 may be coupled to a supervisory MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of one or more main controllers 1536 (e.g., the main computer and / or backup computer of the vehicle 1500). In at least one embodiment, the infotainment SoC 1530 may place the vehicle 1500 into a driver-to-safe parking mode, as described herein.

[0168] In at least one embodiment, vehicle 1500 may further include instrument panel 1532 (e.g., digital instrument panel, electronic instrument panel, digital instrument cluster, etc.). In at least one embodiment, instrument panel 1532 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1532 may include, but is not limited to, any number and combination of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1530 and instrument panel 1532. In at least one embodiment, instrument panel 1532 may be included as part of infotainment SoC 1530, or vice versa.

[0169] In at least one embodiment, with Figure 15C At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0170] Figure 15D It is based on at least one embodiment in one or more cloud-based servers and Figure 15AA diagram of a system for communication between autonomous vehicles 1500. In at least one embodiment, the system may include, but is not limited to, one or more servers 1578, one or more networks 1590, and any number and type of vehicles, including vehicle 1500. In at least one embodiment, one or more servers 1578 may include, but is not limited to, multiple GPUs 1584(A)-1584(H) (collectively referred to herein as GPU 1584), PCIe switches 1582(A)-1582(D) (collectively referred to herein as PCIe switch 1582), and / or CPUs 1580(A)-1580(B) (collectively referred to herein as CPU 1580). In at least one embodiment, GPU 1584, CPU 1580, and PCIe switch 1582 may be interconnected with high-speed interconnects, such as, for example, but not limited to, NVLink interface 1588 and / or PCIe connection 1586 developed by NVIDIA. In at least one embodiment, the GPU 1584 is connected via NVLink and / or NVSwitch SoC, and the GPU 1584 and PCIe switch 1582 are connected via PCIe interconnect. Although eight GPUs 1584, two CPUs 1580, and four PCIe switches 1582 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1578 may include, but is not limited to, any number of GPUs 1584, CPUs 1580, and / or PCIe switches 1582 in any combination. For example, in at least one embodiment, one or more servers 1578 may each include eight, sixteen, thirty-two, and / or more GPUs 1584.

[0171] In at least one embodiment, one or more servers 1578 may receive image data representing an image from a vehicle via one or more networks 1590, the image showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1578 may send updated neural network 1592 and / or map information 1594 to the vehicle via one or more networks 1590, including but not limited to information about traffic and road conditions. In at least one embodiment, updates to map information 1594 may include, but are not limited to, updates to HD map 1522, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1592 and / or map information 1594 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed at a data center (e.g., using one or more servers 1578 and / or other servers).

[0172] In at least one embodiment, one or more servers 1578 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1590, and / or the machine learning model may be used by one or more servers 1578 to remotely monitor the vehicle).

[0173] In at least one embodiment, one or more servers 1578 may receive data from the vehicle and apply the data to a state-of-the-art real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1578 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1584, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1578 may include a deep learning infrastructure in a data center using CPU power.

[0174] In at least one embodiment, the deep learning infrastructure of one or more servers 1578 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in vehicle 1500. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1500, such as image sequences and / or objects located by vehicle 1500 in the image sequences (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1500, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1500 is malfunctioning, one or more servers 1578 may signal to vehicle 1500, instructing vehicle 1500's fail-safe computer to take control, notify passengers, and complete a safe stopping operation.

[0175] In at least one embodiment, one or more servers 1578 may include one or more GPUs 1584 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, servers driven by CPUs, FPGAs, and other processors may be used for inference, such as in situations where performance is less critical. In at least one embodiment, one or more hardware structures 1215 are used to execute one or more embodiments. This document incorporates... Figure 12A and / or Figure 12B Provide details about the hardware architecture 1215.

[0176] Computer System Figure 16 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system with interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit for executing instructions. In at least one embodiment, according to this disclosure, such as in the embodiments described herein, computer system 1600 may include, but is not limited to, components such as processor 1602 for employing execution units (including logic) to execute algorithms for process data. In at least one embodiment, computer system 1600 may include a processor, such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, the computer system 1600 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0177] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0178] In at least one embodiment, the computer system 1600 may include, but is not limited to, a processor 1602, which may include, but is not limited to, one or more execution units 1608 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1600 is a single-processor desktop or server system, but in another embodiment, the computer system 1600 may be a multiprocessor system. In at least one embodiment, the processor 1602 may include, but is not limited to, for example, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1602 may be coupled to a processor bus 1610, which can transmit data signals between the processor 1602 and other components in the computer system 1600.

[0179] In at least one embodiment, processor 1602 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1604. In at least one embodiment, processor 1602 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to processor 1602. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1606 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0180] In at least one embodiment, an execution unit 1608, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1602. In at least one embodiment, the processor 1602 may also include a microcode (“ucode”) read-only memory (“ROM”) storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1608 may include logic for processing a packaged instruction set 1609. In at least one embodiment, by including the packaged instruction set 1609 in the instruction set of the general-purpose processor and the associated circuitry to be executed, packaged data in the processor 1602 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, numerous multimedia applications can be accelerated and executed more efficiently by using the full width of the processor’s data bus to perform operations on packaged data, eliminating the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0181] In at least one embodiment, execution unit 1608 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1600 may include, but is not limited to, memory 1620. In at least one embodiment, memory 1620 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1620 may store one or more instructions 1619 and / or data 1621 represented by data signals executable by processor 1602.

[0182] In at least one embodiment, the system logic chip may be coupled to processor bus 1610 and memory 1620. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1616, and processor 1602 may communicate with MCH 1616 via processor bus 1610. In at least one embodiment, MCH 1616 may provide a high-bandwidth memory path 1618 to memory 1620 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1616 may direct data signals between processor 1602, memory 1620, and other components in computer system 1600, and bridge data signals between processor bus 1610, memory 1620, and system I / O interface 1622. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1616 may be coupled to memory 1620 via high-bandwidth memory path 1618, and graphics / video card 1612 may be coupled to MCH 1616 via Accelerated Graphics Port (“AGP”) interconnect 1614.

[0183] In at least one embodiment, the computer system 1600 may use the system I / O interface 1622 as a proprietary hub interface bus to couple the MCH 1616 to the I / O controller hub (“ICH”) 1630. In at least one embodiment, the ICH 1630 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1620, chipset, and processor 1602. Examples may include, but are not limited to, an audio controller 1229, a firmware hub (“Flash BIOS”) 1628, a wireless transceiver 1626, a data storage 1624, a conventional I / O controller 1623 including a user input and keyboard interface 1625, a serial expansion port 1627 (such as a Universal Serial Bus (“USB”) port), and a network controller 1634. In at least one embodiment, the data storage 1624 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0184] In at least one embodiment, Figure 16 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 16 An exemplary SoC can be shown. In at least one embodiment, Figure 16The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1600 are interconnected using a Compute Fast Link (CXL) interconnect.

[0185] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 can be used in a computer system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0186] In at least one embodiment, with Figure 16 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0187] Figure 17 This is a block diagram illustrating an electronic device 1700 for utilizing a processor 1710 according to at least one embodiment. In at least one embodiment, the electronic device 1700 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0188] In at least one embodiment, the electronic device 1700 may, but is not limited to, a processor 1710 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1710 uses a bus or interface coupling, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 17 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 17 An exemplary SoC can be shown. In at least one embodiment, Figure 17The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 17 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0189] In at least one embodiment, Figure 17 This may include a display 1724, a touchscreen 1725, a touchpad 1730, a near-field communication unit (“NFC”) 1745, a sensor hub 1740, a thermal sensor 1746, a fast chipset (“EC”) 1735, a trusted platform module (“TPM”) 1738, a BIOS / firmware / flash (“BIOS, FW Flash”) 1722, a DSP 1760, a drive 1720 (such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless LAN unit (“WLAN”) 1750, a Bluetooth unit 1752, a wireless wide area network unit (“WWAN”) 1756, a global positioning system (GPS) unit 1755, a camera (“USB 3.0 camera”) 1754 (such as a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1715 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0190] In at least one embodiment, other components may be communicatively coupled to processor 1710 via the components described herein. In at least one embodiment, accelerometer 1741, ambient light sensor (“ALS”) 1742, compass 1743, and gyroscope 1744 may be communicatively coupled to sensor hub 1740. In at least one embodiment, thermal sensor 1739, fan 1737, keyboard 1736, and touchpad 1730 may be communicatively coupled to EC 1735. In at least one embodiment, speaker 1763, earphone 1764, and microphone (“mic”) 1765 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1762, which in turn may be communicatively coupled to DSP 1760. In at least one embodiment, audio unit 1762 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1757 may be communicatively coupled to WWAN unit 1756. In at least one embodiment, components such as WLAN unit 1750, Bluetooth unit 1752, and WWAN unit 1756 may be implemented as next-generation form factors (“NGFF”).

[0191] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in electronic device 1700 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0192] In at least one embodiment, with Figure 17 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0193] Figure 18 A computer system 1800 according to at least one embodiment is shown. In at least one embodiment, the computer system 1800 is configured to implement various processes and methods described throughout this disclosure.

[0194] In at least one embodiment, the computer system 1800 includes, but is not limited to, at least one central processing unit (“CPU”) 1802 connected to a communication bus 1810 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Fast (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1800 includes, but is not limited to, main memory 1804 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in the main memory 1804, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1822 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using the computer system 1800.

[0195] In at least one embodiment, the computer system 1800 includes, but is not limited to, an input device 1808, a parallel processing system 1812, and a display device 1806, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1808 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may reside on a single semiconductor platform to form the processing system.

[0196] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in computer system 1800 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0197] In at least one embodiment, with Figure 18 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0198] Figure 19 A computer system 1900 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1900 includes, but is not limited to, a computer 1910 and a USB flash drive 1920. In at least one embodiment, the computer 1910 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1910 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0199] In at least one embodiment, the USB flash drive 1920 includes, but is not limited to, a processing unit 1930, a USB interface 1940, and USB interface logic 1950. In at least one embodiment, the processing unit 1930 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1930 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1930 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1930 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1930 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0200] In at least one embodiment, the USB interface 1940 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1940 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1940 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1950 may include any amount and type of logic enabling the processing unit 1930 to interface with a device (e.g., computer 1910) via the USB connector 1940.

[0201] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in computer system 1900 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0202] In at least one embodiment, with Figure 19 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0203] Figure 20AAn exemplary architecture is shown in which multiple GPUs 2010(1)-2010(N) are communicatively coupled to multiple multi-core processors 1605(1)-1605(M) via high-speed links 2040(1)-2040(N) (e.g., bus, point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 2040(1)-2040(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 2010(1)-2010(N) include, Figure 23A and Figure 23B The disclosed graphics cores (also referred to simply as "cores") 2300. In at least one embodiment, the graphics cores 2300 may be referred to as streaming multiprocessors ("SM"), streaming processors ("SP"), streaming processing units ("SPU"), compute units ("CU"), execution units ("EU"), and / or slices, wherein, in this context, a slice may refer to a portion of the processing resources within a processing unit (e.g., 16 cores, a ray tracing unit, a thread bootstrap, or a scheduler).

[0204] Furthermore, in at least one embodiment, two or more GPUs 2010 are interconnected via high-speed links 2029(1)-2029(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 2040(1)-2040(N). Similarly, two or more multi-core processors 2005 can be connected via high-speed link 2028, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 20A This shows all communication between the various system components.

[0205] In at least one embodiment, each multi-core processor 2005 is communicatively coupled to processor memory 2001(1)-2001(M) via memory interconnects 2026(1)-2026(M), and each GPU 2010(1)-2010(N) is communicatively coupled to GPU memory 2020(1)-2020(N) via GPU memory interconnects 2050(1)-2050(N). In at least one embodiment, memory interconnects 2026 and 2050 may utilize similar or different memory access technologies. By way of example and not limitation, processor memory 2001(1)-2001(M) and GPU memory 2020 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of the processor memory 2001 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0206] As described herein, although the individual multi-core processors 2005 and GPUs 2010 can be physically coupled to specific memories 2001 and 2020 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the individual physical memories. For example, processor memories 2001(1)–2001(M) can each include 64 GB of system memory address space, and GPU memories 2020(1)–2020(N) can each include 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M = 2 and N = 4. Other values ​​for N and M are possible.

[0207] Figure 20B Additional details are shown regarding the interconnection between a multi-core processor 2007 and a graphics acceleration module 2046 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 2046 may include one or more GPU chips integrated on a line card coupled to the processor 2007 via a high-speed link 2040 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 2046 may alternatively be integrated on a package or chip having the processor 2007.

[0208] In at least one embodiment, the processor 2007 includes a plurality of cores 2060A-2060D (which may be referred to as “execution units”), each core having a translation back cover buffer (“TLB”) 2061A-2061D and one or more caches 2062A-2062D. In at least one embodiment, the cores 2060A-2060D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 2062A-2062D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 2056 may be included in the caches 2062A-2062D and shared by the respective groups of cores 2060A-2060D. For example, one embodiment of the processor 2007 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 2007 and graphics acceleration module 2046 are connected to system memory 2014, which may include... Figure 20A The processor memory in the memory is 2001(1)-2001(M).

[0209] In at least one embodiment, consistency of data and instructions stored in the various caches 2062A-2062D, 2056 and system memory 2014 is maintained via inter-core communication through the consistency bus 2064. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 2064 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 2064 to snoop on cache accesses.

[0210] In at least one embodiment, proxy circuitry 2025 communicatively couples graphics acceleration module 2046 to coherence bus 2064, thereby allowing graphics acceleration module 2046 to participate in cache coherence protocols as a peer of cores 2060A-2060D. Specifically, in at least one embodiment, interface 2035 provides connectivity to proxy circuitry 2025 via high-speed link 2040, and interface 2037 connects graphics acceleration module 2046 to high-speed link 2040.

[0211] In at least one embodiment, the accelerator integrated circuit 2036 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 2031(1)-2031(N) of the graphics acceleration module 2046. In at least one embodiment, each of the graphics processing engines 2031(1)-2031(N) may include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 2031(1)-2031(N) of the graphics acceleration module 2046 includes, as in combination Figure 23A and Figure 23B The discussion concerns one or more graphics cores 2300. In at least one embodiment, graphics processing engines 2031(1)-2031(N) may alternatively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit (block transport) engines. In at least one embodiment, graphics acceleration module 2046 may be a GPU having multiple graphics processing engines 2031(1)-2031(N), or graphics processing engines 2031(1)-2031(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0212] In at least one embodiment, the accelerator integrated circuit 2036 includes a memory management unit (MMU) 2039 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 2014. In at least one embodiment, the MMU 2039 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 2038 may store commands and data for efficient access by graphics processing engines 2031(1)-2031(N). In at least one embodiment, a fetch unit 2044 may be used to keep data stored in cache 2038 and graphics memory 2033(1)-2033(M) consistent with core caches 2062A-2062D, 2056 and system memory 2014. As previously stated, this can mean that cache 2038 and memory 2033(1)-2033(M) are implemented via proxy circuit 2025 (e.g., sending updates related to the modification / access of cache lines on processor caches 2062A-2062D, 2056 to cache 2038 and receiving updates from cache 2038).

[0213] In at least one embodiment, a set of registers 2045 stores context data of threads executed by graphics processing engines 2031(1)-2031(N), and context management circuitry 2048 manages the thread context. For example, context management circuitry 2048 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 2048 can store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 2047 receives and processes interrupts received from system devices.

[0214] In at least one embodiment, MMU 2039 translates virtual / effective addresses from graphics processing engine 2031 into real / physical addresses in system memory 2014. In at least one embodiment, accelerator integrated circuit 2036 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 2046 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 2046 may be dedicated to a single application executing on processor 2007, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 2031(1)-2031(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0215] In at least one embodiment, the accelerator integrated circuit 2036 acts as a bridge to the system of the graphics acceleration module 2046 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 2036 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 2031(1)-2031(N).

[0216] In at least one embodiment, since the hardware resources of the graphics processing engines 2031(1)-2031(N) are explicitly mapped to the real address space seen by the host processor 2007, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 2036 is the physical separation of the graphics processing engines 2031(1)-2031(N), making them appear as independent units to the system.

[0217] In at least one embodiment, one or more graphics memories 2033(1)-2033(M) are coupled to each graphics processing engine 2031(1)-2031(N), where N = M. In at least one embodiment, graphics memories 2033(1)-2033(M) store instructions and data being processed by each graphics processing engine 2031(1)-2031(N). In at least one embodiment, graphics memories 2033(1)-2033(M) may be volatile memories, such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0218] In at least one embodiment, to reduce data traffic on the high-speed link 2040, a biasing technique can be used to ensure that the data stored in the graphics memory 2033(1)-2033(M) is the data most frequently used by the graphics processing engine 2031(1)-2031(N), and preferably data that is not used (or at least not frequently used) by the cores 2060A-2060D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by the graphics processing engine 2031(1)-2031(N)) in the caches 2062A-2062D, 2056 and system memory 2014.

[0219] Figure 20C Another exemplary embodiment is shown, wherein the accelerator integrated circuit 2036 is integrated within the processor 2007. In this embodiment, the graphics processing engines 2031(1)-2031(N) communicate directly with the accelerator integrated circuit 2036 via a high-speed link 2040 through interfaces 2037 and 2035 (again, which can be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 2036 can perform operations related to... Figure 20B The described operation is similar, but due to its close proximity to the coherence bus 2064 and caches 2062A-2062D, 2056, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 2036 and a programming model controlled by the graphics acceleration module 2046.

[0220] In at least one embodiment, graphics processing engines 2031(1)-2031(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 2031(1)-2031(N), thereby providing virtualization within a VM / partition.

[0221] In at least one embodiment, graphics processing engines 2031(1)-2031(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 2031(1)-2031(N) to allow access by each operating system. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 2031(1)-2031(N). In at least one embodiment, the operating system can virtualize graphics processing engines 2031(1)-2031(N) to provide access to each process or application.

[0222] In at least one embodiment, the graphics acceleration module 2046 or the individual graphics processing engines 2031(1)-2031(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 2014 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 2031(1)-2031(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0223] Figure 20DAn exemplary accelerator integration slice 2090 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 2036. In at least one embodiment, the application is an effective address space 2082 in system memory 2014, which stores process element 2083. In at least one embodiment, process element 2083 is stored in response to a GPU call 2081 from an application 2080 executing on processor 2007. In at least one embodiment, process element 2083 contains the process state of the corresponding application 2080. In at least one embodiment, a job descriptor (WD) 2084 contained in process element 2083 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 2084 is a pointer to a job request queue in the effective address space 2082 of the application.

[0224] In at least one embodiment, the graphics acceleration module 2046 and / or the respective graphics processing engines 2031(1)-2031(N) may be shared by all processes or subsets of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 2084 to the graphics acceleration module 2046 to begin operations in a virtualized environment.

[0225] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 2046 or an individual graphics processing engine 2031. In at least one embodiment, when the graphics acceleration module 2046 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 2046 is assigned, the operating system initializes the accelerator integrated circuit 2036 for the owned process.

[0226] In at least one embodiment, during operation, the WD acquisition unit 2091 in the accelerator integration slice 2090 acquires the next WD 2084, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 2046. In at least one embodiment, data from the WD 2084 may be stored in register 2045 and used by MMU 2039, interrupt management circuitry 2047, and / or context management circuitry 2048, as shown. For example, one embodiment of MMU 2039 includes segment / page walk circuitry for accessing segment / page tables 2086 within the OS virtual address space 2085. In at least one embodiment, interrupt management circuitry 2047 may process interrupt events 2092 received from the graphics acceleration module 2046. In at least one embodiment, when performing graphics operations, a valid address 2093 generated by graphics processing engines 2031(1)-2031(N) is translated into a real address by MMU 2039.

[0227] In at least one embodiment, register 2045 is copied for each graphics processing engine 2031(1)-2031(N) and / or graphics acceleration module 2046, and register 2045 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 2090. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 2 shows exemplary registers that can be initialized by the operating system. In at least one embodiment, each WD 2084 is specific to a particular graphics acceleration module 2046 and / or graphics processing engine 2031(1)-2031(N). In at least one embodiment, it contains all the information required for the graphics processing engine 2031(1)-2031(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0228] Figure 20E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 2098, in which a list of process elements 2099 is stored. In at least one embodiment, the hypervisor real address space 2098 can be accessed via a hypervisor 2096, which virtualizes the graphics acceleration module engine for an operating system 2095.

[0229] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 2046. In at least one embodiment, there are two programming models in which the graphics acceleration module 2046 is shared by multiple processes and partitions, namely time-slice sharing and graphics-oriented sharing.

[0230] In at least one embodiment, in this model, the hypervisor 2096 owns the graphics acceleration module 2046 and makes its functionality available to all operating systems 2095. In at least one embodiment, for the graphics acceleration module 2046 to support virtualization through the hypervisor 2096, the graphics acceleration module 2046 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 2046 must provide a context saving and restoring mechanism, (2) the graphics acceleration module 2046 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 2046 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, the fairness of the graphics acceleration module 2046 among processes must be ensured.

[0231] In at least one embodiment, application 2080 needs to make system calls to operating system 2095 using the graphics acceleration module type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 2046 and can take the form of graphics acceleration module 2046 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 2046.

[0232] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 2036 (not shown) and the graphics acceleration module 2046 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 2096 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 2083. In at least one embodiment, CSRP is one of the registers 2045 that contains the effective address of a region in the effective address space 2082 of the application for the graphics acceleration module 2046 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0233] Upon receiving a system call, the operating system 2095 can verify that the application 2080 has been registered and granted permission to use the graphics acceleration module 2046. Then, in at least one embodiment, the operating system 2095 uses the information shown in Table 3 to invoke the hypervisor 2096. In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1596 verifies that the operating system 1595 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the hypervisor 1596 adds the process element 1583 to a linked list of process elements of the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4. In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 2090 registers 2045.

[0234] like Figure 20FAs shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 2001(1)-2001(N) and GPU memories 2020(1)-2020(N). In this implementation, operations performed on GPUs 2010(1)-2010(N) utilize the same virtual / effective memory address space to access processor memories 2001(1)-2001(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 2001(1), a second portion to second processor memory 2001(N), a third portion to GPU memory 2020(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 2001 and GPU memories 2020, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0235] In at least one embodiment, the bias / coherence management circuitry 2094A-2094E within one or more MMUs 2039A-2039E ensures cache coherence between the caches of one or more host processors (e.g., 2005) and the GPU 2010, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 20F Several instances of bias / coherence management circuits 2094A-2094E are shown, but bias / coherence circuits can be implemented within the MMU of one or more host processors 2005 and / or within the accelerator integrated circuit 2036.

[0236] One embodiment allows GPU memory 2020 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability of GPU memory 2020 to be accessed as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 2005 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 2020 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 2010. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0237] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached per GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in the GPU 2010, the bias table can be implemented within the stolen memory range of one or more GPU memories 2020. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0238] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 2020 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 2010 to find its page in the GPU bias is directly forwarded to the corresponding GPU memory 2020. In at least one embodiment, a local request from GPU to find its page in the host bias is forwarded to processor 2005 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 2005 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request to a GPU bias page can be forwarded to GPU 2010. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed by a software-based mechanism, a hardware-assisted software mechanism, or, in a limited set of cases, by a purely hardware-based mechanism.

[0239] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn invokes the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrating from the host processor 2005 bias to the GPU bias, but not for the reverse migration.

[0240] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 2005 cannot cache. In at least one embodiment, to access these pages, the processor 2005 may request access from the GPU 2010, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 2005 and the GPU 2010, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU rather than those needed by the host processor 2005, and vice versa.

[0241] One or more hardware structures 1215 are used to execute one or more embodiments. This can be combined with... Figure 12A and / or Figure 12B Provide details about one or more hardware structures 1215.

[0242] Figure 21Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which can be manufactured using one or more IP cores. In addition to those illustrated, at least one embodiment may also include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0243] Figure 21 This is a block diagram illustrating an exemplary system on a chip integrated circuit 2100 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 2100 includes one or more application processors 2105 (e.g., CPUs), at least one graphics processor 2110, and may additionally include an image processor 2115 and / or a video processor 2120, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 2100 includes peripheral or bus logic including a USB controller 2125, a UART controller 2130, an SPI / SDIO controller 2135, and an I2S / I2C controller 2140. In at least one embodiment, the integrated circuit 2100 may include a display device 2145 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 2150 and a Mobile Industrial Processor Interface (MIPI) display interface 2155. In at least one embodiment, storage may be provided by a flash memory subsystem 2160, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2165 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 2170.

[0244] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in integrated circuit 2100 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0245] In at least one embodiment, with Figure 21 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0246] Figures 22A-22BExemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be fabricated using one or more IP cores. In addition to those illustrated, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0247] Figures 22A-22B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 22A An exemplary graphics processor 2210 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 22B An additional exemplary graphics processor 2240 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 22A The graphics processor 2210 is a low-power graphics processor core. In at least one embodiment, Figure 22B The graphics processor 2240 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 2210, 2240 may be... Figure 21 A variant of the 2110 graphics processor.

[0248] In at least one embodiment, the graphics processor 2210 includes a vertex processor 2205 and one or more fragment processors 2215A-2215N (e.g., 2215A, 2215B, 2215C, 2215D to 2215N-1 and 2215N). In at least one embodiment, the graphics processor 2210 may execute different shader programs via separate logic, such that the vertex processor 2205 is optimized to perform operations for vertex shader programs, while one or more fragment processors 2215A-2215N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 2205 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 2215A-2215N use the primitive and vertex data generated by the vertex processor 2205 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 2215A-2215N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0249] In at least one embodiment, the graphics processor 2210 additionally includes one or more memory management units (MMUs) 2220A-2220B, one or more caches 2225A-2225B, and one or more circuit interconnects 2230A-2230B. In at least one embodiment, the one or more MMUs 2220A-2220B provide virtual-to-physical address mapping for the graphics processor 2210 (including for vertex processors 2205 and / or fragment processors 2215A-2215N), and may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 2225A-2225B. In at least one embodiment, the one or more MMUs 2220A-2220B may be synchronized with other MMUs within the system, including with... Figure 21 One or more application processors 2105, graphics processors 2115, and / or video processors 2120 are associated with one or more MMUs, such that each processor 2105-2120 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2230A-2230B enable the graphics processor 2210 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0250] In at least one embodiment, the graphics processor 2240 includes, as shown below: Figure 22B The one or more shader cores 2255A-2255N (e.g., 2255A, 2255B, 2255C, 2255D, 2255E, 2255F to 2255N-1 and 2255N) shown provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2240 includes an inter-core task manager 2245, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2255A-2255N and a tile unit 2258 to accelerate tile-based rendering operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0251] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12BDetails regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in graphics processors 2210 and / or 2240 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0252] In at least one embodiment, with Figure 22A and / or Figure 22B At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0253] Figures 23A-23B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, in... Figures 23A-23B Chinese illustration and combination Figures 23A-23B The described components are integrated into a single system, such as a graphics processing unit (GPU), a SoC, or another type of processor. In at least one embodiment, Figure 23A It shows that it can be included in Figure 21 The graphics core 2300 within the graphics processor 2110, and in at least one embodiment, may be as follows: Figure 22B The Unified Shader Core 2255A-2255N shown is an example. Figure 23B A highly parallel general-purpose graphics processing unit (“GPGPU”, which may also be referred to as a “graphics processing unit”) 2330 suitable for deployment on a multi-chip module is illustrated in at least one embodiment. In at least one embodiment, the graphics processing unit 2330 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 2100 includes a graphics core 2300, for example, for forming an integrated circuit and / or for forming a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0254] In at least one embodiment, the graphics core 2300 includes a shared instruction cache 2302, texture units 2318, and cache / shared memory 2320 (e.g., including L1, L2, L3, last-level cache, or other caches), which are shared for execution resources within the graphics core 2300. In at least one embodiment, the graphics core 2300 may include multiple slices 2301A-2301N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2300. In at least one embodiment, each slice 2301A-2301N refers to the graphics core 2300. In at least one embodiment, slices 2301A-2301N have sub-slices that are part of slices 2301A-2301N. In at least one embodiment, slices 2301A-2301N are independent of or dependent on other slices. In at least one embodiment, slices 2301A-2301N may include supporting logic, which includes local instruction caches 2304A-2304N, thread schedulers (orderers) 2306A-2306N, thread dispatchers 2308A-2308N, and a set of registers 2310A-2310N. In at least one embodiment, slices 2301A-2301N may include a set of additional functional units (AFU 2312A-2312N), floating-point units (FPU 2314A-2314N), integer arithmetic logic units (ALU 2316A-2316N), address calculation units (ACU 2313A-2313N), double-precision floating-point units (DPFPU 2315A-2315N), and matrix processing units (MPU 2317A-2317N). In at least one embodiment, the MPU 2317A-2317N is referred to as a matrix engine.

[0255] In at least one embodiment, each slice 2301A-2301N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 2301A-2301N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating-point (also known as "FP16"), 32-bit floating-point (also known as "FP32"), or 64-bit floating-point (also known as "FP64"). In at least one embodiment, one or more slices 2301A-2301N include 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, wherein the vector engines and math units are exposed through matrix expansion. In at least one embodiment, a designated portion of the processing unit's processing resources (e.g., 16 cores and ray tracing units or 8 cores), a thread scheduler, a thread allocator, and additional functional units of the processor are sliced. In at least one embodiment, the graphics core 2300 includes one or more matrix engines for computing matrix operations, for example, when computing tensor operations.

[0256] In at least one embodiment, one or more slices 2301A-2301N include one or more ray tracing units for calculating ray tracing operations (e.g., 16 ray tracing units per slice 2301A-2301N). In at least one embodiment, the ray tracing units calculate ray traversal, triangle intersection, bounding box intersection, or other ray tracing operations.

[0257] In at least one embodiment, one or more slices 2301A-2301N include media slices that encode, decode, and / or transcode data; scale and / or format convert data; and / or perform video quality operations on video data.

[0258] In at least one embodiment, one or more slices 2301A-2301N are linked to an L2 cache and memory architecture, a link connector, a high-bandwidth memory (HBM) stack (e.g., HBM2e, HDMI3), and a media engine. In at least one embodiment, one or more slices 2301A-2301N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 2301A-2301N have one or more L1 caches. In at least one embodiment, one or more slices 2301A-2301N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing, for example, data corresponding to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in a geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image having a vector graphics format (e.g., shapes) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel back-ends. In at least one embodiment, slices 2301A-2301N include memory structures, such as L2 caches.

[0259] In at least one embodiment, the FPU 2314A-2314N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2315A-2315N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2316A-2316N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2317A-2317N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2317A-2317N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2312A-2312N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric function operations (e.g., sine, cosine, etc.).

[0260] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in graphics core 2300 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0261] In at least one embodiment, the graphics core 2300 includes an interconnect and link structure sublayer attached to a switch and a GPU-GPU bridge, which enable multiple graphics processors 2300 (e.g., 8) to be interconnected via load / memory units (LSUs), data transfer units, and synchronization semantics across the multiple graphics processors 2300 without being glued together. In at least one embodiment, the interconnect includes standardized interconnects (e.g., PCIe) or some combination thereof.

[0262] In at least one embodiment, the graphics core 2300 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, wherein a single die may be connected to an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 2300 includes compute tiles, memory tiles (e.g., where memory tiles may be exclusively accessed by different tiles or different chipsets (such as Rambo tiles), substrate tiles, pedestal tiles, HMB tiles, link tiles, and EMIB tiles, wherein all tiles are packaged together in the graphics core 2300 as part of the GPU. In at least one embodiment, the graphics core 2300 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile may have eight graphics cores 2300, an L1 cache; and a pedestal tile may have host interfaces with PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, the tiles are bonded to the chip-on-chip face-to-face (F2F) via fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 2300 includes a memory structure that includes memory and is tiles accessible by a plurality of tiles. In at least one embodiment, the graphics core 2300 stores, accesses, or loads its own hardware context into memory, wherein the hardware context is a set of data loaded from registers before process resumption, and wherein the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0263] In at least one embodiment, the graphics core 2300 includes a serializer / deserializer (SERDES) circuit that converts a serial data stream into a parallel data stream, or a parallel data stream into a serial data stream.

[0264] In at least one embodiment, the graphics core 2300 includes a high-speed coherent unified architecture (GPU-to-GPU), a load / store unit, bulk data transfer and synchronization semantics, and a GPU connected via an embedded switch, wherein the GPU-to-GPU bridge is controlled by a controller.

[0265] In at least one embodiment, the graphics core 2300 executes an API, wherein the API abstracts the hardware of the graphics core 2300 and uses instructions to access libraries to perform mathematical operations (e.g., a mathematical kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communication, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0266] In at least one embodiment, with Figure 23A At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0267] Figure 23BA GPGPU 2330 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 2330 can be directly linked to other instances of the GPGPU 2330 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 2330 includes a host interface 2332 for establishing a connection to a host processor. In at least one embodiment, the host interface 2332 is a PCI Express interface. In at least one embodiment, the host interface 2332 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2330 receives commands from the host processor and uses a global scheduler 2334 (which may be referred to as a thread sequencer and / or asynchronous computing engine) to allocate the execution threads associated with those commands to a set of computing clusters 2336A-2336H. In at least one embodiment, the computing clusters 2336A-2336H share a cache memory 2338. In at least one embodiment, cache memory 2338 may be used as a higher-level cache than the cache memory within compute clusters 2336A-2336H. In at least one embodiment, compute clusters 2336A-2336H include slices, or are referred to as "slices". In at least one embodiment, GPGPU 2330 is part of a SoC, such as part of integrated circuit 2100. Figure 21 ).

[0268] In at least one embodiment, the GPGPU 2330 includes memories 2344A-2344B coupled to a computing cluster 2336A-2336H via a set of memory controllers 2342A-2342B (e.g., one or more controllers for HBM2e). In at least one embodiment, memories 2344A-2344B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0269] In at least one embodiment, each of the computing clusters 2336A-2336H includes a set of graphics cores, such as Figure 23AThe graphics core 2300 may include various types of integer and floating-point logic units that can perform computational operations over a range of precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2336A-2336H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0270] In at least one embodiment, multiple instances of GPGPU 2330 can be configured to operate as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by computing clusters 2336A-2336H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2330 communicate via host interface 2332. In at least one embodiment, GPGPU 2330 includes an I / O hub 2339 that couples GPGPU 2330 to GPU link 2340, which provides direct connectivity to other instances of GPGPU 2330. In at least one embodiment, GPU link 2340 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2330. In at least one embodiment, GPU link 2340 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2330 reside in a separate data processing system and communicate via a network device accessible via host interface 2332. In at least one embodiment, in addition to or as an alternative to host interface 2332, GPU link 2340 may also be configured to implement a connection to the host processor.

[0271] In at least one embodiment, the GPGPU 2330 can be configured to train a neural network. In at least one embodiment, the GPGPU 2330 can be used within an inference platform. In at least one embodiment, when using the GPGPU 2330 for inference, the GPGPU 2330 may include fewer compute clusters 2336A-2336H compared to when using the GPGPU 2330 to train a neural network. In at least one embodiment, the memory technology associated with memories 2344A-2344B can differ between inference and training configurations, wherein a higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2330 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0272] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in GPGPU 2330 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0273] In at least one embodiment, with Figure 23B At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0274] Figure 24 This is a block diagram illustrating a computing system 2400 according to at least one embodiment. In at least one embodiment, the computing system 2400 includes a processing subsystem 2401 having one or more processors 2402 and a system memory 2404 communicating via an interconnect path that may include a memory hub 2405. In at least one embodiment, the memory hub 2405 may be a separate component within a chipset assembly or may be integrated within one or more processors 2402. In at least one embodiment, the memory hub 2405 is coupled to an I / O subsystem 2411 via a communication link 2406. In at least one embodiment, the I / O subsystem 2411 includes an I / O hub 2407 that enables the computing system 2400 to receive input from one or more input devices 2408. In at least one embodiment, the I / O hub 2407 enables a display controller to provide output to one or more display devices 2410A, the display controller being included in one or more processors 2402. In at least one embodiment, one or more display devices 2410A coupled to the I / O hub 2407 may include local, internal, or embedded display devices.

[0275] In at least one embodiment, the processing subsystem 2401 includes one or more parallel processors 2412 coupled to the memory hub 2405 via a bus or other communication link 2413. In at least one embodiment, the communication link 2413 may use one of any number of standards based on a communication link technology or protocol (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 2412 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as integrated many-core (MIC) processors. In at least one embodiment, some or all of the parallel processors 2412 form a graphics processing subsystem that can output pixels to one or more display devices 2410A coupled via an I / O hub 2407. In at least one embodiment, one or more parallel processors 2412 may also include a display controller and a display interface (not shown) for implementing direct connection to one or more display devices 2410B. In at least one embodiment, one or more parallel processors 2412 include one or more cores, such as the graphics core 2300 discussed herein.

[0276] In at least one embodiment, system storage unit 2414 may be connected to I / O hub 2407 to provide a storage mechanism for computing system 2400. In at least one embodiment, I / O switch 2416 may be used to provide an interface mechanism for enabling connectivity between I / O hub 2407 and other components, such as network adapter 2418 and / or wireless network adapter 2419 integrated into the platform, and various other devices that may be added via one or more additional devices 2420. In at least one embodiment, network adapter 2418 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2419 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless devices.

[0277] In at least one embodiment, the computing system 2400 may include other components, not explicitly shown, that may also be connected to the I / O hub 2407, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnect can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect or interconnect protocols). Figure 24The communication paths of each component.

[0278] In at least one embodiment, one or more parallel processors 2412 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). For example, one or more parallel processors 2412 include a graphics core 2300. In at least one embodiment, one or more parallel processors 2412 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 2400 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2412, a memory hub 2405, one or more processors 2402, and an I / O hub 2407 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 2400 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 2400 may be integrated into a multi-chip module (MCM), which may interconnect with other MCMs to a modular computing system.

[0279] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in computing system 2400 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0280] In at least one embodiment, with Figure 24 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0281] processor Figure 25A A parallel processor 2500 according to at least one embodiment is illustrated. In at least one embodiment, the various components of the parallel processor 2500 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2500 is according to an exemplary embodiment. Figure 24Variations of the one or more parallel processors 2412 shown. In at least one embodiment, the parallel processor 2500 includes one or more graphics cores 2300.

[0282] In at least one embodiment, the parallel processor 2500 includes a parallel processing unit 2502. In at least one embodiment, the parallel processing unit 2502 includes an I / O unit 2504 that enables communication with other devices, including other instances of the parallel processing unit 2502. In at least one embodiment, the I / O unit 2504 can be directly connected to other devices. In at least one embodiment, the I / O unit 2504 is connected to other devices via a hub or switch interface (e.g., a memory hub 2505). In at least one embodiment, the connection between the memory hub 2505 and the I / O unit 2504 forms a communication link 2513. In at least one embodiment, the I / O unit 2504 is connected to a host interface 2506 and a memory crossbar switch 2516, wherein the host interface 2506 receives commands for performing processing operations, and the memory crossbar switch 2516 receives commands for performing memory operations.

[0283] In at least one embodiment, when host interface 2506 receives a command buffer via I / O unit 2504, host interface 2506 can route work operations for executing those commands to front end 2508. In at least one embodiment, front end 2508 is coupled to scheduler 2510, which (which may be referred to as an orderer) is configured to assign commands or other work items to processing cluster array 2512. In at least one embodiment, scheduler 2510 ensures that processing cluster array 2512 is correctly configured and in an active state before assigning tasks to clusters in processing cluster array 2512. In at least one embodiment, scheduler 2510 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 2510 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing cluster array 2512. In at least one embodiment, host software can demonstrate workloads for scheduling on processing cluster array 2512 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing cluster array 2512 by the scheduler 2510 logic within the microcontroller, which includes the scheduler 2510.

[0284] In at least one embodiment, the processing cluster array 2512 may include up to "N" processing clusters (e.g., clusters 2514A, 2514B to 2514N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other diagrams). In at least one embodiment, each cluster 2514A-2514N of the processing cluster array 2512 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2510 may use various scheduling and / or work allocation algorithms to allocate work to clusters 2514A-2514N in the processing cluster array 2512, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2510, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2512. In at least one embodiment, different clusters 2514A-2514N in the processing cluster array 2512 may be assigned to process different types of programs or to perform different types of computations.

[0285] In at least one embodiment, the processing cluster array 2512 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2512 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2512 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0286] In at least one embodiment, the processing cluster array 2512 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2512 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2512 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2502 may transfer data from system memory via I / O unit 2504 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2522) and then written back to system memory.

[0287] In at least one embodiment, when the parallel processing unit 2502 is used to perform graphics processing, the scheduler 2510 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among multiple clusters 2514A-2514N in the processing cluster array 2512. In at least one embodiment, portions of the processing cluster array 2512 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2514A-2514N can be stored in a buffer to allow intermediate data to be transferred between the clusters 2514A-2514N for further processing.

[0288] In at least one embodiment, the processing cluster array 2512 may receive processing tasks to be executed via a scheduler 2510, which receives commands defining the processing tasks from a front end 2508. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2510 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2508. In at least one embodiment, the front end 2508 may be configured to ensure that the processing cluster array 2512 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0289] In at least one embodiment, each of one or more instances of the parallel processing unit 2502 may be coupled to the parallel processor memory 2522. In at least one embodiment, the parallel processor memory 2522 may be accessed via a memory crossbar switch 2516, which may receive memory requests from the processing cluster array 2512 and the I / O unit 2504. In at least one embodiment, the memory crossbar switch 2516 may be accessed via a memory interface 2518. In at least one embodiment, the memory interface 2518 may include a plurality of partition units (e.g., partition units 2520A, 2520B to 2520N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2522. In at least one embodiment, the number of partition units 2520A-2520N is configured to be equal to the number of memory units, such that the first partition unit 2520A has a corresponding first memory unit 2524A, the second partition unit 2520B has a corresponding second memory unit 2524B, and the Nth partition unit 2520N has a corresponding Nth memory unit 2524N. In at least one embodiment, the number of partition units 2520A-2520N may not be equal to the number of memory units.

[0290] In at least one embodiment, memory cells 2524A-2524N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2524A-2524N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2524A-2524N, allowing partitioning cells 2520A-2520N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2522. In at least one embodiment, local instances of the parallel processor memory 2522 may be excluded to facilitate a unified memory design that utilizes system memory and local cache memory.

[0291] In at least one embodiment, any of clusters 2514A-2514N in the processing cluster array 2512 can process data to be written to any memory cell 2524A-2524N within the parallel processor memory 2522. In at least one embodiment, the memory crossbar switch 2516 can be configured to transfer the output of each cluster 2514A-2514N to any partition cell 2520A-2520N or another cluster 2514A-2514N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2514A-2514N can communicate with the memory interface 2518 via the memory crossbar switch 2516 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar switch 2516 has a connection to a memory interface 2518 for communicating with I / O unit 2504, and a connection to a local instance of parallel processor memory 2522, enabling processing units within different processing clusters 2514A-2514N to communicate with system memory or other memory not local to parallel processing unit 2502. In at least one embodiment, the memory crossbar switch 2516 may use virtual channels to separate traffic flows between clusters 2514A-2514N and partition units 2520A-2520N.

[0292] In at least one embodiment, multiple instances of the parallel processing unit 2502 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2502 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2502 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system including one or more instances of the parallel processing unit 2502 or the parallel processor 2500 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0293] Figure 25B This is a block diagram of a partitioning unit 2520 according to at least one embodiment. In at least one embodiment, the partitioning unit 2520 is... Figure 25AThis is an example of one of the partitioning units 2520A-2520N. In at least one embodiment, the partitioning unit 2520 includes an L2 cache 2521, a frame buffer interface 2525, and a ROP 2526 (raster operation unit). In at least one embodiment, the L2 cache 2521 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2516 and the ROP 2526. In at least one embodiment, the L2 cache 2521 outputs read misses and urgent write-back requests to the frame buffer interface 2525 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2525. In at least one embodiment, the frame buffer interface 2525 communicates with memory cells in the parallel processor memory (such as...). Figure 25A It is coupled to one of the memory cells 2524A-2524N (e.g., within the parallel processor memory 2522).

[0294] In at least one embodiment, ROP 2526 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2526 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2526 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2526 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data per tile.

[0295] In at least one embodiment, ROP 2526 is included within each processing cluster (e.g., Figure 25A The clusters 2514A-2514N are used instead of the partition unit 2520. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted via the memory crossbar switch 2516. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 24 Displayed on one or more display devices 2410, routed by processor 2402 for further processing, or by... Figure 25A One of the processing entities within the parallel processor 2500 is routed for further processing.

[0296] Figure 25C This is a block diagram of a processing cluster 2514 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 25AAn instance of one of the processing clusters 2514A-2514N. In at least one embodiment, the processing cluster 2514 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of typically synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0297] In at least one embodiment, the operation of the processing cluster 2514 can be controlled via a pipeline manager 2532 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2532... Figure 25A The scheduler 2510 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2534 and / or texture unit 2536. In at least one embodiment, the graphics multiprocessor 2534 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2514 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2514 may include one or more instances of the graphics multiprocessor 2534. In at least one embodiment, the graphics multiprocessor 2534 can process data, and the data crossover switch 2540 can be used to allocate the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2532 can facilitate the allocation of processed data by specifying the destination of the processed data to be allocated via the data crossover switch 2540.

[0298] In at least one embodiment, each graphics multiprocessor 2534 within the processing cluster 2514 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0299] In at least one embodiment, instructions sent to the processing cluster 2514 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group can be assigned to a different processing engine within the graphics multiprocessor 2534. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2534. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2534. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2534, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 2534.

[0300] In at least one embodiment, the graphics multiprocessor 2534 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2534 may forgo the internal cache and use a cache memory within the processing cluster 2514 (e.g., L1 cache 2548). In at least one embodiment, each graphics multiprocessor 2534 may also access partition units (e.g., Figure 25A The L2 cache is located within partition units 2520A-2520N, which are shared among all processing clusters 2514 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2534 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2502 can be used as global memory. In at least one embodiment, the processing cluster 2514 includes multiple instances of the graphics multiprocessor 2534, which can share common instructions and data that can be stored in the L1 cache 2548.

[0301] In at least one embodiment, each processing cluster 2514 may include a memory management unit (“MMU”) 2545 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2545 may reside in Figure 25AThe memory interface 2518 is located within the MMU 2545. In at least one embodiment, the MMU 2545 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2545 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2534, the L1 cache 2548, or the processing cluster 2514. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0302] In at least one embodiment, the processing cluster 2514 can be configured such that each graphics multiprocessor 2534 is coupled to a texture unit 2536 to perform a texture mapping operation that determines texture sample locations, reads texture data, and filters texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2534, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2534 outputs a processed task to a data crossbar switch 2540 to provide the processed task to another processing cluster 2514 for further processing, or stores the processed task in an L2 cache, local parallel processor memory, or in system memory via a memory crossbar switch 2516. In at least one embodiment, a preROP 2542 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2534 and direct the data to a ROP unit, which can be associated with a partitioning unit (e.g., [missing information]). Figure 25A The PreROP 2542 unit is located together with the partitioning units 2520A-2520N. In at least one embodiment, the PreROP 2542 unit can perform optimizations for color mixing, organizing pixel color data, and performing address translation.

[0303] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in graphics processing cluster 2514 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0304] In at least one embodiment, with Figure 24 A, Figure 24 B and / or Figure 24 At least one embodiment of C includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0305] Figure 25D A graphics multiprocessor 2534 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2534 is coupled to a pipeline manager 2532 of a processing cluster 2514. In at least one embodiment, the graphics multiprocessor 2534 has an execution pipeline including, but not limited to, an instruction cache 2552, an instruction unit 2554, an address mapping unit 2556, a register file 2558, one or more general-purpose graphics processing unit (GPGPU) cores 2562, and one or more load / store units 2566, wherein one or more load / store units 2566 are capable of performing load / store operations to load / store instructions corresponding to the execution operations. In at least one embodiment, the GPGPU cores 2562 and the load / store units 2566 are coupled to a cache memory 2572 and a shared memory 2570 via a memory and cache interconnect 2568. In at least one embodiment, the GPGPU cores 2562 are part of a SoC, for example... Figure 21 It is part of the integrated circuit 2100.

[0306] In at least one embodiment, instruction cache 2552 receives a stream of instructions to be executed from pipeline manager 2532. In at least one embodiment, instructions are cached in instruction cache 2552 and dispatched for execution by instruction unit 2554. In at least one embodiment, instruction unit 2554 may dispatch instructions as thread groups (e.g., thread bundles, wavefronts, waves), wherein each thread in the thread group is assigned to a different execution unit within GPGPU core 2562. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2556 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2566.

[0307] In at least one embodiment, register file 2558 provides a set of registers for functional units of graphics multiprocessor 2534. In at least one embodiment, register file 2558 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2534 (e.g., GPGPU core 2562, load / store unit 2566). In at least one embodiment, register file 2558 is partitioned between each functional unit, such that a dedicated portion of register file 2558 is allocated to each functional unit. In at least one embodiment, register file 2558 is partitioned between different thread bundles (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 2534.

[0308] In at least one embodiment, each GPGPU core 2562 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2534. In at least one embodiment, the architectures of the various GPGPU cores 2562 may be similar or different. In at least one embodiment, a first portion of the GPGPU core 2562 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2534 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2562 may also include fixed-function or special-function logic.

[0309] In at least one embodiment, the GPGPU core 2562 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2562 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0310] In at least one embodiment, the memory and cache interconnect 2568 is an interconnect network connecting each functional unit of the graphics multiprocessor 2534 to the register file 2558 and the shared memory 2570. In at least one embodiment, the memory and cache interconnect 2568 is a cross-switch interconnect that allows the load / store unit 2566 to perform load and store operations between the shared memory 2570 and the register file 2558. In at least one embodiment, the register file 2558 can operate at the same frequency as the GPGPU core 2562, resulting in very low latency for data transfer between the GPGPU core 2562 and the register file 2558. In at least one embodiment, the shared memory 2570 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 2534. In at least one embodiment, the cache memory 2572 can be used, for example, as a data cache for caching texture data communicated between functional units and texture units 2536. In at least one embodiment, the shared memory 2570 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2572, the thread executing on GPGPU core 2562 can also programmatically store data in shared memory.

[0311] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the SoC includes a parallel processor or GPGPU, as described herein, which executes on the SoC. In at least one embodiment, the GPU may be integrated with the core in a package or on a chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0312] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12BDetails regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in graphics multiprocessor 2534 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0313] In at least one embodiment, with Figure 25D At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0314] Figure 26 A multi-GPU computing system 2600 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 2600 may include a processor 2602 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2606A-D via a host interface switch 2604. In at least one embodiment, the host interface switch 2604 is a PCI Express switch device that couples the processor 2602 to a PCI Express bus, through which the processor 2602 can communicate with the GPGPUs 2606A-D. In at least one embodiment, the GPGPUs 2606A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 2616. In at least one embodiment, the GPU-to-GPU links 2616 are connected to each of the GPGPUs 2606A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2616 enable direct communication between each GPGPU 2606A-D without communication via the host interface bus 2604 to which the processor 2602 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 2616, the host interface bus 2604 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 2600 via one or more network devices. While in at least one embodiment, the GPGPU 2606A-D is connected to the processor 2602 via the host interface switch 2604, in at least one embodiment, the processor 2602 includes direct support for the P2P GPU link 2616 and can be directly connected to the GPGPU 2606A-D. In at least one embodiment, the GPGPU 2606A-D is part of a SoC, such as... Figure 21 It is part of the integrated circuit 2100, in which the GPGPU 2606A-D performs the operations described herein.

[0315] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in a multi-GPU computing system 2600 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0316] In at least one embodiment, the multi-GPU computing system 2600 includes one or more graphics cores 2300.

[0317] In at least one embodiment, with Figure 26 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0318] Figure 27 This is a block diagram of a graphics processor 2700 according to at least one embodiment. In at least one embodiment, the graphics processor 2700 includes a ring interconnect 2702, a pipeline front end 2704, a media engine 2737, and graphics cores 2780A-2780N. In at least one embodiment, the ring interconnect 2702 couples the graphics processor 2700 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2700 is one of many processors integrated within a multi-core processing system. In at least one embodiment, the graphics processor 2700 includes a graphics core 2300.

[0319] In at least one embodiment, the graphics processor 2700 receives multiple batches of commands via a ring interconnect 2702. In at least one embodiment, the input commands are interpreted by a command streamer 2703 in a pipeline front-end 2704. In at least one embodiment, the graphics processor 2700 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2780A-2780N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2703 provides the commands to the geometry pipeline 2736. In at least one embodiment, for at least some media processing commands, the command streamer 2703 provides the commands to a video front-end 2734, which is coupled to a media engine 2737. In at least one embodiment, the media engine 2737 includes a video quality engine (VQE) 2730 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2733 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2736 and the media engine 2737 each generate an execution thread for thread execution resources provided by at least one graphics core 2780.

[0320] In at least one embodiment, the graphics processor 2700 includes scalable thread execution resources featuring graphics cores 2780A-2780N (which may be modular and sometimes referred to as core slices), each graphics core having multiple sub-cores 2750A-2750N, 2760A-2760N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2700 may have any number of graphics cores 2780A. In at least one embodiment, the graphics processor 2700 includes graphics cores 2780A having at least a first sub-core 2750A and a second sub-core 2760A. In at least one embodiment, the graphics processor 2700 is a low-power processor having a single sub-core (e.g., 2750A). In at least one embodiment, the graphics processor 2700 includes multiple graphics cores 2780A-2780N, each graphics core including a set of first sub-cores 2750A-2750N and a set of second sub-cores 2760A-2760N. In at least one embodiment, each of the first sub-cores 2750A-2750N includes at least a first set of execution units 2752A-2752N and media / texture samplers 2754A-2754N. In at least one embodiment, each of the second sub-cores 2760A-2760N includes at least a second set of execution units 2762A-2762N and samplers 2764A-2764N. In at least one embodiment, each sub-core 2750A-2750N and 2760A-2760N shares a set of shared resources 2770A-2770N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic. In at least one embodiment, the graphics processor 2700 includes load / store units in a pipeline front-end 2704.

[0321] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, logic 1215 may be used in graphics processor 2700 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0322] In at least one embodiment, with Figure 27 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0323] Figure 28 This is a block diagram illustrating a microarchitecture for a processor 2800 according to at least one embodiment, the processor 2800 including logic circuitry for executing instructions. In at least one embodiment, the processor 2800 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 2800 can include registers for storing packaged data, such as 64-bit wide MMX™ registers in a microprocessor implemented using MMX technology from Intel Corporation, Santa Clara, California. In at least one embodiment, MMX registers available in both integer and floating-point forms can operate with packaged data elements accompanying Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (beyond) (commonly referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, the processor 2800 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0324] In at least one embodiment, processor 2800 includes an ordered front end (“front end”) 2801 for fetching instructions to be executed and preparing instructions for later use in the processor pipeline. In at least one embodiment, front end 2801 may include several units. In at least one embodiment, instruction prefetcher 2826 fetches instructions from memory and feeds the instructions to instruction decoder 2828, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2828 decodes the received instructions into one or more machine-executable so-called “micro-operations” or “micro-instructions” (also referred to as “micro ops”, “uops”, or “µ-ops”). In at least one embodiment, instruction decoder 2828 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2830 may assemble the decoded micro-operations into an ordered sequence or trace of programs in micro-operation queue 2834 for execution. In at least one embodiment, when the trace cache 2830 encounters a complex instruction, the microcode ROM 2832 provides the micro-operations required to complete the operation.

[0325] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2828 may access the microcode ROM 2832 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-operations for processing at the instruction decoder 2828. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2832. In at least one embodiment, the tracking cache 2830 references the entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2832 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2832 has completed the serialization of the micro-operations of the instruction, the machine front end 2801 may resume fetching micro-operations from the tracking cache 2830.

[0326] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2803 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as the instruction stream moves down the pipeline and is scheduled for execution. In at least one embodiment, the out-of-order execution engine 2803 includes, but is not limited to, an allocator / register renamer 2840, a memory micro-operation queue 2842, an integer / floating-point micro-operation queue 2844, a memory scheduler 2846, a fast scheduler 2802, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2804, and a simple floating-point scheduler (“simple FP scheduler”) 2806. In at least one embodiment, the fast scheduler 2802, the slow / general-purpose floating-point scheduler 2804, and the simple floating-point scheduler 2806 are also collectively referred to herein as “micro-operation schedulers 2802, 2804, 2806”. In at least one embodiment, the allocator / register renamer 2840 allocates the machine buffers and resources required for each micro-operation to execute. In at least one embodiment, the allocator / register renamer 2840 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2840 also allocates entries for each micro-operation in one of two micro-operation queues, preceding the memory scheduler 2846 and micro-operation schedulers 2802, 2804, 2806, with memory micro-operation queue 2842 for memory operations and integer / floating-point micro-operation queue 2844 for non-memory operations. In at least one embodiment, the micro-operation schedulers 2802, 2804, 2806 determine when a micro-operation is ready to be executed based on the readiness of their dependent input register operand sources and the availability of execution resources required for the micro-operation to complete its operation. In at least one embodiment, the fast scheduler 2802 may schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2804 and the simple floating-point scheduler 2806 may schedule once per master processor clock cycle. In at least one embodiment, micro-operation schedulers 2802, 2804, and 2806 arbitrate dispatch ports to schedule micro-operations for execution.

[0327] In at least one embodiment, execution block 2811 includes, but is not limited to, integer register file / bypass network 2808, floating-point register file / bypass network (“FP register file / bypass network”) 2810, address generation units (“AGU”) 2812 and 2814, fast arithmetic logic units (ALU) (“fast ALU”) 2816 and 2818, slow arithmetic logic unit (“slow ALU”) 2820, floating-point ALU (“FP”) 2822, and floating-point move unit (“FP move”) 2824. In at least one embodiment, integer register file / bypass network 2808 and floating-point register file / bypass network 2810 are also referred to herein as “register files 2808, 2810”. In at least one embodiment, AGUs 2812 and 2814, fast ALUs 2816 and 2818, slow ALU 2820, floating-point ALU 2822, and floating-point movement unit 2824 are also referred to herein as "execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824". In at least one embodiment, execution block 2811 may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0328] In at least one embodiment, register networks 2808, 2810 may be arranged between micro-operation schedulers 2802, 2804, 2806 and execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824. In at least one embodiment, integer register file / bypass network 2808 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2810 performs floating-point operations. In at least one embodiment, each of register networks 2808, 2810 may include, but is not limited to, a bypass network that can bypass a recently completed result that has not yet been written to the register file or forward it to a new relevant micro-operation. In at least one embodiment, register networks 2808, 2810 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2808 may include, but is not limited to, two separate register files, one for low-order 32-bit data and the other for high-order 32-bit data. In at least one embodiment, the floating-point register file / bypass network 2810 may include, but is not limited to, 128-bit wide entries, since floating-point instructions typically have operands with widths ranging from 64 to 128 bits.

[0329] In at least one embodiment, execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824 can execute instructions. In at least one embodiment, register networks 2808 and 2810 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2800 can be, but is not limited to, any number of execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824, and combinations thereof. In at least one embodiment, floating-point ALU 2822 and floating-point move unit 2824 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2822 can be, but is not limited to, a 64-bit multiplication-64-bit floating-point divider for performing division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2816 and 2818. In at least one embodiment, the fast ALUs 2816 and 2818 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2820, because the slow ALU 2820 can include, but is not limited to, integer execution hardware for long-delay type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGUs 2812 and 2814. In at least one embodiment, the fast ALU 2816, fast ALU 2818, and slow ALU 2820 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2816, fast ALU 2818, and slow ALU 2820 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2822 and the floating-point moving unit 2824 can be implemented to support a range of operands with various bit widths, such as supporting 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0330] In at least one embodiment, micro-operation schedulers 2802, 2804, and 2806 dispatch dependent operations before the parent load has completed execution. In at least one embodiment, since micro-operations can be speculatively scheduled and executed within processor 2800, processor 2800 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily prevents the scheduler from accessing the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, replaying dependent operations may be necessary and may allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences used for text string comparison operations.

[0331] In at least one embodiment, "register" can refer to an onboard processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register can be one that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuitry. Rather, in at least one embodiment, a register can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0332] In at least one embodiment, processor 2800 or each core of processor 2800 includes one or more prefetchers, one or more extractors, one or more predecoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g., corresponding to operations or API calls), one or more micro-operation (µOP) caches for storing µOPs, one or more micro-operation (µOP) queues, an ordered execution engine, one or more load buffers, one or more store buffers, one or more reorder buffers, one or more fill buffers, an out-of-order execution engine, one or more ports, one or more shift and / or shifter units, one or more fused multiply-accumulate (FMA) units, one or more load and store units (“LSUs”) for performing loads (e.g., instructions) of store operations corresponding to load / store data, for performing operations (e.g., executing APIs, API calls), one or more matrix multiply-accumulate (MMA) units, and / or one or more shuffle units to perform any functions further described herein with respect to the processor 2800. In at least one embodiment, the processor 2800 can access, use, execute, or perform instructions corresponding to calling an API.

[0333] In at least one embodiment, processor 2800 includes, for example, one or more superpath interconnects (UPIs) such as point-to-point processor interconnects; one or more PCIe interfaces; one or more accelerators for accelerating computation or operation; and / or one or more memory controllers. In at least one embodiment, processor 2800 includes a shared final-level cache (LLC) coupled to one or more memory controllers, which enables shared memory access across processor cores.

[0334] In at least one embodiment, the processor 2800 or its core has a mesh architecture, wherein the processor core, on-chip cache, memory controller, and I / O controller are organized into rows and columns, with wires and switches connecting them at each intersection to allow for bends. In at least one embodiment, the processor 2800 has one or more higher memory bandwidths (HMB, e.g., HMBe) to store or cache data, for example, in Double Data Rate 5 Synchronous Dynamic Random Access Memory (DDR5 SDRAM). In at least one embodiment, one or more components of the processor 2800 are interconnected using Compute Fast Link (CXL) interconnects. In at least one embodiment, the memory controller uses a Least Recently Used (LRU) method to determine what is stored in the cache. In at least one embodiment, the processor 2800 includes one or more PCIe instances (e.g., PCIe 5.0).

[0335] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, part or all of logic 1215 may be incorporated into execution block 2811 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2811. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2811 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0336] In at least one embodiment, with Figure 28 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0337] Figure 29A deep learning application processor 2900 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2900 uses instructions that, if executed by the deep learning application processor 2900, cause the deep learning application processor 2900 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2900 is an application-specific integrated circuit (ASIC). In at least one embodiment, as a result of executing one or more instructions or both, the application processor 2900 performs matrix multiplication operations or is "hardwired" into hardware. In at least one embodiment, the deep learning application processor 2900 includes, but is not limited to, processing clusters 2910(1)-2910(12), inter-chip links (“ICL”) 2920(1)-2920(12), inter-chip controllers (“ICC”) 2930(1)-2930(2), second-generation high-bandwidth memory (“HBM2”) 2940(1)-2940(4), memory controllers (“Mem Ctrlr”) 2942(1)-2942(4), high-bandwidth memory physical layers (“HBM PHY”) 2944(1)-2944(4), management controller central processing unit (“management controller CPU”) 2950, ​​serial peripheral device interfaces, internal integrated circuits and general purpose input / output blocks (“SPI, I2C, GPIO”) 2960, peripheral component interconnect fast controllers and direct memory access blocks (“PCIe controllers and DMA”) 2970, and sixteen-channel peripheral component interconnect fast ports (“PCI Express x”). 16”2980.

[0338] In at least one embodiment, processing cluster 2910 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2910 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2900 can include any number and type of processing cluster 2900. In at least one embodiment, inter-chip link 2920 is bidirectional. In at least one embodiment, inter-chip link 2920 and inter-chip controller 2930 enable multiple deep learning application processors 2900 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2900 can include any number (including zero) and type of ICL 2920 and ICC 2930.

[0339] In at least one embodiment, the HBM2 2940 provides a total of 32 GB of memory. In at least one embodiment, the HBM2 2940(i) is associated with both the memory controller 2942(i) and the HBM PHY 2944(i), where “i” is any integer. In at least one embodiment, any number of HBM2 2940s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2942 and HBM PHY 2944. In at least one embodiment, any number and type of blocks implementing any number and type of communication standards can replace SPI, I2C, GPIO 2960, PCIe controller, and DMA 2970 and / or PCIe 2980 in any technically feasible manner.

[0340] Logic 1215 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 12A and / or Figure 12B Details regarding logic 1215 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the deep learning application processor 2900. In at least one embodiment, the deep learning application processor 2900 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2900. In at least one embodiment, the processor 2900 may be used to perform one or more neural network use cases described herein.

[0341] In at least one embodiment, with Figure 29 At least one embodiment consistent with the above includes one or more processors, circuits, or systems for implementing a machine learning platform capable of automatically selecting low-precision data formats for processing neural network models, as described above. Figures 1 to 11 The subject of discussion.

[0342] Figure 30This is a block diagram of a neuromorphic processor 3000 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 3000 may receive one or more inputs from a source external to the neuromorphic processor 3000. In at least one embodiment, these inputs may be transmitted to one or more neurons 3002 within the neuromorphic processor 3000. In at least one embodiment, the neurons 3002 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 3000 may include, but is not limited to, thousands or millions of instances of neurons 3002, but any suitable number of neurons 3002 may be used. In at least one embodiment, each instance of a neuron 3002 may include a neuron input 3004 and a neuron output 3006. In at least one embodiment, a neuron 3002 may generate an output that can be transmitted to inputs of other instances of the neuron 3002. For example, in at least one embodiment, neuron inputs 3004 and neuron outputs 3006 may be interconnected via synapses 3008.

[0343] In at least one embodiment, neuron 3002 and synapse 3008 may be interconnected, causing neuromorphic processor 3000 to operate to process or analyze information received by neuromorphic processor 3000. In at least one embodiment, neuron 3002 may send an output pulse (or "fire" or "spike") when the input received through neuron input 3004 exceeds a threshold. In at least one embodiment, neuron 3002 may sum or integrate the signal received at neuron input 3004. For example, in at least one embodiment, neuron 3002 may be implemented as a leaky integrate-and-fire neuron, wherein if the summation (referred to as "membrane potential") exceeds a threshold, neuron 3002 may use a transfer function such as a sigmoid or threshold function to generate an output (or "fire"). In at least one embodiment, the leaky integrate-and-fire neuron may sum the signal received at neuron input 3004 to a membrane potential and may also apply an attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky, integrated firing neuron may fire if multiple input signals are received at neuron input 3004 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to fire). In at least one embodiment, neuron 3002 may be implemented using circuitry or logic that receives input, integrates the input into a membrane potential, and decays the membrane potential. In at least one embodiment, the input may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 3002 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 3006 when the result of applying the transfer function to neuron input 3004 exceeds a threshold. In at least one embodiment, once neuron 3002 fires, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 3002 may resume normal operation after a suitable time period (or refractory period).

[0344] In at least one embodiment, neurons 3002 can be interconnected via synapses 3008. In at least one embodiment, synapses 3008 are operable to transmit signals from the output of a first neuron 3002 to the input of a second neuron 3002. In at least one embodiment, neurons 3002 can transmit information on more than one instance of synapses 3008. In at least one embodiment, one or more instances of neuron outputs 3006 can be connected via instances of synapses 3008 to instances of neuron inputs 3004 in the same neuron 3002. In at least one embodiment, an instance of neuron 3002 that generates an output to be transmitted on that instance of synapse 3008 may be referred to as a "presynaptic neuron" relative to an instance of synapse 3008. In at least one embodiment, an instance of neuron 3002 that receives input transmitted via that instance of synapse 3008 may be referred to as a "postsynaptic neuron" relative to an instance of synapse 3008. In at least one embodiment, relative to each instance of synapse 3008, because an instance of neuron 3002 can receive input from one or more instances of synapse 3008 and can also transmit output through one or more instances of synapse 3008, a single instance of neuron 3002 can be both a "presynaptic neuron" and...

Claims

1. A processor, comprising: One or more circuits, said one or more circuits being configured to cause the accuracy of one or more parts of a neural network to be measured at least in part based on the quantization of weights within said one or more parts.

2. The processor of claim 1, wherein the one or more portions of the neural network comprise one or more layers of a pre-trained model of the neural network.

3. The processor of claim 1, wherein the one or more circuits further cause one or more encoding formats of a plurality of encoding formats to be selected according to the measured accuracy for application to the one or more portions of the neural network.

4. The processor of claim 3, wherein the multiple encoding formats are supported by additional circuitry of the processor.

5. The processor of claim 3, wherein the one or more portions of the neural network comprise multiple layers of a pre-trained model, and wherein the one or more encoding formats comprise a first encoding format and a second encoding format different from the first encoding format.

6. The processor of claim 3, wherein the one or more circuits further cause the measured accuracy to be incorporated into a loss function for training the neural network, and wherein the one or more encoding formats are selected to minimize the loss function.

7. The processor of claim 6, wherein the one or more circuits further cause the neural network to be trained using various encoding formats among the plurality of encoding formats, wherein training the neural network using the encoding formats among the plurality of encoding formats comprises: The neural network is trained according to an imitation mask, wherein the imitation mask selectively determines the quantization of individual elements of one or more parts of the neural network, and The neural network is fine-tuned to minimize the corresponding error of selective quantization of each element.

8. A system comprising: One or more processors, said one or more processors being configured to make the accuracy of one or more parts of a neural network measured at least in part based on the quantization of weights within said one or more parts.

9. The system of claim 8, wherein the one or more portions of the neural network comprise one or more layers of a pre-trained model of the neural network.

10. The system of claim 8, wherein the one or more circuits further cause one or more encoding formats of a plurality of encoding formats to be selected according to the measured accuracy for application to the one or more portions of the neural network.

11. The system of claim 10, wherein the multiple encoding formats are supported by additional circuitry of the processor.

12. The system of claim 10, wherein the one or more portions of the neural network comprise multiple layers of a pre-trained model, and wherein the one or more encoding formats comprise a first encoding format and a second encoding format different from the first encoding format.

13. The system of claim 10, wherein the one or more circuits further cause the measured accuracy to be incorporated into a loss function for training the neural network, and wherein the one or more encoding formats are selected to minimize the loss function.

14. The system of claim 13, wherein one or more circuits further cause the neural network to be trained using various encoding formats among the plurality of encoding formats, wherein training the neural network using the encoding formats among the plurality of encoding formats comprises: The neural network is trained according to an imitation mask, wherein the imitation mask selectively determines the quantization of individual elements of one or more parts of the neural network, and The neural network is fine-tuned to minimize the corresponding error of selective quantization of each element.

15. A method comprising: The accuracy of one or more parts of a neural network is measured, at least in part, based on the quantization of weights within those parts, by one or more processors.

16. The method of claim 15, wherein the one or more portions of the neural network comprise one or more layers of a pre-trained model of the neural network.

17. The method of claim 15, wherein the one or more circuits further cause one or more encoding formats of a plurality of encoding formats to be selected according to the measured accuracy for application to the one or more portions of the neural network.

18. The method of claim 17, wherein the one or more portions of the neural network comprise multiple layers of a pre-trained model, and wherein the one or more encoding formats comprise a first encoding format and a second encoding format different from the first encoding format.

19. The method of claim 17, wherein the one or more circuits further cause the measured accuracy to be incorporated into a loss function for training the neural network, and wherein the one or more encoding formats are selected to minimize the loss function.

20. The method of claim 17, wherein the one or more circuits further cause the neural network to be trained using various encoding formats among the plurality of encoding formats, wherein training the neural network using the encoding formats among the plurality of encoding formats comprises: The neural network is trained according to an imitation mask, wherein the imitation mask selectively determines the quantization of individual elements of one or more parts of the neural network, and The neural network is fine-tuned to minimize the corresponding error of selective quantization of each element.

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